diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-08-25 09:32:19 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-08-26 18:23:52 +0000 |
| commit | 58966086cd437be7d169bfbf0edb6e8827c07e23 (patch) | |
| tree | c79c3fb848fac7225be2ddc48efa417787f6c04d /src | |
| parent | 091dfa1ca027d93fc6a78ded758b6ccd49c0f72a (diff) | |
soc/intel/tigerlake: Lock PAM registers in finalize
Use the support from the previous patch to have coreboot lock the PAM
registers instead of the FSP when the lockdown configuration is set to
coreboot.
Change-Id: Ice4c727f2b75893cd012345a556fd21d9807dfaa
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/tigerlake/finalize.c | 9 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/fsp_params.c | 1 |
2 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c index a28dccd110..6ed60e7eef 100644 --- a/src/soc/intel/tigerlake/finalize.c +++ b/src/soc/intel/tigerlake/finalize.c @@ -15,8 +15,10 @@ #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> #include <intelblocks/pmclib.h> +#include <intelblocks/systemagent.h> #include <intelblocks/tco.h> #include <intelblocks/thermal.h> +#include <intelpch/lockdown.h> #include <soc/p2sb.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> @@ -66,6 +68,12 @@ static void tbt_finalize(void) } } +static void sa_finalize(void) +{ + if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) + sa_lock_pam(); +} + static void soc_finalize(void *unused) { printk(BIOS_DEBUG, "Finalizing chipset.\n"); @@ -73,6 +81,7 @@ static void soc_finalize(void *unused) pch_finalize(); apm_control(APM_CNT_FINALIZE); tbt_finalize(); + sa_finalize(); /* Indicate finalize step with post code */ post_code(POST_OS_BOOT); diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 1d7db64be9..15ba280b92 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -398,6 +398,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PchLockDownBiosInterface = lockdown_by_fsp; params->PchUnlockGpioPads = !lockdown_by_fsp; params->RtcMemoryLock = lockdown_by_fsp; + params->SkipPamLock = !lockdown_by_fsp; /* coreboot will send EOP before loading payload */ params->EndOfPostMessage = EOP_DISABLE; |