diff options
| author | Luigi Semenzato <semenzato@chromium.org> | 2014-01-13 17:45:54 -0800 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2014-07-12 20:19:14 +0200 |
| commit | 562db3bb3fa16abf6f758e97f9e5496f1c14d423 (patch) | |
| tree | c9076f5fc2b526f2088dfde880024540019a17f8 /src | |
| parent | f4d1f3a4d9f57b0c36bf90cd9326fdc38ea78de3 (diff) | |
libpayload: find source of input characters
This change makes it possible for vboot to avoid an
exploit that could cause involuntary switch to dev mode.
It gives depthcharge/vboot some information on the
type of input device that generated a key.
BUG=chrome-os-partner:21729
TEST=manually tested for panther
BRANCH=none
CQ-DEPEND=CL:182420,CL:182241,CL:182946
Change-Id: I87bdac34bfc50f3adb0b35a2c57a8f95f4fbc35b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/182357
Reviewed-by: Luigi Semenzato <semenzato@chromium.org>
Tested-by: Luigi Semenzato <semenzato@chromium.org>
Commit-Queue: Luigi Semenzato <semenzato@chromium.org>
Reviewed-on: http://review.coreboot.org/6003
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/panther/devicetree.cb | 3 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/lpc.c | 1 |
2 files changed, 3 insertions, 1 deletions
diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb index 7cc3672f84..d37b622268 100644 --- a/src/mainboard/google/panther/devicetree.cb +++ b/src/mainboard/google/panther/devicetree.cb @@ -115,7 +115,8 @@ chip northbridge/intel/haswell io 0x60 = 0x700 io 0x62 = 0x710 irq 0x70 = 0x09 - irq 0xf4 = 0x20 + irq 0xf2 = 0x20 + irq 0xf4 = 0x0 irq 0xfa = 0x12 end device pnp 2e.7 on # GPIO diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index ecb8af92be..05b4d601af 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -195,6 +195,7 @@ static void pch_power_options(device_t dev) * If the option is not existent (Laptops), use Kconfig setting. */ get_option(&pwr_on, "power_on_after_fail"); + pwr_on = MAINBOARD_POWER_KEEP; reg16 = pci_read_config16(dev, GEN_PMCON_3); reg16 &= 0xfffe; |