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authorRyan Lin <ryan.lin@intel.com>2021-09-28 15:59:34 +0800
committerTim Wawrzynczak <twawrzynczak@chromium.org>2021-10-04 17:45:38 +0000
commit4a48dbe60bb39b2114f1a4c9bfc02a8d1a8e258f (patch)
treeb41eb17ae89bb8b833fd673c778493539230e8a8 /src
parent15066ba8d4696b299d93e5872ee035fc20570d13 (diff)
src/soc/intel/alderlake: Add PsysPmax setting
This patch feeds PsysPmax setting to FSP through UPD and adds a PsysPmax member in chip information so that we can set PsysPmax through devicetree. The PsysPmax needs to be set correctly mapping to maximum system power. Otherwise, system performance would be limited due to the default PsysPmax setting in FSP is only 21W. BUG=b:193864533, b:195615830 TEST=Set PsysPmax to an example value eg 145 in devicetree && put debug code in FSP to print the PsysPmax value before sending to Pcode, ensure the setting is correctly programmed. Change-Id: Ia07aa815f90739240f110cab984068237c02d896 Signed-off-by: Ryan Lin <ryan.lin@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/alderlake/chip.h3
-rw-r--r--src/soc/intel/alderlake/fsp_params.c7
2 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 3192478f77..270400b341 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -492,6 +492,9 @@ struct soc_intel_alderlake_config {
POWER_CYCLE_DURATION_3S,
POWER_CYCLE_DURATION_4S,
} pch_reset_power_cycle_duration;
+
+ /* Platform Power Pmax */
+ uint16_t PsysPmax;
};
typedef struct soc_intel_alderlake_config config_t;
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 8003471128..4ae25371cb 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -652,6 +652,13 @@ static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg,
s_cfg->PchPmSlpS3MinAssert,
s_cfg->PchPmSlpAMinAssert,
power_cycle_duration);
+
+ /* Set PsysPmax if it is available from DT */
+ if (config->PsysPmax) {
+ printk(BIOS_DEBUG, "PsysPmax = %dW\n", config->PsysPmax);
+ /* PsysPmax is in unit of 1/8 Watt */
+ s_cfg->PsysPmax = config->PsysPmax * 8;
+ }
}
static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg,