diff options
| author | Subrata Banik <subratabanik@google.com> | 2023-07-20 20:55:36 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-07-22 17:50:50 +0000 |
| commit | 449c6d981c216e05d5238056f03c7794e43600ec (patch) | |
| tree | a6e861897f15e502b7e6a8eb2f7af06a20a446fc /src | |
| parent | 4a58d14506ef139a24d44df9390e5b45b166ab1f (diff) | |
mb/google/rex/var/screebo: Reduce TCC from 90°C to 80°C
This patch increases the `tcc_offset` to reduce the TCC
(Thermal Control Circuit) activation temperature to avoid running
into abrupt power off during power cycle tests.
On Intel processors, the core frequency can be by an HW agent when
the current temperature reaches the TCC activation temperature.
The default TCC activation temperature is specified by MSR_IA32_TEMPERATURE_TARGET (which is 90°C for google/rex variants).
However, this patch adjusted the TCC by specifying an offset in
degrees C (i.e., using `tcc_offset` from variant override device tree).
Note: The bigger the TCC offset is, the lower the effective TCC activation temperature would be, to ensure that processors can be throttled earlier before the system critical overheats.
BUG=b:283008762
TEST=Able to perform power cycle on google/screebo w/o any crash/shutdown.
Change-Id: Ib19703877dbbfc26b2d9f538dda4f10c27cf872d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76658
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/rex/variants/screebo/overridetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb index cfe907cc6c..67bc4f80f5 100644 --- a/src/mainboard/google/rex/variants/screebo/overridetree.cb +++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb @@ -39,6 +39,9 @@ chip soc/intel/meteorlake # Enable HDMI in Port B register "ddi_port_B_config" = "0" + # Temporary setting TCC of 80C = Tj max (110) - TCC_Offset (30) + register "tcc_offset" = "30" + # Enable Display Port Configuration register "ddi_ports_config" = "{ [DDI_PORT_A] = DDI_ENABLE_HPD, |