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authorRobert Zieba <robertzieba@google.com>2022-08-10 16:31:27 -0600
committerMartin L Roth <gaumless@gmail.com>2022-11-09 23:57:49 +0000
commit44281956928348bb5df14a8257921c49991dace5 (patch)
tree0b213a12e21276a70159f0614b38f36987903d22 /src
parent065c5870e4678367f5be7014361772c9d03933c8 (diff)
device/xhci: Factor out common PORTSC code
This commit factors out some code for XHCI port status values. BUG=b:186792595 TEST=Built coreboot for volteer device Change-Id: I045405ed224aa8f48f6f628b7d49ec6bafb450d7 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/include/device/xhci.h38
-rw-r--r--src/soc/intel/common/block/xhci/elog.c43
2 files changed, 42 insertions, 39 deletions
diff --git a/src/include/device/xhci.h b/src/include/device/xhci.h
index 17ce846459..e5ce8b514c 100644
--- a/src/include/device/xhci.h
+++ b/src/include/device/xhci.h
@@ -3,7 +3,7 @@
#ifndef __DEVICE_XHCI_H__
#define __DEVICE_XHCI_H__
-#include <stdint.h>
+#include <types.h>
#include <device/device.h>
#include <commonlib/bsd/cb_err.h>
@@ -12,6 +12,42 @@
#define XHCI_ECP_CAP_ID_LEGACY 1
#define XHCI_ECP_CAP_ID_SUPP 2
+/* Status flags */
+/* Wake on disconnect enable */
+#define XHCI_STATUS_WDE BIT(26)
+/* Wake on connect enable */
+#define XHCI_STATUS_WCE BIT(25)
+/* Port link status change */
+#define XHCI_STATUS_PLC BIT(22)
+/* Connect status change */
+#define XHCI_STATUS_CSC BIT(17)
+/* Port link status */
+#define XHCI_STATUS_PLS_SHIFT 5
+#define XHCI_STATUS_PLS_MASK (0xf << XHCI_STATUS_PLS_SHIFT)
+#define XHCI_STATUS_PLS_RESUME (15 << XHCI_STATUS_PLS_SHIFT)
+
+static inline bool xhci_portsc_csc(uint32_t port_status)
+{
+ return port_status & XHCI_STATUS_CSC;
+}
+
+static inline bool xhci_portsc_wake_capable(uint32_t port_status)
+{
+ return (port_status & XHCI_STATUS_WCE) |
+ (port_status & XHCI_STATUS_WDE);
+}
+
+static inline bool xhci_portsc_plc(uint32_t port_status)
+{
+ return port_status & XHCI_STATUS_PLC;
+}
+
+static inline bool xhci_portsc_resume(uint32_t port_status)
+{
+ return (port_status & XHCI_STATUS_PLS_MASK) == XHCI_STATUS_PLS_RESUME;
+}
+
+
struct xhci_supported_protocol {
union {
uint32_t reg0;
diff --git a/src/soc/intel/common/block/xhci/elog.c b/src/soc/intel/common/block/xhci/elog.c
index e6a1c0f5da..8acefba40c 100644
--- a/src/soc/intel/common/block/xhci/elog.c
+++ b/src/soc/intel/common/block/xhci/elog.c
@@ -2,45 +2,12 @@
#include <device/mmio.h>
#include <device/pci_ops.h>
+#include <device/xhci.h>
#include <elog.h>
#include <intelblocks/xhci.h>
#include <soc/pci_devs.h>
#include <stdint.h>
-/* Wake on disconnect enable */
-#define XHCI_STATUS_WDE (1 << 26)
-/* Wake on connect enable */
-#define XHCI_STATUS_WCE (1 << 25)
-/* Port link status change */
-#define XHCI_STATUS_PLC (1 << 22)
-/* Connect status change */
-#define XHCI_STATUS_CSC (1 << 17)
-/* Port link status */
-#define XHCI_STATUS_PLS_SHIFT (5)
-#define XHCI_STATUS_PLS_MASK (0xF << XHCI_STATUS_PLS_SHIFT)
-#define XHCI_STATUS_PLS_RESUME (15 << XHCI_STATUS_PLS_SHIFT)
-
-static bool xhci_csc_set(uint32_t port_status)
-{
- return !!(port_status & XHCI_STATUS_CSC);
-}
-
-static bool xhci_wake_capable(uint32_t port_status)
-{
- return !!((port_status & XHCI_STATUS_WCE) |
- (port_status & XHCI_STATUS_WDE));
-}
-
-static bool xhci_plc_set(uint32_t port_status)
-{
- return !!(port_status & XHCI_STATUS_PLC);
-}
-
-static bool xhci_resume(uint32_t port_status)
-{
- return (port_status & XHCI_STATUS_PLS_MASK) == XHCI_STATUS_PLS_RESUME;
-}
-
/*
* Check if a particular USB port caused wake by:
* 1. Change in connect/disconnect status (if enabled)
@@ -73,8 +40,8 @@ static bool xhci_port_wake_check(uintptr_t base, uint8_t num, uint8_t host_event
* connect/disconnect to identify if the port caused wake
* event for USB attach/detach.
*/
- if (xhci_csc_set(port_status) &&
- xhci_wake_capable(port_status)) {
+ if (xhci_portsc_csc(port_status) &&
+ xhci_portsc_wake_capable(port_status)) {
elog_add_event_wake(host_event, 0);
elog_add_event_wake(event, i + 1);
found = true;
@@ -85,8 +52,8 @@ static bool xhci_port_wake_check(uintptr_t base, uint8_t num, uint8_t host_event
* Check if PLC is set and PLS indicates resume to identify if
* the port caused wake event for USB activity.
*/
- if (xhci_plc_set(port_status) &&
- xhci_resume(port_status)) {
+ if (xhci_portsc_plc(port_status) &&
+ xhci_portsc_resume(port_status)) {
elog_add_event_wake(host_event, 0);
elog_add_event_wake(event, i + 1);
found = true;