diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2022-06-20 21:22:27 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2022-11-02 21:07:12 +0000 |
| commit | 3fa42ac553e0e7583a0e8db2e8c34fbd09a07225 (patch) | |
| tree | 1d0ace21886d83a8ffffbdc72d66d93abd69e916 /src | |
| parent | 8998ab8b020d6711f56634880b26b2b908d1340c (diff) | |
mb/clevo/l140mu: work around PECI staying high when idle, blocking s0ix
According to Intel doc# 575683 the PECI bus should be low when idle and
is pulled up by clients with strong drive. However, for unknown reasons
the bus stays high on this board, blocking s0ix entry.
The PECI reference schematic in the ASPEED AST2400 BMC datasheet
(actually not related to this board) says that a pull-down is *required*
for the idle state.
This might be just a requirement of this BMC, since this is nowhere
documented in Intel datasheets, schematics or elsewhere. However,
configuring a weak pull-down (20 k) on the PECI pad indeed solves this
problem for now.
Change-Id: I85193000af67cd2c0465bdbb58cdd51b68fd5b4f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68794
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/clevo/tgl-u/variants/l140mu/gpio.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/gpio.c b/src/mainboard/clevo/tgl-u/variants/l140mu/gpio.c index 6919baf418..831b5fe9b1 100644 --- a/src/mainboard/clevo/tgl-u/variants/l140mu/gpio.c +++ b/src/mainboard/clevo/tgl-u/variants/l140mu/gpio.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <intelblocks/pcr.h> #include <soc/gpe.h> #include <soc/gpio.h> #include <variant/gpio.h> @@ -232,4 +233,7 @@ static const struct pad_config gpio_table[] = { void variant_configure_gpios(void) { gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + /* PECI idle workaround */ + pcr_rmw32(0x6b, 0x744, ~PAD_CFG1_PULL_MASK, PAD_CFG1_PULL_DN_20K); } |