src: Drop useless cache flush settings in FADT

They are ignored if the ACPI_FADT_WBINVD flag is set, which is required
on current ACPI versions and only maintained for ACPI 1.0 compatibility.

Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.

Change-Id: Ief1219542ba71d18153b64180e0ff60bd1e7687b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>

21 files changed, 0 insertions, 44 deletions

diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c
index d3966607e2..6d5d937ccb 100644
--- a/src/soc/amd/picasso/acpi.c
+++ b/src/soc/amd/picasso/acpi.c
@@ -110,8 +110,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 
 	fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
 	fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
-	fadt->flush_size = 0;	/* set to 0 if WBINVD is 1 in flags */
-	fadt->flush_stride = 0;	/* set to 0 if WBINVD is 1 in flags */
 	fadt->duty_offset = 1;	/* CLK_VAL bits 3:1 */
 	fadt->duty_width = 3;	/* CLK_VAL bits 3:1 */
 	fadt->day_alrm = 0;	/* 0x7d these have to be */
diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c
index fb8a469d34..7f199ccacb 100644
--- a/src/soc/amd/stoneyridge/acpi.c
+++ b/src/soc/amd/stoneyridge/acpi.c
@@ -82,8 +82,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 
 	fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
 	fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
-	fadt->flush_size = 0;	/* set to 0 if WBINVD is 1 in flags */
-	fadt->flush_stride = 0;	/* set to 0 if WBINVD is 1 in flags */
 	fadt->duty_offset = 1;	/* CLK_VAL bits 3:1 */
 	fadt->duty_width = 3;	/* CLK_VAL bits 3:1 */
 	fadt->day_alrm = 0;	/* 0x7d these have to be */
diff --git a/src/soc/intel/baytrail/fadt.c b/src/soc/intel/baytrail/fadt.c
index b19d4ce6ee..900805b683 100644
--- a/src/soc/intel/baytrail/fadt.c
+++ b/src/soc/intel/baytrail/fadt.c
@@ -32,8 +32,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->gpe0_blk_len = 2 * (GPE0_EN - GPE0_STS);
 	fadt->p_lvl2_lat = 1;
 	fadt->p_lvl3_lat = 87;
-	fadt->flush_size = 1024;
-	fadt->flush_stride = 16;
 	fadt->duty_offset = 1;
 	fadt->duty_width = 0;
 	fadt->day_alrm = 0xd;
diff --git a/src/soc/intel/braswell/fadt.c b/src/soc/intel/braswell/fadt.c
index b19d4ce6ee..900805b683 100644
--- a/src/soc/intel/braswell/fadt.c
+++ b/src/soc/intel/braswell/fadt.c
@@ -32,8 +32,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->gpe0_blk_len = 2 * (GPE0_EN - GPE0_STS);
 	fadt->p_lvl2_lat = 1;
 	fadt->p_lvl3_lat = 87;
-	fadt->flush_size = 1024;
-	fadt->flush_stride = 16;
 	fadt->duty_offset = 1;
 	fadt->duty_width = 0;
 	fadt->day_alrm = 0xd;
diff --git a/src/soc/intel/broadwell/fadt.c b/src/soc/intel/broadwell/fadt.c
index 4e4074ff6d..2a4019db94 100644
--- a/src/soc/intel/broadwell/fadt.c
+++ b/src/soc/intel/broadwell/fadt.c
@@ -31,8 +31,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->gpe0_blk_len = 32;
 	fadt->p_lvl2_lat = 1;
 	fadt->p_lvl3_lat = 87;
-	fadt->flush_size = 1024;
-	fadt->flush_stride = 16;
 	fadt->duty_offset = 1;
 	fadt->duty_width = 0;
 	fadt->day_alrm = 0xd;
diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c
index 1ce34fa7f4..9f99984aab 100644
--- a/src/soc/intel/common/block/acpi/acpi.c
+++ b/src/soc/intel/common/block/acpi/acpi.c
@@ -114,8 +114,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	/* GPE0 STS/EN pairs each 32 bits wide. */
 	fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t);
 
-	fadt->flush_size = 0x400;	/* twice of cache size */
-	fadt->flush_stride = 0x10;	/* Cache line width  */
 	fadt->duty_offset = 1;
 	fadt->day_alrm = 0xd;
 
diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c
index 99782b7ff0..f4204da5ef 100644
--- a/src/soc/intel/denverton_ns/acpi.c
+++ b/src/soc/intel/denverton_ns/acpi.c
@@ -129,8 +129,6 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
 
 	fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
 	fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
-	fadt->flush_size = 0;   /* set to 0 if WBINVD is 1 in flags */
-	fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */
 	fadt->duty_offset = 1;
 	fadt->duty_width = 0;
 
diff --git a/src/soc/intel/skylake/fadt.c b/src/soc/intel/skylake/fadt.c
index 732f6b6bf5..0c0ae8db7a 100644
--- a/src/soc/intel/skylake/fadt.c
+++ b/src/soc/intel/skylake/fadt.c
@@ -35,8 +35,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t);
 	fadt->p_lvl2_lat = 1;
 	fadt->p_lvl3_lat = 87;
-	fadt->flush_size = 1024;
-	fadt->flush_stride = 16;
 	fadt->duty_offset = 1;
 	fadt->duty_width = 0;
 	fadt->day_alrm = 0xd;
diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c
index db233cbca5..1ca3fc6de6 100644
--- a/src/soc/intel/xeon_sp/cpx/acpi.c
+++ b/src/soc/intel/xeon_sp/cpx/acpi.c
@@ -293,8 +293,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	/* GPE0 STS/EN pairs each 32 bits wide. */
 	fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t);
 
-	fadt->flush_size = 0x400;	/* twice of cache size */
-	fadt->flush_stride = 0x10;	/* Cache line width  */
 	fadt->duty_offset = 1;
 	fadt->day_alrm = 0xd;
 
diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c
index 13bddfc3bb..478b8a4174 100644
--- a/src/soc/intel/xeon_sp/skx/acpi.c
+++ b/src/soc/intel/xeon_sp/skx/acpi.c
@@ -252,8 +252,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t);
 	fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
 	fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
-	fadt->flush_size = 0;   /* set to 0 if WBINVD is 1 in flags */
-	fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */
 	fadt->duty_offset = 1;
 	fadt->duty_width = 0;
 
diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c
index 3e880fec35..efd0b41cbc 100644
--- a/src/southbridge/amd/agesa/hudson/fadt.c
+++ b/src/southbridge/amd/agesa/hudson/fadt.c
@@ -46,8 +46,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 
 	fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
 	fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
-	fadt->flush_size = 0;	/* set to 0 if WBINVD is 1 in flags */
-	fadt->flush_stride = 0;	/* set to 0 if WBINVD is 1 in flags */
 	fadt->duty_offset = 1;	/* CLK_VAL bits 3:1 */
 	fadt->duty_width = 3;	/* CLK_VAL bits 3:1 */
 	fadt->day_alrm = 0;	/* 0x7d these have to be */
diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c
index 5f31cd5c4e..a163ff7e02 100644
--- a/src/southbridge/amd/cimx/sb800/fadt.c
+++ b/src/southbridge/amd/cimx/sb800/fadt.c
@@ -72,8 +72,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 
 	fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
 	fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
-	fadt->flush_size = 0;	/* set to 0 if WBINVD is 1 in flags */
-	fadt->flush_stride = 0;	/* set to 0 if WBINVD is 1 in flags */
 	fadt->duty_offset = 1;	/* CLK_VAL bits 3:1 */
 	fadt->duty_width = 3;	/* CLK_VAL bits 3:1 */
 	fadt->day_alrm = 0;	/* 0x7d these have to be */
diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c
index e085df1f3d..2d71b0918a 100644
--- a/src/southbridge/amd/pi/hudson/fadt.c
+++ b/src/southbridge/amd/pi/hudson/fadt.c
@@ -46,8 +46,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 
 	fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
 	fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
-	fadt->flush_size = 0;	/* set to 0 if WBINVD is 1 in flags */
-	fadt->flush_stride = 0;	/* set to 0 if WBINVD is 1 in flags */
 	fadt->duty_offset = 1;	/* CLK_VAL bits 3:1 */
 	fadt->duty_width = 3;	/* CLK_VAL bits 3:1 */
 	fadt->day_alrm = 0;	/* 0x7d these have to be */
diff --git a/src/southbridge/intel/bd82x6x/fadt.c b/src/southbridge/intel/bd82x6x/fadt.c
index 7b36583495..c7ba5c25ae 100644
--- a/src/southbridge/intel/bd82x6x/fadt.c
+++ b/src/southbridge/intel/bd82x6x/fadt.c
@@ -39,9 +39,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	}
 	fadt->p_lvl2_lat = c2_latency;
 	fadt->p_lvl3_lat = 87;
-	/* flush_* is ignored if ACPI_FADT_WBINVD is set */
-	fadt->flush_size = 0;
-	fadt->flush_stride = 0;
 	/* P_CNT not supported */
 	fadt->duty_offset = 0;
 	fadt->duty_width = 0;
diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c
index c775af0c92..249b22b5bc 100644
--- a/src/southbridge/intel/i82371eb/fadt.c
+++ b/src/southbridge/intel/i82371eb/fadt.c
@@ -38,8 +38,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 
 	fadt->p_lvl2_lat = 101; /* >100 means c2 not supported */
 	fadt->p_lvl3_lat = 1001; /* >1000 means c3 not supported */
-	fadt->flush_size = 0; /* only needed if CPU wbinvd is broken */
-	fadt->flush_stride = 0;
 	fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */
 	fadt->duty_width = 3; /* this width is in bits */
 	fadt->day_alrm = 0x0d; /* rtc CMOS RAM offset */
diff --git a/src/southbridge/intel/i82801dx/fadt.c b/src/southbridge/intel/i82801dx/fadt.c
index 8be39bfdb6..b2f7d5fff8 100644
--- a/src/southbridge/intel/i82801dx/fadt.c
+++ b/src/southbridge/intel/i82801dx/fadt.c
@@ -41,8 +41,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->gpe0_blk_len = 8;
 	fadt->p_lvl2_lat = 1;
 	fadt->p_lvl3_lat = 85;
-	fadt->flush_size = 1024;
-	fadt->flush_stride = 16;
 	fadt->duty_offset = 1;
 	fadt->duty_width = 0;
 	fadt->day_alrm = 0xd;
diff --git a/src/southbridge/intel/i82801gx/fadt.c b/src/southbridge/intel/i82801gx/fadt.c
index 35a1facb55..11d4aac79d 100644
--- a/src/southbridge/intel/i82801gx/fadt.c
+++ b/src/southbridge/intel/i82801gx/fadt.c
@@ -38,8 +38,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->gpe0_blk_len = 8;
 	fadt->p_lvl2_lat = 1;
 	fadt->p_lvl3_lat = chip->c3_latency;
-	fadt->flush_size = 0;
-	fadt->flush_stride = 0;
 	fadt->duty_offset = 1;
 	if (chip->p_cnt_throttling_supported)
 		fadt->duty_width = 3;
diff --git a/src/southbridge/intel/i82801ix/fadt.c b/src/southbridge/intel/i82801ix/fadt.c
index 710f585f8c..8ea69e8058 100644
--- a/src/southbridge/intel/i82801ix/fadt.c
+++ b/src/southbridge/intel/i82801ix/fadt.c
@@ -34,8 +34,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->gpe0_blk_len = 16;
 	fadt->p_lvl2_lat = 1;
 	fadt->p_lvl3_lat = 0x39;
-	fadt->flush_size = 0;
-	fadt->flush_stride = 0;
 	fadt->duty_offset = 1;
 	fadt->duty_width = 3;
 	fadt->day_alrm = 0xd;
diff --git a/src/southbridge/intel/i82801jx/fadt.c b/src/southbridge/intel/i82801jx/fadt.c
index 6f80aa6d66..ac2ba76b70 100644
--- a/src/southbridge/intel/i82801jx/fadt.c
+++ b/src/southbridge/intel/i82801jx/fadt.c
@@ -37,8 +37,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->gpe0_blk_len = 16;
 	fadt->p_lvl2_lat = 1;
 	fadt->p_lvl3_lat = chip->c3_latency;
-	fadt->flush_size = 0;
-	fadt->flush_stride = 0;
 	fadt->duty_offset = 1;
 	fadt->duty_width = 0;
 	fadt->day_alrm = 0xd;
diff --git a/src/southbridge/intel/ibexpeak/fadt.c b/src/southbridge/intel/ibexpeak/fadt.c
index 103fda6ca9..93c95b5692 100644
--- a/src/southbridge/intel/ibexpeak/fadt.c
+++ b/src/southbridge/intel/ibexpeak/fadt.c
@@ -39,9 +39,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	}
 	fadt->p_lvl2_lat = c2_latency;
 	fadt->p_lvl3_lat = 87;
-	/* flush_* is ignored if ACPI_FADT_WBINVD is set */
-	fadt->flush_size = 0;
-	fadt->flush_stride = 0;
 	/* P_CNT not supported */
 	fadt->duty_offset = 0;
 	fadt->duty_width = 0;
diff --git a/src/southbridge/intel/lynxpoint/fadt.c b/src/southbridge/intel/lynxpoint/fadt.c
index 7c1bef9941..2868b5f943 100644
--- a/src/southbridge/intel/lynxpoint/fadt.c
+++ b/src/southbridge/intel/lynxpoint/fadt.c
@@ -46,8 +46,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 
 	fadt->p_lvl2_lat = 1;
 	fadt->p_lvl3_lat = 87;
-	fadt->flush_size = 0;
-	fadt->flush_stride = 0;
 	fadt->duty_offset = 0;
 	fadt->duty_width = 0;
 	fadt->day_alrm = 0xd;