diff options
| author | Subrata Banik <subratabanik@google.com> | 2024-07-18 23:04:14 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-07-22 06:41:39 +0000 |
| commit | 3b3a05259640b2c80c500193c5c93e7a1d432a91 (patch) | |
| tree | e3bf50aa0fcc5e83eaaac46dffd205bc6c61568b /src | |
| parent | 4403c384986de98eb51cc6405bb7f5a4ac4b5781 (diff) | |
mb/google/brya/var/trulo: Add TCSS port descriptions
This patch adds descriptions for TCSS port, including over-current
(OC) pin configuration, to the device tree.
It also includes entries that will generate ACPI code at runtime
with port definitions, locations, and type information.
Additionally, implement the TCSS PMC MUX programming.
BUG=b:351976770
TEST=Builds successfully for google/trulo.
Change-Id: I60de314a92514d153ca039f6eaeb904b117b786c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83548
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/brya/variants/trulo/overridetree.cb | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb index 56d96ff1c4..03f7f9e552 100644 --- a/src/mainboard/google/brya/variants/trulo/overridetree.cb +++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb @@ -17,8 +17,28 @@ chip soc/intel/alderlake register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 (MLB) register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1 (DB) + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + + # Bit 0 - C0 has no redriver, so enable SBU muxing in the SoC. + # Bit 2 - C1 has a redriver which does SBU muxing. + # Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1. + register "tcss_aux_ori" = "0" + device domain 0 on device ref igpu on end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + end + end + end device ref xhci on chip drivers/usb/acpi device ref xhci_root_hub on @@ -84,8 +104,20 @@ chip soc/intel/alderlake device ref ufs on end device ref pch_espi on chip ec/google/chromeec + use conn0 as mux_conn[0] device pnp 0c09.0 on end end end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port5 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end end end |