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authorJack Rosenthal <jrosenth@chromium.org>2022-06-29 16:18:45 -0600
committerTim Wawrzynczak <twawrzynczak@chromium.org>2022-07-08 21:39:40 +0000
commit341ece9680e5d1d6a38082044671e91816b776e7 (patch)
tree0f0be28194b6d16817e309823c57d9291392aae9 /src
parent72b4196d8111dd209c3d9766d1601c56f7a35914 (diff)
mb/google/brya/var/ghost4adl: Add early GPIO table
Customize brya baseboard early GPIO table to add mem straps for ghost4adl, change I2C bus for TPM to pins H6/H7, and remove pins which are not used on ghost4adl (E16, H13). BUG=b:234626939 BRANCH=firmware-brya-14505.B TEST=emerge-ghost coreboot Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I126a66fc5d24fbefec99abf87862c55b50c5e398 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65534 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/brya/variants/ghost4adl/gpio.c49
1 files changed, 49 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/ghost4adl/gpio.c b/src/mainboard/google/brya/variants/ghost4adl/gpio.c
index b455041a57..ac6ad4bcea 100644
--- a/src/mainboard/google/brya/variants/ghost4adl/gpio.c
+++ b/src/mainboard/google/brya/variants/ghost4adl/gpio.c
@@ -343,6 +343,49 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_T3, NONE),
};
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+ /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
+ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+ /* B4 : PROC_GP3 ==> SSD_PERST_L */
+ PAD_CFG_GPO(GPP_B4, 0, DEEP),
+ /*
+ * D1 : ISH_GP1 ==> FP_RST_ODL
+ * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
+ * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
+ * early on in bootblock, followed by enabling of power. Reset signal is deasserted
+ * later on in ramstage. Since reset signal is asserted in bootblock, it results in
+ * FPMCU not working after a S3 resume. This is a known issue.
+ */
+ PAD_CFG_GPO(GPP_D1, 0, DEEP),
+ /* D2 : ISH_GP2 ==> EN_FP_PWR */
+ PAD_CFG_GPO(GPP_D2, 1, DEEP),
+ /* E15 : RSVD_TP ==> PCH_WP_OD */
+ PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG),
+ /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
+ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+ /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
+ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+
+ /* TPM is on I2C port 1 */
+ /* H6 : [NF1: I2C1_SDA NF6: USB_C_GPP_H6] ==> PCH_I2C_TPM_R_SDA */
+ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+ /* H7 : [NF1: I2C1_SCL NF6: USB_C_GPP_H7] ==> PCH_I2C_TPM_R_SCL */
+ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+
+ /* Mem straps */
+ /* B3 : PROC_GP2 ==> MEM_CH_SEL */
+ PAD_CFG_GPI(GPP_B3, NONE, DEEP),
+ /* E3 : PROC_GP0 ==> MEM_STRAP_0 */
+ PAD_CFG_GPI(GPP_E3, NONE, DEEP),
+ /* E2 : THC0_SPI1_IO3 ==> MEM_STRAP_1 */
+ PAD_CFG_GPI(GPP_E2, NONE, DEEP),
+ /* E1 : THC0_SPI1_IO2 ==> MEM_STRAP_2 */
+ PAD_CFG_GPI(GPP_E1, NONE, DEEP),
+ /* E7 : PROC_GP1 ==> MEM_STRAP_3 */
+ PAD_CFG_GPI(GPP_E7, NONE, DEEP),
+};
+
const struct pad_config *__weak variant_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(gpio_table);
@@ -354,3 +397,9 @@ const struct pad_config *__weak variant_gpio_override_table(size_t *num)
*num = 0;
return NULL;
}
+
+const struct pad_config *__weak variant_early_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(early_gpio_table);
+ return early_gpio_table;
+}