broadwell: Compute channel disable masks at runtime

Introduce the `SPD_MEMORY_DOWN` macro to indicate that a slot is used
with memory-down. This enables computing the channel disable masks as
the bits for slots where the SPD address is zero. To preserve current
behavior, zero the SPD addresses for memory-down slots afterwards.

Change-Id: I75b7be7c72062d1a26cfc7b09b79de62de0a9cea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55807
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

13 files changed, 26 insertions, 34 deletions

diff --git a/src/mainboard/google/auron/spd.c b/src/mainboard/google/auron/spd.c
index 49ee42c5e1..686a24225e 100644
--- a/src/mainboard/google/auron/spd.c
+++ b/src/mainboard/google/auron/spd.c
@@ -104,9 +104,10 @@ void mainboard_fill_spd_data(struct pei_data *pei_data)
 	const unsigned int spd_index = variant_get_spd_index();
 
 	fill_spd_for_index(pei_data->spd_data[0][0], spd_index);
+	pei_data->spd_addresses[0] = SPD_MEMORY_DOWN;
 
-	if (variant_is_dual_channel(spd_index))
+	if (variant_is_dual_channel(spd_index)) {
 		memcpy(pei_data->spd_data[1][0], pei_data->spd_data[0][0], SPD_LEN);
-	else
-		pei_data->dimm_channel1_disabled = 3;
+		pei_data->spd_addresses[2] = SPD_MEMORY_DOWN;
+	}
 }
diff --git a/src/mainboard/google/auron/variants/auron_paine/pei_data.c b/src/mainboard/google/auron/variants/auron_paine/pei_data.c
index 9a6fe7bcae..b157fcdf80 100644
--- a/src/mainboard/google/auron/variants/auron_paine/pei_data.c
+++ b/src/mainboard/google/auron/variants/auron_paine/pei_data.c
@@ -7,10 +7,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
 	pei_data->ec_present = 1;
 
-	/* One installed DIMM per channel -- can be changed by SPD init */
-	pei_data->dimm_channel0_disabled = 2;
-	pei_data->dimm_channel1_disabled = 2;
-
 	/* P0: LTE */
 	pei_data_usb2_port(pei_data, 0, 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE);
 	/* P1: POrt A, CN10 */
diff --git a/src/mainboard/google/auron/variants/auron_yuna/pei_data.c b/src/mainboard/google/auron/variants/auron_yuna/pei_data.c
index 9a6fe7bcae..b157fcdf80 100644
--- a/src/mainboard/google/auron/variants/auron_yuna/pei_data.c
+++ b/src/mainboard/google/auron/variants/auron_yuna/pei_data.c
@@ -7,10 +7,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
 	pei_data->ec_present = 1;
 
-	/* One installed DIMM per channel -- can be changed by SPD init */
-	pei_data->dimm_channel0_disabled = 2;
-	pei_data->dimm_channel1_disabled = 2;
-
 	/* P0: LTE */
 	pei_data_usb2_port(pei_data, 0, 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE);
 	/* P1: POrt A, CN10 */
diff --git a/src/mainboard/google/auron/variants/buddy/spd/spd.c b/src/mainboard/google/auron/variants/buddy/spd/spd.c
index 6fb439b96c..571aaafd33 100644
--- a/src/mainboard/google/auron/variants/buddy/spd/spd.c
+++ b/src/mainboard/google/auron/variants/buddy/spd/spd.c
@@ -9,8 +9,6 @@ void mainboard_fill_spd_data(struct pei_data *pei_data)
 {
 	pei_data->spd_addresses[0] = 0xa0;
 	pei_data->spd_addresses[2] = 0xa4;
-	pei_data->dimm_channel0_disabled = 2;
-	pei_data->dimm_channel1_disabled = 2;
 	/* Enable 2x refresh mode */
 	pei_data->ddr_refresh_2x = 1;
 	pei_data->dq_pins_interleaved = 1;
diff --git a/src/mainboard/google/auron/variants/gandof/pei_data.c b/src/mainboard/google/auron/variants/gandof/pei_data.c
index 9a6fe7bcae..b157fcdf80 100644
--- a/src/mainboard/google/auron/variants/gandof/pei_data.c
+++ b/src/mainboard/google/auron/variants/gandof/pei_data.c
@@ -7,10 +7,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
 	pei_data->ec_present = 1;
 
-	/* One installed DIMM per channel -- can be changed by SPD init */
-	pei_data->dimm_channel0_disabled = 2;
-	pei_data->dimm_channel1_disabled = 2;
-
 	/* P0: LTE */
 	pei_data_usb2_port(pei_data, 0, 0x0150, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE);
 	/* P1: POrt A, CN10 */
diff --git a/src/mainboard/google/auron/variants/lulu/pei_data.c b/src/mainboard/google/auron/variants/lulu/pei_data.c
index 812bd3ba17..663dd359e9 100644
--- a/src/mainboard/google/auron/variants/lulu/pei_data.c
+++ b/src/mainboard/google/auron/variants/lulu/pei_data.c
@@ -7,10 +7,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
 	pei_data->ec_present = 1;
 
-	/* One installed DIMM per channel -- can be changed by SPD init */
-	pei_data->dimm_channel0_disabled = 2;
-	pei_data->dimm_channel1_disabled = 2;
-
 	/* P0: Port B, CN01 (IOBoard) */
 	pei_data_usb2_port(pei_data, 0, 0x0150, 1, 0, USB_PORT_BACK_PANEL);
 	/* P1: Port A, CN01 */
diff --git a/src/mainboard/google/auron/variants/samus/pei_data.c b/src/mainboard/google/auron/variants/samus/pei_data.c
index 549e8d9a53..4ef45ee10c 100644
--- a/src/mainboard/google/auron/variants/samus/pei_data.c
+++ b/src/mainboard/google/auron/variants/samus/pei_data.c
@@ -20,10 +20,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 
 	pei_data->ec_present = 1;
 
-	/* One installed DIMM per channel */
-	pei_data->dimm_channel0_disabled = 2;
-	pei_data->dimm_channel1_disabled = 2;
-
 	memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
 	memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
 
diff --git a/src/mainboard/google/jecht/spd/spd.c b/src/mainboard/google/jecht/spd/spd.c
index 942b9a33e9..6446a937e1 100644
--- a/src/mainboard/google/jecht/spd/spd.c
+++ b/src/mainboard/google/jecht/spd/spd.c
@@ -8,8 +8,6 @@ void mainboard_fill_spd_data(struct pei_data *pei_data)
 {
 	pei_data->spd_addresses[0] = 0xa0;
 	pei_data->spd_addresses[2] = 0xa4;
-	pei_data->dimm_channel0_disabled = 2;
-	pei_data->dimm_channel1_disabled = 2;
 	// Enable 2x refresh mode
 	pei_data->ddr_refresh_2x = 1;
 	pei_data->dq_pins_interleaved = 1;
diff --git a/src/mainboard/intel/wtm2/pei_data.c b/src/mainboard/intel/wtm2/pei_data.c
index bcb877dd64..b0e8123783 100644
--- a/src/mainboard/intel/wtm2/pei_data.c
+++ b/src/mainboard/intel/wtm2/pei_data.c
@@ -6,9 +6,6 @@
 void mainboard_fill_spd_data(struct pei_data *pei_data)
 {
 	/* One installed DIMM per channel */
-	pei_data->dimm_channel0_disabled = 2;
-	pei_data->dimm_channel1_disabled = 2;
-
 	pei_data->spd_addresses[0] = 0xa2;
 	pei_data->spd_addresses[2] = 0xa2;
 }
diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c b/src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c
index 64cac287c1..0025617146 100644
--- a/src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c
+++ b/src/mainboard/purism/librem_bdw/variants/librem13v1/pei_data.c
@@ -6,7 +6,6 @@
 void mainboard_fill_spd_data(struct pei_data *pei_data)
 {
 	/* One DIMM slot */
-	pei_data->dimm_channel1_disabled = 3;
 	pei_data->spd_addresses[0] = 0xa0;
 }
 
diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c b/src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c
index 275cbadeee..1cb7e756e7 100644
--- a/src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c
+++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/pei_data.c
@@ -8,9 +8,6 @@ void mainboard_fill_spd_data(struct pei_data *pei_data)
 	pei_data->dq_pins_interleaved = 1;
 
 	/* One DIMM slot */
-	pei_data->dimm_channel0_disabled = 2;
-	pei_data->dimm_channel1_disabled = 2;
-
 	pei_data->spd_addresses[0] = 0xa0;
 	pei_data->spd_addresses[2] = 0xa4;
 }
diff --git a/src/soc/intel/broadwell/include/soc/pei_wrapper.h b/src/soc/intel/broadwell/include/soc/pei_wrapper.h
index 4a38a2afa6..cfdb910064 100644
--- a/src/soc/intel/broadwell/include/soc/pei_wrapper.h
+++ b/src/soc/intel/broadwell/include/soc/pei_wrapper.h
@@ -26,6 +26,8 @@ static inline void pei_data_usb3_port(struct pei_data *pei_data, int port,
 	pei_data->usb3_ports[port].fixed_eq = fixed_eq;
 }
 
+#define SPD_MEMORY_DOWN	0xff
+
 void broadwell_fill_pei_data(struct pei_data *pei_data);
 void mainboard_fill_pei_data(struct pei_data *pei_data);
 void mainboard_fill_spd_data(struct pei_data *pei_data);
diff --git a/src/soc/intel/broadwell/raminit.c b/src/soc/intel/broadwell/raminit.c
index 95073d3194..70f38043cd 100644
--- a/src/soc/intel/broadwell/raminit.c
+++ b/src/soc/intel/broadwell/raminit.c
@@ -177,6 +177,17 @@ static void setup_sdram_meminfo(struct pei_data *pei_data)
 	}
 }
 
+/*
+ * 0 = leave channel enabled
+ * 1 = disable dimm 0 on channel
+ * 2 = disable dimm 1 on channel
+ * 3 = disable dimm 0+1 on channel
+ */
+static int make_channel_disabled_mask(const struct pei_data *pd, int ch)
+{
+	return (!pd->spd_addresses[ch + ch] << 0) | (!pd->spd_addresses[ch + ch + 1] << 1);
+}
+
 void perform_raminit(const struct chipset_power_state *const power_state)
 {
 	const int s3resume = power_state->prev_sleep_state == ACPI_S3;
@@ -186,6 +197,15 @@ void perform_raminit(const struct chipset_power_state *const power_state)
 	mainboard_fill_pei_data(&pei_data);
 	mainboard_fill_spd_data(&pei_data);
 
+	/* Calculate unimplemented DIMM slots for each channel */
+	pei_data.dimm_channel0_disabled = make_channel_disabled_mask(&pei_data, 0);
+	pei_data.dimm_channel1_disabled = make_channel_disabled_mask(&pei_data, 1);
+
+	for (size_t i = 0; i < ARRAY_SIZE(pei_data.spd_addresses); i++) {
+		const uint8_t addr = pei_data.spd_addresses[i];
+		pei_data.spd_addresses[i] = addr == SPD_MEMORY_DOWN ? 0 : addr;
+	}
+
 	post_code(0x32);
 
 	timestamp_add_now(TS_INITRAM_START);