diff options
| author | Ashish Kumar Mishra <ashish.k.mishra@intel.com> | 2024-02-02 20:18:56 +0530 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2024-02-08 06:02:54 +0000 |
| commit | 32ebaef73c8e1cc367e1c63af587250041fce32a (patch) | |
| tree | cb21b257f38e60eadf225773379ed1384fb1a52b /src | |
| parent | 33659d246e5d89885413d4ea30525dacdacc56ee (diff) | |
mb/google/brox: Handle GPI_INT pin lower to GPI_WAKE
In case where PAD_CFG_GPI_INT() is initialized with a pin value
lower to PAD_CFG_GPI_IRQ_WAKE() for same GPIO community
the set_ioapic_used() is only called for the PAD_CFG_GPI_IRQ_WAKE() pin.
Due to this the IRQ associated with PAD_CFG_GPI_INT() is found free by
find_free_unique_irq() during IRQ assignment and assigned to other pins
which causes IRQ conflicts
BUG=b:322984217
BRANCH=None
TEST=Boot test on brox, check if correct IRQ assigned to EC
Change-Id: I8c3d557e888b8d0ceac203f49b702910fba26d6d
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80334
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/brox/variants/baseboard/brox/gpio.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/common/block/gpio/gpio.c | 6 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/gpio_defs.h | 21 |
3 files changed, 26 insertions, 3 deletions
diff --git a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c index 5432bd1143..3f39f1813f 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c +++ b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c @@ -140,7 +140,7 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_C7, NONE), /* GPP_D0 : [NF1: ISH_GP0 NF2: BK0 NF5: SBK0 NF6: USB_C_GPP_D0] ==> PCH_EC_PCH_INT_ODL */ - PAD_CFG_GPI_INT(GPP_D0, NONE, PLTRST, LEVEL), + PAD_CFG_GPI_INT_SWAPPED(GPP_D0, NONE, PLTRST, LEVEL), /* GPP_D1 : [NF1: ISH_GP1 NF2: BK1 NF5: SBK1 NF6: USB_C_GPP_D1] ==> PCH_EC_PCH_WAKE_ODL */ PAD_CFG_GPI_IRQ_WAKE(GPP_D1, NONE, DEEP, EDGE_SINGLE, INVERT), /* GPP_D2 : [NF1: ISH_GP2 NF2: BK2 NF5: SBK2 NF6: USB_C_GPP_D2] ==> ISH_ACCEL_DB_INT_L (NC) */ diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index 63d59daa57..09ada90ccc 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -276,7 +276,8 @@ static void gpio_configure_itss(const struct pad_config *cfg, uint16_t port, * in the GPIO pad configuration so that a hardware active low * signal looks that way to the APIC (double inversion). */ - if (!(cfg->pad_config[0] & PAD_CFG0_ROUTE_IOAPIC)) + if (!(cfg->pad_config[0] & PAD_CFG0_ROUTE_SWAPPED) && + !(cfg->pad_config[0] & PAD_CFG0_ROUTE_IOAPIC)) return; irq = pcr_read32(port, PAD_CFG1_OFFSET(pad_cfg_offset)); @@ -287,7 +288,8 @@ static void gpio_configure_itss(const struct pad_config *cfg, uint16_t port, return; } - if (CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG) && + !(cfg->pad_config[0] & PAD_CFG0_ROUTE_SWAPPED)) itss_set_irq_polarity(irq, !!(cfg->pad_config[0] & PAD_CFG0_RX_POL_INVERT)); diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 654d6f2d98..a51ebf3667 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -44,6 +44,7 @@ #define PAD_CFG0_ROUTE_SMI (1 << 18) #define PAD_CFG0_ROUTE_SCI (1 << 19) #define PAD_CFG0_ROUTE_IOAPIC (1 << 20) +#define PAD_CFG0_ROUTE_SWAPPED (1 << 27) #define PAD_CFG0_RXTENCFG_MASK (3 << 21) #define PAD_CFG0_RXINV_MASK (1 << 23) #define PAD_CFG0_RX_POL_INVERT (1 << 23) @@ -336,12 +337,26 @@ PAD_TRIG(trig) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE), \ PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) +#define PAD_CFG_GPI_TRIG_OWN_SWAPPED(pad, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_TRIG(trig) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE) | \ + PAD_IRQ_ROUTE(SWAPPED), \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) + #define PAD_CFG_GPI_TRIG_OWN_LOCK(pad, pull, rst, trig, own, lock_action) \ _PAD_CFG_STRUCT_LOCK(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | \ PAD_TRIG(trig) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE), \ PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own), PAD_LOCK(lock_action)) +#define PAD_CFG_GPI_TRIG_OWN_LOCK_SWAPPED(pad, pull, rst, trig, own, lock_action) \ + _PAD_CFG_STRUCT_LOCK(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_TRIG(trig) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE) | \ + PAD_IRQ_ROUTE(SWAPPED), \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own), PAD_LOCK(lock_action)) + #define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | \ @@ -370,10 +385,16 @@ #define PAD_CFG_GPI_INT(pad, pull, rst, trig) \ PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, DRIVER) +#define PAD_CFG_GPI_INT_SWAPPED(pad, pull, rst, trig) \ + PAD_CFG_GPI_TRIG_OWN_SWAPPED(pad, pull, rst, trig, DRIVER) + /* GPIO Interrupt with lock */ #define PAD_CFG_GPI_INT_LOCK(pad, pull, trig, lock_action) \ PAD_CFG_GPI_TRIG_OWN_LOCK(pad, pull, PWROK, trig, DRIVER, lock_action) +#define PAD_CFG_GPI_INT_LOCK_SWAPPED(pad, pull, trig, lock_action) \ + PAD_CFG_GPI_TRIG_OWN_LOCK_SWAPPED(pad, pull, PWROK, trig, DRIVER, lock_action) + /* * No Connect configuration for unconnected or unused pad. * Both TX and RX are disabled. RX disabling is done to avoid unnecessary |