diff options
| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2021-04-08 16:50:18 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-15 07:40:09 +0000 |
| commit | 31316cfccaa3991e443ce1ddcdd7e49486fa7101 (patch) | |
| tree | 1e9576252954a32845839fdcfd11eaa22f18d695 /src | |
| parent | 4ae7ee6e2b9f920b012ea9f60d5f5bbb32e62f3a (diff) | |
mb/google/brya: Add FPMCU power control
Enable CRFP power control in gpio table. RST needs to drive low
before PWR enable. Since reset signal is asserted in bootblock,
it results in FPMCU not working after a S3 resume. This is a known issue.
BUG=b:181377402
BRANCH=None
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I8a8fae80c3cc186e0a097ab2007abb656f382cbd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52185
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/gpio.c | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/gpio.c b/src/mainboard/google/brya/variants/baseboard/gpio.c index 4e8a303f14..b95ece1deb 100644 --- a/src/mainboard/google/brya/variants/baseboard/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/gpio.c @@ -120,7 +120,7 @@ static const struct pad_config gpio_table[] = { /* D0 : ISH_GP0 ==> PCH_FP_BOOT0 */ PAD_NC(GPP_D0, NONE), /* D1 : ISH_GP1 ==> FP_RST_ODL */ - PAD_CFG_GPO(GPP_D1, 0, DEEP), + PAD_CFG_GPO(GPP_D1, 1, DEEP), /* D2 : ISH_GP2 ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_D2, 1, DEEP), /* D3 : ISH_GP3 ==> WCAM_RST_L */ @@ -373,6 +373,17 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* + * D1 : ISH_GP1 ==> FP_RST_ODL + * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. + * To ensure proper power sequencing for the FPMCU device, reset signal is driven low + * early on in bootblock, followed by enabling of power. Reset signal is deasserted + * later on in ramstage. Since reset signal is asserted in bootblock, it results in + * FPMCU not working after a S3 resume. This is a known issue. + */ + PAD_CFG_GPO(GPP_D1, 0, DEEP), + /* D2 : ISH_GP2 ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_D2, 1, DEEP), /* E0 : SATAXPCIE0 ==> WWAN_PERST_L */ PAD_CFG_GPO(GPP_E0, 0, DEEP), /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ |