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authorMichał Żygowski <michal.zygowski@3mdeb.com>2019-11-24 16:32:05 +0100
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-11-30 06:02:12 +0000
commit2fa1cb15de4b03155277ae96c389753690a5e517 (patch)
tree42e0f65595047f130cb6d4a58657061845e420ef /src
parentc57494722319274710533b99692e29510b5cf5ba (diff)
AGESA,binaryPI: Remove __x86_64__ long mode in CAR
Change-Id: I83a8b2325b751feeb046ce74fabd37aeb27c28dc Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37350 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/drivers/amd/agesa/cache_as_ram.S45
1 files changed, 0 insertions, 45 deletions
diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S
index e429bba966..4f1cbea574 100644
--- a/src/drivers/amd/agesa/cache_as_ram.S
+++ b/src/drivers/amd/agesa/cache_as_ram.S
@@ -39,51 +39,6 @@ _cache_as_ram_setup:
/* Align the stack. */
and $0xFFFFFFF0, %esp
-#ifdef __x86_64__
- /* switch to 64 bit long mode */
- mov %esi, %ecx
- add $0, %ecx # core number
- xor %eax, %eax
- lea (0x1000+0x23)(%ecx), %edi
- mov %edi, (%ecx)
- mov %eax, 4(%ecx)
-
- lea 0x1000(%ecx), %edi
- movl $0x000000e3, 0x00(%edi)
- movl %eax, 0x04(%edi)
- movl $0x400000e3, 0x08(%edi)
- movl %eax, 0x0c(%edi)
- movl $0x800000e3, 0x10(%edi)
- movl %eax, 0x14(%edi)
- movl $0xc00000e3, 0x18(%edi)
- movl %eax, 0x1c(%edi)
-
- # load ROM based identity mapped page tables
- mov %ecx, %eax
- mov %eax, %cr3
-
- # enable PAE
- mov %cr4, %eax
- bts $5, %eax
- mov %eax, %cr4
-
- # enable long mode
- mov $0xC0000080, %ecx
- rdmsr
- bts $8, %eax
- wrmsr
-
- # enable paging
- mov %cr0, %eax
- bts $31, %eax
- mov %eax, %cr0
-
- # use call far to switch to 64-bit code segment
- ljmp $0x18, $1f
-1:
-
-#endif
-
/* Must maintain 16-byte stack alignment here. */
pushl $0x0
pushl $0x0