diff options
| author | Sean Rhodes <sean@starlabs.systems> | 2023-08-25 13:51:35 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-09-13 13:14:03 +0000 |
| commit | 2e10a6d6f3ec46bcaf75bd066319d51f001be764 (patch) | |
| tree | 760bedc018c39319d0e93418209bc956293710ac /src | |
| parent | 53048c2a541be7b483d4b916a04c32296e328f41 (diff) | |
soc/intel/{tigerlake,meteorlake}: Check ITBT FW version
The ensures that ITBT is ready to operate.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If60404a88208c632cd60e8aaa6ba70494eefbed2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77454
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/meteorlake/acpi/tcss.asl | 8 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/acpi/tcss_dma.asl | 3 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/acpi/tcss.asl | 8 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/acpi/tcss_dma.asl | 3 |
4 files changed, 20 insertions, 2 deletions
diff --git a/src/soc/intel/meteorlake/acpi/tcss.asl b/src/soc/intel/meteorlake/acpi/tcss.asl index e9ef6c390a..49ee86b745 100644 --- a/src/soc/intel/meteorlake/acpi/tcss.asl +++ b/src/soc/intel/meteorlake/acpi/tcss.asl @@ -455,6 +455,10 @@ Scope (\_SB.PCI0) /* DMA0 is not in D3Cold now. */ \_SB.PCI0.TDM0.D3CE() /* Enable DMA RTD3 */ + If (\_SB.PCI0.TDM0.IF30 != 1) { + Return + } + Printf("Push TBT RPs to D3Cold together") If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) { /* Put RP0 to D3 cold. */ @@ -513,6 +517,10 @@ Scope (\_SB.PCI0) /* DMA1 is not in D3Cold now */ \_SB.PCI0.TDM1.D3CE() /* Enable DMA RTD3. */ + If (\_SB.PCI0.TDM1.IF30 != 1) { + Return + } + Printf("Push TBT RPs to D3Cold together") If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) { /* Put RP2 to D3 cold. */ diff --git a/src/soc/intel/meteorlake/acpi/tcss_dma.asl b/src/soc/intel/meteorlake/acpi/tcss_dma.asl index 90824698bb..2586ecbbc7 100644 --- a/src/soc/intel/meteorlake/acpi/tcss_dma.asl +++ b/src/soc/intel/meteorlake/acpi/tcss_dma.asl @@ -11,7 +11,8 @@ Field (DPME, AnyAcc, NoLock, Preserve) , 6, PMES, 1, /* 15, PME_STATUS */ Offset(0xC8), /* 0xC8, TBT NVM FW Revision */ - , 31, + , 30, + IF30, 1, /* ITBT FW Version Bit30 */ INFR, 1, /* TBT NVM FW Ready */ Offset(0xEC), /* 0xEC, TBT TO PCIE Register */ TB2P, 32, /* TBT to PCIe */ diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index 5af78edb8a..2ae7049ee1 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -567,6 +567,10 @@ Scope (\_SB.PCI0) /* DMA0 is not in D3Cold now. */ \_SB.PCI0.TDM0.D3CE() /* Enable DMA RTD3 */ + If (\_SB.PCI0.TDM0.IF30 != 1) { + Return + } + Printf("Push TBT RPs to D3Cold together") If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) { /* Put RP0 to D3 cold. */ @@ -622,6 +626,10 @@ Scope (\_SB.PCI0) /* DMA1 is not in D3Cold now */ \_SB.PCI0.TDM1.D3CE() /* Enable DMA RTD3. */ + If (\_SB.PCI0.TDM1.IF30 != 1) { + Return + } + Printf("Push TBT RPs to D3Cold together") If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) { /* Put RP2 to D3 cold. */ diff --git a/src/soc/intel/tigerlake/acpi/tcss_dma.asl b/src/soc/intel/tigerlake/acpi/tcss_dma.asl index bbb0b6a1ad..dd6d1bb3ac 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_dma.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_dma.asl @@ -11,7 +11,8 @@ Field (DPME, AnyAcc, NoLock, Preserve) , 6, PMES, 1, /* 15, PME_STATUS */ Offset(0xC8), /* 0xC8, TBT NVM FW Revision */ - , 31, + , 30, + IF30, 1, /* ITBT FW Version Bit30 */ INFR, 1, /* TBT NVM FW Ready */ Offset(0xEC), /* 0xEC, TBT TO PCIE Register */ TB2P, 32, /* TBT to PCIe */ |