soc/intel/skylake: Add USB Port Over Current (OC) Pin programming

Program USB Overcurrent pins as per board schematics definition.

BUG=none
BRANCH=none
TEST=Build and boot kunimitsu from USB device.

Change-Id: I6aeb65953c753e09ad639469de7d866a54f42f11
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/17570
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

9 files changed, 104 insertions, 74 deletions

diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb
index 238a5a5109..34250d3450 100644
--- a/src/mainboard/google/chell/devicetree.cb
+++ b/src/mainboard/google/chell/devicetree.cb
@@ -151,17 +151,17 @@ chip soc/intel/skylake
 	# RP 1 uses SRCCLKREQ1#
 	register "PcieRpClkReqNumber[0]" = "1"
 
-	register "usb2_ports[0]" = "USB2_PORT_LONG"    # Type-C Port 1
-	register "usb2_ports[1]" = "USB2_PORT_LONG"    # Type-C Port 2
-	register "usb2_ports[2]" = "USB2_PORT_MID"     # Bluetooth
-	register "usb2_ports[4]" = "USB2_PORT_MID"     # Type-A Port
-	register "usb2_ports[6]" = "USB2_PORT_FLEX"    # Camera
-	register "usb2_ports[8]" = "USB2_PORT_MID"     # SD
+	register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)"	# Type-C Port 1
+	register "usb2_ports[1]" = "USB2_PORT_LONG(OC3)"	# Type-C Port 2
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"		# Type-A Port
+	register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)"	# Camera
+	register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)"	# SD
 
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT" # Type-C Port 1
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # Type-C Port 2
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port
-	register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # SD
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)"	# Type-C Port 1
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)"	# Type-C Port 2
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"	# Type-A Port
+	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# SD
 
 	register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"  # I2C4 is 1.8V
 
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index 37a5ff0712..f757d317ee 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -148,15 +148,15 @@ chip soc/intel/skylake
 	# RP 1 uses SRCCLKREQ1#
 	register "PcieRpClkReqNumber[0]" = "1"
 
-	register "usb2_ports[0]" = "USB2_PORT_LONG"	# Type-C Port 1
-	register "usb2_ports[1]" = "USB2_PORT_FLEX"	# Camera
-	register "usb2_ports[2]" = "USB2_PORT_MID"	# Bluetooth
-	register "usb2_ports[4]" = "USB2_PORT_LONG"	# Type-C Port 2
-	register "usb2_ports[6]" = "USB2_PORT_MID"	# Type-A Port
-	register "usb2_ports[8]" = "USB2_PORT_EMPTY"	# Empty
+	register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)"	# Type-C Port 1
+	register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)"	# Camera
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth
+	register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)"	# Type-C Port 2
+	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port
+	register "usb2_ports[8]" = "USB2_PORT_EMPTY"		# Empty
 
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT"	# Type-C Port 1
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT"	# Type-C Port 2
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# Type-C Port 1
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)"	# Type-C Port 2
 	register "usb3_ports[2]" = "USB3_PORT_EMPTY"	# Empty
 	register "usb3_ports[3]" = "USB3_PORT_EMPTY"	# Empty
 
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index d17ef6cc0c..d0584ea7c9 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -151,17 +151,17 @@ chip soc/intel/skylake
 	# RP 1 uses SRCCLKREQ1#
 	register "PcieRpClkReqNumber[0]" = "1"
 
-	register "usb2_ports[0]" = "USB2_PORT_TYPE_C"  # Type-C Port (board)
-	register "usb2_ports[1]" = "USB2_PORT_MAX"     # Type-C Port (flex)
-	register "usb2_ports[2]" = "USB2_PORT_MID"     # Bluetooth
-	register "usb2_ports[4]" = "USB2_PORT_MID"     # Type-A Port 1
-	register "usb2_ports[6]" = "USB2_PORT_FLEX"    # Camera
-	register "usb2_ports[8]" = "USB2_PORT_MID"     # Type-A Port 2
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)"   # Type-C Port (board)
+	register "usb2_ports[1]" = "USB2_PORT_MAX(OC3)"      # Type-C Port (flex)
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"  # Bluetooth
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"      # Type-A Port 1
+	register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
+	register "usb2_ports[8]" = "USB2_PORT_MID(OC1)"      # Type-A Port 2
 
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT" # Type-C Port (board)
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # Type-C Port (flex)
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port 1
-	register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port 2
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port (board)
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-C Port (flex)
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 1
+	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 2
 
 	register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"  # I2C4 is 1.8V
 
diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb
index dab95de41a..4291e5f851 100644
--- a/src/mainboard/google/lars/devicetree.cb
+++ b/src/mainboard/google/lars/devicetree.cb
@@ -148,17 +148,17 @@ chip soc/intel/skylake
 	# RP 1 uses SRCCLKREQ1#
 	register "PcieRpClkReqNumber[0]" = "1"
 
-	register "usb2_ports[0]" = "USB2_PORT_TYPE_C"  # Type-C Port 1
-	register "usb2_ports[1]" = "USB2_PORT_FLEX"    # Camera
-	register "usb2_ports[2]" = "USB2_PORT_MID"     # Bluetooth
-	register "usb2_ports[4]" = "USB2_PORT_MID"     # Type-A Port (card)
-	register "usb2_ports[5]" = "USB2_PORT_MID"     # SD
-	register "usb2_ports[8]" = "USB2_PORT_LONG"    # Type-A Port (board)
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"	# Type-C Port 1
+	register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)"	# Camera
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC2)"		# Type-A Port (card)
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# SD
+	register "usb2_ports[8]" = "USB2_PORT_LONG(OC3)"	# Type-A Port (board)
 
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT" # Type-C Port 1
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # SD
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port (card)
-	register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port (board)
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# Type-C Port 1
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)"	# Type-A Port (card)
+	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)"	# Type-A Port (board)
 
 	register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"  # I2C4 is 1.8V
 
diff --git a/src/mainboard/intel/kblrvp/devicetree.cb b/src/mainboard/intel/kblrvp/devicetree.cb
index 11d5062664..c2dde4f526 100644
--- a/src/mainboard/intel/kblrvp/devicetree.cb
+++ b/src/mainboard/intel/kblrvp/devicetree.cb
@@ -168,23 +168,23 @@ chip soc/intel/skylake
 	register "PcieRpClkReqNumber[9]" = "4"
 
 	# USB 2.0 Enable all ports
-	register "usb2_ports[0]" = "USB2_PORT_MAX"	# TYPE-A Port
-	register "usb2_ports[1]" = "USB2_PORT_MAX"	# TYPE-A Port
-	register "usb2_ports[2]" = "USB2_PORT_MAX"	# Bluetooth
-	register "usb2_ports[4]" = "USB2_PORT_MAX"	# Type-A Port
-	register "usb2_ports[5]" = "USB2_PORT_MAX"	# TYPE-A Port
-	register "usb2_ports[6]" = "USB2_PORT_MAX"	# TYPE-A Port
-	register "usb2_ports[7]" = "USB2_PORT_MAX"	# TYPE-A Port
-	register "usb2_ports[8]" = "USB2_PORT_MAX"	# TYPE-A Port
-	register "usb2_ports[9]" = "USB2_PORT_MAX"	# TYPE-A Port
-	register "usb2_ports[10]" = "USB2_PORT_MAX"	# TYPE-A Port
-	register "usb2_ports[11]" = "USB2_PORT_MAX"	# TYPE-A Port
+	register "usb2_ports[0]" = "USB2_PORT_MAX(OC0)"		# TYPE-A Port
+	register "usb2_ports[1]" = "USB2_PORT_MAX(OC2)"		# TYPE-A Port
+	register "usb2_ports[2]" = "USB2_PORT_MAX(OC_SKIP)"	# Bluetooth
+	register "usb2_ports[4]" = "USB2_PORT_MAX(OC_SKIP)"	# Type-A Port
+	register "usb2_ports[5]" = "USB2_PORT_MAX(OC2)"		# TYPE-A Port
+	register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)"	# TYPE-A Port
+	register "usb2_ports[7]" = "USB2_PORT_MAX(OC_SKIP)"	# TYPE-A Port
+	register "usb2_ports[8]" = "USB2_PORT_MAX(OC_SKIP)"	# TYPE-A Port
+	register "usb2_ports[9]" = "USB2_PORT_MAX(OC1)"		# TYPE-A Port
+	register "usb2_ports[10]" = "USB2_PORT_MAX(OC_SKIP)"	# TYPE-A Port
+	register "usb2_ports[11]" = "USB2_PORT_MAX(OC_SKIP)"	# TYPE-A Port
 
 	# USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT"	# TYPE-A Port
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT"	# TYPE-A Port
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT"	# TYPE-A Port
-	register "usb3_ports[3]" = "USB3_PORT_DEFAULT"	# TYPE-A Port
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# TYPE-A Port
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# TYPE-A Port
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# TYPE-A Port
+	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)"	# TYPE-A Port
 	register "usb3_ports[4]" = "USB3_PORT_EMPTY"	# Disabled
 	register "usb3_ports[5]" = "USB3_PORT_EMPTY"	# Disabled
 
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index 3cdaa0670c..6a6c2ce0e4 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -152,17 +152,17 @@ chip soc/intel/skylake
 	register "PcieRpClkReqNumber[0]" = "1"
 	register "PcieRpClkReqNumber[4]" = "2"
 
-	register "usb2_ports[0]" = "USB2_PORT_TYPE_C"  # Type-C Port 1
-	register "usb2_ports[1]" = "USB2_PORT_TYPE_C"  # Type-C Port 2
-	register "usb2_ports[2]" = "USB2_PORT_MID"     # Bluetooth
-	register "usb2_ports[4]" = "USB2_PORT_MID"     # Type-A Port (card)
-	register "usb2_ports[6]" = "USB2_PORT_FLEX"    # Camera
-	register "usb2_ports[8]" = "USB2_PORT_LONG"    # Type-A Port (board)
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"	# Type-C Port 1
+	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)"	# Type-C Port 2
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC2)"		# Type-A Port (card)
+	register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)"	# Camera
+	register "usb2_ports[8]" = "USB2_PORT_LONG(OC3)"	# Type-A Port (board)
 
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT" # Type-C Port 1
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # Type-C Port 2
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port (card)
-	register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port (board)
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port (card)
+	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port (board)
 
 	register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"  # I2C4 is 1.8V
 
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 2703224883..c64a8df589 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -90,6 +90,8 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
 	for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
 		params->PortUsb20Enable[i] =
 			config->usb2_ports[i].enable;
+		params->Usb2OverCurrentPin[i] =
+			config->usb2_ports[i].ocpin;
 		params->Usb2AfePetxiset[i] =
 			config->usb2_ports[i].pre_emp_bias;
 		params->Usb2AfeTxiset[i] =
@@ -102,6 +104,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
 
 	for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
 		params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
+		params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
 		if (config->usb3_ports[i].tx_de_emp) {
 			params->Usb3HsioTxDeEmphEnable[i] = 1;
 			params->Usb3HsioTxDeEmph[i] =
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 582cdbf31d..f90f6bc096 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -121,6 +121,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
 		params->PortUsb20Enable[i] =
 				config->usb2_ports[i].enable;
+		params->Usb2OverCurrentPin[i] =
+				config->usb2_ports[i].ocpin;
 		params->Usb2AfePetxiset[i] =
 				config->usb2_ports[i].pre_emp_bias;
 		params->Usb2AfeTxiset[i] =
@@ -133,6 +135,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 
 	for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
 		params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
+		params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
 		if (config->usb3_ports[i].tx_de_emp) {
 			params->Usb3HsioTxDeEmphEnable[i] = 1;
 			params->Usb3HsioTxDeEmph[i] =
diff --git a/src/soc/intel/skylake/include/soc/usb.h b/src/soc/intel/skylake/include/soc/usb.h
index a18e79ce66..77a94a8765 100644
--- a/src/soc/intel/skylake/include/soc/usb.h
+++ b/src/soc/intel/skylake/include/soc/usb.h
@@ -38,14 +38,25 @@
 
 struct usb2_port_config {
 	uint8_t enable;
+	uint8_t ocpin;
 	uint8_t tx_bias;
 	uint8_t tx_emp_enable;
 	uint8_t pre_emp_bias;
 	uint8_t pre_emp_bit;
 };
 
+/* USB Overcurrent pins definition */
+enum {
+	OC0,
+	OC1,
+	OC2,
+	OC3,
+	OC_SKIP = 8, /* Skip OC programming */
+};
+
 #define USB2_PORT_EMPTY { \
 	.enable        = 0, \
+	.ocpin         = OC_SKIP, \
 	.tx_bias       = USB2_BIAS_0MV, \
 	.tx_emp_enable = USB2_EMP_OFF, \
 	.pre_emp_bias  = USB2_BIAS_0MV, \
@@ -62,8 +73,9 @@ struct usb2_port_config {
  */
 
 /* Max TX and Pre-emp settings */
-#define USB2_PORT_MAX { \
+#define USB2_PORT_MAX(pin) { \
 	.enable        = 1, \
+	.ocpin         = pin, \
 	.tx_bias       = USB2_BIAS_56MV, \
 	.tx_emp_enable = USB2_PRE_EMP_ON, \
 	.pre_emp_bias  = USB2_BIAS_56MV, \
@@ -71,8 +83,9 @@ struct usb2_port_config {
 }
 
 /* 11.5"-12" */
-#define USB2_PORT_LONG { \
+#define USB2_PORT_LONG(pin) { \
 	.enable        = 1, \
+	.ocpin         = pin, \
 	.tx_bias       = USB2_BIAS_39MV, \
 	.tx_emp_enable = USB2_PRE_EMP_ON, \
 	.pre_emp_bias  = USB2_BIAS_56MV, \
@@ -80,8 +93,9 @@ struct usb2_port_config {
 }
 
 /* 6"-11.5" */
-#define USB2_PORT_MID { \
+#define USB2_PORT_MID(pin) { \
 	.enable        = 1, \
+	.ocpin         = pin, \
 	.tx_bias       = USB2_BIAS_0MV, \
 	.tx_emp_enable = USB2_PRE_EMP_ON, \
 	.pre_emp_bias  = USB2_BIAS_56MV, \
@@ -89,8 +103,9 @@ struct usb2_port_config {
 }
 
 /* 3"-6" */
-#define USB2_PORT_SHORT { \
+#define USB2_PORT_SHORT(pin) { \
 	.enable        = 1, \
+	.ocpin         = pin, \
 	.tx_bias       = USB2_BIAS_39MV, \
 	.tx_emp_enable = USB2_PRE_EMP_ON | USB2_DE_EMP_ON, \
 	.pre_emp_bias  = USB2_BIAS_39MV, \
@@ -98,8 +113,9 @@ struct usb2_port_config {
 }
 
 /* Type-C Port, no BC1.2 charge detect module / MUX */
-#define USB2_PORT_TYPE_C { \
+#define USB2_PORT_TYPE_C(pin) { \
 	.enable        = 1, \
+	.ocpin         = pin, \
 	.tx_bias       = USB2_BIAS_0MV, \
 	.tx_emp_enable = USB2_PRE_EMP_ON, \
 	.pre_emp_bias  = USB2_BIAS_56MV, \
@@ -107,8 +123,9 @@ struct usb2_port_config {
 }
 
 /* Port with BC1.2 charge detect module / MUX */
-#define USB2_PORT_BC12_MUX { \
+#define USB2_PORT_BC12_MUX(pin) { \
 	.enable        = 1, \
+	.ocpin         = pin, \
 	.tx_bias       = USB2_BIAS_0MV, \
 	.tx_emp_enable = USB2_PRE_EMP_ON, \
 	.pre_emp_bias  = USB2_BIAS_56MV, \
@@ -116,8 +133,9 @@ struct usb2_port_config {
 }
 
 /* Internal Flex Cable, 3"-5" + cable + 2" card */
-#define USB2_PORT_FLEX { \
+#define USB2_PORT_FLEX(pin) { \
 	.enable        = 1, \
+	.ocpin         = pin, \
 	.tx_bias       = USB2_BIAS_0MV, \
 	.tx_emp_enable = USB2_PRE_EMP_ON, \
 	.pre_emp_bias  = USB2_BIAS_56MV, \
@@ -125,8 +143,9 @@ struct usb2_port_config {
 }
 
 /* Docking, 3"-9" */
-#define USB2_PORT_DOCKING_LONG { \
+#define USB2_PORT_DOCKING_LONG(pin) { \
 	.enable        = 1, \
+	.ocpin         = pin, \
 	.tx_bias       = USB2_BIAS_0MV, \
 	.tx_emp_enable = USB2_PRE_EMP_ON, \
 	.pre_emp_bias  = USB2_BIAS_56MV, \
@@ -134,8 +153,9 @@ struct usb2_port_config {
 }
 
 /* Docking, 3"-6" */
-#define USB2_PORT_DOCKING_SHORT { \
+#define USB2_PORT_DOCKING_SHORT(pin) { \
 	.enable        = 1, \
+	.ocpin         = pin, \
 	.tx_bias       = USB2_BIAS_17MV, \
 	.tx_emp_enable = USB2_PRE_EMP_ON | USB2_DE_EMP_ON, \
 	.pre_emp_bias  = USB2_BIAS_45MV, \
@@ -143,8 +163,9 @@ struct usb2_port_config {
 }
 
 /* 2:1 Detachable, 2"-4" on tablet + 2"-4" on base */
-#define USB2_PORT_DETACHABLE_TABLET { \
+#define USB2_PORT_DETACHABLE_TABLET(pin) { \
 	.enable        = 1, \
+	.ocpin         = pin, \
 	.tx_bias       = USB2_BIAS_56MV, \
 	.tx_emp_enable = USB2_PRE_EMP_ON, \
 	.pre_emp_bias  = USB2_BIAS_56MV, \
@@ -153,18 +174,21 @@ struct usb2_port_config {
 
 struct usb3_port_config {
 	uint8_t enable;
+	uint8_t ocpin;
 	uint8_t tx_de_emp;
 	uint8_t tx_downscale_amp;
 };
 
 #define USB3_PORT_EMPTY { \
 	.enable           = 0, \
+	.ocpin            = OC_SKIP, \
 	.tx_de_emp        = 0x00, \
 	.tx_downscale_amp = 0x00, \
 }
 
-#define USB3_PORT_DEFAULT { \
+#define USB3_PORT_DEFAULT(pin) { \
 	.enable           = 1, \
+	.ocpin            = pin, \
 	.tx_de_emp        = 0x29, \
 	.tx_downscale_amp = 0x00, \
 }