diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-07-12 11:09:55 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-07-14 08:16:22 +0000 |
| commit | 2837cf81820308e50a06fce60d49cca9eb77ff25 (patch) | |
| tree | 2f9dd4ae2cf8186cee1dbbb3dcacc0058b5adbea /src | |
| parent | 6386cc99736dd7501faeb332d9c231ec685bf898 (diff) | |
soc/intel/skylake: Rename `Rmt` devicetree setting
Rename `Rmt` to `RMT` for consistency with the UPD name.
Change-Id: I905b9b65fa6c5711c6e726cc09d3cad5ba3640a1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/skylake/romstage/fsp_params.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index d30547ec26..59f75bf353 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -94,7 +94,7 @@ struct soc_intel_skylake_config { } SaGv; /* Enable/disable Rank Margin Tool */ - u8 Rmt; + u8 RMT; /* Disable Command TriState */ u8 CmdTriStateDis; diff --git a/src/soc/intel/skylake/romstage/fsp_params.c b/src/soc/intel/skylake/romstage/fsp_params.c index f05532c416..21526e4848 100644 --- a/src/soc/intel/skylake/romstage/fsp_params.c +++ b/src/soc/intel/skylake/romstage/fsp_params.c @@ -83,7 +83,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->ProbelessTrace = 0; m_cfg->SaGv = config->SaGv; m_cfg->UserBd = BOARD_TYPE_ULT_ULX; - m_cfg->RMT = config->Rmt; + m_cfg->RMT = config->RMT; m_cfg->CmdTriStateDis = config->CmdTriStateDis; m_cfg->DdrFreqLimit = 0; m_cfg->VmxEnable = CONFIG(ENABLE_VMX); |