Brain: Apply differences between Jerry and Brain

This applies the differences between Jerry and Brain:
- No EC
- No SD card
- Minor changes to GPIOs (no lid, power button active low)
- No variations between board IDs (yet)
- No backlight/display attached, but we do have some HDMI
  and VOP configuration (need to double check that it's right).

BUG=none
BRANCH=none
TEST=built and booted on Brain (requires follow-up CL
to get into depthcharge)

Change-Id: Idbbc19856e05a145637c28d87c3e19855d13f03b
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 67151129c28ca7dd83464e5a5c183d006299293c
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I3c761d3d4d186a6208a772c05193bdcbd4a5c105
Original-Reviewed-on: https://chromium-review.googlesource.com/235921
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9638
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>

6 files changed, 19 insertions, 99 deletions

diff --git a/src/mainboard/google/veyron_brain/Kconfig b/src/mainboard/google/veyron_brain/Kconfig
index 1ec1d56ad4..b4d1a0773a 100644
--- a/src/mainboard/google/veyron_brain/Kconfig
+++ b/src/mainboard/google/veyron_brain/Kconfig
@@ -24,16 +24,13 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select BOARD_ID_SUPPORT
 	select BOARD_ROMSIZE_KB_4096
 	select COMMON_CBFS_SPI_WRAPPER
-	select EC_GOOGLE_CHROMEEC
-	select EC_GOOGLE_CHROMEEC_SPI
-	select EC_SOFTWARE_SYNC
-	select RAM_CODE_SUPPORT
-	select SOC_ROCKCHIP_RK3288
+	select HAVE_HARD_RESET
 	select MAINBOARD_DO_NATIVE_VGA_INIT
 	select MAINBOARD_HAS_CHROMEOS
 	select MAINBOARD_HAS_BOOTBLOCK_INIT
-	select HAVE_HARD_RESET
+	select RAM_CODE_SUPPORT
 	select RETURN_FROM_VERSTAGE
+	select SOC_ROCKCHIP_RK3288
 	select SPI_FLASH
 	select SPI_FLASH_GIGADEVICE
 	select SPI_FLASH_WINBOND
@@ -45,20 +42,12 @@ config MAINBOARD_DIR
 
 config MAINBOARD_PART_NUMBER
 	string
-	default "Veyron_Jerry"
+	default "Veyron_Brain"
 
 config MAINBOARD_VENDOR
 	string
 	default "Google"
 
-config EC_GOOGLE_CHROMEEC_SPI_BUS
-	hex
-	default 0
-
-config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
-	int
-	default 100
-
 config VBOOT_RAMSTAGE_INDEX
 	hex
 	default 0x3
diff --git a/src/mainboard/google/veyron_brain/board.h b/src/mainboard/google/veyron_brain/board.h
index 2b1643d4bd..c9583cf30c 100644
--- a/src/mainboard/google/veyron_brain/board.h
+++ b/src/mainboard/google/veyron_brain/board.h
@@ -17,8 +17,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#ifndef __MAINBOARD_GOOGLE_VEYRON_JERRY_BOARD_H
-#define __MAINBOARD_GOOGLE_VEYRON_JERRY_BOARD_H
+#ifndef __MAINBOARD_GOOGLE_VEYRON_BRAIN_BOARD_H
+#define __MAINBOARD_GOOGLE_VEYRON_BRAIN_BOARD_H
 
 #include <boardid.h>
 #include <gpio.h>
@@ -29,4 +29,4 @@
 
 /* TODO: move setup_chromeos_gpios() here once bootblock code is in mainboard */
 
-#endif	/* __MAINBOARD_GOOGLE_VEYRON_JERRY_BOARD_H */
+#endif	/* __MAINBOARD_GOOGLE_VEYRON_BRAIN_BOARD_H */
diff --git a/src/mainboard/google/veyron_brain/bootblock.c b/src/mainboard/google/veyron_brain/bootblock.c
index 5571d456f8..af353f89fa 100644
--- a/src/mainboard/google/veyron_brain/bootblock.c
+++ b/src/mainboard/google/veyron_brain/bootblock.c
@@ -45,6 +45,8 @@ void bootblock_mainboard_early_init()
 
 void bootblock_mainboard_init(void)
 {
+	gpio_output(GPIO(7, A, 0), 1);	/* Power LED */
+
 	/* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
 	setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
 	setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
@@ -71,9 +73,5 @@ void bootblock_mainboard_init(void)
 	writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx);
 	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz);
 
-	/* spi0 for chrome ec */
-	writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0);
-	rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9*MHz);
-
 	setup_chromeos_gpios();
 }
diff --git a/src/mainboard/google/veyron_brain/chromeos.c b/src/mainboard/google/veyron_brain/chromeos.c
index 069b28b91a..14f078c81b 100644
--- a/src/mainboard/google/veyron_brain/chromeos.c
+++ b/src/mainboard/google/veyron_brain/chromeos.c
@@ -1,4 +1,4 @@
-/*
+/*
  * This file is part of the coreboot project.
  *
  * Copyright 2014 Rockchip Inc.
@@ -19,8 +19,6 @@
 
 #include <boot/coreboot_tables.h>
 #include <console/console.h>
-#include <ec/google/chromeec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
 #include <gpio.h>
 #include <string.h>
 #include <vendorcode/google/chromeos/chromeos.h>
@@ -28,15 +26,12 @@
 #include "board.h"
 
 #define GPIO_WP		GPIO(7, A, 6)
-#define GPIO_LID	GPIO(0, A, 6)
 #define GPIO_POWER	GPIO(0, A, 5)
 #define GPIO_RECOVERY	GPIO(0, B, 1)
-#define GPIO_ECINRW	GPIO(0, A, 7)
 
 void setup_chromeos_gpios(void)
 {
 	gpio_input(GPIO_WP);
-	gpio_input_pullup(GPIO_LID);
 	gpio_input(GPIO_POWER);
 	gpio_input_pullup(GPIO_RECOVERY);
 }
@@ -55,20 +50,13 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 
 	/* Recovery: active low */
 	gpios->gpios[count].port = GPIO_RECOVERY.raw;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = get_recovery_mode_switch();
+	gpios->gpios[count].polarity = ACTIVE_LOW;
+	gpios->gpios[count].value = gpio_get(GPIO_RECOVERY);
 	strncpy((char *)gpios->gpios[count].name, "recovery",
 		GPIO_MAX_NAME_LENGTH);
 	count++;
 
-	/* Lid: active high */
-	gpios->gpios[count].port = GPIO_LID.raw;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH);
-	count++;
-
-	/* Power:GPIO active high */
+	/* Power Button: GPIO active low */
 	gpios->gpios[count].port = GPIO_POWER.raw;
 	gpios->gpios[count].polarity = ACTIVE_LOW;
 	gpios->gpios[count].value = -1;
@@ -84,14 +72,6 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 		GPIO_MAX_NAME_LENGTH);
 	count++;
 
-	/* EC in RW: GPIO active high */
-	gpios->gpios[count].port = GPIO_ECINRW.raw;
-	gpios->gpios[count].polarity = ACTIVE_HIGH;
-	gpios->gpios[count].value = -1;
-	strncpy((char *)gpios->gpios[count].name, "EC in RW",
-		GPIO_MAX_NAME_LENGTH);
-	count++;
-
 	/* Reset: GPIO active high (output) */
 	gpios->gpios[count].port = GPIO_RESET.raw;
 	gpios->gpios[count].polarity = ACTIVE_HIGH;
@@ -113,15 +93,7 @@ int get_developer_mode_switch(void)
 
 int get_recovery_mode_switch(void)
 {
-	uint32_t ec_events;
-
-	/* The GPIO is active low. */
-	if (!gpio_get(GPIO_RECOVERY))
-		return 1;
-
-	ec_events = google_chromeec_get_events_b();
-	return !!(ec_events &
-		  EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
+	return !gpio_get(GPIO_RECOVERY);
 }
 
 int get_write_protect_state(void)
diff --git a/src/mainboard/google/veyron_brain/devicetree.cb b/src/mainboard/google/veyron_brain/devicetree.cb
index 4a2533dcd8..59a18267aa 100644
--- a/src/mainboard/google/veyron_brain/devicetree.cb
+++ b/src/mainboard/google/veyron_brain/devicetree.cb
@@ -22,5 +22,4 @@ chip soc/rockchip/rk3288
 	device cpu_cluster 0 on end
 	register "vop_id" = "1"
 	register "framebuffer_bits_per_pixel" = "16"
-	register "lcd_power_on_udelay" = "200000"
 end
diff --git a/src/mainboard/google/veyron_brain/mainboard.c b/src/mainboard/google/veyron_brain/mainboard.c
index d9952605dc..d8719c06b4 100644
--- a/src/mainboard/google/veyron_brain/mainboard.c
+++ b/src/mainboard/google/veyron_brain/mainboard.c
@@ -46,20 +46,6 @@ static void configure_usb(void)
 	gpio_output(GPIO(7, C, 5), 1);			/* 5V_DRV */
 }
 
-static void configure_sdmmc(void)
-{
-	writel(IOMUX_SDMMC0, &rk3288_grf->iomux_sdmmc0);
-
-	/* use sdmmc0 io, disable JTAG function */
-	writel(RK_CLRBITS(1 << 12), &rk3288_grf->soc_con0);
-
-	/* Note: these power rail definitions are copied in romstage.c */
-	rk808_configure_ldo(PMIC_BUS, 4, 3300); /* VCCIO_SD */
-	rk808_configure_ldo(PMIC_BUS, 5, 3300); /* VCC33_SD */
-
-	gpio_input(GPIO(7, A, 5));		/* SD_DET */
-}
-
 static void configure_emmc(void)
 {
 	writel(IOMUX_EMMCDATA, &rk3288_grf->iomux_emmcdata);
@@ -91,19 +77,9 @@ static void configure_vop(void)
 	/* lcdc(vop) iodomain select 1.8V */
 	writel(RK_SETBITS(1 << 0), &rk3288_grf->io_vsel);
 
-	switch (board_id()) {
-	case 2:
-		rk808_configure_switch(PMIC_BUS, 2, 1);	/* VCC18_LCD */
-		rk808_configure_ldo(PMIC_BUS, 7, 2500);	/* VCC10_LCD_PWREN_H */
-		rk808_configure_switch(PMIC_BUS, 1, 1);	/* VCC33_LCD */
-		break;
-	default:
-		gpio_output(GPIO(2, B, 5), 1);	/* AVDD_1V8_DISP_EN */
-		rk808_configure_ldo(PMIC_BUS, 7, 2500);	/* VCC10_LCD_PWREN_H */
-		gpio_output(GPIO(7, B, 6), 1);	/* LCD_EN */
-		rk808_configure_switch(PMIC_BUS, 1, 1);	/* VCC33_LCD */
-		break;
-	}
+	rk808_configure_switch(PMIC_BUS, 2, 1);	/* VCC18_LCD (HDMI_AVDD_1V8) */
+	rk808_configure_ldo(PMIC_BUS, 7, 1000);	/* VDD10_LCD (HDMI_AVDD_1V0) */
+	rk808_configure_switch(PMIC_BUS, 1, 1);	/* VCC33_LCD */
 }
 
 static void mainboard_init(device_t dev)
@@ -111,7 +87,6 @@ static void mainboard_init(device_t dev)
 	gpio_output(GPIO_RESET, 0);
 
 	configure_usb();
-	configure_sdmmc();
 	configure_emmc();
 	configure_codec();
 	configure_vop();
@@ -137,21 +112,8 @@ void lb_board(struct lb_header *header)
 	dma->range_size = _dma_coherent_size;
 }
 
+/* called from rk3288 display.c, but there is no backlight for this platform */
 void mainboard_power_on_backlight(void)
 {
-	switch (board_id()) {
-	case 2:
-		gpio_output(GPIO(7, A, 0), 0);	/* BL_EN */
-		gpio_output(GPIO(7, A, 2), 1);	/* LCD_BL */
-		mdelay(10);
-		gpio_output(GPIO(7, A, 0), 1);	/* BL_EN */
-		break;
-	default:
-		gpio_output(GPIO(2, B, 4), 1);	/* BL_PWR_EN */
-		mdelay(10);
-		gpio_output(GPIO(7, A, 2), 1);	/* LCD_BL */
-		mdelay(10);
-		gpio_output(GPIO(7, A, 0), 1);	/* BL_EN */
-		break;
-	}
+	return;
 }