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authorTim Wawrzynczak <twawrzynczak@chromium.org>2021-06-17 12:44:06 -0600
committerTim Wawrzynczak <twawrzynczak@chromium.org>2021-06-30 22:20:06 +0000
commit25d24523886f7f2feb5b017ea24f8900c4c603d4 (patch)
tree0027328d0db83b4fdbd4cff58f361ff74d597231 /src
parentc0e82e705d9a4747b1ccf7e6863c91c1e01bada7 (diff)
soc/intel/tigerlake: Send End-of-Post message to CSE
This is done to ensure the CSE will not execute any pre-boot commands after it receives this command. Verified EOP and error recovery sequence from Intel doc#612229 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iae6b2eac11c065749e57c5337d81ed20044fc903 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/tigerlake/Kconfig1
-rw-r--r--src/soc/intel/tigerlake/fsp_params.c12
2 files changed, 7 insertions, 6 deletions
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 7bc2ba2b0c..e41d7a7dfd 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -72,6 +72,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_RESET
select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
+ select SOC_INTEL_CSE_SET_EOP
select SSE2
select SUPPORT_CPU_UCODE_IN_CBFS
select TSC_MONOTONIC_TIMER
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 63332fea12..e7fe51a2cd 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -43,10 +43,10 @@
* 2 - Send in DXE (Not applicable for FSP in API mode)
*/
enum {
- EOP_DISABLE,
- EOP_PEI,
- EOP_DXE,
-} EndOfPost;
+ EOP_DISABLE = 0,
+ EOP_PEI = 1,
+ EOP_DXE = 2,
+};
/*
* Chip config parameter PcieRpL1Substates uses (UPD value + 1)
@@ -403,8 +403,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->RtcMemoryLock = 1;
}
- /* Enable End of Post in PEI phase */
- params->EndOfPostMessage = EOP_PEI;
+ /* coreboot will send EOP before loading payload */
+ params->EndOfPostMessage = EOP_DISABLE;
/* USB */
for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {