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authorKenneth Chan <kenneth.chan@quanta.corp-partner.google.com>2024-05-30 15:53:57 +0800
committerFelix Held <felix-coreboot@felixheld.de>2024-05-31 16:18:12 +0000
commit1f97d801ce5a0908bbe6adaf4c4b7f656d40a198 (patch)
tree75a5dc983778623541c02ce0825e2897e973bd19 /src
parenteaaa630e7d2c0bf742a877801070c8d81ced79dc (diff)
mb/google/brya/var/nova: Update USB ports setting
Update used USB port[2][3](type-a) setting for nova. BUG=b:328711879 TEST=emerge-constitution coreboot chromeos-bootimage Change-Id: I63cf97b23627feac05743f2a6e514a33fcaf7dff Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82703 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/brya/variants/nova/overridetree.cb2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/nova/overridetree.cb b/src/mainboard/google/brya/variants/nova/overridetree.cb
index bd0bc863cd..950bb9beab 100644
--- a/src/mainboard/google/brya/variants/nova/overridetree.cb
+++ b/src/mainboard/google/brya/variants/nova/overridetree.cb
@@ -6,6 +6,8 @@ chip soc/intel/alderlake
register "sagv" = "SaGv_Enabled"
register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port 1
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A3
+ register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A2
register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2 Port 4
register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Disable USB2 Port 5
register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2 Port 6