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authorFelix Held <felix-coreboot@felixheld.de>2024-01-12 19:52:56 +0100
committerFelix Held <felix-coreboot@felixheld.de>2024-01-15 21:15:05 +0000
commit1c626b01c23cb3bf573cbc69ed0dba4ca8c65a97 (patch)
tree52f35ce7b428405c1c20ecb99c495b453e6c066a /src
parent2c9688c65a3fad9542a170129ea7c2a6295b42ee (diff)
soc/cavium/cn81xx/Kconfig: specify ECAM_MMCONF_BUS_NUMBER
The Cavium CN81xx SoC selects ECAM_MMCONF_SUPPORT, but doesn't set a value for ECAM_MMCONF_BUS_NUMBER which results in it defaulting to 0 which is wrong. Both the Cavium CN8100 SFF EVB and the OpenCellular Elgon (GBCv2) mainboard specify 32 PCI buses in their Linux devicetree files, so set the SoC's ECAM_MMCONF_BUS_NUMBER Kconfig option to 32 to match this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Change-Id: Ic98381e2cc597cf23af249c71911545692e40f64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79931 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/cavium/cn81xx/Kconfig3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfig
index 368581f8f1..5593685a37 100644
--- a/src/soc/cavium/cn81xx/Kconfig
+++ b/src/soc/cavium/cn81xx/Kconfig
@@ -39,4 +39,7 @@ config STACK_SIZE
config ECAM_MMCONF_BASE_ADDRESS
default 0x848000000000
+config ECAM_MMCONF_BUS_NUMBER
+ default 32
+
endif