superio/ite/it8720f: add new IT8720F Super I/O

This device is extremely similar to the IT8718F, so support is based on
existing support for the IT8718F. The CIR device is only detected by
Linux/Windows from the ACPI tables, so ACPI support is extended from the
IT8783E/F (for ACPI). This Super I/O is used on the Foxconn G41S-K.

Tested, working:
* Serial port 1
* Environment controller
  - Temperature monitoring
  - Voltage monitoring
  - Fan control (automatic and manual)
* PS/2 keyboard and mouse

Appears, OS driver loads, but otherwise untested:
* Serial port 2
* Consumer IR

Untested:
* Floppy controller
* Parallel port
* GPIO

Change-Id: Ib9a6fe91a772d78f4d122a6c516feff8658ada0a
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-on: https://review.coreboot.org/20026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

7 files changed, 414 insertions, 0 deletions

diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc
index fa3775a58a..f27a3335f2 100644
--- a/src/superio/ite/Makefile.inc
+++ b/src/superio/ite/Makefile.inc
@@ -23,6 +23,7 @@ subdirs-y += it8671f
 subdirs-y += it8712f
 subdirs-y += it8716f
 subdirs-y += it8718f
+subdirs-y += it8720f
 subdirs-y += it8721f
 subdirs-y += it8728f
 subdirs-y += it8772f
diff --git a/src/superio/ite/it8720f/Kconfig b/src/superio/ite/it8720f/Kconfig
new file mode 100644
index 0000000000..da42e0b87d
--- /dev/null
+++ b/src/superio/ite/it8720f/Kconfig
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Ronald G. Minnich
+## Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
+## Copyright (C) 2017 Samuel Holland <samuel@sholland.org>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+config SUPERIO_ITE_IT8720F
+	bool
+	select SUPERIO_ITE_COMMON_ROMSTAGE
+	select SUPERIO_ITE_ENV_CTRL
+	select SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG
+	select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2
diff --git a/src/superio/ite/it8720f/Makefile.inc b/src/superio/ite/it8720f/Makefile.inc
new file mode 100644
index 0000000000..87f89dc190
--- /dev/null
+++ b/src/superio/ite/it8720f/Makefile.inc
@@ -0,0 +1,18 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
+## Copyright (C) 2017 Samuel Holland <samuel@sholland.org>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+ramstage-$(CONFIG_SUPERIO_ITE_IT8720F) += superio.c
diff --git a/src/superio/ite/it8720f/acpi/superio.asl b/src/superio/ite/it8720f/acpi/superio.asl
new file mode 100644
index 0000000000..1e94655753
--- /dev/null
+++ b/src/superio/ite/it8720f/acpi/superio.asl
@@ -0,0 +1,211 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Christoph Grenz <christophg+cb@grenz-bonn.de>
+ * Copyright (C) 2013, 2016 secunet Security Networks AG
+ * Copyright (C) 2017 Samuel Holland <samuel@sholland.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Include this file into a mainboard's DSDT _SB device tree and it will
+ * expose the IT8720F SuperIO and some of its functionality.
+ *
+ * It allows the change of IO ports, IRQs and DMA settings on logical
+ * devices, disabling and reenabling logical devices.
+ *
+ *   LDN		State
+ * 0x0 FDC		Not implemented
+ * 0x1 SP1		Implemented, untested
+ * 0x2 SP2		Implemented, untested
+ * 0x3 PP		Not implemented
+ * 0x4 EC		Implemented, untested
+ * 0x5 KBCK		Implemented, untested
+ * 0x6 KBCM		Implemented, untested
+ * 0x7 GPIO		Implemented, untested
+ * 0xa CIR		Implemented, untested
+ *
+ * Controllable through preprocessor defines:
+ * SUPERIO_DEV		Device identifier for this SIO (e.g. SIO0)
+ * SUPERIO_PNP_BASE	I/O address of the first PnP configuration register
+ * IT8720F_SHOW_SP1	If defined, Serial Port 1 will be exposed.
+ * IT8720F_SHOW_SP2	If defined, Serial Port 2 will be exposed.
+ * IT8720F_SHOW_EC	If defined, the Environment Controller will be exposed.
+ * IT8720F_SHOW_KBCK	If defined, the Keyboard Controller will be exposed.
+ * IT8720F_SHOW_KBCM	If defined, PS/2 mouse support will be exposed.
+ * IT8720F_SHOW_GPIO	If defined, GPIO support will be exposed.
+ * IT8720F_SHOW_CIR	If defined, Consumer IR support will be exposed.
+ */
+
+#undef SUPERIO_CHIP_NAME
+#define SUPERIO_CHIP_NAME IT8720F
+#include <superio/acpi/pnp.asl>
+
+#undef PNP_DEFAULT_PSC
+#define PNP_DEFAULT_PSC Return (0) /* no power management */
+
+#define CONFIGURE_CONTROL CCTL
+
+Device(SUPERIO_DEV) {
+	Name (_HID, EisaId("PNP0A05"))
+	Name (_STR, Unicode("ITE IT8720F Super I/O"))
+	Name (_UID, SUPERIO_UID(SUPERIO_DEV,))
+
+	/* SuperIO configuration ports */
+	OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02)
+	Field (CREG, ByteAcc, NoLock, Preserve)
+	{
+		PNP_ADDR_REG,	8,
+		PNP_DATA_REG,   8
+	}
+	IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve)
+	{
+		Offset (0x02),
+		CONFIGURE_CONTROL,	8, /* Global configure control */
+
+		Offset (0x07),
+		PNP_LOGICAL_DEVICE,	8, /* Logical device selector */
+
+		Offset (0x30),
+		PNP_DEVICE_ACTIVE,	1, /* Logical device activation */
+
+		Offset (0x60),
+		PNP_IO0_HIGH_BYTE,	8, /* First I/O port base - high byte */
+		PNP_IO0_LOW_BYTE,	8, /* First I/O port base - low byte */
+		Offset (0x62),
+		PNP_IO1_HIGH_BYTE,	8, /* Second I/O port base - high byte */
+		PNP_IO1_LOW_BYTE,	8, /* Second I/O port base - low byte */
+		Offset (0x64),
+		PNP_IO2_HIGH_BYTE,	8, /* Third I/O port base - high byte */
+		PNP_IO2_LOW_BYTE,	8, /* Third I/O port base - low byte */
+
+		Offset (0x70),
+		PNP_IRQ0,		8, /* First IRQ */
+	}
+
+	Method (_CRS)
+	{
+		/* Announce the used I/O ports to the OS */
+		Return (ResourceTemplate () {
+			IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02)
+		})
+	}
+
+	#undef PNP_ENTER_MAGIC_1ST
+	#undef PNP_ENTER_MAGIC_2ND
+	#undef PNP_ENTER_MAGIC_3RD
+	#undef PNP_ENTER_MAGIC_4TH
+	#undef PNP_EXIT_MAGIC_1ST
+	#undef PNP_EXIT_SPECIAL_REG
+	#undef PNP_EXIT_SPECIAL_VAL
+	#define PNP_ENTER_MAGIC_1ST	0x87
+	#define PNP_ENTER_MAGIC_2ND	0x01
+	#define PNP_ENTER_MAGIC_3RD	0x55
+#if SUPERIO_PNP_BASE == 0x2e
+	#define PNP_ENTER_MAGIC_4TH	0x55
+#else
+	#define PNP_ENTER_MAGIC_4TH	0xaa
+#endif
+	#define PNP_EXIT_SPECIAL_REG	CONFIGURE_CONTROL
+	#define PNP_EXIT_SPECIAL_VAL	0x02
+	#include <superio/acpi/pnp_config.asl>
+
+#ifdef IT8720F_SHOW_SP1
+	#undef SUPERIO_UART_LDN
+	#undef SUPERIO_UART_DDN
+	#undef SUPERIO_UART_PM_REG
+	#undef SUPERIO_UART_PM_VAL
+	#undef SUPERIO_UART_PM_LDN
+	#define SUPERIO_UART_LDN 1
+	#include <superio/acpi/pnp_uart.asl>
+#endif
+
+#ifdef IT8720F_SHOW_SP2
+	#undef SUPERIO_UART_LDN
+	#undef SUPERIO_UART_DDN
+	#undef SUPERIO_UART_PM_REG
+	#undef SUPERIO_UART_PM_VAL
+	#undef SUPERIO_UART_PM_LDN
+	#define SUPERIO_UART_LDN 2
+	#include <superio/acpi/pnp_uart.asl>
+#endif
+
+#ifdef IT8720F_SHOW_EC
+	#undef SUPERIO_PNP_HID
+	#undef SUPERIO_PNP_LDN
+	#undef SUPERIO_PNP_DDN
+	#undef SUPERIO_PNP_PM_REG
+	#undef SUPERIO_PNP_PM_VAL
+	#undef SUPERIO_PNP_PM_LDN
+	#undef SUPERIO_PNP_IO0
+	#undef SUPERIO_PNP_IO1
+	#undef SUPERIO_PNP_IO2
+	#undef SUPERIO_PNP_IRQ0
+	#undef SUPERIO_PNP_IRQ1
+	#undef SUPERIO_PNP_DMA
+	#define SUPERIO_PNP_LDN 4
+	#define SUPERIO_PNP_IO0 0x08, 0x08
+	#define SUPERIO_PNP_IO1 0x08, 0x04
+	#define SUPERIO_PNP_IRQ0
+	#include <superio/acpi/pnp_generic.asl>
+#endif
+
+#ifdef IT8720F_SHOW_KBC
+	#undef SUPERIO_KBC_LDN
+	#undef SUPERIO_KBC_PS2M
+	#undef SUPERIO_KBC_PS2LDN
+	#define SUPERIO_KBC_LDN 5
+#ifdef IT8720F_SHOW_PS2M
+	#define SUPERIO_KBC_PS2LDN 6
+#endif
+	#include <superio/acpi/pnp_kbc.asl>
+#endif
+
+#ifdef IT8720F_SHOW_GPIO
+	#undef SUPERIO_PNP_HID
+	#undef SUPERIO_PNP_LDN
+	#undef SUPERIO_PNP_DDN
+	#undef SUPERIO_PNP_PM_REG
+	#undef SUPERIO_PNP_PM_VAL
+	#undef SUPERIO_PNP_PM_LDN
+	#undef SUPERIO_PNP_IO0
+	#undef SUPERIO_PNP_IO1
+	#undef SUPERIO_PNP_IO2
+	#undef SUPERIO_PNP_IRQ0
+	#undef SUPERIO_PNP_IRQ1
+	#undef SUPERIO_PNP_DMA
+	#define SUPERIO_PNP_LDN 7
+	#define SUPERIO_PNP_IO0 0x08, 0x08
+	#define SUPERIO_PNP_IO1 0x08, 0x08
+	#define SUPERIO_PNP_IO2 0x08, 0x08
+	#include <superio/acpi/pnp_generic.asl>
+#endif
+
+#ifdef IT8720F_SHOW_CIR
+	#undef SUPERIO_PNP_HID
+	#undef SUPERIO_PNP_LDN
+	#undef SUPERIO_PNP_DDN
+	#undef SUPERIO_PNP_PM_REG
+	#undef SUPERIO_PNP_PM_VAL
+	#undef SUPERIO_PNP_PM_LDN
+	#undef SUPERIO_PNP_IO0
+	#undef SUPERIO_PNP_IO1
+	#undef SUPERIO_PNP_IO2
+	#undef SUPERIO_PNP_IRQ0
+	#undef SUPERIO_PNP_IRQ1
+	#undef SUPERIO_PNP_DMA
+	#define SUPERIO_PNP_HID "ITE8704"
+	#define SUPERIO_PNP_LDN 10
+	#define SUPERIO_PNP_IO0 0x08, 0x08
+	#define SUPERIO_PNP_IRQ0
+	#include <superio/acpi/pnp_generic.asl>
+#endif
+}
diff --git a/src/superio/ite/it8720f/chip.h b/src/superio/ite/it8720f/chip.h
new file mode 100644
index 0000000000..2c623a997f
--- /dev/null
+++ b/src/superio/ite/it8720f/chip.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 secunet Security Networks AG
+ * Copyright (C) 2017 Samuel Holland <samuel@sholland.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SUPERIO_ITE_IT8720F_CHIP_H
+#define SUPERIO_ITE_IT8720F_CHIP_H
+
+#include <superio/ite/common/env_ctrl_chip.h>
+
+struct superio_ite_it8720f_config {
+	struct ite_ec_config ec;
+};
+
+#endif /* SUPERIO_ITE_IT8720F_CHIP_H */
diff --git a/src/superio/ite/it8720f/it8720f.h b/src/superio/ite/it8720f/it8720f.h
new file mode 100644
index 0000000000..f8b7efbc56
--- /dev/null
+++ b/src/superio/ite/it8720f/it8720f.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
+ * Copyright (C) 2011 QingPei Wang <wangqingpei@gmail.com>
+ * Copyright (C) 2017 Samuel Holland <samuel@sholland.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SUPERIO_ITE_IT8720F_H
+#define SUPERIO_ITE_IT8720F_H
+
+/* Logical Device Numbers (LDN). */
+#define IT8720F_FDC  0x00 /* Floppy */
+#define IT8720F_SP1  0x01 /* Serial port 1 */
+#define IT8720F_SP2  0x02 /* Serial port 2 */
+#define IT8720F_PP   0x03 /* Parallel port */
+#define IT8720F_EC   0x04 /* Environment controller */
+#define IT8720F_KBCK 0x05 /* PS/2 keyboard */
+#define IT8720F_KBCM 0x06 /* PS/2 mouse */
+#define IT8720F_GPIO 0x07 /* GPIO (including SPI flash interface) */
+#define IT8720F_CIR  0x0a /* Consumer IR */
+
+#endif /* SUPERIO_ITE_IT8720F_H */
diff --git a/src/superio/ite/it8720f/superio.c b/src/superio/ite/it8720f/superio.c
new file mode 100644
index 0000000000..74ffefa44c
--- /dev/null
+++ b/src/superio/ite/it8720f/superio.c
@@ -0,0 +1,101 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 secunet Security Networks AG
+ * Copyright (C) 2017 Samuel Holland <samuel@sholland.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <device/pnp.h>
+#include <pc80/keyboard.h>
+#include <superio/ite/common/env_ctrl.h>
+#include <superio/conf_mode.h>
+
+#include "chip.h"
+#include "it8720f.h"
+
+static void it8720f_init(struct device *dev)
+{
+	const struct superio_ite_it8720f_config *conf;
+	const struct resource *res;
+
+	if (!dev->enabled)
+		return;
+
+	switch (dev->path.pnp.device) {
+	case IT8720F_EC:
+		conf = dev->chip_info;
+		res = find_resource(dev, PNP_IDX_IO0);
+		if (!conf || !res)
+			break;
+		ite_ec_init(res->base, &conf->ec);
+		break;
+	case IT8720F_KBCK:
+		pc_keyboard_init(NO_AUX_DEVICE);
+		break;
+	default:
+		break;
+	}
+}
+
+static struct device_operations ops = {
+	.read_resources   = pnp_read_resources,
+	.set_resources    = pnp_set_resources,
+	.enable_resources = pnp_enable_resources,
+	.enable           = pnp_enable,
+	.init             = it8720f_init,
+	.ops_pnp_mode     = &pnp_conf_mode_870155_aa,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+	{ &ops, IT8720F_FDC,
+		PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_MSC0 | PNP_MSC1,
+		{0x0ff8, 0}, },
+	{ &ops, IT8720F_SP1,
+		PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1,
+		{0x0ff8, 0}, },
+	{ &ops, IT8720F_SP2,
+		PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1,
+		{0x0ff8, 0}, },
+	{ &ops, IT8720F_PP,
+		PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_DRQ0 | PNP_MSC0,
+		{0x0ff8, 0}, {0x0ffc, 0}, },
+	{ &ops, IT8720F_EC,
+		PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | PNP_MSC2 |
+		PNP_MSC3 | PNP_MSC4 | PNP_MSC5 | PNP_MSC6,
+		{0x0ff8, 0}, {0x0ffc, 0}, },
+	{ &ops, IT8720F_KBCK,
+		PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0,
+		{0x0fff, 0}, {0x0fff, 0}, },
+	{ &ops, IT8720F_KBCM,
+		PNP_IRQ0 | PNP_MSC0, },
+	{ &ops, IT8720F_GPIO,
+		PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_MSC0 | PNP_MSC1 | PNP_MSC2 |
+		PNP_MSC3 | PNP_MSC4 | PNP_MSC5 | PNP_MSC6 | PNP_MSC7 |
+		PNP_MSC8 | PNP_MSC9 | PNP_MSCA | PNP_MSCB | PNP_MSCD | PNP_MSCE,
+		{0x0ff8, 0}, {0x0ff8, 0}, {0x0ff8, 0}, },
+	{ &ops, IT8720F_CIR,
+		PNP_IO0 | PNP_IRQ0 | PNP_MSC0,
+		{0x0ff8, 0}, },
+};
+
+static void enable_dev(struct device *dev)
+{
+	pnp_enable_devices(dev, &pnp_ops,
+		ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_ite_it8720f_ops = {
+	CHIP_NAME("ITE IT8720F Super I/O")
+	.enable_dev = enable_dev,
+};