[REMOVAL] tyan/s4880

As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: I41d1f9eac2f4c37bec4d046a68f3f1cf95b51703
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12384
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

9 files changed, 0 insertions, 892 deletions

diff --git a/src/mainboard/tyan/s4880/Kconfig b/src/mainboard/tyan/s4880/Kconfig
deleted file mode 100644
index 6c85c6c524..0000000000
--- a/src/mainboard/tyan/s4880/Kconfig
+++ /dev/null
@@ -1,57 +0,0 @@
-if BOARD_TYAN_S4880
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select CPU_AMD_SOCKET_940
-	select NORTHBRIDGE_AMD_AMDK8
-	select SOUTHBRIDGE_AMD_AMD8111
-	select SOUTHBRIDGE_AMD_AMD8131
-	select SUPERIO_WINBOND_W83627HF
-	select HAVE_OPTION_TABLE
-	select HAVE_PIRQ_TABLE
-	select HAVE_MP_TABLE
-	select BOARD_ROMSIZE_KB_512
-	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
-	select QRANK_DIMM_SUPPORT
-
-config MAINBOARD_DIR
-	string
-	default tyan/s4880
-
-config DCACHE_RAM_BASE
-	hex
-	default 0xcf000
-
-config DCACHE_RAM_SIZE
-	hex
-	default 0x01000
-
-config APIC_ID_OFFSET
-	hex
-	default 0x10
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "S4880"
-
-config MAX_CPUS
-	int
-	default 8
-
-config MAX_PHYSICAL_CPUS
-	int
-	default 4
-
-config HT_CHAIN_END_UNITID_BASE
-	hex
-	default 0x20
-
-config HT_CHAIN_UNITID_BASE
-	hex
-	default 0x1
-
-config IRQ_SLOT_COUNT
-	int
-	default 22
-
-endif # BOARD_TYAN_S4880
diff --git a/src/mainboard/tyan/s4880/Kconfig.name b/src/mainboard/tyan/s4880/Kconfig.name
deleted file mode 100644
index 2e71996867..0000000000
--- a/src/mainboard/tyan/s4880/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_TYAN_S4880
-	bool "S4880 (Thunder K8QS)"
diff --git a/src/mainboard/tyan/s4880/board_info.txt b/src/mainboard/tyan/s4880/board_info.txt
deleted file mode 100644
index d2ab0ab718..0000000000
--- a/src/mainboard/tyan/s4880/board_info.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-Board name: Thunder K8QS (S4880)
-Category: server
-Board URL: http://www.tyan.com/archive/products/html/thunderk8qs.html
-Release year: 2004
diff --git a/src/mainboard/tyan/s4880/cmos.layout b/src/mainboard/tyan/s4880/cmos.layout
deleted file mode 100644
index 4e081ea1aa..0000000000
--- a/src/mainboard/tyan/s4880/cmos.layout
+++ /dev/null
@@ -1,60 +0,0 @@
-entries
-
-0          384       r       0        reserved_memory
-384          1       e       4        boot_option
-388          4       r       0        reboot_bits
-392          3       e       5        baud_rate
-395          1       e       1        hw_scrubber
-396          1       e       1        interleave_chip_selects
-397          2       e       8        max_mem_clock
-399          1       e       2        multi_core
-400          1       e       1        power_on_after_fail
-412          4       e       6        debug_level
-440          4       e       9        slow_cpu
-444          1       e       1        nmi
-445          1       e       1        iommu
-456          1       e       1        ECC_memory
-728        256       h       0        user_data
-984         16       h       0        check_sum
-# Reserve the extended AMD configuration registers
-1000        24       r       0        amd_reserved
-
-
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-5     0     115200
-5     1     57600
-5     2     38400
-5     3     19200
-5     4     9600
-5     5     4800
-5     6     2400
-5     7     1200
-6     6     Notice
-6     7     Info
-6     8     Debug
-6     9     Spew
-8     0     DDR400
-8     1     DDR333
-8     2     DDR266
-8     3     DDR200
-9     0     off
-9     1     87.5%
-9     2     75.0%
-9     3     62.5%
-9     4     50.0%
-9     5     37.5%
-9     6     25.0%
-9     7     12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/tyan/s4880/devicetree.cb b/src/mainboard/tyan/s4880/devicetree.cb
deleted file mode 100644
index d64d054c29..0000000000
--- a/src/mainboard/tyan/s4880/devicetree.cb
+++ /dev/null
@@ -1,98 +0,0 @@
-chip northbridge/amd/amdk8/root_complex
-        device cpu_cluster 0 on
-                chip cpu/amd/socket_940
-                        device lapic 0 on end
-                end
-        end
-
-	device domain 0 on
-		subsystemid 0x10f1 0x4880 inherit
-		chip northbridge/amd/amdk8
-			device pci 18.0 on end # LDT0
-			device pci 18.0 on end # LDT1
-			device pci 18.0 on #  northbridge
-				#  devices on link 2, link 2 == LDT 2
-				chip southbridge/amd/amd8131
-					# the on/off keyword is mandatory
-                                        device pci 0.0 on
-#                                                chip drivers/lsi/53c1030
-#                                                        device pci 4.0 on end
-#                                                        device pci 4.1 on end
-#                                                        register "fw_address" = "0xfff8c000"
-#                                                end
-                                                device pci 9.0 on end
-                                                device pci 9.1 on end
-					end
-					device pci 0.1 on end
-					device pci 1.0 on end
-					device pci 1.1 on end
-				end
-				chip southbridge/amd/amd8111
-					# this "device pci 0.0" is the parent the next one
-					# PCI bridge
-					device pci 0.0 on
-						device pci 0.0 on end
-						device pci 0.1 on end
-						device pci 0.2 off end
-						device pci 1.0 off end
-                                                device pci 6.0 on end
-					end
-					device pci 1.0 on
-						chip superio/winbond/w83627hf
-							device pnp 2e.0 on #  Floppy
-                	                 			io 0x60 = 0x3f0
-                	                			irq 0x70 = 6
-                	                			drq 0x74 = 2
-							end
-                	        			device pnp 2e.1 off #  Parallel Port
-                	                 			io 0x60 = 0x378
-                	                			irq 0x70 = 7
-							end
-                	        			device pnp 2e.2 on #  Com1
-                	                 			io 0x60 = 0x3f8
-                	                			irq 0x70 = 4
-							end
-                	        			device pnp 2e.3 off #  Com2
-                	                 			io 0x60 = 0x2f8
-                	                			irq 0x70 = 3
-							end
-                	        			device pnp 2e.5 on #  Keyboard
-                	                 			io 0x60 = 0x60
-                	                 			io 0x62 = 0x64
-                	                			irq 0x70 = 1
-								irq 0x72 = 12
-							end
-                	                                device pnp 2e.6 off #  CIR
-                	                                        io 0x60 = 0x100
-                	                                end
-                	                                device pnp 2e.7 off #  GAME_MIDI_GIPO1
-                	                                        io 0x60 = 0x220
-                	                                        io 0x62 = 0x300
-                	                                        irq 0x70 = 9
-                	                                end
-                	                                device pnp 2e.8 off end #  GPIO2
-                	                                device pnp 2e.9 off end #  GPIO3
-                	                                device pnp 2e.a off end #  ACPI
-                	                                device pnp 2e.b on #  HW Monitor
-                	                                        io 0x60 = 0x290
-                	                                        irq 0x70 = 5
-                	                                end
-						end
-					end
-					device pci 1.1 on end
-					device pci 1.2 on end
-					device pci 1.3 on end
-					device pci 1.5 off end
-					device pci 1.6 off end
-                                        register "ide0_enable" = "1"
-                                        register "ide1_enable" = "1"
-				end
-			end #  device pci 18.0
-
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end
-
-	end #domain
-end
diff --git a/src/mainboard/tyan/s4880/irq_tables.c b/src/mainboard/tyan/s4880/irq_tables.c
deleted file mode 100644
index 848d2d9259..0000000000
--- a/src/mainboard/tyan/s4880/irq_tables.c
+++ /dev/null
@@ -1,43 +0,0 @@
-#include <arch/pirq_routing.h>
-
-static const struct irq_routing_table intel_irq_routing_table = {
-	PIRQ_SIGNATURE, /* u32 signature */
-	PIRQ_VERSION,   /* u16 version   */
-	32+16*CONFIG_IRQ_SLOT_COUNT,        /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
-	1,           /* Where the interrupt router lies (bus) */
-	(4<<3)|3,           /* Where the interrupt router lies (dev) */
-	0,         /* IRQs devoted exclusively to PCI usage */
-	0x1022,         /* Vendor */
-	0x7400,         /* Device */
-	0,         /* Miniport data */
-	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0x9a,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
-	{
-		{0,0xc0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
-		{1,(3<<3)|0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
-		{0x4,0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
-		{0x4,0x8, {{0x1, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
-		{0x4,0x20, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0},
-		{0x4,0x18, {{0x2, 0xdef8}, {0x1, 0xdef8}, {0x3, 0xdef8}, {0, 0xdef8}}, 0, 0},
-		{0x4,0x28, {{0x4, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
-		{0x4,0x30, {{0x3, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
-		{1,(4<<3)|0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
-		{1,(1<<3)|0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
-		{0x2,0x18, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x2, 0},
-		{0x2,0x10, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x3, 0},
-		{0x2,0x48, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
-		{0x2,0x20, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
-		{1,(2<<3)|0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
-		{0x3,0x18, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x4, 0},
-		{0x3,0x8, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x5, 0},
-		{0x3,0x20, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x6, 0},
-		{0x3,0x28, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x7, 0},
-		{0,0xc8, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
-		{0,0xd0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
-		{0,0xd8, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
-	}
-};
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-        return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/tyan/s4880/mptable.c b/src/mainboard/tyan/s4880/mptable.c
deleted file mode 100644
index b315c40678..0000000000
--- a/src/mainboard/tyan/s4880/mptable.c
+++ /dev/null
@@ -1,214 +0,0 @@
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS
-#include <cpu/amd/multicore.h>
-#endif
-
-static unsigned node_link_to_bus(unsigned node, unsigned link)
-{
-        device_t dev;
-        unsigned reg;
-
-        dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
-        if (!dev) {
-                return 0;
-        }
-        for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
-                uint32_t config_map;
-                unsigned dst_node;
-                unsigned dst_link;
-                unsigned bus_base;
-                config_map = pci_read_config32(dev, reg);
-                if ((config_map & 3) != 3) {
-                        continue;
-                }
-                dst_node = (config_map >> 4) & 7;
-                dst_link = (config_map >> 8) & 3;
-                bus_base = (config_map >> 16) & 0xff;
-#if 0
-                printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
-                        dst_node, dst_link, bus_base,
-                        reg, config_map);
-#endif
-                if ((dst_node == node) && (dst_link == link))
-                {
-                        return bus_base;
-                }
-        }
-        return 0;
-}
-
-static void *smp_write_config_table(void *v)
-{
-        struct mp_config_table *mc;
-        int bus_isa;
-	unsigned char bus_chain_0;
-        unsigned char bus_8131_1;
-        unsigned char bus_8131_2;
-        unsigned char bus_8111_1;
-        unsigned apicid_base;
-        unsigned apicid_8111;
-        unsigned apicid_8131_1;
-        unsigned apicid_8131_2;
-
-        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
-	mptable_init(mc, LOCAL_APIC_ADDR);
-
-        smp_write_processors(mc);
-
-        {
-                device_t dev;
-
-                /* HT chain 0 */
-                bus_chain_0 = node_link_to_bus(0, 2);
-                if (bus_chain_0 == 0) {
-                        printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n");
-                        bus_chain_0 = 1;
-                }
-
-                /* 8111 */
-                dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0));
-                if (dev) {
-                        bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-                }
-                else {
-                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
-
-                        bus_8111_1 = 4;
-                }
-                /* 8131-1 */
-                dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0));
-                if (dev) {
-                        bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
-                }
-                else {
-                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
-
-                        bus_8131_1 = 2;
-                }
-                /* 8131-2 */
-                dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0));
-                if (dev) {
-                        bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
-                }
-                else {
-                        printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
-
-                        bus_8131_2 = 3;
-                }
-        }
-
-/*Bus:          Bus ID  Type*/
-	mptable_write_buses(mc, NULL, &bus_isa);
-
-/*I/O APICs:	APIC ID	Version	State		Address*/
-#if CONFIG_LOGICAL_CPUS
-	apicid_base = get_apicid_base(3);
-#else
-        apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
-#endif
-        apicid_8111 = apicid_base+0;
-        apicid_8131_1 = apicid_base+1;
-        apicid_8131_2 = apicid_base+2;
-
-	smp_write_ioapic(mc, apicid_8111, 0x11, VIO_APIC_VADDR);
-        {
-                device_t dev;
-                struct resource *res;
-                dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1));
-                if (dev) {
-                        res = find_resource(dev, PCI_BASE_ADDRESS_0);
-                        if (res) {
-                                smp_write_ioapic(mc, apicid_8131_1, 0x11,
-						 res2mmio(res, 0, 0));
-                        }
-                }
-                dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x2,1));
-                if (dev) {
-                        res = find_resource(dev, PCI_BASE_ADDRESS_0);
-                        if (res) {
-                                smp_write_ioapic(mc, apicid_8131_2, 0x11,
-						 res2mmio(res, 0, 0));
-                        }
-                }
-
-	}
-
-	mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0);
-
-/*I/O Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN# */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (4<<2)|0, apicid_8111, 0x13);
-
-
-//On Board AMD USB
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);
-
-//On Board Via USB 1.1 and 2
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|0, apicid_8111, 0x11); //1.1
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|1, apicid_8111, 0x10); //1.1
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|2, apicid_8111, 0x12); //2
-
-//Slot 5 PCI 32
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|0, apicid_8111, 0x10);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|1, apicid_8111, 0x11);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|2, apicid_8111, 0x12); //
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|3, apicid_8111, 0x13); //
-
-
-//On Board SI Serial ATA
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|0, apicid_8111, 0x13);
-//On Board ATI Display Adapter
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (6<<2)|0, apicid_8111, 0x12);
-
-
-//Slot 4 PCIX 100/66
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|0, apicid_8131_1, 0x3);
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|1, apicid_8131_1, 0x0);
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|2, apicid_8131_1, 0x1);//
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|3, apicid_8131_1, 0x2);//
-
-//Slot 3 PCIX 100/66
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|0, apicid_8131_1, 0x2);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|1, apicid_8131_1, 0x3);//
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|2, apicid_8131_1, 0x0);//
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|3, apicid_8131_1, 0x1);//
-
-//On Board LSI scsi and NIC
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|0, apicid_8131_1, 0x0);
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|1, apicid_8131_1, 0x1);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, apicid_8131_1, 0x0);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|1, apicid_8131_1, 0x1);
-
-//Slot 2 PCI-X 133/100/66
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, apicid_8131_2, 0x0);
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|1, apicid_8131_2, 0x1);
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, apicid_8131_2, 0x2); //
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, apicid_8131_2, 0x3); //
-
-//Slot 1 PCI-X 133/100/66
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|0, apicid_8131_2, 0x1);
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|1, apicid_8131_2, 0x2);
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|2, apicid_8131_2, 0x3);//
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|3, apicid_8131_2, 0x0);//
-
-/*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	mptable_lintsrc(mc, bus_isa);
-	/* There is no extension information... */
-
-	/* Compute the checksums */
-	return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
-	void *v;
-	v = smp_write_floating_table(addr, 0);
-	return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/tyan/s4880/resourcemap.c b/src/mainboard/tyan/s4880/resourcemap.c
deleted file mode 100644
index f6801f1a3e..0000000000
--- a/src/mainboard/tyan/s4880/resourcemap.c
+++ /dev/null
@@ -1,263 +0,0 @@
-/*
- * Tyan S4880 needs a different resource map
- *
- */
-
-static void setup_s4880_resource_map(void)
-{
-	static const unsigned int register_values[] = {
-	/* Careful set limit registers before base registers which contain the enables */
-	/* DRAM Limit i Registers
-	 * F1:0x44 i = 0
-	 * F1:0x4C i = 1
-	 * F1:0x54 i = 2
-	 * F1:0x5C i = 3
-	 * F1:0x64 i = 4
-	 * F1:0x6C i = 5
-	 * F1:0x74 i = 6
-	 * F1:0x7C i = 7
-	 * [ 2: 0] Destination Node ID
-	 *	   000 = Node 0
-	 *	   001 = Node 1
-	 *	   010 = Node 2
-	 *	   011 = Node 3
-	 *	   100 = Node 4
-	 *	   101 = Node 5
-	 *	   110 = Node 6
-	 *	   111 = Node 7
-	 * [ 7: 3] Reserved
-	 * [10: 8] Interleave select
-	 *	   specifies the values of A[14:12] to use with interleave enable.
-	 * [15:11] Reserved
-	 * [31:16] DRAM Limit Address i Bits 39-24
-	 *	   This field defines the upper address bits of a 40 bit  address
-	 *	   that define the end of the DRAM region.
-	 */
-	PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
-	PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
-	PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
-	PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
-	PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
-	PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
-	PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
-	/* DRAM Base i Registers
-	 * F1:0x40 i = 0
-	 * F1:0x48 i = 1
-	 * F1:0x50 i = 2
-	 * F1:0x58 i = 3
-	 * F1:0x60 i = 4
-	 * F1:0x68 i = 5
-	 * F1:0x70 i = 6
-	 * F1:0x78 i = 7
-	 * [ 0: 0] Read Enable
-	 *	   0 = Reads Disabled
-	 *	   1 = Reads Enabled
-	 * [ 1: 1] Write Enable
-	 *	   0 = Writes Disabled
-	 *	   1 = Writes Enabled
-	 * [ 7: 2] Reserved
-	 * [10: 8] Interleave Enable
-	 *	   000 = No interleave
-	 *	   001 = Interleave on A[12] (2 nodes)
-	 *	   010 = reserved
-	 *	   011 = Interleave on A[12] and A[14] (4 nodes)
-	 *	   100 = reserved
-	 *	   101 = reserved
-	 *	   110 = reserved
-	 *	   111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
-	 * [15:11] Reserved
-	 * [13:16] DRAM Base Address i Bits 39-24
-	 *	   This field defines the upper address bits of a 40-bit address
-	 *	   that define the start of the DRAM region.
-	 */
-	PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
-
-	/* Memory-Mapped I/O Limit i Registers
-	 * F1:0x84 i = 0
-	 * F1:0x8C i = 1
-	 * F1:0x94 i = 2
-	 * F1:0x9C i = 3
-	 * F1:0xA4 i = 4
-	 * F1:0xAC i = 5
-	 * F1:0xB4 i = 6
-	 * F1:0xBC i = 7
-	 * [ 2: 0] Destination Node ID
-	 *	   000 = Node 0
-	 *	   001 = Node 1
-	 *	   010 = Node 2
-	 *	   011 = Node 3
-	 *	   100 = Node 4
-	 *	   101 = Node 5
-	 *	   110 = Node 6
-	 *	   111 = Node 7
-	 * [ 3: 3] Reserved
-	 * [ 5: 4] Destination Link ID
-	 *	   00 = Link 0
-	 *	   01 = Link 1
-	 *	   10 = Link 2
-	 *	   11 = Reserved
-	 * [ 6: 6] Reserved
-	 * [ 7: 7] Non-Posted
-	 *	   0 = CPU writes may be posted
-	 *	   1 = CPU writes must be non-posted
-	 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
-	 *	   This field defines the upp adddress bits of a 40-bit address that
-	 *	   defines the end of a memory-mapped I/O region n
-	 */
-	PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff20,
-
-	/* Memory-Mapped I/O Base i Registers
-	 * F1:0x80 i = 0
-	 * F1:0x88 i = 1
-	 * F1:0x90 i = 2
-	 * F1:0x98 i = 3
-	 * F1:0xA0 i = 4
-	 * F1:0xA8 i = 5
-	 * F1:0xB0 i = 6
-	 * F1:0xB8 i = 7
-	 * [ 0: 0] Read Enable
-	 *	   0 = Reads disabled
-	 *	   1 = Reads Enabled
-	 * [ 1: 1] Write Enable
-	 *	   0 = Writes disabled
-	 *	   1 = Writes Enabled
-	 * [ 2: 2] Cpu Disable
-	 *	   0 = Cpu can use this I/O range
-	 *	   1 = Cpu requests do not use this I/O range
-	 * [ 3: 3] Lock
-	 *	   0 = base/limit registers i are read/write
-	 *	   1 = base/limit registers i are read-only
-	 * [ 7: 4] Reserved
-	 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
-	 *	   This field defines the upper address bits of a 40bit address
-	 *	   that defines the start of memory-mapped I/O region i
-	 */
-	PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
-
-	/* PCI I/O Limit i Registers
-	 * F1:0xC4 i = 0
-	 * F1:0xCC i = 1
-	 * F1:0xD4 i = 2
-	 * F1:0xDC i = 3
-	 * [ 2: 0] Destination Node ID
-	 *	   000 = Node 0
-	 *	   001 = Node 1
-	 *	   010 = Node 2
-	 *	   011 = Node 3
-	 *	   100 = Node 4
-	 *	   101 = Node 5
-	 *	   110 = Node 6
-	 *	   111 = Node 7
-	 * [ 3: 3] Reserved
-	 * [ 5: 4] Destination Link ID
-	 *	   00 = Link 0
-	 *	   01 = Link 1
-	 *	   10 = Link 2
-	 *	   11 = reserved
-	 * [11: 6] Reserved
-	 * [24:12] PCI I/O Limit Address i
-	 *	   This field defines the end of PCI I/O region n
-	 * [31:25] Reserved
-	 */
-	PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff020,
-	PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
-
-	/* PCI I/O Base i Registers
-	 * F1:0xC0 i = 0
-	 * F1:0xC8 i = 1
-	 * F1:0xD0 i = 2
-	 * F1:0xD8 i = 3
-	 * [ 0: 0] Read Enable
-	 *	   0 = Reads Disabled
-	 *	   1 = Reads Enabled
-	 * [ 1: 1] Write Enable
-	 *	   0 = Writes Disabled
-	 *	   1 = Writes Enabled
-	 * [ 3: 2] Reserved
-	 * [ 4: 4] VGA Enable
-	 *	   0 = VGA matches Disabled
-	 *	   1 = matches all address < 64K and where A[9:0] is in the
-	 *	       range 3B0-3BB or 3C0-3DF independen of the base & limit registers
-	 * [ 5: 5] ISA Enable
-	 *	   0 = ISA matches Disabled
-	 *	   1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
-	 *	       from matching agains this base/limit pair
-	 * [11: 6] Reserved
-	 * [24:12] PCI I/O Base i
-	 *	   This field defines the start of PCI I/O region n
-	 * [31:25] Reserved
-	 */
-	PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
-	PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
-
-	/* Config Base and Limit i Registers
-	 * F1:0xE0 i = 0
-	 * F1:0xE4 i = 1
-	 * F1:0xE8 i = 2
-	 * F1:0xEC i = 3
-	 * [ 0: 0] Read Enable
-	 *	   0 = Reads Disabled
-	 *	   1 = Reads Enabled
-	 * [ 1: 1] Write Enable
-	 *	   0 = Writes Disabled
-	 *	   1 = Writes Enabled
-	 * [ 2: 2] Device Number Compare Enable
-	 *	   0 = The ranges are based on bus number
-	 *	   1 = The ranges are ranges of devices on bus 0
-	 * [ 3: 3] Reserved
-	 * [ 6: 4] Destination Node
-	 *	   000 = Node 0
-	 *	   001 = Node 1
-	 *	   010 = Node 2
-	 *	   011 = Node 3
-	 *	   100 = Node 4
-	 *	   101 = Node 5
-	 *	   110 = Node 6
-	 *	   111 = Node 7
-	 * [ 7: 7] Reserved
-	 * [ 9: 8] Destination Link
-	 *	   00 = Link 0
-	 *	   01 = Link 1
-	 *	   10 = Link 2
-	 *	   11 - Reserved
-	 * [15:10] Reserved
-	 * [23:16] Bus Number Base i
-	 *	   This field defines the lowest bus number in configuration region i
-	 * [31:24] Bus Number Limit i
-	 *	   This field defines the highest bus number in configuration regin i
-	 */
-//	PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000203,
-	PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
-	};
-	int max;
-	max = ARRAY_SIZE(register_values);
-	setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c
deleted file mode 100644
index 5c0b1281ec..0000000000
--- a/src/mainboard/tyan/s4880/romstage.c
+++ /dev/null
@@ -1,151 +0,0 @@
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <stdlib.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <lib.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/early_smbus.c"
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627hf/w83627hf.h>
-#include <cpu/x86/bist.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/early_ctrl.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-static void memreset_setup(void)
-{
-   if (is_cpu_pre_c0())
-        outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
-   else
-        outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
-   outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-   if (is_cpu_pre_c0()) {
-        udelay(800);
-        outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
-        udelay(90);
-   }
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-#define SMBUS_HUB 0x18
-        unsigned device=(ctrl->channel0[0])>>8;
-        smbus_write_byte(SMBUS_HUB, 0x01, device);
-        smbus_write_byte(SMBUS_HUB, 0x03, 0);
-}
-
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/raminit.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "lib/generic_sdram.c"
-#include "resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include <spd.h>
-#include "cpu/amd/model_fxx/init_cpus.c"
-
-#define RC0 ((1<<2)<<8)
-#define RC1 ((1<<1)<<8)
-#define RC2 ((1<<4)<<8)
-#define RC3 ((1<<3)<<8)
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-	static const struct mem_controller cpu[] = {
-                {
-                        .node_id = 0,
-                        .f0 = PCI_DEV(0, 0x18, 0),
-                        .f1 = PCI_DEV(0, 0x18, 1),
-                        .f2 = PCI_DEV(0, 0x18, 2),
-                        .f3 = PCI_DEV(0, 0x18, 3),
-                        .channel0 = { RC0|DIMM0, RC0|DIMM2, 0, 0 },
-                        .channel1 = { RC0|DIMM1, RC0|DIMM3, 0, 0 },
-                },
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
-                {
-                        .node_id = 1,
-                        .f0 = PCI_DEV(0, 0x19, 0),
-                        .f1 = PCI_DEV(0, 0x19, 1),
-                        .f2 = PCI_DEV(0, 0x19, 2),
-                        .f3 = PCI_DEV(0, 0x19, 3),
-                        .channel0 = { RC1|DIMM0, RC1|DIMM2 , 0, 0 },
-                        .channel1 = { RC1|DIMM1, RC1|DIMM3 , 0, 0 },
-
-                },
-#endif
-#if CONFIG_MAX_PHYSICAL_CPUS > 2
-                {
-                        .node_id = 2,
-                        .f0 = PCI_DEV(0, 0x1a, 0),
-                        .f1 = PCI_DEV(0, 0x1a, 1),
-                        .f2 = PCI_DEV(0, 0x1a, 2),
-                        .f3 = PCI_DEV(0, 0x1a, 3),
-                        .channel0 = { RC2|DIMM0, RC2|DIMM2, 0, 0 },
-                        .channel1 = { RC2|DIMM1, RC2|DIMM3, 0, 0 },
-
-                },
-                {
-                        .node_id = 3,
-                        .f0 = PCI_DEV(0, 0x1b, 0),
-                        .f1 = PCI_DEV(0, 0x1b, 1),
-                        .f2 = PCI_DEV(0, 0x1b, 2),
-                        .f3 = PCI_DEV(0, 0x1b, 3),
-                        .channel0 = { RC3|DIMM0, RC3|DIMM2, 0, 0 },
-                        .channel1 = { RC3|DIMM1, RC3|DIMM3, 0, 0 },
-
-                },
-#endif
-	};
-
-        int needs_reset;
-
-        if (bist == 0)
-		init_cpus(cpu_init_detectedx);
-
-	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-        setup_s4880_resource_map();
-
-	needs_reset = setup_coherent_ht_domain();
-
-#if CONFIG_LOGICAL_CPUS
-        // It is said that we should start core1 after all core0 launched
-        start_other_cores();
-#endif
-	// automatically set that for you, but you might meet tight space
-        needs_reset |= ht_setup_chains_x();
-
-       	if (needs_reset) {
-               	printk(BIOS_INFO, "ht reset -\n");
-               	soft_reset();
-       	}
-
-	enable_smbus();
-
-	memreset_setup();
-	sdram_initialize(ARRAY_SIZE(cpu), cpu);
-
-	post_cache_as_ram();
-}