diff options
| author | Meera Ravindranath <meera.ravindranath@intel.com> | 2020-04-29 12:19:33 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-01 06:27:32 +0000 |
| commit | 0d6cc2201713fef102d7229f24e97428679aec68 (patch) | |
| tree | 44ba6073adaf450c880c4606e047e2ecee587313 /src | |
| parent | 4c7bc8db749ffaf0bb3a54b43b0a56652285cde9 (diff) | |
soc/intel/tigerlake: Fill PcieRpClkReqDetect from devicetree
This CL adds support to fill PcieRpClkReqDetect UPD from devicetree.
Filling this UPD will allow FSP to enable proper clksrc gpio
configuration.
BUG=None
BRANCH=None
TEST=Build and boot tglrvp.
Change-Id: Iad0ba94fea019623a5b98fff0cb4a2cd1d2a7bd7
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/tigerlake/chip.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/fsp_params.c | 5 |
2 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index a3319d4ee4..fe338352fb 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -107,6 +107,9 @@ struct soc_intel_tigerlake_config { * clksrc. */ uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS]; + /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/ + uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS]; + /* PCIe RP L1 substate */ enum L1_substates_control { L1_SS_FSP_DEFAULT, diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 5acad201c6..fc2a3c026a 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -151,6 +151,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PcieRpAdvancedErrorReporting[i] = config->PcieRpAdvancedErrorReporting[i]; } + + /* Enable ClkReqDetect for enabled port */ + memcpy(params->PcieRpClkReqDetect, config->PcieRpClkReqDetect, + sizeof(config->PcieRpClkReqDetect)); + /* Enable xDCI controller if enabled in devicetree and allowed */ dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); if (dev) { |