diff options
| author | Cliff Huang <cliff.huang@intel.corp-partner.google.com> | 2022-04-28 18:20:27 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-09 13:40:08 +0000 |
| commit | 0d590b7d915f47c2102b2515aca8b608205c4258 (patch) | |
| tree | 90028ccf76aac457885332d1878c47c94ace4970 /src | |
| parent | 61a442ec01b1a7d9a2d83604956f8355ea391b3e (diff) | |
soc/intel/alderlake: add support for external source clock
Support up to 10 PCIe source clock out, including source clock out 7, 8, 9.
This allows boards to use source clock 7, 8, 9.
BUG=b:233252409
BRANCH=firmware-brya-14505.B
Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: I0296974fb8557de1edea7f9ca2d96db0afd8a743
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63943
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 4e10f3d2de..e6151313ae 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -232,11 +232,17 @@ config MAX_ROOT_PORTS default MAX_PCH_ROOT_PORTS config MAX_PCIE_CLOCK_SRC + prompt "Number of Source Clock supported from SOC" int default 6 if SOC_INTEL_ALDERLAKE_PCH_M default 5 if SOC_INTEL_ALDERLAKE_PCH_N - default 7 if SOC_INTEL_ALDERLAKE_PCH_P default 18 if SOC_INTEL_ALDERLAKE_PCH_S + default 10 if SOC_INTEL_ALDERLAKE_PCH_P + help + With external clock buffer, Alderlake-P can support up to three additional source clocks. + This is done by setting the corresponding GPIO pin(s) to native function to use as + SRCCLK_OE[6..9]. In addition, SRCCLK6 does not need to be set to free running clock. + If any of SRCCLKReq 6..9 is asserted, SRCCLK6 will be turned on. config MAX_PCIE_CLOCK_REQ int |