diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2016-08-06 13:41:51 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-08-09 01:31:59 +0200 |
| commit | 0c634159a35ff567fc4897df25dddddd181a1a8c (patch) | |
| tree | 95314a0c45f2a7c8dff4e30d419163b85f45bcee /src | |
| parent | e67cd9ee909e1ac415711fec243a0ca0a47d87fd (diff) | |
mainboard/google/rush_ryu: remove rush_ryu mainboard
The rush_ryu board was a development platform that never made it into
a product. Remove it as it's not available to anyone.
BUG=chrome-os-partner:55932
Change-Id: Ia3836ff8cade3009730543177a66736ae197572b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16107
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src')
29 files changed, 0 insertions, 4003 deletions
diff --git a/src/mainboard/google/rush_ryu/Kconfig b/src/mainboard/google/rush_ryu/Kconfig deleted file mode 100644 index 7b559a92f6..0000000000 --- a/src/mainboard/google/rush_ryu/Kconfig +++ /dev/null @@ -1,99 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright 2014 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -if BOARD_GOOGLE_RUSH_RYU - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select BOARD_ID_AUTO - select EC_GOOGLE_CHROMEEC - select EC_GOOGLE_CHROMEEC_I2C - select EC_GOOGLE_CHROMEEC_I2C_PROTO3 - select MAINBOARD_HAS_NATIVE_VGA_INIT - select MAINBOARD_DO_NATIVE_VGA_INIT - select SPI_FLASH - select SOC_NVIDIA_TEGRA132 - select MAINBOARD_DO_DSI_INIT - select MAINBOARD_HAS_CHROMEOS - select BOARD_ROMSIZE_KB_8192 - -config CHROMEOS - select EC_SOFTWARE_SYNC - select VBOOT_VBNV_EC - select VIRTUAL_DEV_SWITCH - -config MAINBOARD_DIR - string - default google/rush_ryu - -config MAINBOARD_PART_NUMBER - string - default "Rush Ryu" - -choice - prompt "BCT boot media" - default RUSH_RYU_BCT_CFG_SPI - help - Which boot media to configure the BCT for. - -config RUSH_RYU_BCT_CFG_SPI - bool "SPI" - help - Configure the BCT for booting from SPI. - -config RUSH_RYU_BCT_CFG_EMMC - bool "eMMC" - help - Configure the BCT for booting from eMMC. - -endchoice - -config BOOT_MEDIA_SPI_BUS - int "SPI bus with boot media ROM" - range 1 6 - depends on RUSH_RYU_BCT_CFG_SPI - default 4 - help - Which SPI bus the boot media is connected to. - -config BOOT_MEDIA_SPI_CHIP_SELECT - int "Chip select for SPI boot media" - range 0 3 - depends on RUSH_RYU_BCT_CFG_SPI - default 0 - help - Which chip select to use for boot media. - -config DRIVER_TPM_I2C_BUS - hex - default 0x2 - -config DRIVER_TPM_I2C_ADDR - hex - default 0x20 - -config EC_GOOGLE_CHROMEEC_I2C_BUS - hex - default 1 - -config EC_GOOGLE_CHROMEEC_BOARDNAME - string - default "ryu" - -config GBB_HWID - string - depends on CHROMEOS - default "RYU TEST 9382" -endif # BOARD_GOOGLE_RUSH_RYU diff --git a/src/mainboard/google/rush_ryu/Kconfig.name b/src/mainboard/google/rush_ryu/Kconfig.name deleted file mode 100644 index a616f23fdb..0000000000 --- a/src/mainboard/google/rush_ryu/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_GOOGLE_RUSH_RYU - bool "Rush Ryu" diff --git a/src/mainboard/google/rush_ryu/Makefile.inc b/src/mainboard/google/rush_ryu/Makefile.inc deleted file mode 100644 index 6c63eedefd..0000000000 --- a/src/mainboard/google/rush_ryu/Makefile.inc +++ /dev/null @@ -1,49 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright 2014 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# Add a handler for BCT config files -$(call add-special-class,bct-cfg) -bct-cfg-handler= $(eval $(obj)/generated/bct.cfg: $(1)$(2)) - -$(obj)/generated/bct.cfg: - @printf " CAT $(subst $(obj)/,,$(@))\n" - cat $^ > $@ - -subdirs-y += bct - -bootblock-y += bootblock.c -bootblock-y += pmic.c -bootblock-y += reset.c - -verstage-y += verstage.c -verstage-y += chromeos.c -verstage-y += reset.c - -romstage-y += chromeos.c -romstage-y += pmic.c -romstage-y += reset.c -romstage-y += romstage.c -romstage-y += sdram_configs.c - -ramstage-y += boardid.c -ramstage-y += mainboard.c -ramstage-y += reset.c -ramstage-y += chromeos.c -ramstage-y += pmic.c - -bootblock-y += memlayout.ld -romstage-y += memlayout.ld -ramstage-y += memlayout.ld -verstage-y += memlayout.ld diff --git a/src/mainboard/google/rush_ryu/bct/Makefile.inc b/src/mainboard/google/rush_ryu/bct/Makefile.inc deleted file mode 100644 index c677751b83..0000000000 --- a/src/mainboard/google/rush_ryu/bct/Makefile.inc +++ /dev/null @@ -1,25 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright 2014 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -bct-cfg-$(CONFIG_RUSH_RYU_BCT_CFG_EMMC) += emmc.cfg -bct-cfg-$(CONFIG_RUSH_RYU_BCT_CFG_SPI) += spi.cfg -bct-cfg-y += odmdata.cfg -bct-cfg-y += jtag.cfg -#NOTE: When full LPDDR3 SDRAM config is done in bootblock, remove this -bct-cfg-$(CONFIG_BOOTROM_SDRAM_INIT) += sdram-4GB-924.cfg - -# Note when SDRAM config (sdram-*.cfg) files are changed, we have to regenerate -# the include files (sdram-*.inc) by running "./cfg2inc.sh sdram-*.cfg". -# TODO(hungte) Change cfg2inc.sh to NVIDIA's official tool in cbootimage. diff --git a/src/mainboard/google/rush_ryu/bct/cfg2inc.sh b/src/mainboard/google/rush_ryu/bct/cfg2inc.sh deleted file mode 100755 index 0d0369746c..0000000000 --- a/src/mainboard/google/rush_ryu/bct/cfg2inc.sh +++ /dev/null @@ -1,30 +0,0 @@ -#!/bin/sh -# -# This file is part of the coreboot project. -# -# Copyright 2014 Google Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. - -bct_cfg2inc() { - local in_file="$1" - local out_file="$2" - echo "{ /* generated from ${in_file}; do not edit. */" >"${out_file}" - # Note currently we can only handle DDR3 type memory, even in C - # implementation. - sed "/^#.*$/d; s/^SDRAM.0./ /; s/\r$//; s/;$/,/;" \ - "${in_file}" >> "${out_file}" - echo "}," >>"${out_file}" -} - -for file in $@; do - echo "Generating $file => ${file%cfg}inc..." - bct_cfg2inc "${file}" "${file%cfg}inc" -done diff --git a/src/mainboard/google/rush_ryu/bct/emmc.cfg b/src/mainboard/google/rush_ryu/bct/emmc.cfg deleted file mode 100644 index 430ffd6d4b..0000000000 --- a/src/mainboard/google/rush_ryu/bct/emmc.cfg +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2013 The Chromium OS Authors. All rights reserved. -# Distributed under the terms of the GNU General Public License v2 - -Version = 0x00130001; -BlockSize = 0x00004000; -PageSize = 0x00000200; -PartitionSize = 0x01000000; - -DevType[0] = NvBootDevType_Sdmmc; -DeviceParam[0].SdmmcParams.ClockDivider = 0x00000009; -DeviceParam[0].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_8Bit; -DeviceParam[0].SdmmcParams.MaxPowerClassSupported = 0x00000000; -DeviceParam[0].SdmmcParams.MultiPageSupport = 0x00000000; diff --git a/src/mainboard/google/rush_ryu/bct/jtag.cfg b/src/mainboard/google/rush_ryu/bct/jtag.cfg deleted file mode 100644 index f43e143377..0000000000 --- a/src/mainboard/google/rush_ryu/bct/jtag.cfg +++ /dev/null @@ -1,16 +0,0 @@ -# -# Set JtagCtrl to 1 to reenable Jtag -# -JtagCtrl = 0; -# -# Fill in chip unique id -# -# ChipUid can be found by running tegrarcm in tegra recovery mode -# (also hooking up A-A USB cable) and looking for console output -# on line starting with "Chip UID:" -# -# Command example: -# $ sudo tegrarcm --bct=/build/nyan/firmware/bct/board.bct --bootloader=/build/nyan/firmware/u-boot.bin --loadaddr=0x80108000 -# Where board.bct and u-boot.bin do not have to be prebuilt. -# -ChipUid = 0x00000000000000000000000000000000; diff --git a/src/mainboard/google/rush_ryu/bct/odmdata.cfg b/src/mainboard/google/rush_ryu/bct/odmdata.cfg deleted file mode 100644 index d0ab2bf8fb..0000000000 --- a/src/mainboard/google/rush_ryu/bct/odmdata.cfg +++ /dev/null @@ -1 +0,0 @@ -OdmData = 0x80080000; diff --git a/src/mainboard/google/rush_ryu/bct/sdram-4GB-924.cfg b/src/mainboard/google/rush_ryu/bct/sdram-4GB-924.cfg deleted file mode 100644 index 4291a0b669..0000000000 --- a/src/mainboard/google/rush_ryu/bct/sdram-4GB-924.cfg +++ /dev/null @@ -1,1387 +0,0 @@ -# CFG Version SEC02 - Samsung_4GB_K4E6E304ED-EGCF -# Do not edit. Generated by T132_emc_reg_toolV6.0.4 V6.0.4. Command: -# T132_emc_reg_toolV6.0.4 -i Samsung_4GB_K4E6E304ED-EGCF_lpddr3.par -b A44_924MHz_emc_reg.txt 1.08225 -# -o A44_64_924_tool_emcregtoolv4.cfg -dram_board_cfg 3 -round_trip_dly_ps 589.6 -# Parameter file: Samsung_4GB_K4E6E304ED-EGCF_lpddr3.par, tck = 1.08 ns (924.00 MHz) -# bkv file: A44_924MHz_emc_reg.txt -SDRAM[0].MemoryType = NvBootMemoryType_LpDdr2; -SDRAM[0].PllMInputDivider = 0x00000001; -SDRAM[0].PllMFeedbackDivider = 0x0000004d; -SDRAM[0].PllMStableTime = 0x0000012c; -SDRAM[0].PllMSetupControl = 0x00000000; -SDRAM[0].PllMSelectDiv2 = 0x00000000; -SDRAM[0].PllMPDLshiftPh45 = 0x00000001; -SDRAM[0].PllMPDLshiftPh90 = 0x00000001; -SDRAM[0].PllMPDLshiftPh135 = 0x00000001; -SDRAM[0].PllMKCP = 0x00000000; -SDRAM[0].PllMKVCO = 0x00000000; -SDRAM[0].EmcBctSpare0 = 0x00000000; -SDRAM[0].EmcBctSpare1 = 0x00000000; -SDRAM[0].EmcBctSpare2 = 0x00000000; -SDRAM[0].EmcBctSpare3 = 0x00000000; -SDRAM[0].EmcBctSpare4 = 0x00000000; -SDRAM[0].EmcBctSpare5 = 0x00000000; -SDRAM[0].EmcBctSpare6 = 0x00000000; -SDRAM[0].EmcBctSpare7 = 0x00000000; -SDRAM[0].EmcBctSpare8 = 0x00000000; -SDRAM[0].EmcBctSpare9 = 0x00000000; -SDRAM[0].EmcBctSpare10 = 0x00000000; -SDRAM[0].EmcBctSpare11 = 0x00000000; -SDRAM[0].EmcClockSource = 0x80000000; -SDRAM[0].EmcAutoCalInterval = 0x001fffff; -SDRAM[0].EmcAutoCalConfig = 0xa1430000; -SDRAM[0].EmcAutoCalConfig2 = 0x00000000; -SDRAM[0].EmcAutoCalConfig3 = 0x00000000; -SDRAM[0].EmcAutoCalWait = 0x00000190; -SDRAM[0].EmcAdrCfg = 0x00000001; -SDRAM[0].EmcPinProgramWait = 0x00000000; -SDRAM[0].EmcPinExtraWait = 0x00000000; -SDRAM[0].EmcTimingControlWait = 0x00000000; -SDRAM[0].EmcRc = 0x00000037; -SDRAM[0].EmcRfc = 0x00000078; -SDRAM[0].EmcRfcSlr = 0x00000000; -SDRAM[0].EmcRas = 0x00000026; -SDRAM[0].EmcRp = 0x00000010; -SDRAM[0].EmcR2r = 0x00000000; -SDRAM[0].EmcW2w = 0x00000000; -SDRAM[0].EmcR2w = 0x00000010; -SDRAM[0].EmcW2r = 0x00000010; -SDRAM[0].EmcR2p = 0x00000006; -SDRAM[0].EmcW2p = 0x00000017; -SDRAM[0].EmcRdRcd = 0x00000010; -SDRAM[0].EmcWrRcd = 0x00000010; -SDRAM[0].EmcRrd = 0x00000009; -SDRAM[0].EmcRext = 0x00000005; -SDRAM[0].EmcWext = 0x00000000; -SDRAM[0].EmcWdv = 0x00000007; -SDRAM[0].EmcWdvMask = 0x00000007; -SDRAM[0].EmcQUse = 0x00000011; -SDRAM[0].EmcQuseWidth = 0x00000004; -SDRAM[0].EmcIbdly = 0x00000000; -SDRAM[0].EmcEInput = 0x00000006; -SDRAM[0].EmcEInputDuration = 0x00000011; -SDRAM[0].EmcPutermExtra = 0x000e0000; -SDRAM[0].EmcPutermWidth = 0x00000006; -SDRAM[0].EmcPutermAdj = 0x00000000; -SDRAM[0].EmcCdbCntl1 = 0x00000000; -SDRAM[0].EmcCdbCntl2 = 0x00000000; -SDRAM[0].EmcCdbCntl3 = 0x00000000; -SDRAM[0].EmcQRst = 0x00000005; -SDRAM[0].EmcQSafe = 0x00000018; -SDRAM[0].EmcRdv = 0x00000020; -SDRAM[0].EmcRdvMask = 0x00000022; -SDRAM[0].EmcQpop = 0x00000017; -SDRAM[0].EmcCtt = 0x00000000; -SDRAM[0].EmcCttDuration = 0x00000006; -SDRAM[0].EmcRefresh = 0x00000dd4; -SDRAM[0].EmcBurstRefreshNum = 0x00000000; -SDRAM[0].EmcPreRefreshReqCnt = 0x00000375; -SDRAM[0].EmcPdEx2Wr = 0x00000006; -SDRAM[0].EmcPdEx2Rd = 0x00000006; -SDRAM[0].EmcPChg2Pden = 0x00000010; -SDRAM[0].EmcAct2Pden = 0x00000000; -SDRAM[0].EmcAr2Pden = 0x00000001; -SDRAM[0].EmcRw2Pden = 0x0000001b; -SDRAM[0].EmcTxsr = 0x00000082; -SDRAM[0].EmcTxsrDll = 0x00000082; -SDRAM[0].EmcTcke = 0x00000007; -SDRAM[0].EmcTckesr = 0x0000000e; -SDRAM[0].EmcTpd = 0x00000007; -SDRAM[0].EmcTfaw = 0x0000002d; -SDRAM[0].EmcTrpab = 0x00000014; -SDRAM[0].EmcTClkStable = 0x00000003; -SDRAM[0].EmcTClkStop = 0x00000003; -SDRAM[0].EmcTRefBw = 0x00000f04; -SDRAM[0].EmcFbioCfg5 = 0x1363a896; -SDRAM[0].EmcFbioCfg6 = 0x00000000; -SDRAM[0].EmcFbioSpare = 0x00000000; -SDRAM[0].EmcCfgRsv = 0xff00ff00; -SDRAM[0].EmcMrs = 0x00000000; -SDRAM[0].EmcEmrs = 0x00000000; -SDRAM[0].EmcEmrs2 = 0x00000000; -SDRAM[0].EmcEmrs3 = 0x00000000; -SDRAM[0].EmcMrw1 = 0x00010083; -SDRAM[0].EmcMrw2 = 0x0002001c; -SDRAM[0].EmcMrw3 = 0x00030001; -SDRAM[0].EmcMrw4 = 0x800b0000; -SDRAM[0].EmcMrwExtra = 0x00010083; -SDRAM[0].EmcWarmBootMrwExtra = 0x0002001c; -SDRAM[0].EmcWarmBootExtraModeRegWriteEnable = 0x00000000; -SDRAM[0].EmcExtraModeRegWriteEnable = 0x00000000; -SDRAM[0].EmcMrwResetCommand = 0x003f00fc; -SDRAM[0].EmcMrwResetNInitWait = 0x0000000a; -SDRAM[0].EmcMrsWaitCnt = 0x039c0019; -SDRAM[0].EmcMrsWaitCnt2 = 0x039c0019; -SDRAM[0].EmcCfg = 0xf3300000; -SDRAM[0].EmcCfg2 = 0x0000089f; -SDRAM[0].EmcCfgPipe = 0x00004080; -SDRAM[0].EmcDbg = 0x01000c00; -SDRAM[0].EmcCmdQ = 0x10004408; -SDRAM[0].EmcMc2EmcQ = 0x06000404; -SDRAM[0].EmcDynSelfRefControl = 0x80001c77; -SDRAM[0].AhbArbitrationXbarCtrlMemInitDone = 0x00000001; -SDRAM[0].EmcCfgDigDll = 0xe00400b9; -SDRAM[0].EmcCfgDigDllPeriod = 0x00008000; -SDRAM[0].EmcDevSelect = 0x00000000; -SDRAM[0].EmcSelDpdCtrl = 0x0004001c; -SDRAM[0].EmcDllXformDqs0 = 0x007fc00a; ##0x007f400a; -SDRAM[0].EmcDllXformDqs1 = 0x007fc00a; ##0x007f400a; -SDRAM[0].EmcDllXformDqs2 = 0x007fc00a; ##0x007f400a; -SDRAM[0].EmcDllXformDqs3 = 0x007fc00a; ##0x007f400a; -SDRAM[0].EmcDllXformDqs4 = 0x007f800c; ##0x007f800a; ##0x007f400a; -SDRAM[0].EmcDllXformDqs5 = 0x00000008; ##0x007fc008; ##0x007f400a; -SDRAM[0].EmcDllXformDqs6 = 0x007f800a; ##0x007f400a; -SDRAM[0].EmcDllXformDqs7 = 0x007fc00a; ##0x007f800a; ##0x007f400a; -SDRAM[0].EmcDllXformDqs8 = 0x007f400a; -SDRAM[0].EmcDllXformDqs9 = 0x007f400a; -SDRAM[0].EmcDllXformDqs10 = 0x007f400a; -SDRAM[0].EmcDllXformDqs11 = 0x007f400a; -SDRAM[0].EmcDllXformDqs12 = 0x007f400a; -SDRAM[0].EmcDllXformDqs13 = 0x007f400a; -SDRAM[0].EmcDllXformDqs14 = 0x007f400a; -SDRAM[0].EmcDllXformDqs15 = 0x007f400a; -SDRAM[0].EmcDllXformQUse0 = 0x00000000; -SDRAM[0].EmcDllXformQUse1 = 0x00000000; -SDRAM[0].EmcDllXformQUse2 = 0x00000000; -SDRAM[0].EmcDllXformQUse3 = 0x00000000; -SDRAM[0].EmcDllXformQUse4 = 0x00000000; -SDRAM[0].EmcDllXformQUse5 = 0x00000000; -SDRAM[0].EmcDllXformQUse6 = 0x00000000; -SDRAM[0].EmcDllXformQUse7 = 0x00000000; -SDRAM[0].EmcDllXformAddr0 = 0x00018002; ##0x00020000; ##0x0001c000 -SDRAM[0].EmcDllXformAddr1 = 0x00018002; ##0x00020000; ##0x0001c000 -SDRAM[0].EmcDllXformAddr2 = 0x00000008; ##0x00000006 -SDRAM[0].EmcDllXformAddr3 = 0x00018002; ##0x00020000; ##0x0001c000 -SDRAM[0].EmcDllXformAddr4 = 0x00018002; ##0x00020000; ##0x0001c000 -SDRAM[0].EmcDllXformAddr5 = 0x00000008; ##0x00000006 -SDRAM[0].EmcDllXformQUse8 = 0x00000000; -SDRAM[0].EmcDllXformQUse9 = 0x00000000; -SDRAM[0].EmcDllXformQUse10 = 0x00000000; -SDRAM[0].EmcDllXformQUse11 = 0x00000000; -SDRAM[0].EmcDllXformQUse12 = 0x00000000; -SDRAM[0].EmcDllXformQUse13 = 0x00000000; -SDRAM[0].EmcDllXformQUse14 = 0x00000000; -SDRAM[0].EmcDllXformQUse15 = 0x00000000; -SDRAM[0].EmcDliTrimTxDqs0 = 0x00000008; -SDRAM[0].EmcDliTrimTxDqs1 = 0x00000008; -SDRAM[0].EmcDliTrimTxDqs2 = 0x00000008; -SDRAM[0].EmcDliTrimTxDqs3 = 0x00000008; -SDRAM[0].EmcDliTrimTxDqs4 = 0x00000008; -SDRAM[0].EmcDliTrimTxDqs5 = 0x00000008; -SDRAM[0].EmcDliTrimTxDqs6 = 0x00000008; -SDRAM[0].EmcDliTrimTxDqs7 = 0x00000008; -SDRAM[0].EmcDliTrimTxDqs8 = 0x00000008; -SDRAM[0].EmcDliTrimTxDqs9 = 0x00000008; -SDRAM[0].EmcDliTrimTxDqs10 = 0x00000008; -SDRAM[0].EmcDliTrimTxDqs11 = 0x00000008; -SDRAM[0].EmcDliTrimTxDqs12 = 0x00000008; -SDRAM[0].EmcDliTrimTxDqs13 = 0x00000008; -SDRAM[0].EmcDliTrimTxDqs14 = 0x00000008; -SDRAM[0].EmcDliTrimTxDqs15 = 0x00000008; -SDRAM[0].EmcDllXformDq0 = 0x0000000c; -SDRAM[0].EmcDllXformDq1 = 0x0000000c; -SDRAM[0].EmcDllXformDq2 = 0x0000000c; -SDRAM[0].EmcDllXformDq3 = 0x0000000c; -SDRAM[0].EmcDllXformDq4 = 0x0000000c; -SDRAM[0].EmcDllXformDq5 = 0x0000000c; -SDRAM[0].EmcDllXformDq6 = 0x0000000c; -SDRAM[0].EmcDllXformDq7 = 0x0000000c; -SDRAM[0].WarmBootWait = 0x00000001; -SDRAM[0].EmcCttTermCtrl = 0x00000802; -SDRAM[0].EmcOdtWrite = 0x00000000; -SDRAM[0].EmcOdtRead = 0x00000000; -SDRAM[0].EmcZcalInterval = 0x00064000; -SDRAM[0].EmcZcalWaitCnt = 0x00000058; -SDRAM[0].EmcZcalMrwCmd = 0x000a0056; -SDRAM[0].EmcMrsResetDll = 0x00000000; -SDRAM[0].EmcZcalInitDev0 = 0x840a00ff; -SDRAM[0].EmcZcalInitDev1 = 0x440a00ff; -SDRAM[0].EmcZcalInitWait = 0x00000001; -SDRAM[0].EmcZcalWarmColdBootEnables = 0x00000003; -SDRAM[0].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab; -SDRAM[0].EmcZqCalDdr3WarmBoot = 0x00000000; -SDRAM[0].EmcZcalWarmBootWait = 0x00000001; -SDRAM[0].EmcMrsWarmBootEnable = 0x00000001; -SDRAM[0].EmcMrsResetDllWait = 0x00000000; -SDRAM[0].EmcMrsExtra = 0x00000000; -SDRAM[0].EmcWarmBootMrsExtra = 0x00000000; -SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000; -SDRAM[0].EmcMrsDdr2DllReset = 0x00000000; -SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000; -SDRAM[0].EmcDdr2Wait = 0x00000000; -SDRAM[0].EmcClkenOverride = 0x00000000; -SDRAM[0].McDisExtraSnapLevels = 0x00000000; -SDRAM[0].EmcExtraRefreshNum = 0x00000002; -SDRAM[0].EmcClkenOverrideAllWarmBoot = 0x00000000; -SDRAM[0].McClkenOverrideAllWarmBoot = 0x00000000; -SDRAM[0].EmcCfgDigDllPeriodWarmBoot = 0x00000003; -SDRAM[0].PmcVddpSel = 0x00000001; -SDRAM[0].PmcVddpSelWait = 0x00000002; -SDRAM[0].PmcDdrPwr = 0x00000003; -SDRAM[0].PmcDdrCfg = 0x00001000; -SDRAM[0].PmcIoDpd3Req = 0x4ffefef7; -SDRAM[0].PmcIoDpd3ReqWait = 0x00000000; -SDRAM[0].PmcRegShort = 0x0000330f; -SDRAM[0].PmcNoIoPower = 0x00000000; -SDRAM[0].PmcPorDpdCtrlWait = 0x00000001; -SDRAM[0].EmcXm2CmdPadCtrl = 0x00000220; -SDRAM[0].EmcXm2CmdPadCtrl2 = 0x770c0000; -SDRAM[0].EmcXm2CmdPadCtrl3 = 0x050c0000; -SDRAM[0].EmcXm2CmdPadCtrl4 = 0x00000000; -SDRAM[0].EmcXm2CmdPadCtrl5 = 0x00100100; -SDRAM[0].EmcXm2DqsPadCtrl = 0x770c1414; -SDRAM[0].EmcXm2DqsPadCtrl2 = 0x0120103d; -SDRAM[0].EmcXm2DqsPadCtrl3 = 0x55555520; ##0x65965920; -SDRAM[0].EmcXm2DqsPadCtrl4 = 0x00596596; -SDRAM[0].EmcXm2DqsPadCtrl5 = 0x00596596; -SDRAM[0].EmcXm2DqsPadCtrl6 = 0x55555500; ##0x65965900; -SDRAM[0].EmcXm2DqPadCtrl = 0x770c2990; -SDRAM[0].EmcXm2DqPadCtrl2 = 0x00000000; -SDRAM[0].EmcXm2DqPadCtrl3 = 0x00000000; -SDRAM[0].EmcXm2ClkPadCtrl = 0x77ffc004; -SDRAM[0].EmcXm2ClkPadCtrl2 = 0x00000000; -SDRAM[0].EmcXm2CompPadCtrl = 0x81f1f008; -SDRAM[0].EmcXm2VttGenPadCtrl = 0x07070000; -SDRAM[0].EmcXm2VttGenPadCtrl2 = 0x00000000; -SDRAM[0].EmcXm2VttGenPadCtrl3 = 0x015ddddd; -SDRAM[0].EmcAcpdControl = 0x00000000; -SDRAM[0].EmcSwizzleRank0ByteCfg = 0x00001032; -SDRAM[0].EmcSwizzleRank0Byte0 = 0x53067142; -SDRAM[0].EmcSwizzleRank0Byte1 = 0x73025146; -SDRAM[0].EmcSwizzleRank0Byte2 = 0x20136475; -SDRAM[0].EmcSwizzleRank0Byte3 = 0x46273150; -SDRAM[0].EmcSwizzleRank1ByteCfg = 0x00003210; -SDRAM[0].EmcSwizzleRank1Byte0 = 0x73451026; -SDRAM[0].EmcSwizzleRank1Byte1 = 0x73025146; -SDRAM[0].EmcSwizzleRank1Byte2 = 0x20641735; -SDRAM[0].EmcSwizzleRank1Byte3 = 0x42136075; -SDRAM[0].EmcDsrVttgenDrv = 0x0000003f; -SDRAM[0].EmcTxdsrvttgen = 0x00000000; -SDRAM[0].EmcBgbiasCtl0 = 0x00000000; -SDRAM[0].McEmemAdrCfg = 0x00000001; -SDRAM[0].McEmemAdrCfgDev0 = 0x00080304; -SDRAM[0].McEmemAdrCfgDev1 = 0x00080304; -SDRAM[0].McEmemAdrCfgBankMask0 = 0x00001248; -SDRAM[0].McEmemAdrCfgBankMask1 = 0x00002490; -SDRAM[0].McEmemAdrCfgBankMask2 = 0x00000920; -SDRAM[0].McEmemAdrCfgBankSwizzle3 = 0x00000001; -SDRAM[0].McEmemCfg = 0x00001000; -SDRAM[0].McEmemArbCfg = 0x0e00000d; -SDRAM[0].McEmemArbOutstandingReq = 0x80000040; -SDRAM[0].McEmemArbTimingRcd = 0x00000007; -SDRAM[0].McEmemArbTimingRp = 0x00000008; -SDRAM[0].McEmemArbTimingRc = 0x0000001b; -SDRAM[0].McEmemArbTimingRas = 0x00000012; -SDRAM[0].McEmemArbTimingFaw = 0x00000017; -SDRAM[0].McEmemArbTimingRrd = 0x00000004; -SDRAM[0].McEmemArbTimingRap2Pre = 0x00000004; -SDRAM[0].McEmemArbTimingWap2Pre = 0x0000000e; -SDRAM[0].McEmemArbTimingR2R = 0x00000004; -SDRAM[0].McEmemArbTimingW2W = 0x00000001; -SDRAM[0].McEmemArbTimingR2W = 0x00000009; -SDRAM[0].McEmemArbTimingW2R = 0x00000009; -SDRAM[0].McEmemArbDaTurns = 0x09090104; -SDRAM[0].McEmemArbDaCovers = 0x001e141b; -SDRAM[0].McEmemArbMisc0 = 0x71ae2a1c; -SDRAM[0].McEmemArbMisc1 = 0x70000f02; -SDRAM[0].McEmemArbRing1Throttle = 0x001f0000; -SDRAM[0].McEmemArbOverride = 0x10000000; -SDRAM[0].McEmemArbOverride1 = 0x00000000; -SDRAM[0].McEmemArbRsv = 0xff00ff00; -SDRAM[0].McClkenOverride = 0x00000000; -SDRAM[0].McStatControl = 0x00000000; -SDRAM[0].McDisplaySnapRing = 0x00000003; -SDRAM[0].McVideoProtectBom = 0xfff00000; -SDRAM[0].McVideoProtectBomAdrHi = 0x00000000; -SDRAM[0].McVideoProtectSizeMb = 0x00000000; -SDRAM[0].McVideoProtectVprOverride = 0xe4bac743; -SDRAM[0].McVideoProtectVprOverride1 = 0x00000013; -SDRAM[0].McVideoProtectGpuOverride0 = 0x00000000; -SDRAM[0].McVideoProtectGpuOverride1 = 0x00000000; -SDRAM[0].McSecCarveoutBom = 0xfff00000; -SDRAM[0].McSecCarveoutAdrHi = 0x00000000; -SDRAM[0].McSecCarveoutSizeMb = 0x00000000; -SDRAM[0].McVideoProtectWriteAccess = 0x00000000; -SDRAM[0].McSecCarveoutProtectWriteAccess = 0x00000000; -SDRAM[0].EmcCaTrainingEnable = 0x00000001; -SDRAM[0].EmcCaTrainingTimingCntl1 = 0x09257359; -SDRAM[0].EmcCaTrainingTimingCntl2 = 0x00000017; -SDRAM[0].SwizzleRankByteEncode = 0x00000008; -SDRAM[0].BootRomPatchControl = 0x00000000; -SDRAM[0].BootRomPatchData = 0x00000000; -SDRAM[0].McMtsCarveoutBom = 0x78000000; -SDRAM[0].McMtsCarveoutAdrHi = 0x00000001; -SDRAM[0].McMtsCarveoutSizeMb = 0x00000080; -SDRAM[0].McMtsCarveoutRegCtrl = 0x00000001; -#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x00000017; -#@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x000001bb; -#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x006e0038; -#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x006e0038; -#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x006e003c; -#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x006e0090; -#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x006e0041; -#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x006e0090; -#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x006e0041; -#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049; -#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x006e0080; -#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x006e0004; -#@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x006e0004; -#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080016; -#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x0000006e; -#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x006e0004; -#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x006e0019; -#@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x006e0018; -#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x006e0024; -#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x006e001b; -#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x0000006e; -#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036; -#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x006e006e; -#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036; -#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x006e006e; -#@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff; -#@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029; -#@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x006e006e; -#@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x006e006e; -#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x006e0065; -#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x006e001c; -# -# CFG Version 01 HYNIX -# Do not edit. Generated by T132_emc_reg_toolV6.0.4 V6.0.4. Command: -# T132_emc_reg_toolV6.0.4 -i denali_sil_lpddr3_edfa232a2ma_4GB_X64_933.par -b A44_924MHz_emc_reg.txt 1.08225 -# -o A44_64_924_tool_emcregtoolv4.cfg -dram_board_cfg 3 -round_trip_dly_ps 589.6 -# Parameter file: denali_sil_lpddr3_edfa232a2ma_4GB_X64_933.par, tck = 1.08 ns (924.00 MHz) -# bkv file: A44_924MHz_emc_reg.txt -SDRAM[1].MemoryType = NvBootMemoryType_LpDdr2; -SDRAM[1].PllMInputDivider = 0x00000001; -SDRAM[1].PllMFeedbackDivider = 0x0000004d; -SDRAM[1].PllMStableTime = 0x0000012c; -SDRAM[1].PllMSetupControl = 0x00000000; -SDRAM[1].PllMSelectDiv2 = 0x00000000; -SDRAM[1].PllMPDLshiftPh45 = 0x00000001; -SDRAM[1].PllMPDLshiftPh90 = 0x00000001; -SDRAM[1].PllMPDLshiftPh135 = 0x00000001; -SDRAM[1].PllMKCP = 0x00000000; -SDRAM[1].PllMKVCO = 0x00000000; -SDRAM[1].EmcBctSpare0 = 0x00000000; -SDRAM[1].EmcBctSpare1 = 0x00000000; -SDRAM[1].EmcBctSpare2 = 0x00000000; -SDRAM[1].EmcBctSpare3 = 0x00000000; -SDRAM[1].EmcBctSpare4 = 0x00000000; -SDRAM[1].EmcBctSpare5 = 0x00000000; -SDRAM[1].EmcBctSpare6 = 0x00000000; -SDRAM[1].EmcBctSpare7 = 0x00000000; -SDRAM[1].EmcBctSpare8 = 0x00000000; -SDRAM[1].EmcBctSpare9 = 0x00000000; -SDRAM[1].EmcBctSpare10 = 0x00000000; -SDRAM[1].EmcBctSpare11 = 0x00000000; -SDRAM[1].EmcClockSource = 0x80000000; -SDRAM[1].EmcAutoCalInterval = 0x001fffff; -SDRAM[1].EmcAutoCalConfig = 0xa1430000; -SDRAM[1].EmcAutoCalConfig2 = 0x00000000; -SDRAM[1].EmcAutoCalConfig3 = 0x00000000; -SDRAM[1].EmcAutoCalWait = 0x00000190; -SDRAM[1].EmcAdrCfg = 0x00000001; -SDRAM[1].EmcPinProgramWait = 0x00000000; -SDRAM[1].EmcPinExtraWait = 0x00000000; -SDRAM[1].EmcTimingControlWait = 0x00000000; -SDRAM[1].EmcRc = 0x00000037; -SDRAM[1].EmcRfc = 0x00000078; -SDRAM[1].EmcRfcSlr = 0x00000000; -SDRAM[1].EmcRas = 0x00000026; -SDRAM[1].EmcRp = 0x00000010; -SDRAM[1].EmcR2r = 0x00000000; -SDRAM[1].EmcW2w = 0x00000000; -SDRAM[1].EmcR2w = 0x00000010; -SDRAM[1].EmcW2r = 0x00000010; -SDRAM[1].EmcR2p = 0x00000006; -SDRAM[1].EmcW2p = 0x00000017; -SDRAM[1].EmcRdRcd = 0x00000010; -SDRAM[1].EmcWrRcd = 0x00000010; -SDRAM[1].EmcRrd = 0x00000009; -SDRAM[1].EmcRext = 0x00000005; -SDRAM[1].EmcWext = 0x00000000; -SDRAM[1].EmcWdv = 0x00000007; -SDRAM[1].EmcWdvMask = 0x00000007; -SDRAM[1].EmcQUse = 0x00000011; -SDRAM[1].EmcQuseWidth = 0x00000004; -SDRAM[1].EmcIbdly = 0x00000000; -SDRAM[1].EmcEInput = 0x00000006; -SDRAM[1].EmcEInputDuration = 0x00000011; -SDRAM[1].EmcPutermExtra = 0x000e0000; -SDRAM[1].EmcPutermWidth = 0x00000006; -SDRAM[1].EmcPutermAdj = 0x00000000; -SDRAM[1].EmcCdbCntl1 = 0x00000000; -SDRAM[1].EmcCdbCntl2 = 0x00000000; -SDRAM[1].EmcCdbCntl3 = 0x00000000; -SDRAM[1].EmcQRst = 0x00000005; -SDRAM[1].EmcQSafe = 0x00000018; -SDRAM[1].EmcRdv = 0x00000020; -SDRAM[1].EmcRdvMask = 0x00000022; -SDRAM[1].EmcQpop = 0x00000017; -SDRAM[1].EmcCtt = 0x00000000; -SDRAM[1].EmcCttDuration = 0x00000006; -SDRAM[1].EmcRefresh = 0x00000dd4; -SDRAM[1].EmcBurstRefreshNum = 0x00000000; -SDRAM[1].EmcPreRefreshReqCnt = 0x00000375; -SDRAM[1].EmcPdEx2Wr = 0x00000006; -SDRAM[1].EmcPdEx2Rd = 0x00000006; -SDRAM[1].EmcPChg2Pden = 0x00000010; -SDRAM[1].EmcAct2Pden = 0x00000000; -SDRAM[1].EmcAr2Pden = 0x00000001; -SDRAM[1].EmcRw2Pden = 0x0000001b; -SDRAM[1].EmcTxsr = 0x00000082; -SDRAM[1].EmcTxsrDll = 0x00000082; -SDRAM[1].EmcTcke = 0x00000007; -SDRAM[1].EmcTckesr = 0x0000000e; -SDRAM[1].EmcTpd = 0x00000007; -SDRAM[1].EmcTfaw = 0x0000002d; -SDRAM[1].EmcTrpab = 0x00000014; -SDRAM[1].EmcTClkStable = 0x00000003; -SDRAM[1].EmcTClkStop = 0x00000003; -SDRAM[1].EmcTRefBw = 0x00000f04; -SDRAM[1].EmcFbioCfg5 = 0x1363a896; -SDRAM[1].EmcFbioCfg6 = 0x00000000; -SDRAM[1].EmcFbioSpare = 0x00000000; -SDRAM[1].EmcCfgRsv = 0xff00ff00; -SDRAM[1].EmcMrs = 0x00000000; -SDRAM[1].EmcEmrs = 0x00000000; -SDRAM[1].EmcEmrs2 = 0x00000000; -SDRAM[1].EmcEmrs3 = 0x00000000; -SDRAM[1].EmcMrw1 = 0x00010083; -SDRAM[1].EmcMrw2 = 0x0002001c; -SDRAM[1].EmcMrw3 = 0x00030001; -SDRAM[1].EmcMrw4 = 0x800b0000; -SDRAM[1].EmcMrwExtra = 0x00010083; -SDRAM[1].EmcWarmBootMrwExtra = 0x0002001c; -SDRAM[1].EmcWarmBootExtraModeRegWriteEnable = 0x00000000; -SDRAM[1].EmcExtraModeRegWriteEnable = 0x00000000; -SDRAM[1].EmcMrwResetCommand = 0x003f00fc; -SDRAM[1].EmcMrwResetNInitWait = 0x0000000a; -SDRAM[1].EmcMrsWaitCnt = 0x039c0019; -SDRAM[1].EmcMrsWaitCnt2 = 0x039c0019; -SDRAM[1].EmcCfg = 0xd3300000; -SDRAM[1].EmcCfg2 = 0x0000089f; -SDRAM[1].EmcCfgPipe = 0x00004080; -SDRAM[1].EmcDbg = 0x01000c00; -SDRAM[1].EmcCmdQ = 0x10004408; -SDRAM[1].EmcMc2EmcQ = 0x06000404; -SDRAM[1].EmcDynSelfRefControl = 0x80001c77; -SDRAM[1].AhbArbitrationXbarCtrlMemInitDone = 0x00000001; -SDRAM[1].EmcCfgDigDll = 0xe00400b9; -SDRAM[1].EmcCfgDigDllPeriod = 0x00008000; -SDRAM[1].EmcDevSelect = 0x00000000; -SDRAM[1].EmcSelDpdCtrl = 0x0004001c; -SDRAM[1].EmcDllXformDqs0 = 0x0000000a; ##0x007fc008; ##0x0000000a; -SDRAM[1].EmcDllXformDqs1 = 0x0000000a; -SDRAM[1].EmcDllXformDqs2 = 0x0000000c; ##0x0000000a; -SDRAM[1].EmcDllXformDqs3 = 0x0000000a; ##0x007f800a; ##0x0000000a; -SDRAM[1].EmcDllXformDqs4 = 0x00000008; ##0x007fc00a; ##0x0000000a; -SDRAM[1].EmcDllXformDqs5 = 0x00004008; ##0x0000000a; -SDRAM[1].EmcDllXformDqs6 = 0x0000000a; ##0x0000000a; -SDRAM[1].EmcDllXformDqs7 = 0x00000008; ##0x007f800a; ##0x0000000a; -SDRAM[1].EmcDllXformDqs8 = 0x0000000a; -SDRAM[1].EmcDllXformDqs9 = 0x0000000a; -SDRAM[1].EmcDllXformDqs10 = 0x0000000a; -SDRAM[1].EmcDllXformDqs11 = 0x0000000a; -SDRAM[1].EmcDllXformDqs12 = 0x0000000a; -SDRAM[1].EmcDllXformDqs13 = 0x0000000a; -SDRAM[1].EmcDllXformDqs14 = 0x0000000a; -SDRAM[1].EmcDllXformDqs15 = 0x0000000a; -SDRAM[1].EmcDllXformQUse0 = 0x00000000; -SDRAM[1].EmcDllXformQUse1 = 0x00000000; -SDRAM[1].EmcDllXformQUse2 = 0x00000000; -SDRAM[1].EmcDllXformQUse3 = 0x00000000; -SDRAM[1].EmcDllXformQUse4 = 0x00000000; -SDRAM[1].EmcDllXformQUse5 = 0x00000000; -SDRAM[1].EmcDllXformQUse6 = 0x00000000; -SDRAM[1].EmcDllXformQUse7 = 0x00000000; -SDRAM[1].EmcDllXformAddr0 = 0x00024002; ##0x00028002; ##0x00020000; -SDRAM[1].EmcDllXformAddr1 = 0x00024002; ##0x00028002; ##0x00020000; -SDRAM[1].EmcDllXformAddr2 = 0x00000008; ##0x00000006 -SDRAM[1].EmcDllXformAddr3 = 0x00024002; ##0x00028002; ##0x00020000; -SDRAM[1].EmcDllXformAddr4 = 0x00024002; ##0x00028002; ##0x00020000; -SDRAM[1].EmcDllXformAddr5 = 0x00000008; ##0x00000006 -SDRAM[1].EmcDllXformQUse8 = 0x00000000; -SDRAM[1].EmcDllXformQUse9 = 0x00000000; -SDRAM[1].EmcDllXformQUse10 = 0x00000000; -SDRAM[1].EmcDllXformQUse11 = 0x00000000; -SDRAM[1].EmcDllXformQUse12 = 0x00000000; -SDRAM[1].EmcDllXformQUse13 = 0x00000000; -SDRAM[1].EmcDllXformQUse14 = 0x00000000; -SDRAM[1].EmcDllXformQUse15 = 0x00000000; -SDRAM[1].EmcDliTrimTxDqs0 = 0x00000008; -SDRAM[1].EmcDliTrimTxDqs1 = 0x00000008; -SDRAM[1].EmcDliTrimTxDqs2 = 0x00000008; -SDRAM[1].EmcDliTrimTxDqs3 = 0x00000008; -SDRAM[1].EmcDliTrimTxDqs4 = 0x00000008; -SDRAM[1].EmcDliTrimTxDqs5 = 0x00000008; -SDRAM[1].EmcDliTrimTxDqs6 = 0x00000008; -SDRAM[1].EmcDliTrimTxDqs7 = 0x00000008; -SDRAM[1].EmcDliTrimTxDqs8 = 0x00000008; -SDRAM[1].EmcDliTrimTxDqs9 = 0x00000008; -SDRAM[1].EmcDliTrimTxDqs10 = 0x00000008; -SDRAM[1].EmcDliTrimTxDqs11 = 0x00000008; -SDRAM[1].EmcDliTrimTxDqs12 = 0x00000008; -SDRAM[1].EmcDliTrimTxDqs13 = 0x00000008; -SDRAM[1].EmcDliTrimTxDqs14 = 0x00000008; -SDRAM[1].EmcDliTrimTxDqs15 = 0x00000008; -SDRAM[1].EmcDllXformDq0 = 0x0000000e; ##0x0000000c; -SDRAM[1].EmcDllXformDq1 = 0x0000000e; ##0x0000000c; -SDRAM[1].EmcDllXformDq2 = 0x0000000e; ##0x0000000c; -SDRAM[1].EmcDllXformDq3 = 0x0000000e; ##0x0000000c; -SDRAM[1].EmcDllXformDq4 = 0x0000000e; ##0x0000000c; -SDRAM[1].EmcDllXformDq5 = 0x0000000e; ##0x0000000c; -SDRAM[1].EmcDllXformDq6 = 0x0000000e; ##0x0000000c; -SDRAM[1].EmcDllXformDq7 = 0x0000000e; ##0x0000000c; -SDRAM[1].WarmBootWait = 0x00000001; -SDRAM[1].EmcCttTermCtrl = 0x00000802; -SDRAM[1].EmcOdtWrite = 0x00000000; -SDRAM[1].EmcOdtRead = 0x00000000; -SDRAM[1].EmcZcalInterval = 0x00064000; -SDRAM[1].EmcZcalWaitCnt = 0x00000058; -SDRAM[1].EmcZcalMrwCmd = 0x000a0056; -SDRAM[1].EmcMrsResetDll = 0x00000000; -SDRAM[1].EmcZcalInitDev0 = 0x840a00ff; -SDRAM[1].EmcZcalInitDev1 = 0x440a00ff; -SDRAM[1].EmcZcalInitWait = 0x00000001; -SDRAM[1].EmcZcalWarmColdBootEnables = 0x00000003; -SDRAM[1].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab; -SDRAM[1].EmcZqCalDdr3WarmBoot = 0x00000000; -SDRAM[1].EmcZcalWarmBootWait = 0x00000001; -SDRAM[1].EmcMrsWarmBootEnable = 0x00000001; -SDRAM[1].EmcMrsResetDllWait = 0x00000000; -SDRAM[1].EmcMrsExtra = 0x00000000; -SDRAM[1].EmcWarmBootMrsExtra = 0x00000000; -SDRAM[1].EmcEmrsDdr2DllEnable = 0x00000000; -SDRAM[1].EmcMrsDdr2DllReset = 0x00000000; -SDRAM[1].EmcEmrsDdr2OcdCalib = 0x00000000; -SDRAM[1].EmcDdr2Wait = 0x00000000; -SDRAM[1].EmcClkenOverride = 0x00000000; -SDRAM[1].McDisExtraSnapLevels = 0x00000000; -SDRAM[1].EmcExtraRefreshNum = 0x00000002; -SDRAM[1].EmcClkenOverrideAllWarmBoot = 0x00000000; -SDRAM[1].McClkenOverrideAllWarmBoot = 0x00000000; -SDRAM[1].EmcCfgDigDllPeriodWarmBoot = 0x00000003; -SDRAM[1].PmcVddpSel = 0x00000001; -SDRAM[1].PmcVddpSelWait = 0x00000002; -SDRAM[1].PmcDdrPwr = 0x00000003; -SDRAM[1].PmcDdrCfg = 0x00001000; -SDRAM[1].PmcIoDpd3Req = 0x4ffefef7; -SDRAM[1].PmcIoDpd3ReqWait = 0x00000000; -SDRAM[1].PmcRegShort = 0x0000330f; -SDRAM[1].PmcNoIoPower = 0x00000000; -SDRAM[1].PmcPorDpdCtrlWait = 0x00000001; -SDRAM[1].EmcXm2CmdPadCtrl = 0x00000220; -SDRAM[1].EmcXm2CmdPadCtrl2 = 0x770c0000; -SDRAM[1].EmcXm2CmdPadCtrl3 = 0x050c0000; -SDRAM[1].EmcXm2CmdPadCtrl4 = 0x00000000; -SDRAM[1].EmcXm2CmdPadCtrl5 = 0x00100100; -SDRAM[1].EmcXm2DqsPadCtrl = 0x770c1414; -SDRAM[1].EmcXm2DqsPadCtrl2 = 0x0120103d; -SDRAM[1].EmcXm2DqsPadCtrl3 = 0x55555520; ##0x65965920; -SDRAM[1].EmcXm2DqsPadCtrl4 = 0x00492492; ##0x00596596; -SDRAM[1].EmcXm2DqsPadCtrl5 = 0x00492492; ##0x00596596; -SDRAM[1].EmcXm2DqsPadCtrl6 = 0x55555500; ##0x65965900; -SDRAM[1].EmcXm2DqPadCtrl = 0x770c2990; -SDRAM[1].EmcXm2DqPadCtrl2 = 0x00000000; -SDRAM[1].EmcXm2DqPadCtrl3 = 0x00000000; -SDRAM[1].EmcXm2ClkPadCtrl = 0x77ffc004; -SDRAM[1].EmcXm2ClkPadCtrl2 = 0x00000000; -SDRAM[1].EmcXm2CompPadCtrl = 0x81f1f008; -SDRAM[1].EmcXm2VttGenPadCtrl = 0x07070000; -SDRAM[1].EmcXm2VttGenPadCtrl2 = 0x00000000; -SDRAM[1].EmcXm2VttGenPadCtrl3 = 0x015ddddd; -SDRAM[1].EmcAcpdControl = 0x00000000; -SDRAM[1].EmcSwizzleRank0ByteCfg = 0x00001032; -SDRAM[1].EmcSwizzleRank0Byte0 = 0x53067142; -SDRAM[1].EmcSwizzleRank0Byte1 = 0x73025146; -SDRAM[1].EmcSwizzleRank0Byte2 = 0x20136475; -SDRAM[1].EmcSwizzleRank0Byte3 = 0x46273150; -SDRAM[1].EmcSwizzleRank1ByteCfg = 0x00003210; -SDRAM[1].EmcSwizzleRank1Byte0 = 0x73451026; -SDRAM[1].EmcSwizzleRank1Byte1 = 0x73025146; -SDRAM[1].EmcSwizzleRank1Byte2 = 0x20641735; -SDRAM[1].EmcSwizzleRank1Byte3 = 0x42136075; -SDRAM[1].EmcDsrVttgenDrv = 0x0000003f; -SDRAM[1].EmcTxdsrvttgen = 0x00000000; -SDRAM[1].EmcBgbiasCtl0 = 0x00000000; -SDRAM[1].McEmemAdrCfg = 0x00000001; -SDRAM[1].McEmemAdrCfgDev0 = 0x00080304; -SDRAM[1].McEmemAdrCfgDev1 = 0x00080304; -SDRAM[1].McEmemAdrCfgBankMask0 = 0x00001248; -SDRAM[1].McEmemAdrCfgBankMask1 = 0x00002490; -SDRAM[1].McEmemAdrCfgBankMask2 = 0x00000920; -SDRAM[1].McEmemAdrCfgBankSwizzle3 = 0x00000001; -SDRAM[1].McEmemCfg = 0x00001000; -SDRAM[1].McEmemArbCfg = 0x0e00000d; -SDRAM[1].McEmemArbOutstandingReq = 0x80000040; -SDRAM[1].McEmemArbTimingRcd = 0x00000007; -SDRAM[1].McEmemArbTimingRp = 0x00000008; -SDRAM[1].McEmemArbTimingRc = 0x0000001b; -SDRAM[1].McEmemArbTimingRas = 0x00000012; -SDRAM[1].McEmemArbTimingFaw = 0x00000017; -SDRAM[1].McEmemArbTimingRrd = 0x00000004; -SDRAM[1].McEmemArbTimingRap2Pre = 0x00000004; -SDRAM[1].McEmemArbTimingWap2Pre = 0x0000000e; -SDRAM[1].McEmemArbTimingR2R = 0x00000004; -SDRAM[1].McEmemArbTimingW2W = 0x00000001; -SDRAM[1].McEmemArbTimingR2W = 0x00000009; -SDRAM[1].McEmemArbTimingW2R = 0x00000009; -SDRAM[1].McEmemArbDaTurns = 0x09090104; -SDRAM[1].McEmemArbDaCovers = 0x001e141b; -SDRAM[1].McEmemArbMisc0 = 0x71ae2a1c; -SDRAM[1].McEmemArbMisc1 = 0x70000f02; -SDRAM[1].McEmemArbRing1Throttle = 0x001f0000; -SDRAM[1].McEmemArbOverride = 0x10000000; -SDRAM[1].McEmemArbOverride1 = 0x00000000; -SDRAM[1].McEmemArbRsv = 0xff00ff00; -SDRAM[1].McClkenOverride = 0x00000000; -SDRAM[1].McStatControl = 0x00000000; -SDRAM[1].McDisplaySnapRing = 0x00000003; -SDRAM[1].McVideoProtectBom = 0xfff00000; -SDRAM[1].McVideoProtectBomAdrHi = 0x00000000; -SDRAM[1].McVideoProtectSizeMb = 0x00000000; -SDRAM[1].McVideoProtectVprOverride = 0xe4bac743; -SDRAM[1].McVideoProtectVprOverride1 = 0x00000013; -SDRAM[1].McVideoProtectGpuOverride0 = 0x00000000; -SDRAM[1].McVideoProtectGpuOverride1 = 0x00000000; -SDRAM[1].McSecCarveoutBom = 0xfff00000; -SDRAM[1].McSecCarveoutAdrHi = 0x00000000; -SDRAM[1].McSecCarveoutSizeMb = 0x00000000; -SDRAM[1].McVideoProtectWriteAccess = 0x00000000; -SDRAM[1].McSecCarveoutProtectWriteAccess = 0x00000000; -SDRAM[1].EmcCaTrainingEnable = 0x00000001; -SDRAM[1].EmcCaTrainingTimingCntl1 = 0x09257359; -SDRAM[1].EmcCaTrainingTimingCntl2 = 0x00000017; -SDRAM[1].SwizzleRankByteEncode = 0x00000008; -SDRAM[1].BootRomPatchControl = 0x00000000; -SDRAM[1].BootRomPatchData = 0x00000000; -SDRAM[1].McMtsCarveoutBom = 0x78000000; -SDRAM[1].McMtsCarveoutAdrHi = 0x00000001; -SDRAM[1].McMtsCarveoutSizeMb = 0x00000080; -SDRAM[1].McMtsCarveoutRegCtrl = 0x00000001; -#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x00000017; -#@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x000001bb; -#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x006e0038; -#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x006e0038; -#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x006e003c; -#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x006e0090; -#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x006e0041; -#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x006e0090; -#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x006e0041; -#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049; -#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x006e0080; -#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x006e0004; -#@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x006e0004; -#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080016; -#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x0000006e; -#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x006e0004; -#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x006e0019; -#@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x006e0018; -#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x006e0024; -#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x006e001b; -#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x0000006e; -#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036; -#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x006e006e; -#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036; -#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x006e006e; -#@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff; -#@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029; -#@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x006e006e; -#@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x006e006e; -#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x006e0065; -#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x006e001c; -# -# CFG Version MICRON -# Do not edit. Generated by T132_emc_reg_toolV6.0.4 V6.0.4. Command: -# T132_emc_reg_toolV6.0.4 -i denali_sil_lpddr3_edfa232a2ma_4GB_X64_933.par -b A44_924MHz_emc_reg.txt 1.08225 -# -o A44_64_924_tool_emcregtoolv4.cfg -dram_board_cfg 3 -round_trip_dly_ps 589.6 -# Parameter file: denali_sil_lpddr3_edfa232a2ma_4GB_X64_933.par, tck = 1.08 ns (924.00 MHz) -# bkv file: A44_924MHz_emc_reg.txt -SDRAM[2].MemoryType = NvBootMemoryType_LpDdr2; -SDRAM[2].PllMInputDivider = 0x00000001; -SDRAM[2].PllMFeedbackDivider = 0x0000004d; -SDRAM[2].PllMStableTime = 0x0000012c; -SDRAM[2].PllMSetupControl = 0x00000000; -SDRAM[2].PllMSelectDiv2 = 0x00000000; -SDRAM[2].PllMPDLshiftPh45 = 0x00000001; -SDRAM[2].PllMPDLshiftPh90 = 0x00000001; -SDRAM[2].PllMPDLshiftPh135 = 0x00000001; -SDRAM[2].PllMKCP = 0x00000000; -SDRAM[2].PllMKVCO = 0x00000000; -SDRAM[2].EmcBctSpare0 = 0x00000000; -SDRAM[2].EmcBctSpare1 = 0x00000000; -SDRAM[2].EmcBctSpare2 = 0x00000000; -SDRAM[2].EmcBctSpare3 = 0x00000000; -SDRAM[2].EmcBctSpare4 = 0x00000000; -SDRAM[2].EmcBctSpare5 = 0x00000000; -SDRAM[2].EmcBctSpare6 = 0x00000000; -SDRAM[2].EmcBctSpare7 = 0x00000000; -SDRAM[2].EmcBctSpare8 = 0x00000000; -SDRAM[2].EmcBctSpare9 = 0x00000000; -SDRAM[2].EmcBctSpare10 = 0x00000000; -SDRAM[2].EmcBctSpare11 = 0x00000000; -SDRAM[2].EmcClockSource = 0x80000000; -SDRAM[2].EmcAutoCalInterval = 0x001fffff; -SDRAM[2].EmcAutoCalConfig = 0xa1430000; -SDRAM[2].EmcAutoCalConfig2 = 0x00000000; -SDRAM[2].EmcAutoCalConfig3 = 0x00000000; -SDRAM[2].EmcAutoCalWait = 0x00000190; -SDRAM[2].EmcAdrCfg = 0x00000001; -SDRAM[2].EmcPinProgramWait = 0x00000000; -SDRAM[2].EmcPinExtraWait = 0x00000000; -SDRAM[2].EmcTimingControlWait = 0x00000000; -SDRAM[2].EmcRc = 0x00000037; -SDRAM[2].EmcRfc = 0x00000078; -SDRAM[2].EmcRfcSlr = 0x00000000; -SDRAM[2].EmcRas = 0x00000026; -SDRAM[2].EmcRp = 0x00000010; -SDRAM[2].EmcR2r = 0x00000000; -SDRAM[2].EmcW2w = 0x00000000; -SDRAM[2].EmcR2w = 0x00000010; -SDRAM[2].EmcW2r = 0x00000010; -SDRAM[2].EmcR2p = 0x00000006; -SDRAM[2].EmcW2p = 0x00000017; -SDRAM[2].EmcRdRcd = 0x00000010; -SDRAM[2].EmcWrRcd = 0x00000010; -SDRAM[2].EmcRrd = 0x00000009; -SDRAM[2].EmcRext = 0x00000005; -SDRAM[2].EmcWext = 0x00000000; -SDRAM[2].EmcWdv = 0x00000007; -SDRAM[2].EmcWdvMask = 0x00000007; -SDRAM[2].EmcQUse = 0x00000011; -SDRAM[2].EmcQuseWidth = 0x00000004; -SDRAM[2].EmcIbdly = 0x00000000; -SDRAM[2].EmcEInput = 0x00000006; -SDRAM[2].EmcEInputDuration = 0x00000011; -SDRAM[2].EmcPutermExtra = 0x000e0000; -SDRAM[2].EmcPutermWidth = 0x00000006; -SDRAM[2].EmcPutermAdj = 0x00000000; -SDRAM[2].EmcCdbCntl1 = 0x00000000; -SDRAM[2].EmcCdbCntl2 = 0x00000000; -SDRAM[2].EmcCdbCntl3 = 0x00000000; -SDRAM[2].EmcQRst = 0x00000005; -SDRAM[2].EmcQSafe = 0x00000018; -SDRAM[2].EmcRdv = 0x00000020; -SDRAM[2].EmcRdvMask = 0x00000022; -SDRAM[2].EmcQpop = 0x00000017; -SDRAM[2].EmcCtt = 0x00000000; -SDRAM[2].EmcCttDuration = 0x00000006; -SDRAM[2].EmcRefresh = 0x00000dd4; -SDRAM[2].EmcBurstRefreshNum = 0x00000000; -SDRAM[2].EmcPreRefreshReqCnt = 0x00000375; -SDRAM[2].EmcPdEx2Wr = 0x00000006; -SDRAM[2].EmcPdEx2Rd = 0x00000006; -SDRAM[2].EmcPChg2Pden = 0x00000010; -SDRAM[2].EmcAct2Pden = 0x00000000; -SDRAM[2].EmcAr2Pden = 0x00000001; -SDRAM[2].EmcRw2Pden = 0x0000001b; -SDRAM[2].EmcTxsr = 0x00000082; -SDRAM[2].EmcTxsrDll = 0x00000082; -SDRAM[2].EmcTcke = 0x00000007; -SDRAM[2].EmcTckesr = 0x0000000e; -SDRAM[2].EmcTpd = 0x00000007; -SDRAM[2].EmcTfaw = 0x0000002d; -SDRAM[2].EmcTrpab = 0x00000014; -SDRAM[2].EmcTClkStable = 0x00000003; -SDRAM[2].EmcTClkStop = 0x00000003; -SDRAM[2].EmcTRefBw = 0x00000f04; -SDRAM[2].EmcFbioCfg5 = 0x1363a896; -SDRAM[2].EmcFbioCfg6 = 0x00000000; -SDRAM[2].EmcFbioSpare = 0x00000000; -SDRAM[2].EmcCfgRsv = 0xff00ff00; -SDRAM[2].EmcMrs = 0x00000000; -SDRAM[2].EmcEmrs = 0x00000000; -SDRAM[2].EmcEmrs2 = 0x00000000; -SDRAM[2].EmcEmrs3 = 0x00000000; -SDRAM[2].EmcMrw1 = 0x00010083; -SDRAM[2].EmcMrw2 = 0x0002001c; -SDRAM[2].EmcMrw3 = 0x00030001; -SDRAM[2].EmcMrw4 = 0x800b0000; -SDRAM[2].EmcMrwExtra = 0x00010083; -SDRAM[2].EmcWarmBootMrwExtra = 0x0002001c; -SDRAM[2].EmcWarmBootExtraModeRegWriteEnable = 0x00000000; -SDRAM[2].EmcExtraModeRegWriteEnable = 0x00000000; -SDRAM[2].EmcMrwResetCommand = 0x003f00fc; -SDRAM[2].EmcMrwResetNInitWait = 0x0000000a; -SDRAM[2].EmcMrsWaitCnt = 0x039c0019; -SDRAM[2].EmcMrsWaitCnt2 = 0x039c0019; -SDRAM[2].EmcCfg = 0xf3300000; -SDRAM[2].EmcCfg2 = 0x0000089f; -SDRAM[2].EmcCfgPipe = 0x00004080; -SDRAM[2].EmcDbg = 0x01000c00; -SDRAM[2].EmcCmdQ = 0x10004408; -SDRAM[2].EmcMc2EmcQ = 0x06000404; -SDRAM[2].EmcDynSelfRefControl = 0x80001c77; -SDRAM[2].AhbArbitrationXbarCtrlMemInitDone = 0x00000001; -SDRAM[2].EmcCfgDigDll = 0xe00400b9; -SDRAM[2].EmcCfgDigDllPeriod = 0x00008000; -SDRAM[2].EmcDevSelect = 0x00000000; -SDRAM[2].EmcSelDpdCtrl = 0x0004001c; -SDRAM[2].EmcDllXformDqs0 = 0x00004006; ##0x007f400a; -SDRAM[2].EmcDllXformDqs1 = 0x007f800c; ##0x007f400a; -SDRAM[2].EmcDllXformDqs2 = 0x007fc008; ##0x007f400a; -SDRAM[2].EmcDllXformDqs3 = 0x007f400c; ##0x007f400a; -SDRAM[2].EmcDllXformDqs4 = 0x007fc006; ##0x007f400a; -SDRAM[2].EmcDllXformDqs5 = 0x00000006; ##0x007f400a; -SDRAM[2].EmcDllXformDqs6 = 0x007f800a; ##0x007f400a; -SDRAM[2].EmcDllXformDqs7 = 0x007f800c; ##0x007f400a; -SDRAM[2].EmcDllXformDqs8 = 0x007f400a; -SDRAM[2].EmcDllXformDqs9 = 0x007f400a; -SDRAM[2].EmcDllXformDqs10 = 0x007f400a; -SDRAM[2].EmcDllXformDqs11 = 0x007f400a; -SDRAM[2].EmcDllXformDqs12 = 0x007f400a; -SDRAM[2].EmcDllXformDqs13 = 0x007f400a; -SDRAM[2].EmcDllXformDqs14 = 0x007f400a; -SDRAM[2].EmcDllXformDqs15 = 0x007f400a; -SDRAM[2].EmcDllXformQUse0 = 0x00000000; -SDRAM[2].EmcDllXformQUse1 = 0x00000000; -SDRAM[2].EmcDllXformQUse2 = 0x00000000; -SDRAM[2].EmcDllXformQUse3 = 0x00000000; -SDRAM[2].EmcDllXformQUse4 = 0x00000000; -SDRAM[2].EmcDllXformQUse5 = 0x00000000; -SDRAM[2].EmcDllXformQUse6 = 0x00000000; -SDRAM[2].EmcDllXformQUse7 = 0x00000000; -SDRAM[2].EmcDllXformAddr0 = 0x00018004; ##0x0001c000; -SDRAM[2].EmcDllXformAddr1 = 0x00018004; ##0x0001c000; -SDRAM[2].EmcDllXformAddr2 = 0x00000008; ##0x00000006; -SDRAM[2].EmcDllXformAddr3 = 0x00014004; ##0x0001c000; -SDRAM[2].EmcDllXformAddr4 = 0x0001c002; ##0x0001c000; -SDRAM[2].EmcDllXformAddr5 = 0x00000008; ##0x00000006; -SDRAM[2].EmcDllXformQUse8 = 0x00000000; -SDRAM[2].EmcDllXformQUse9 = 0x00000000; -SDRAM[2].EmcDllXformQUse10 = 0x00000000; -SDRAM[2].EmcDllXformQUse11 = 0x00000000; -SDRAM[2].EmcDllXformQUse12 = 0x00000000; -SDRAM[2].EmcDllXformQUse13 = 0x00000000; -SDRAM[2].EmcDllXformQUse14 = 0x00000000; -SDRAM[2].EmcDllXformQUse15 = 0x00000000; -SDRAM[2].EmcDliTrimTxDqs0 = 0x00000008; -SDRAM[2].EmcDliTrimTxDqs1 = 0x00000008; -SDRAM[2].EmcDliTrimTxDqs2 = 0x00000008; -SDRAM[2].EmcDliTrimTxDqs3 = 0x00000008; -SDRAM[2].EmcDliTrimTxDqs4 = 0x00000008; -SDRAM[2].EmcDliTrimTxDqs5 = 0x00000008; -SDRAM[2].EmcDliTrimTxDqs6 = 0x00000008; -SDRAM[2].EmcDliTrimTxDqs7 = 0x00000008; -SDRAM[2].EmcDliTrimTxDqs8 = 0x00000008; -SDRAM[2].EmcDliTrimTxDqs9 = 0x00000008; -SDRAM[2].EmcDliTrimTxDqs10 = 0x00000008; -SDRAM[2].EmcDliTrimTxDqs11 = 0x00000008; -SDRAM[2].EmcDliTrimTxDqs12 = 0x00000008; -SDRAM[2].EmcDliTrimTxDqs13 = 0x00000008; -SDRAM[2].EmcDliTrimTxDqs14 = 0x00000008; -SDRAM[2].EmcDliTrimTxDqs15 = 0x00000008; -SDRAM[2].EmcDllXformDq0 = 0x0000000a; -SDRAM[2].EmcDllXformDq1 = 0x0000000a; -SDRAM[2].EmcDllXformDq2 = 0x0000000a; -SDRAM[2].EmcDllXformDq3 = 0x0000000a; -SDRAM[2].EmcDllXformDq4 = 0x0000000a; -SDRAM[2].EmcDllXformDq5 = 0x0000000a; -SDRAM[2].EmcDllXformDq6 = 0x0000000a; -SDRAM[2].EmcDllXformDq7 = 0x0000000a; -SDRAM[2].WarmBootWait = 0x00000001; -SDRAM[2].EmcCttTermCtrl = 0x00000802; -SDRAM[2].EmcOdtWrite = 0x00000000; -SDRAM[2].EmcOdtRead = 0x00000000; -SDRAM[2].EmcZcalInterval = 0x00064000; -SDRAM[2].EmcZcalWaitCnt = 0x00000058; -SDRAM[2].EmcZcalMrwCmd = 0x000a0056; -SDRAM[2].EmcMrsResetDll = 0x00000000; -SDRAM[2].EmcZcalInitDev0 = 0x840a00ff; -SDRAM[2].EmcZcalInitDev1 = 0x440a00ff; -SDRAM[2].EmcZcalInitWait = 0x00000001; -SDRAM[2].EmcZcalWarmColdBootEnables = 0x00000003; -SDRAM[2].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab; -SDRAM[2].EmcZqCalDdr3WarmBoot = 0x00000000; -SDRAM[2].EmcZcalWarmBootWait = 0x00000001; -SDRAM[2].EmcMrsWarmBootEnable = 0x00000001; -SDRAM[2].EmcMrsResetDllWait = 0x00000000; -SDRAM[2].EmcMrsExtra = 0x00000000; -SDRAM[2].EmcWarmBootMrsExtra = 0x00000000; -SDRAM[2].EmcEmrsDdr2DllEnable = 0x00000000; -SDRAM[2].EmcMrsDdr2DllReset = 0x00000000; -SDRAM[2].EmcEmrsDdr2OcdCalib = 0x00000000; -SDRAM[2].EmcDdr2Wait = 0x00000000; -SDRAM[2].EmcClkenOverride = 0x00000000; -SDRAM[2].McDisExtraSnapLevels = 0x00000000; -SDRAM[2].EmcExtraRefreshNum = 0x00000002; -SDRAM[2].EmcClkenOverrideAllWarmBoot = 0x00000000; -SDRAM[2].McClkenOverrideAllWarmBoot = 0x00000000; -SDRAM[2].EmcCfgDigDllPeriodWarmBoot = 0x00000003; -SDRAM[2].PmcVddpSel = 0x00000001; -SDRAM[2].PmcVddpSelWait = 0x00000002; -SDRAM[2].PmcDdrPwr = 0x00000003; -SDRAM[2].PmcDdrCfg = 0x00001000; -SDRAM[2].PmcIoDpd3Req = 0x4ffefef7; -SDRAM[2].PmcIoDpd3ReqWait = 0x00000000; -SDRAM[2].PmcRegShort = 0x0000330f; -SDRAM[2].PmcNoIoPower = 0x00000000; -SDRAM[2].PmcPorDpdCtrlWait = 0x00000001; -SDRAM[2].EmcXm2CmdPadCtrl = 0x00000220; -SDRAM[2].EmcXm2CmdPadCtrl2 = 0x770c0000; -SDRAM[2].EmcXm2CmdPadCtrl3 = 0x050c0000; -SDRAM[2].EmcXm2CmdPadCtrl4 = 0x00000000; -SDRAM[2].EmcXm2CmdPadCtrl5 = 0x00100100; -SDRAM[2].EmcXm2DqsPadCtrl = 0x770c1414; -SDRAM[2].EmcXm2DqsPadCtrl2 = 0x0120103d; -SDRAM[2].EmcXm2DqsPadCtrl3 = 0x65965920; -SDRAM[2].EmcXm2DqsPadCtrl4 = 0x00596596; -SDRAM[2].EmcXm2DqsPadCtrl5 = 0x00596596; -SDRAM[2].EmcXm2DqsPadCtrl6 = 0x65965900; -SDRAM[2].EmcXm2DqPadCtrl = 0x770c2990; -SDRAM[2].EmcXm2DqPadCtrl2 = 0x00000000; -SDRAM[2].EmcXm2DqPadCtrl3 = 0x00000000; -SDRAM[2].EmcXm2ClkPadCtrl = 0x77ffc004; -SDRAM[2].EmcXm2ClkPadCtrl2 = 0x00000000; -SDRAM[2].EmcXm2CompPadCtrl = 0x81f1f008; -SDRAM[2].EmcXm2VttGenPadCtrl = 0x07070000; -SDRAM[2].EmcXm2VttGenPadCtrl2 = 0x00000000; -SDRAM[2].EmcXm2VttGenPadCtrl3 = 0x015ddddd; -SDRAM[2].EmcAcpdControl = 0x00000000; -SDRAM[2].EmcSwizzleRank0ByteCfg = 0x00001032; -SDRAM[2].EmcSwizzleRank0Byte0 = 0x53067142; -SDRAM[2].EmcSwizzleRank0Byte1 = 0x73025146; -SDRAM[2].EmcSwizzleRank0Byte2 = 0x20136475; -SDRAM[2].EmcSwizzleRank0Byte3 = 0x46273150; -SDRAM[2].EmcSwizzleRank1ByteCfg = 0x00003210; -SDRAM[2].EmcSwizzleRank1Byte0 = 0x73451026; -SDRAM[2].EmcSwizzleRank1Byte1 = 0x73025146; -SDRAM[2].EmcSwizzleRank1Byte2 = 0x20641735; -SDRAM[2].EmcSwizzleRank1Byte3 = 0x42136075; -SDRAM[2].EmcDsrVttgenDrv = 0x0000003f; -SDRAM[2].EmcTxdsrvttgen = 0x00000000; -SDRAM[2].EmcBgbiasCtl0 = 0x00000000; -SDRAM[2].McEmemAdrCfg = 0x00000001; -SDRAM[2].McEmemAdrCfgDev0 = 0x00080304; -SDRAM[2].McEmemAdrCfgDev1 = 0x00080304; -SDRAM[2].McEmemAdrCfgBankMask0 = 0x00001248; -SDRAM[2].McEmemAdrCfgBankMask1 = 0x00002490; -SDRAM[2].McEmemAdrCfgBankMask2 = 0x00000920; -SDRAM[2].McEmemAdrCfgBankSwizzle3 = 0x00000001; -SDRAM[2].McEmemCfg = 0x00001000; -SDRAM[2].McEmemArbCfg = 0x0e00000d; -SDRAM[2].McEmemArbOutstandingReq = 0x80000040; -SDRAM[2].McEmemArbTimingRcd = 0x00000007; -SDRAM[2].McEmemArbTimingRp = 0x00000008; -SDRAM[2].McEmemArbTimingRc = 0x0000001b; -SDRAM[2].McEmemArbTimingRas = 0x00000012; -SDRAM[2].McEmemArbTimingFaw = 0x00000017; -SDRAM[2].McEmemArbTimingRrd = 0x00000004; -SDRAM[2].McEmemArbTimingRap2Pre = 0x00000004; -SDRAM[2].McEmemArbTimingWap2Pre = 0x0000000e; -SDRAM[2].McEmemArbTimingR2R = 0x00000004; -SDRAM[2].McEmemArbTimingW2W = 0x00000001; -SDRAM[2].McEmemArbTimingR2W = 0x00000009; -SDRAM[2].McEmemArbTimingW2R = 0x00000009; -SDRAM[2].McEmemArbDaTurns = 0x09090104; -SDRAM[2].McEmemArbDaCovers = 0x001e141b; -SDRAM[2].McEmemArbMisc0 = 0x71ae2a1c; -SDRAM[2].McEmemArbMisc1 = 0x70000f02; -SDRAM[2].McEmemArbRing1Throttle = 0x001f0000; -SDRAM[2].McEmemArbOverride = 0x10000000; -SDRAM[2].McEmemArbOverride1 = 0x00000000; -SDRAM[2].McEmemArbRsv = 0xff00ff00; -SDRAM[2].McClkenOverride = 0x00000000; -SDRAM[2].McStatControl = 0x00000000; -SDRAM[2].McDisplaySnapRing = 0x00000003; -SDRAM[2].McVideoProtectBom = 0xfff00000; -SDRAM[2].McVideoProtectBomAdrHi = 0x00000000; -SDRAM[2].McVideoProtectSizeMb = 0x00000000; -SDRAM[2].McVideoProtectVprOverride = 0xe4bac743; -SDRAM[2].McVideoProtectVprOverride1 = 0x00000013; -SDRAM[2].McVideoProtectGpuOverride0 = 0x00000000; -SDRAM[2].McVideoProtectGpuOverride1 = 0x00000000; -SDRAM[2].McSecCarveoutBom = 0xfff00000; -SDRAM[2].McSecCarveoutAdrHi = 0x00000000; -SDRAM[2].McSecCarveoutSizeMb = 0x00000000; -SDRAM[2].McVideoProtectWriteAccess = 0x00000000; -SDRAM[2].McSecCarveoutProtectWriteAccess = 0x00000000; -SDRAM[2].EmcCaTrainingEnable = 0x00000001; -SDRAM[2].EmcCaTrainingTimingCntl1 = 0x09257359; -SDRAM[2].EmcCaTrainingTimingCntl2 = 0x00000017; -SDRAM[2].SwizzleRankByteEncode = 0x00000008; -SDRAM[2].BootRomPatchControl = 0x00000000; -SDRAM[2].BootRomPatchData = 0x00000000; -SDRAM[2].McMtsCarveoutBom = 0x78000000; -SDRAM[2].McMtsCarveoutAdrHi = 0x00000001; -SDRAM[2].McMtsCarveoutSizeMb = 0x00000080; -SDRAM[2].McMtsCarveoutRegCtrl = 0x00000001; -#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x00000017; -#@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x000001bb; -#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x006e0038; -#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x006e0038; -#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x006e003c; -#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x006e0090; -#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x006e0041; -#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x006e0090; -#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x006e0041; -#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049; -#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x006e0080; -#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x006e0004; -#@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x006e0004; -#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080016; -#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x0000006e; -#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x006e0004; -#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x006e0019; -#@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x006e0018; -#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x006e0024; -#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x006e001b; -#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x0000006e; -#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036; -#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x006e006e; -#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036; -#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x006e006e; -#@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff; -#@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029; -#@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x006e006e; -#@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x006e006e; -#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x006e0065; -#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x006e001c; -# -# CFG Version 01 Spare (using Micron part) -# Do not edit. Generated by T132_emc_reg_toolV6.0.4 V6.0.4. Command: -# T132_emc_reg_toolV6.0.4 -i denali_sil_lpddr3_edfa232a2ma_4GB_X64_933.par -b A44_528MHz_emc_reg.txt 1.89394 -# -o A44_64_528_tool_emcregtoolv4.cfg -dram_board_cfg 3 -round_trip_dly_ps 589.6 -# Parameter file: denali_sil_lpddr3_edfa232a2ma_4GB_X64_933.par, tck = 1.89 ns (528.00 MHz) -# bkv file: A44_528MHz_emc_reg.txt -SDRAM[3].MemoryType = NvBootMemoryType_LpDdr2; -SDRAM[3].PllMInputDivider = 0x00000001; -SDRAM[3].PllMFeedbackDivider = 0x0000002c; -SDRAM[3].PllMStableTime = 0x0000012c; -SDRAM[3].PllMSetupControl = 0x00000000; -SDRAM[3].PllMSelectDiv2 = 0x00000000; -SDRAM[3].PllMPDLshiftPh45 = 0x00000001; -SDRAM[3].PllMPDLshiftPh90 = 0x00000001; -SDRAM[3].PllMPDLshiftPh135 = 0x00000001; -SDRAM[3].PllMKCP = 0x00000000; -SDRAM[3].PllMKVCO = 0x00000000; -SDRAM[3].EmcBctSpare0 = 0x00000000; -SDRAM[3].EmcBctSpare1 = 0x00000000; -SDRAM[3].EmcBctSpare2 = 0x00000000; -SDRAM[3].EmcBctSpare3 = 0x00000000; -SDRAM[3].EmcBctSpare4 = 0x00000000; -SDRAM[3].EmcBctSpare5 = 0x00000000; -SDRAM[3].EmcBctSpare6 = 0x00000000; -SDRAM[3].EmcBctSpare7 = 0x00000000; -SDRAM[3].EmcBctSpare8 = 0x00000000; -SDRAM[3].EmcBctSpare9 = 0x00000000; -SDRAM[3].EmcBctSpare10 = 0x00000000; -SDRAM[3].EmcBctSpare11 = 0x00000000; -SDRAM[3].EmcClockSource = 0x80000000; -SDRAM[3].EmcAutoCalInterval = 0x001fffff; -SDRAM[3].EmcAutoCalConfig = 0xa1430000; -SDRAM[3].EmcAutoCalConfig2 = 0x00000000; -SDRAM[3].EmcAutoCalConfig3 = 0x00000000; -SDRAM[3].EmcAutoCalWait = 0x00000190; -SDRAM[3].EmcAdrCfg = 0x00000001; -SDRAM[3].EmcPinProgramWait = 0x00000000; -SDRAM[3].EmcPinExtraWait = 0x00000000; -SDRAM[3].EmcTimingControlWait = 0x00000000; -SDRAM[3].EmcRc = 0x0000001f; -SDRAM[3].EmcRfc = 0x00000044; -SDRAM[3].EmcRfcSlr = 0x00000000; -SDRAM[3].EmcRas = 0x00000016; -SDRAM[3].EmcRp = 0x00000009; -SDRAM[3].EmcR2r = 0x00000000; -SDRAM[3].EmcW2w = 0x00000000; -SDRAM[3].EmcR2w = 0x0000000a; -SDRAM[3].EmcW2r = 0x00000009; -SDRAM[3].EmcR2p = 0x00000003; -SDRAM[3].EmcW2p = 0x0000000d; -SDRAM[3].EmcRdRcd = 0x00000009; -SDRAM[3].EmcWrRcd = 0x00000009; -SDRAM[3].EmcRrd = 0x00000005; -SDRAM[3].EmcRext = 0x00000004; -SDRAM[3].EmcWext = 0x00000000; -SDRAM[3].EmcWdv = 0x00000002; -SDRAM[3].EmcWdvMask = 0x00000002; -SDRAM[3].EmcQUse = 0x00000008; -SDRAM[3].EmcQuseWidth = 0x00000003; -SDRAM[3].EmcIbdly = 0x00000000; -SDRAM[3].EmcEInput = 0x00000003; -SDRAM[3].EmcEInputDuration = 0x0000000a; -SDRAM[3].EmcPutermExtra = 0x00050000; -SDRAM[3].EmcPutermWidth = 0x00000004; -SDRAM[3].EmcPutermAdj = 0x00000000; -SDRAM[3].EmcCdbCntl1 = 0x00000000; -SDRAM[3].EmcCdbCntl2 = 0x00000000; -SDRAM[3].EmcCdbCntl3 = 0x00000000; -SDRAM[3].EmcQRst = 0x00000002; -SDRAM[3].EmcQSafe = 0x00000011; -SDRAM[3].EmcRdv = 0x00000015; -SDRAM[3].EmcRdvMask = 0x00000017; -SDRAM[3].EmcQpop = 0x0000000d; -SDRAM[3].EmcCtt = 0x00000000; -SDRAM[3].EmcCttDuration = 0x00000004; -SDRAM[3].EmcRefresh = 0x000007cd; -SDRAM[3].EmcBurstRefreshNum = 0x00000000; -SDRAM[3].EmcPreRefreshReqCnt = 0x000001f3; -SDRAM[3].EmcPdEx2Wr = 0x00000003; -SDRAM[3].EmcPdEx2Rd = 0x00000003; -SDRAM[3].EmcPChg2Pden = 0x00000009; -SDRAM[3].EmcAct2Pden = 0x00000000; -SDRAM[3].EmcAr2Pden = 0x00000001; -SDRAM[3].EmcRw2Pden = 0x00000011; -SDRAM[3].EmcTxsr = 0x0000004a; -SDRAM[3].EmcTxsrDll = 0x0000004a; -SDRAM[3].EmcTcke = 0x00000004; -SDRAM[3].EmcTckesr = 0x00000008; -SDRAM[3].EmcTpd = 0x00000004; -SDRAM[3].EmcTfaw = 0x00000019; -SDRAM[3].EmcTrpab = 0x0000000c; -SDRAM[3].EmcTClkStable = 0x00000003; -SDRAM[3].EmcTClkStop = 0x00000003; -SDRAM[3].EmcTRefBw = 0x00000895; -SDRAM[3].EmcFbioCfg5 = 0x1363a096; -SDRAM[3].EmcFbioCfg6 = 0x00000000; -SDRAM[3].EmcFbioSpare = 0x00000000; -SDRAM[3].EmcCfgRsv = 0xff00ff00; -SDRAM[3].EmcMrs = 0x00000000; -SDRAM[3].EmcEmrs = 0x00000000; -SDRAM[3].EmcEmrs2 = 0x00000000; -SDRAM[3].EmcEmrs3 = 0x00000000; -SDRAM[3].EmcMrw1 = 0x000100c3; -SDRAM[3].EmcMrw2 = 0x00020006; -SDRAM[3].EmcMrw3 = 0x00030001; -SDRAM[3].EmcMrw4 = 0x800b0000; -SDRAM[3].EmcMrwExtra = 0x000100c3; -SDRAM[3].EmcWarmBootMrwExtra = 0x00020006; -SDRAM[3].EmcWarmBootExtraModeRegWriteEnable = 0x00000000; -SDRAM[3].EmcExtraModeRegWriteEnable = 0x00000000; -SDRAM[3].EmcMrwResetCommand = 0x003f00fc; -SDRAM[3].EmcMrwResetNInitWait = 0x0000000a; -SDRAM[3].EmcMrsWaitCnt = 0x02100013; -SDRAM[3].EmcMrsWaitCnt2 = 0x02100013; -SDRAM[3].EmcCfg = 0xf3300000; -SDRAM[3].EmcCfg2 = 0x0000089f; -SDRAM[3].EmcCfgPipe = 0x000042a0; -SDRAM[3].EmcDbg = 0x01000c00; -SDRAM[3].EmcCmdQ = 0x10004408; -SDRAM[3].EmcMc2EmcQ = 0x06000404; -SDRAM[3].EmcDynSelfRefControl = 0x800010b3; -SDRAM[3].AhbArbitrationXbarCtrlMemInitDone = 0x00000001; -SDRAM[3].EmcCfgDigDll = 0xe01200b9; -SDRAM[3].EmcCfgDigDllPeriod = 0x00008000; -SDRAM[3].EmcDevSelect = 0x00000000; -SDRAM[3].EmcSelDpdCtrl = 0x0004001c; -SDRAM[3].EmcDllXformDqs0 = 0x007f400a; -SDRAM[3].EmcDllXformDqs1 = 0x007f400a; -SDRAM[3].EmcDllXformDqs2 = 0x007f400a; -SDRAM[3].EmcDllXformDqs3 = 0x007f400a; -SDRAM[3].EmcDllXformDqs4 = 0x007f400a; -SDRAM[3].EmcDllXformDqs5 = 0x007f400a; -SDRAM[3].EmcDllXformDqs6 = 0x007f400a; -SDRAM[3].EmcDllXformDqs7 = 0x007f400a; -SDRAM[3].EmcDllXformDqs8 = 0x007f400a; -SDRAM[3].EmcDllXformDqs9 = 0x007f400a; -SDRAM[3].EmcDllXformDqs10 = 0x007f400a; -SDRAM[3].EmcDllXformDqs11 = 0x007f400a; -SDRAM[3].EmcDllXformDqs12 = 0x007f400a; -SDRAM[3].EmcDllXformDqs13 = 0x007f400a; -SDRAM[3].EmcDllXformDqs14 = 0x007f400a; -SDRAM[3].EmcDllXformDqs15 = 0x007f400a; -SDRAM[3].EmcDllXformQUse0 = 0x00000000; -SDRAM[3].EmcDllXformQUse1 = 0x00000000; -SDRAM[3].EmcDllXformQUse2 = 0x00000000; -SDRAM[3].EmcDllXformQUse3 = 0x00000000; -SDRAM[3].EmcDllXformQUse4 = 0x00000000; -SDRAM[3].EmcDllXformQUse5 = 0x00000000; -SDRAM[3].EmcDllXformQUse6 = 0x00000000; -SDRAM[3].EmcDllXformQUse7 = 0x00000000; -SDRAM[3].EmcDllXformAddr0 = 0x00024000; -SDRAM[3].EmcDllXformAddr1 = 0x00024000; -SDRAM[3].EmcDllXformAddr2 = 0x00000006; -SDRAM[3].EmcDllXformAddr3 = 0x00024000; -SDRAM[3].EmcDllXformAddr4 = 0x00024000; -SDRAM[3].EmcDllXformAddr5 = 0x00000006; -SDRAM[3].EmcDllXformQUse8 = 0x00000000; -SDRAM[3].EmcDllXformQUse9 = 0x00000000; -SDRAM[3].EmcDllXformQUse10 = 0x00000000; -SDRAM[3].EmcDllXformQUse11 = 0x00000000; -SDRAM[3].EmcDllXformQUse12 = 0x00000000; -SDRAM[3].EmcDllXformQUse13 = 0x00000000; -SDRAM[3].EmcDllXformQUse14 = 0x00000000; -SDRAM[3].EmcDllXformQUse15 = 0x00000000; -SDRAM[3].EmcDliTrimTxDqs0 = 0x0000000b; -SDRAM[3].EmcDliTrimTxDqs1 = 0x0000000b; -SDRAM[3].EmcDliTrimTxDqs2 = 0x00000008; -SDRAM[3].EmcDliTrimTxDqs3 = 0x0000000b; -SDRAM[3].EmcDliTrimTxDqs4 = 0x0000000b; -SDRAM[3].EmcDliTrimTxDqs5 = 0x00000008; -SDRAM[3].EmcDliTrimTxDqs6 = 0x0000000b; -SDRAM[3].EmcDliTrimTxDqs7 = 0x0000000b; -SDRAM[3].EmcDliTrimTxDqs8 = 0x0000000b; -SDRAM[3].EmcDliTrimTxDqs9 = 0x0000000b; -SDRAM[3].EmcDliTrimTxDqs10 = 0x00000008; -SDRAM[3].EmcDliTrimTxDqs11 = 0x0000000b; -SDRAM[3].EmcDliTrimTxDqs12 = 0x0000000b; -SDRAM[3].EmcDliTrimTxDqs13 = 0x00000008; -SDRAM[3].EmcDliTrimTxDqs14 = 0x0000000b; -SDRAM[3].EmcDliTrimTxDqs15 = 0x0000000b; -SDRAM[3].EmcDllXformDq0 = 0x0000000c; -SDRAM[3].EmcDllXformDq1 = 0x0000000c; -SDRAM[3].EmcDllXformDq2 = 0x0000000c; -SDRAM[3].EmcDllXformDq3 = 0x0000000c; -SDRAM[3].EmcDllXformDq4 = 0x0000000c; -SDRAM[3].EmcDllXformDq5 = 0x0000000c; -SDRAM[3].EmcDllXformDq6 = 0x0000000c; -SDRAM[3].EmcDllXformDq7 = 0x0000000c; -SDRAM[3].WarmBootWait = 0x00000001; -SDRAM[3].EmcCttTermCtrl = 0x00000802; -SDRAM[3].EmcOdtWrite = 0x00000000; -SDRAM[3].EmcOdtRead = 0x00000000; -SDRAM[3].EmcZcalInterval = 0x00064000; -SDRAM[3].EmcZcalWaitCnt = 0x00000034; -SDRAM[3].EmcZcalMrwCmd = 0x000a0056; -SDRAM[3].EmcMrsResetDll = 0x00000000; -SDRAM[3].EmcZcalInitDev0 = 0x840a00ff; -SDRAM[3].EmcZcalInitDev1 = 0x440a00ff; -SDRAM[3].EmcZcalInitWait = 0x00000001; -SDRAM[3].EmcZcalWarmColdBootEnables = 0x00000003; -SDRAM[3].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab; -SDRAM[3].EmcZqCalDdr3WarmBoot = 0x00000000; -SDRAM[3].EmcZcalWarmBootWait = 0x00000001; -SDRAM[3].EmcMrsWarmBootEnable = 0x00000001; -SDRAM[3].EmcMrsResetDllWait = 0x00000000; -SDRAM[3].EmcMrsExtra = 0x00000000; -SDRAM[3].EmcWarmBootMrsExtra = 0x00000000; -SDRAM[3].EmcEmrsDdr2DllEnable = 0x00000000; -SDRAM[3].EmcMrsDdr2DllReset = 0x00000000; -SDRAM[3].EmcEmrsDdr2OcdCalib = 0x00000000; -SDRAM[3].EmcDdr2Wait = 0x00000000; -SDRAM[3].EmcClkenOverride = 0x00000000; -SDRAM[3].McDisExtraSnapLevels = 0x00000000; -SDRAM[3].EmcExtraRefreshNum = 0x00000002; -SDRAM[3].EmcClkenOverrideAllWarmBoot = 0x00000000; -SDRAM[3].McClkenOverrideAllWarmBoot = 0x00000000; -SDRAM[3].EmcCfgDigDllPeriodWarmBoot = 0x00000003; -SDRAM[3].PmcVddpSel = 0x00000001; -SDRAM[3].PmcVddpSelWait = 0x00000002; -SDRAM[3].PmcDdrPwr = 0x00000003; -SDRAM[3].PmcDdrCfg = 0x00001000; -SDRAM[3].PmcIoDpd3Req = 0x4ffefef7; -SDRAM[3].PmcIoDpd3ReqWait = 0x00000000; -SDRAM[3].PmcRegShort = 0x0000330f; -SDRAM[3].PmcNoIoPower = 0x00000000; -SDRAM[3].PmcPorDpdCtrlWait = 0x00000001; -SDRAM[3].EmcXm2CmdPadCtrl = 0x00000220; -SDRAM[3].EmcXm2CmdPadCtrl2 = 0x770c0000; -SDRAM[3].EmcXm2CmdPadCtrl3 = 0x050c0000; -SDRAM[3].EmcXm2CmdPadCtrl4 = 0x00000000; -SDRAM[3].EmcXm2CmdPadCtrl5 = 0x00100100; -SDRAM[3].EmcXm2DqsPadCtrl = 0x770c1414; -SDRAM[3].EmcXm2DqsPadCtrl2 = 0x0123123d; -SDRAM[3].EmcXm2DqsPadCtrl3 = 0x51451420; -SDRAM[3].EmcXm2DqsPadCtrl4 = 0x00514514; -SDRAM[3].EmcXm2DqsPadCtrl5 = 0x00514514; -SDRAM[3].EmcXm2DqsPadCtrl6 = 0x51451400; -SDRAM[3].EmcXm2DqPadCtrl = 0x770c2990; -SDRAM[3].EmcXm2DqPadCtrl2 = 0x00000000; -SDRAM[3].EmcXm2DqPadCtrl3 = 0x00000000; -SDRAM[3].EmcXm2ClkPadCtrl = 0x77ffc004; -SDRAM[3].EmcXm2ClkPadCtrl2 = 0x00000000; -SDRAM[3].EmcXm2CompPadCtrl = 0x81f1f008; -SDRAM[3].EmcXm2VttGenPadCtrl = 0x07070000; -SDRAM[3].EmcXm2VttGenPadCtrl2 = 0x0000003f; -SDRAM[3].EmcXm2VttGenPadCtrl3 = 0x015ddddd; -SDRAM[3].EmcAcpdControl = 0x00000000; -SDRAM[3].EmcSwizzleRank0ByteCfg = 0x00001032; -SDRAM[3].EmcSwizzleRank0Byte0 = 0x53067142; -SDRAM[3].EmcSwizzleRank0Byte1 = 0x73025146; -SDRAM[3].EmcSwizzleRank0Byte2 = 0x20136475; -SDRAM[3].EmcSwizzleRank0Byte3 = 0x46273150; -SDRAM[3].EmcSwizzleRank1ByteCfg = 0x00003210; -SDRAM[3].EmcSwizzleRank1Byte0 = 0x73451026; -SDRAM[3].EmcSwizzleRank1Byte1 = 0x73025146; -SDRAM[3].EmcSwizzleRank1Byte2 = 0x20641735; -SDRAM[3].EmcSwizzleRank1Byte3 = 0x42136075; -SDRAM[3].EmcDsrVttgenDrv = 0x0000003f; -SDRAM[3].EmcTxdsrvttgen = 0x00000000; -SDRAM[3].EmcBgbiasCtl0 = 0x00000000; -SDRAM[3].McEmemAdrCfg = 0x00000001; -SDRAM[3].McEmemAdrCfgDev0 = 0x00080304; -SDRAM[3].McEmemAdrCfgDev1 = 0x00080304; -SDRAM[3].McEmemAdrCfgBankMask0 = 0x00001248; -SDRAM[3].McEmemAdrCfgBankMask1 = 0x00002490; -SDRAM[3].McEmemAdrCfgBankMask2 = 0x00000920; -SDRAM[3].McEmemAdrCfgBankSwizzle3 = 0x00000001; -SDRAM[3].McEmemCfg = 0x00001000; -SDRAM[3].McEmemArbCfg = 0x0f000007; -SDRAM[3].McEmemArbOutstandingReq = 0x80000040; -SDRAM[3].McEmemArbTimingRcd = 0x00000003; -SDRAM[3].McEmemArbTimingRp = 0x00000004; -SDRAM[3].McEmemArbTimingRc = 0x00000010; -SDRAM[3].McEmemArbTimingRas = 0x0000000a; -SDRAM[3].McEmemArbTimingFaw = 0x0000000d; -SDRAM[3].McEmemArbTimingRrd = 0x00000002; -SDRAM[3].McEmemArbTimingRap2Pre = 0x00000002; -SDRAM[3].McEmemArbTimingWap2Pre = 0x00000009; -SDRAM[3].McEmemArbTimingR2R = 0x00000003; -SDRAM[3].McEmemArbTimingW2W = 0x00000001; -SDRAM[3].McEmemArbTimingR2W = 0x00000006; -SDRAM[3].McEmemArbTimingW2R = 0x00000006; -SDRAM[3].McEmemArbDaTurns = 0x06060103; -SDRAM[3].McEmemArbDaCovers = 0x00120b10; -SDRAM[3].McEmemArbMisc0 = 0x71c81811; -SDRAM[3].McEmemArbMisc1 = 0x70000f03; -SDRAM[3].McEmemArbRing1Throttle = 0x001f0000; -SDRAM[3].McEmemArbOverride = 0x10000000; -SDRAM[3].McEmemArbOverride1 = 0x00000000; -SDRAM[3].McEmemArbRsv = 0xff00ff00; -SDRAM[3].McClkenOverride = 0x00000000; -SDRAM[3].McStatControl = 0x00000000; -SDRAM[3].McDisplaySnapRing = 0x00000003; -SDRAM[3].McVideoProtectBom = 0xfff00000; -SDRAM[3].McVideoProtectBomAdrHi = 0x00000000; -SDRAM[3].McVideoProtectSizeMb = 0x00000000; -SDRAM[3].McVideoProtectVprOverride = 0xe4bac743; -SDRAM[3].McVideoProtectVprOverride1 = 0x00000013; -SDRAM[3].McVideoProtectGpuOverride0 = 0x00000000; -SDRAM[3].McVideoProtectGpuOverride1 = 0x00000000; -SDRAM[3].McSecCarveoutBom = 0xfff00000; -SDRAM[3].McSecCarveoutAdrHi = 0x00000000; -SDRAM[3].McSecCarveoutSizeMb = 0x00000000; -SDRAM[3].McVideoProtectWriteAccess = 0x00000000; -SDRAM[3].McSecCarveoutProtectWriteAccess = 0x00000000; -SDRAM[3].EmcCaTrainingEnable = 0x00000001; -SDRAM[3].EmcCaTrainingTimingCntl1 = 0x09257359; -SDRAM[3].EmcCaTrainingTimingCntl2 = 0x00000017; -SDRAM[3].SwizzleRankByteEncode = 0x00000008; -SDRAM[3].BootRomPatchControl = 0x00000000; -SDRAM[3].BootRomPatchData = 0x00000000; -SDRAM[3].McMtsCarveoutBom = 0x78000000; -SDRAM[3].McMtsCarveoutAdrHi = 0x00000001; -SDRAM[3].McMtsCarveoutSizeMb = 0x00000080; -SDRAM[3].McMtsCarveoutRegCtrl = 0x00000001; -#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x0000000d; -#@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x000000fd; -#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x00c10038; -#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x00c10038; -#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x00c1003c; -#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x00c10090; -#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x00c10041; -#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x00c10090; -#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x00c10041; -#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049; -#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x00c10080; -#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x00c10004; -#@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x00c10004; -#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080021; -#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x000000c1; -#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x00c10004; -#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x00c10026; -#@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x00c1001a; -#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x00c10024; -#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x00c10029; -#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x000000c1; -#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036; -#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x00c100c1; -#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036; -#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x00c100c1; -#@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff; -#@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029; -#@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x00c100c1; -#@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x00c100c1; -#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x00c10065; -#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x00c1002a; diff --git a/src/mainboard/google/rush_ryu/bct/sdram-hynix-4GB-924.inc b/src/mainboard/google/rush_ryu/bct/sdram-hynix-4GB-924.inc deleted file mode 100644 index bf40ef5b03..0000000000 --- a/src/mainboard/google/rush_ryu/bct/sdram-hynix-4GB-924.inc +++ /dev/null @@ -1,311 +0,0 @@ -{ /* generated from sdram-hynix-4GB-924.cfg; do not edit. This is Hynix LPDDR3 */ - .MemoryType = NvBootMemoryType_LpDdr2, - .PllMInputDivider = 0x00000001, - .PllMFeedbackDivider = 0x0000004d, - .PllMStableTime = 0x0000012c, - .PllMSetupControl = 0x00000000, - .PllMSelectDiv2 = 0x00000000, - .PllMPDLshiftPh45 = 0x00000001, - .PllMPDLshiftPh90 = 0x00000001, - .PllMPDLshiftPh135 = 0x00000001, - .PllMKCP = 0x00000000, - .PllMKVCO = 0x00000000, - .EmcBctSpare0 = 0x00000000, - .EmcBctSpare1 = 0x00000000, - .EmcBctSpare2 = 0x00000000, - .EmcBctSpare3 = 0x00000000, - .EmcBctSpare4 = 0x00000000, - .EmcBctSpare5 = 0x00000000, - .EmcBctSpare6 = 0x00000000, - .EmcBctSpare7 = 0x00000000, - .EmcBctSpare8 = 0x00000000, - .EmcBctSpare9 = 0x00000000, - .EmcBctSpare10 = 0x00000000, - .EmcBctSpare11 = 0x00000000, - .EmcClockSource = 0x80000000, - .EmcAutoCalInterval = 0x001fffff, - .EmcAutoCalConfig = 0xa1430000, - .EmcAutoCalConfig2 = 0x00000000, - .EmcAutoCalConfig3 = 0x00000000, - .EmcAutoCalWait = 0x00000190, - .EmcAdrCfg = 0x00000001, - .EmcPinProgramWait = 0x00000000, - .EmcPinExtraWait = 0x00000000, - .EmcTimingControlWait = 0x00000000, - .EmcRc = 0x00000037, - .EmcRfc = 0x00000078, - .EmcRfcSlr = 0x00000000, - .EmcRas = 0x00000026, - .EmcRp = 0x00000010, - .EmcR2r = 0x00000000, - .EmcW2w = 0x00000000, - .EmcR2w = 0x00000010, - .EmcW2r = 0x00000010, - .EmcR2p = 0x00000006, - .EmcW2p = 0x00000017, - .EmcRdRcd = 0x00000010, - .EmcWrRcd = 0x00000010, - .EmcRrd = 0x00000009, - .EmcRext = 0x00000005, - .EmcWext = 0x00000000, - .EmcWdv = 0x00000007, - .EmcWdvMask = 0x00000007, - .EmcQUse = 0x00000011, - .EmcQuseWidth = 0x00000004, - .EmcIbdly = 0x00000000, - .EmcEInput = 0x00000006, - .EmcEInputDuration = 0x00000011, - .EmcPutermExtra = 0x000e0000, - .EmcPutermWidth = 0x00000006, - .EmcPutermAdj = 0x00000000, - .EmcCdbCntl1 = 0x00000000, - .EmcCdbCntl2 = 0x00000000, - .EmcCdbCntl3 = 0x00000000, - .EmcQRst = 0x00000005, - .EmcQSafe = 0x00000018, - .EmcRdv = 0x00000020, - .EmcRdvMask = 0x00000022, - .EmcQpop = 0x00000017, - .EmcCtt = 0x00000000, - .EmcCttDuration = 0x00000006, - .EmcRefresh = 0x00000dd4, - .EmcBurstRefreshNum = 0x00000000, - .EmcPreRefreshReqCnt = 0x00000375, - .EmcPdEx2Wr = 0x00000006, - .EmcPdEx2Rd = 0x00000006, - .EmcPChg2Pden = 0x00000010, - .EmcAct2Pden = 0x00000000, - .EmcAr2Pden = 0x00000001, - .EmcRw2Pden = 0x0000001b, - .EmcTxsr = 0x00000082, - .EmcTxsrDll = 0x00000082, - .EmcTcke = 0x00000007, - .EmcTckesr = 0x0000000e, - .EmcTpd = 0x00000007, - .EmcTfaw = 0x0000002d, - .EmcTrpab = 0x00000014, - .EmcTClkStable = 0x00000003, - .EmcTClkStop = 0x00000003, - .EmcTRefBw = 0x00000f04, - .EmcFbioCfg5 = 0x1363a896, - .EmcFbioCfg6 = 0x00000000, - .EmcFbioSpare = 0x00000000, - .EmcCfgRsv = 0xff00ff00, - .EmcMrs = 0x00000000, - .EmcEmrs = 0x00000000, - .EmcEmrs2 = 0x00000000, - .EmcEmrs3 = 0x00000000, - .EmcMrw1 = 0x00010083, - .EmcMrw2 = 0x0002001c, - .EmcMrw3 = 0x00030001, - .EmcMrw4 = 0x800b0000, - .EmcMrwExtra = 0x00010083, - .EmcWarmBootMrwExtra = 0x0002001c, - .EmcWarmBootExtraModeRegWriteEnable = 0x00000000, - .EmcExtraModeRegWriteEnable = 0x00000000, - .EmcMrwResetCommand = 0x003f00fc, - .EmcMrwResetNInitWait = 0x0000000a, - .EmcMrsWaitCnt = 0x039c0019, - .EmcMrsWaitCnt2 = 0x039c0019, - .EmcCfg = 0xd3300000, - .EmcCfg2 = 0x0000089f, - .EmcCfgPipe = 0x00004080, - .EmcDbg = 0x01000c00, - .EmcCmdQ = 0x10004408, - .EmcMc2EmcQ = 0x06000404, - .EmcDynSelfRefControl = 0x80001c77, - .AhbArbitrationXbarCtrlMemInitDone = 0x00000001, - .EmcCfgDigDll = 0xe00400b9, - .EmcCfgDigDllPeriod = 0x00008000, - .EmcDevSelect = 0x00000000, - .EmcSelDpdCtrl = 0x0004001c, - .EmcDllXformDqs0 = 0x0000000a, - .EmcDllXformDqs1 = 0x0000000a, - .EmcDllXformDqs2 = 0x0000000c, - .EmcDllXformDqs3 = 0x0000000a, - .EmcDllXformDqs4 = 0x00000008, - .EmcDllXformDqs5 = 0x00004008, - .EmcDllXformDqs6 = 0x0000000a, - .EmcDllXformDqs7 = 0x00000008, - .EmcDllXformDqs8 = 0x0000000a, - .EmcDllXformDqs9 = 0x0000000a, - .EmcDllXformDqs10 = 0x0000000a, - .EmcDllXformDqs11 = 0x0000000a, - .EmcDllXformDqs12 = 0x0000000a, - .EmcDllXformDqs13 = 0x0000000a, - .EmcDllXformDqs14 = 0x0000000a, - .EmcDllXformDqs15 = 0x0000000a, - .EmcDllXformQUse0 = 0x00000000, - .EmcDllXformQUse1 = 0x00000000, - .EmcDllXformQUse2 = 0x00000000, - .EmcDllXformQUse3 = 0x00000000, - .EmcDllXformQUse4 = 0x00000000, - .EmcDllXformQUse5 = 0x00000000, - .EmcDllXformQUse6 = 0x00000000, - .EmcDllXformQUse7 = 0x00000000, - .EmcDllXformAddr0 = 0x00024002, - .EmcDllXformAddr1 = 0x00024002, - .EmcDllXformAddr2 = 0x00000008, - .EmcDllXformAddr3 = 0x00024002, - .EmcDllXformAddr4 = 0x00024002, - .EmcDllXformAddr5 = 0x00000008, - .EmcDllXformQUse8 = 0x00000000, - .EmcDllXformQUse9 = 0x00000000, - .EmcDllXformQUse10 = 0x00000000, - .EmcDllXformQUse11 = 0x00000000, - .EmcDllXformQUse12 = 0x00000000, - .EmcDllXformQUse13 = 0x00000000, - .EmcDllXformQUse14 = 0x00000000, - .EmcDllXformQUse15 = 0x00000000, - .EmcDliTrimTxDqs0 = 0x00000008, - .EmcDliTrimTxDqs1 = 0x00000008, - .EmcDliTrimTxDqs2 = 0x00000008, - .EmcDliTrimTxDqs3 = 0x00000008, - .EmcDliTrimTxDqs4 = 0x00000008, - .EmcDliTrimTxDqs5 = 0x00000008, - .EmcDliTrimTxDqs6 = 0x00000008, - .EmcDliTrimTxDqs7 = 0x00000008, - .EmcDliTrimTxDqs8 = 0x00000008, - .EmcDliTrimTxDqs9 = 0x00000008, - .EmcDliTrimTxDqs10 = 0x00000008, - .EmcDliTrimTxDqs11 = 0x00000008, - .EmcDliTrimTxDqs12 = 0x00000008, - .EmcDliTrimTxDqs13 = 0x00000008, - .EmcDliTrimTxDqs14 = 0x00000008, - .EmcDliTrimTxDqs15 = 0x00000008, - .EmcDllXformDq0 = 0x0000000e, - .EmcDllXformDq1 = 0x0000000e, - .EmcDllXformDq2 = 0x0000000e, - .EmcDllXformDq3 = 0x0000000e, - .EmcDllXformDq4 = 0x0000000e, - .EmcDllXformDq5 = 0x0000000e, - .EmcDllXformDq6 = 0x0000000e, - .EmcDllXformDq7 = 0x0000000e, - .WarmBootWait = 0x00000001, - .EmcCttTermCtrl = 0x00000802, - .EmcOdtWrite = 0x00000000, - .EmcOdtRead = 0x00000000, - .EmcZcalInterval = 0x00064000, - .EmcZcalWaitCnt = 0x00000058, - .EmcZcalMrwCmd = 0x000a0056, - .EmcMrsResetDll = 0x00000000, - .EmcZcalInitDev0 = 0x840a00ff, - .EmcZcalInitDev1 = 0x440a00ff, - .EmcZcalInitWait = 0x00000001, - .EmcZcalWarmColdBootEnables = 0x00000003, - .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab, - .EmcZqCalDdr3WarmBoot = 0x00000000, - .EmcZcalWarmBootWait = 0x00000001, - .EmcMrsWarmBootEnable = 0x00000001, - .EmcMrsResetDllWait = 0x00000000, - .EmcMrsExtra = 0x00000000, - .EmcWarmBootMrsExtra = 0x00000000, - .EmcEmrsDdr2DllEnable = 0x00000000, - .EmcMrsDdr2DllReset = 0x00000000, - .EmcEmrsDdr2OcdCalib = 0x00000000, - .EmcDdr2Wait = 0x00000000, - .EmcClkenOverride = 0x00000000, - .McDisExtraSnapLevels = 0x00000000, - .EmcExtraRefreshNum = 0x00000002, - .EmcClkenOverrideAllWarmBoot = 0x00000000, - .McClkenOverrideAllWarmBoot = 0x00000000, - .EmcCfgDigDllPeriodWarmBoot = 0x00000003, - .PmcVddpSel = 0x00000001, - .PmcVddpSelWait = 0x00000002, - .PmcDdrPwr = 0x00000003, - .PmcDdrCfg = 0x00001000, - .PmcIoDpd3Req = 0x4ffefef7, - .PmcIoDpd3ReqWait = 0x00000000, - .PmcRegShort = 0x0000330f, - .PmcNoIoPower = 0x00000000, - .PmcPorDpdCtrlWait = 0x00000001, - .EmcXm2CmdPadCtrl = 0x00000220, - .EmcXm2CmdPadCtrl2 = 0x770c0000, - .EmcXm2CmdPadCtrl3 = 0x050c0000, - .EmcXm2CmdPadCtrl4 = 0x00000000, - .EmcXm2CmdPadCtrl5 = 0x00100100, - .EmcXm2DqsPadCtrl = 0x770c1414, - .EmcXm2DqsPadCtrl2 = 0x0120103d, - .EmcXm2DqsPadCtrl3 = 0x55555520, - .EmcXm2DqsPadCtrl4 = 0x00492492, - .EmcXm2DqsPadCtrl5 = 0x00492492, - .EmcXm2DqsPadCtrl6 = 0x55555500, - .EmcXm2DqPadCtrl = 0x770c2990, - .EmcXm2DqPadCtrl2 = 0x00000000, - .EmcXm2DqPadCtrl3 = 0x00000000, - .EmcXm2ClkPadCtrl = 0x77ffc004, - .EmcXm2ClkPadCtrl2 = 0x00000000, - .EmcXm2CompPadCtrl = 0x81f1f008, - .EmcXm2VttGenPadCtrl = 0x07070000, - .EmcXm2VttGenPadCtrl2 = 0x00000000, - .EmcXm2VttGenPadCtrl3 = 0x015ddddd, - .EmcAcpdControl = 0x00000000, - .EmcSwizzleRank0ByteCfg = 0x00001032, - .EmcSwizzleRank0Byte0 = 0x53067142, - .EmcSwizzleRank0Byte1 = 0x73025146, - .EmcSwizzleRank0Byte2 = 0x20136475, - .EmcSwizzleRank0Byte3 = 0x46273150, - .EmcSwizzleRank1ByteCfg = 0x00003210, - .EmcSwizzleRank1Byte0 = 0x73451026, - .EmcSwizzleRank1Byte1 = 0x73025146, - .EmcSwizzleRank1Byte2 = 0x20641735, - .EmcSwizzleRank1Byte3 = 0x42136075, - .EmcDsrVttgenDrv = 0x0000003f, - .EmcTxdsrvttgen = 0x00000000, - .EmcBgbiasCtl0 = 0x00000000, - .McEmemAdrCfg = 0x00000001, - .McEmemAdrCfgDev0 = 0x00080304, - .McEmemAdrCfgDev1 = 0x00080304, - .McEmemAdrCfgBankMask0 = 0x00001248, - .McEmemAdrCfgBankMask1 = 0x00002490, - .McEmemAdrCfgBankMask2 = 0x00000920, - .McEmemAdrCfgBankSwizzle3 = 0x00000001, - .McEmemCfg = 0x00001000, - .McEmemArbCfg = 0x0e00000d, - .McEmemArbOutstandingReq = 0x80000040, - .McEmemArbTimingRcd = 0x00000007, - .McEmemArbTimingRp = 0x00000008, - .McEmemArbTimingRc = 0x0000001b, - .McEmemArbTimingRas = 0x00000012, - .McEmemArbTimingFaw = 0x00000017, - .McEmemArbTimingRrd = 0x00000004, - .McEmemArbTimingRap2Pre = 0x00000004, - .McEmemArbTimingWap2Pre = 0x0000000e, - .McEmemArbTimingR2R = 0x00000004, - .McEmemArbTimingW2W = 0x00000001, - .McEmemArbTimingR2W = 0x00000009, - .McEmemArbTimingW2R = 0x00000009, - .McEmemArbDaTurns = 0x09090104, - .McEmemArbDaCovers = 0x001e141b, - .McEmemArbMisc0 = 0x71ae2a1c, - .McEmemArbMisc1 = 0x70000f02, - .McEmemArbRing1Throttle = 0x001f0000, - .McEmemArbOverride = 0x10000000, - .McEmemArbOverride1 = 0x00000000, - .McEmemArbRsv = 0xff00ff00, - .McClkenOverride = 0x00000000, - .McStatControl = 0x00000000, - .McDisplaySnapRing = 0x00000003, - .McVideoProtectBom = 0xfff00000, - .McVideoProtectBomAdrHi = 0x00000000, - .McVideoProtectSizeMb = 0x00000000, - .McVideoProtectVprOverride = 0xe4bac743, - .McVideoProtectVprOverride1 = 0x00000013, - .McVideoProtectGpuOverride0 = 0x00000000, - .McVideoProtectGpuOverride1 = 0x00000000, - .McSecCarveoutBom = 0xfff00000, - .McSecCarveoutAdrHi = 0x00000000, - .McSecCarveoutSizeMb = 0x00000000, - .McVideoProtectWriteAccess = 0x00000000, - .McSecCarveoutProtectWriteAccess = 0x00000000, - .EmcCaTrainingEnable = 0x00000001, - .EmcCaTrainingTimingCntl1 = 0x09257359, - .EmcCaTrainingTimingCntl2 = 0x00000017, - .SwizzleRankByteEncode = 0x00000008, - .BootRomPatchControl = 0x00000000, - .BootRomPatchData = 0x00000000, - .McMtsCarveoutBom = 0x78000000, - .McMtsCarveoutAdrHi = 0x00000001, - .McMtsCarveoutSizeMb = 0x00000080, - .McMtsCarveoutRegCtrl = 0x00000001, -}, diff --git a/src/mainboard/google/rush_ryu/bct/sdram-micron-4GB-528.inc b/src/mainboard/google/rush_ryu/bct/sdram-micron-4GB-528.inc deleted file mode 100644 index 52180ccff6..0000000000 --- a/src/mainboard/google/rush_ryu/bct/sdram-micron-4GB-528.inc +++ /dev/null @@ -1,311 +0,0 @@ -{ /* generated from sdram-micron-4GB-528.cfg; do not edit. */ - .MemoryType = NvBootMemoryType_LpDdr2, - .PllMInputDivider = 0x00000001, - .PllMFeedbackDivider = 0x0000002c, - .PllMStableTime = 0x0000012c, - .PllMSetupControl = 0x00000000, - .PllMSelectDiv2 = 0x00000000, - .PllMPDLshiftPh45 = 0x00000001, - .PllMPDLshiftPh90 = 0x00000001, - .PllMPDLshiftPh135 = 0x00000001, - .PllMKCP = 0x00000000, - .PllMKVCO = 0x00000000, - .EmcBctSpare0 = 0x00000000, - .EmcBctSpare1 = 0x00000000, - .EmcBctSpare2 = 0x00000000, - .EmcBctSpare3 = 0x00000000, - .EmcBctSpare4 = 0x00000000, - .EmcBctSpare5 = 0x00000000, - .EmcBctSpare6 = 0x00000000, - .EmcBctSpare7 = 0x00000000, - .EmcBctSpare8 = 0x00000000, - .EmcBctSpare9 = 0x00000000, - .EmcBctSpare10 = 0x00000000, - .EmcBctSpare11 = 0x00000000, - .EmcClockSource = 0x80000000, - .EmcAutoCalInterval = 0x001fffff, - .EmcAutoCalConfig = 0xa1430000, - .EmcAutoCalConfig2 = 0x00000000, - .EmcAutoCalConfig3 = 0x00000000, - .EmcAutoCalWait = 0x00000190, - .EmcAdrCfg = 0x00000001, - .EmcPinProgramWait = 0x00000000, - .EmcPinExtraWait = 0x00000000, - .EmcTimingControlWait = 0x00000000, - .EmcRc = 0x0000001f, - .EmcRfc = 0x00000044, - .EmcRfcSlr = 0x00000000, - .EmcRas = 0x00000016, - .EmcRp = 0x00000009, - .EmcR2r = 0x00000000, - .EmcW2w = 0x00000000, - .EmcR2w = 0x0000000a, - .EmcW2r = 0x00000009, - .EmcR2p = 0x00000003, - .EmcW2p = 0x0000000d, - .EmcRdRcd = 0x00000009, - .EmcWrRcd = 0x00000009, - .EmcRrd = 0x00000005, - .EmcRext = 0x00000004, - .EmcWext = 0x00000000, - .EmcWdv = 0x00000002, - .EmcWdvMask = 0x00000002, - .EmcQUse = 0x00000008, - .EmcQuseWidth = 0x00000003, - .EmcIbdly = 0x00000000, - .EmcEInput = 0x00000003, - .EmcEInputDuration = 0x0000000a, - .EmcPutermExtra = 0x00050000, - .EmcPutermWidth = 0x00000004, - .EmcPutermAdj = 0x00000000, - .EmcCdbCntl1 = 0x00000000, - .EmcCdbCntl2 = 0x00000000, - .EmcCdbCntl3 = 0x00000000, - .EmcQRst = 0x00000002, - .EmcQSafe = 0x00000011, - .EmcRdv = 0x00000015, - .EmcRdvMask = 0x00000017, - .EmcQpop = 0x0000000d, - .EmcCtt = 0x00000000, - .EmcCttDuration = 0x00000004, - .EmcRefresh = 0x000007cd, - .EmcBurstRefreshNum = 0x00000000, - .EmcPreRefreshReqCnt = 0x000001f3, - .EmcPdEx2Wr = 0x00000003, - .EmcPdEx2Rd = 0x00000003, - .EmcPChg2Pden = 0x00000009, - .EmcAct2Pden = 0x00000000, - .EmcAr2Pden = 0x00000001, - .EmcRw2Pden = 0x00000011, - .EmcTxsr = 0x0000004a, - .EmcTxsrDll = 0x0000004a, - .EmcTcke = 0x00000004, - .EmcTckesr = 0x00000008, - .EmcTpd = 0x00000004, - .EmcTfaw = 0x00000019, - .EmcTrpab = 0x0000000c, - .EmcTClkStable = 0x00000003, - .EmcTClkStop = 0x00000003, - .EmcTRefBw = 0x00000895, - .EmcFbioCfg5 = 0x1363a096, - .EmcFbioCfg6 = 0x00000000, - .EmcFbioSpare = 0x00000000, - .EmcCfgRsv = 0xff00ff00, - .EmcMrs = 0x00000000, - .EmcEmrs = 0x00000000, - .EmcEmrs2 = 0x00000000, - .EmcEmrs3 = 0x00000000, - .EmcMrw1 = 0x000100c3, - .EmcMrw2 = 0x00020006, - .EmcMrw3 = 0x00030001, - .EmcMrw4 = 0x800b0000, - .EmcMrwExtra = 0x000100c3, - .EmcWarmBootMrwExtra = 0x00020006, - .EmcWarmBootExtraModeRegWriteEnable = 0x00000000, - .EmcExtraModeRegWriteEnable = 0x00000000, - .EmcMrwResetCommand = 0x003f00fc, - .EmcMrwResetNInitWait = 0x0000000a, - .EmcMrsWaitCnt = 0x02100013, - .EmcMrsWaitCnt2 = 0x02100013, - .EmcCfg = 0xf3300000, - .EmcCfg2 = 0x0000089f, - .EmcCfgPipe = 0x000042a0, - .EmcDbg = 0x01000c00, - .EmcCmdQ = 0x10004408, - .EmcMc2EmcQ = 0x06000404, - .EmcDynSelfRefControl = 0x800010b3, - .AhbArbitrationXbarCtrlMemInitDone = 0x00000001, - .EmcCfgDigDll = 0xe01200b9, - .EmcCfgDigDllPeriod = 0x00008000, - .EmcDevSelect = 0x00000000, - .EmcSelDpdCtrl = 0x0004001c, - .EmcDllXformDqs0 = 0x007f400a, - .EmcDllXformDqs1 = 0x007f400a, - .EmcDllXformDqs2 = 0x007f400a, - .EmcDllXformDqs3 = 0x007f400a, - .EmcDllXformDqs4 = 0x007f400a, - .EmcDllXformDqs5 = 0x007f400a, - .EmcDllXformDqs6 = 0x007f400a, - .EmcDllXformDqs7 = 0x007f400a, - .EmcDllXformDqs8 = 0x007f400a, - .EmcDllXformDqs9 = 0x007f400a, - .EmcDllXformDqs10 = 0x007f400a, - .EmcDllXformDqs11 = 0x007f400a, - .EmcDllXformDqs12 = 0x007f400a, - .EmcDllXformDqs13 = 0x007f400a, - .EmcDllXformDqs14 = 0x007f400a, - .EmcDllXformDqs15 = 0x007f400a, - .EmcDllXformQUse0 = 0x00000000, - .EmcDllXformQUse1 = 0x00000000, - .EmcDllXformQUse2 = 0x00000000, - .EmcDllXformQUse3 = 0x00000000, - .EmcDllXformQUse4 = 0x00000000, - .EmcDllXformQUse5 = 0x00000000, - .EmcDllXformQUse6 = 0x00000000, - .EmcDllXformQUse7 = 0x00000000, - .EmcDllXformAddr0 = 0x00024000, - .EmcDllXformAddr1 = 0x00024000, - .EmcDllXformAddr2 = 0x00000006, - .EmcDllXformAddr3 = 0x00024000, - .EmcDllXformAddr4 = 0x00024000, - .EmcDllXformAddr5 = 0x00000006, - .EmcDllXformQUse8 = 0x00000000, - .EmcDllXformQUse9 = 0x00000000, - .EmcDllXformQUse10 = 0x00000000, - .EmcDllXformQUse11 = 0x00000000, - .EmcDllXformQUse12 = 0x00000000, - .EmcDllXformQUse13 = 0x00000000, - .EmcDllXformQUse14 = 0x00000000, - .EmcDllXformQUse15 = 0x00000000, - .EmcDliTrimTxDqs0 = 0x0000000b, - .EmcDliTrimTxDqs1 = 0x0000000b, - .EmcDliTrimTxDqs2 = 0x00000008, - .EmcDliTrimTxDqs3 = 0x0000000b, - .EmcDliTrimTxDqs4 = 0x0000000b, - .EmcDliTrimTxDqs5 = 0x00000008, - .EmcDliTrimTxDqs6 = 0x0000000b, - .EmcDliTrimTxDqs7 = 0x0000000b, - .EmcDliTrimTxDqs8 = 0x0000000b, - .EmcDliTrimTxDqs9 = 0x0000000b, - .EmcDliTrimTxDqs10 = 0x00000008, - .EmcDliTrimTxDqs11 = 0x0000000b, - .EmcDliTrimTxDqs12 = 0x0000000b, - .EmcDliTrimTxDqs13 = 0x00000008, - .EmcDliTrimTxDqs14 = 0x0000000b, - .EmcDliTrimTxDqs15 = 0x0000000b, - .EmcDllXformDq0 = 0x0000000c, - .EmcDllXformDq1 = 0x0000000c, - .EmcDllXformDq2 = 0x0000000c, - .EmcDllXformDq3 = 0x0000000c, - .EmcDllXformDq4 = 0x0000000c, - .EmcDllXformDq5 = 0x0000000c, - .EmcDllXformDq6 = 0x0000000c, - .EmcDllXformDq7 = 0x0000000c, - .WarmBootWait = 0x00000001, - .EmcCttTermCtrl = 0x00000802, - .EmcOdtWrite = 0x00000000, - .EmcOdtRead = 0x00000000, - .EmcZcalInterval = 0x00064000, - .EmcZcalWaitCnt = 0x00000034, - .EmcZcalMrwCmd = 0x000a0056, - .EmcMrsResetDll = 0x00000000, - .EmcZcalInitDev0 = 0x840a00ff, - .EmcZcalInitDev1 = 0x440a00ff, - .EmcZcalInitWait = 0x00000001, - .EmcZcalWarmColdBootEnables = 0x00000003, - .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab, - .EmcZqCalDdr3WarmBoot = 0x00000000, - .EmcZcalWarmBootWait = 0x00000001, - .EmcMrsWarmBootEnable = 0x00000001, - .EmcMrsResetDllWait = 0x00000000, - .EmcMrsExtra = 0x00000000, - .EmcWarmBootMrsExtra = 0x00000000, - .EmcEmrsDdr2DllEnable = 0x00000000, - .EmcMrsDdr2DllReset = 0x00000000, - .EmcEmrsDdr2OcdCalib = 0x00000000, - .EmcDdr2Wait = 0x00000000, - .EmcClkenOverride = 0x00000000, - .McDisExtraSnapLevels = 0x00000000, - .EmcExtraRefreshNum = 0x00000002, - .EmcClkenOverrideAllWarmBoot = 0x00000000, - .McClkenOverrideAllWarmBoot = 0x00000000, - .EmcCfgDigDllPeriodWarmBoot = 0x00000003, - .PmcVddpSel = 0x00000001, - .PmcVddpSelWait = 0x00000002, - .PmcDdrPwr = 0x00000003, - .PmcDdrCfg = 0x00001000, - .PmcIoDpd3Req = 0x4ffefef7, - .PmcIoDpd3ReqWait = 0x00000000, - .PmcRegShort = 0x0000330f, - .PmcNoIoPower = 0x00000000, - .PmcPorDpdCtrlWait = 0x00000001, - .EmcXm2CmdPadCtrl = 0x00000220, - .EmcXm2CmdPadCtrl2 = 0x770c0000, - .EmcXm2CmdPadCtrl3 = 0x050c0000, - .EmcXm2CmdPadCtrl4 = 0x00000000, - .EmcXm2CmdPadCtrl5 = 0x00100100, - .EmcXm2DqsPadCtrl = 0x770c1414, - .EmcXm2DqsPadCtrl2 = 0x0123123d, - .EmcXm2DqsPadCtrl3 = 0x51451420, - .EmcXm2DqsPadCtrl4 = 0x00514514, - .EmcXm2DqsPadCtrl5 = 0x00514514, - .EmcXm2DqsPadCtrl6 = 0x51451400, - .EmcXm2DqPadCtrl = 0x770c2990, - .EmcXm2DqPadCtrl2 = 0x00000000, - .EmcXm2DqPadCtrl3 = 0x00000000, - .EmcXm2ClkPadCtrl = 0x77ffc004, - .EmcXm2ClkPadCtrl2 = 0x00000000, - .EmcXm2CompPadCtrl = 0x81f1f008, - .EmcXm2VttGenPadCtrl = 0x07070000, - .EmcXm2VttGenPadCtrl2 = 0x0000003f, - .EmcXm2VttGenPadCtrl3 = 0x015ddddd, - .EmcAcpdControl = 0x00000000, - .EmcSwizzleRank0ByteCfg = 0x00001032, - .EmcSwizzleRank0Byte0 = 0x53067142, - .EmcSwizzleRank0Byte1 = 0x73025146, - .EmcSwizzleRank0Byte2 = 0x20136475, - .EmcSwizzleRank0Byte3 = 0x46273150, - .EmcSwizzleRank1ByteCfg = 0x00003210, - .EmcSwizzleRank1Byte0 = 0x73451026, - .EmcSwizzleRank1Byte1 = 0x73025146, - .EmcSwizzleRank1Byte2 = 0x20641735, - .EmcSwizzleRank1Byte3 = 0x42136075, - .EmcDsrVttgenDrv = 0x0000003f, - .EmcTxdsrvttgen = 0x00000000, - .EmcBgbiasCtl0 = 0x00000000, - .McEmemAdrCfg = 0x00000001, - .McEmemAdrCfgDev0 = 0x00080304, - .McEmemAdrCfgDev1 = 0x00080304, - .McEmemAdrCfgBankMask0 = 0x00001248, - .McEmemAdrCfgBankMask1 = 0x00002490, - .McEmemAdrCfgBankMask2 = 0x00000920, - .McEmemAdrCfgBankSwizzle3 = 0x00000001, - .McEmemCfg = 0x00001000, - .McEmemArbCfg = 0x0f000007, - .McEmemArbOutstandingReq = 0x80000040, - .McEmemArbTimingRcd = 0x00000003, - .McEmemArbTimingRp = 0x00000004, - .McEmemArbTimingRc = 0x00000010, - .McEmemArbTimingRas = 0x0000000a, - .McEmemArbTimingFaw = 0x0000000d, - .McEmemArbTimingRrd = 0x00000002, - .McEmemArbTimingRap2Pre = 0x00000002, - .McEmemArbTimingWap2Pre = 0x00000009, - .McEmemArbTimingR2R = 0x00000003, - .McEmemArbTimingW2W = 0x00000001, - .McEmemArbTimingR2W = 0x00000006, - .McEmemArbTimingW2R = 0x00000006, - .McEmemArbDaTurns = 0x06060103, - .McEmemArbDaCovers = 0x00120b10, - .McEmemArbMisc0 = 0x71c81811, - .McEmemArbMisc1 = 0x70000f03, - .McEmemArbRing1Throttle = 0x001f0000, - .McEmemArbOverride = 0x10000000, - .McEmemArbOverride1 = 0x00000000, - .McEmemArbRsv = 0xff00ff00, - .McClkenOverride = 0x00000000, - .McStatControl = 0x00000000, - .McDisplaySnapRing = 0x00000003, - .McVideoProtectBom = 0xfff00000, - .McVideoProtectBomAdrHi = 0x00000000, - .McVideoProtectSizeMb = 0x00000000, - .McVideoProtectVprOverride = 0xe4bac743, - .McVideoProtectVprOverride1 = 0x00000013, - .McVideoProtectGpuOverride0 = 0x00000000, - .McVideoProtectGpuOverride1 = 0x00000000, - .McSecCarveoutBom = 0xfff00000, - .McSecCarveoutAdrHi = 0x00000000, - .McSecCarveoutSizeMb = 0x00000000, - .McVideoProtectWriteAccess = 0x00000000, - .McSecCarveoutProtectWriteAccess = 0x00000000, - .EmcCaTrainingEnable = 0x00000001, - .EmcCaTrainingTimingCntl1 = 0x09257359, - .EmcCaTrainingTimingCntl2 = 0x00000017, - .SwizzleRankByteEncode = 0x00000008, - .BootRomPatchControl = 0x00000000, - .BootRomPatchData = 0x00000000, - .McMtsCarveoutBom = 0x78000000, - .McMtsCarveoutAdrHi = 0x00000001, - .McMtsCarveoutSizeMb = 0x00000080, - .McMtsCarveoutRegCtrl = 0x00000001, -}, diff --git a/src/mainboard/google/rush_ryu/bct/sdram-micron-4GB-924.inc b/src/mainboard/google/rush_ryu/bct/sdram-micron-4GB-924.inc deleted file mode 100644 index 5f2594b927..0000000000 --- a/src/mainboard/google/rush_ryu/bct/sdram-micron-4GB-924.inc +++ /dev/null @@ -1,311 +0,0 @@ -{ /* generated from sdram-micron-4GB-924.cfg; do not edit. This is Micron LPDDR3 */ - .MemoryType = NvBootMemoryType_LpDdr2, - .PllMInputDivider = 0x00000001, - .PllMFeedbackDivider = 0x0000004d, - .PllMStableTime = 0x0000012c, - .PllMSetupControl = 0x00000000, - .PllMSelectDiv2 = 0x00000000, - .PllMPDLshiftPh45 = 0x00000001, - .PllMPDLshiftPh90 = 0x00000001, - .PllMPDLshiftPh135 = 0x00000001, - .PllMKCP = 0x00000000, - .PllMKVCO = 0x00000000, - .EmcBctSpare0 = 0x00000000, - .EmcBctSpare1 = 0x00000000, - .EmcBctSpare2 = 0x00000000, - .EmcBctSpare3 = 0x00000000, - .EmcBctSpare4 = 0x00000000, - .EmcBctSpare5 = 0x00000000, - .EmcBctSpare6 = 0x00000000, - .EmcBctSpare7 = 0x00000000, - .EmcBctSpare8 = 0x00000000, - .EmcBctSpare9 = 0x00000000, - .EmcBctSpare10 = 0x00000000, - .EmcBctSpare11 = 0x00000000, - .EmcClockSource = 0x80000000, - .EmcAutoCalInterval = 0x001fffff, - .EmcAutoCalConfig = 0xa1430000, - .EmcAutoCalConfig2 = 0x00000000, - .EmcAutoCalConfig3 = 0x00000000, - .EmcAutoCalWait = 0x00000190, - .EmcAdrCfg = 0x00000001, - .EmcPinProgramWait = 0x00000000, - .EmcPinExtraWait = 0x00000000, - .EmcTimingControlWait = 0x00000000, - .EmcRc = 0x00000037, - .EmcRfc = 0x00000078, - .EmcRfcSlr = 0x00000000, - .EmcRas = 0x00000026, - .EmcRp = 0x00000010, - .EmcR2r = 0x00000000, - .EmcW2w = 0x00000000, - .EmcR2w = 0x00000010, - .EmcW2r = 0x00000010, - .EmcR2p = 0x00000006, - .EmcW2p = 0x00000017, - .EmcRdRcd = 0x00000010, - .EmcWrRcd = 0x00000010, - .EmcRrd = 0x00000009, - .EmcRext = 0x00000005, - .EmcWext = 0x00000000, - .EmcWdv = 0x00000007, - .EmcWdvMask = 0x00000007, - .EmcQUse = 0x00000011, - .EmcQuseWidth = 0x00000004, - .EmcIbdly = 0x00000000, - .EmcEInput = 0x00000006, - .EmcEInputDuration = 0x00000011, - .EmcPutermExtra = 0x000e0000, - .EmcPutermWidth = 0x00000006, - .EmcPutermAdj = 0x00000000, - .EmcCdbCntl1 = 0x00000000, - .EmcCdbCntl2 = 0x00000000, - .EmcCdbCntl3 = 0x00000000, - .EmcQRst = 0x00000005, - .EmcQSafe = 0x00000018, - .EmcRdv = 0x00000020, - .EmcRdvMask = 0x00000022, - .EmcQpop = 0x00000017, - .EmcCtt = 0x00000000, - .EmcCttDuration = 0x00000006, - .EmcRefresh = 0x00000dd4, - .EmcBurstRefreshNum = 0x00000000, - .EmcPreRefreshReqCnt = 0x00000375, - .EmcPdEx2Wr = 0x00000006, - .EmcPdEx2Rd = 0x00000006, - .EmcPChg2Pden = 0x00000010, - .EmcAct2Pden = 0x00000000, - .EmcAr2Pden = 0x00000001, - .EmcRw2Pden = 0x0000001b, - .EmcTxsr = 0x00000082, - .EmcTxsrDll = 0x00000082, - .EmcTcke = 0x00000007, - .EmcTckesr = 0x0000000e, - .EmcTpd = 0x00000007, - .EmcTfaw = 0x0000002d, - .EmcTrpab = 0x00000014, - .EmcTClkStable = 0x00000003, - .EmcTClkStop = 0x00000003, - .EmcTRefBw = 0x00000f04, - .EmcFbioCfg5 = 0x1363a896, - .EmcFbioCfg6 = 0x00000000, - .EmcFbioSpare = 0x00000000, - .EmcCfgRsv = 0xff00ff00, - .EmcMrs = 0x00000000, - .EmcEmrs = 0x00000000, - .EmcEmrs2 = 0x00000000, - .EmcEmrs3 = 0x00000000, - .EmcMrw1 = 0x00010083, - .EmcMrw2 = 0x0002001c, - .EmcMrw3 = 0x00030001, - .EmcMrw4 = 0x800b0000, - .EmcMrwExtra = 0x00010083, - .EmcWarmBootMrwExtra = 0x0002001c, - .EmcWarmBootExtraModeRegWriteEnable = 0x00000000, - .EmcExtraModeRegWriteEnable = 0x00000000, - .EmcMrwResetCommand = 0x003f00fc, - .EmcMrwResetNInitWait = 0x0000000a, - .EmcMrsWaitCnt = 0x039c0019, - .EmcMrsWaitCnt2 = 0x039c0019, - .EmcCfg = 0xf3300000, - .EmcCfg2 = 0x0000089f, - .EmcCfgPipe = 0x00004080, - .EmcDbg = 0x01000c00, - .EmcCmdQ = 0x10004408, - .EmcMc2EmcQ = 0x06000404, - .EmcDynSelfRefControl = 0x80001c77, - .AhbArbitrationXbarCtrlMemInitDone = 0x00000001, - .EmcCfgDigDll = 0xe00400b9, - .EmcCfgDigDllPeriod = 0x00008000, - .EmcDevSelect = 0x00000000, - .EmcSelDpdCtrl = 0x0004001c, - .EmcDllXformDqs0 = 0x00004006, - .EmcDllXformDqs1 = 0x007f800c, - .EmcDllXformDqs2 = 0x007fc008, - .EmcDllXformDqs3 = 0x007f400c, - .EmcDllXformDqs4 = 0x007fc006, - .EmcDllXformDqs5 = 0x00000006, - .EmcDllXformDqs6 = 0x007f800a, - .EmcDllXformDqs7 = 0x007f800c, - .EmcDllXformDqs8 = 0x007f400a, - .EmcDllXformDqs9 = 0x007f400a, - .EmcDllXformDqs10 = 0x007f400a, - .EmcDllXformDqs11 = 0x007f400a, - .EmcDllXformDqs12 = 0x007f400a, - .EmcDllXformDqs13 = 0x007f400a, - .EmcDllXformDqs14 = 0x007f400a, - .EmcDllXformDqs15 = 0x007f400a, - .EmcDllXformQUse0 = 0x00000000, - .EmcDllXformQUse1 = 0x00000000, - .EmcDllXformQUse2 = 0x00000000, - .EmcDllXformQUse3 = 0x00000000, - .EmcDllXformQUse4 = 0x00000000, - .EmcDllXformQUse5 = 0x00000000, - .EmcDllXformQUse6 = 0x00000000, - .EmcDllXformQUse7 = 0x00000000, - .EmcDllXformAddr0 = 0x00018004, - .EmcDllXformAddr1 = 0x00018004, - .EmcDllXformAddr2 = 0x00000008, - .EmcDllXformAddr3 = 0x00014004, - .EmcDllXformAddr4 = 0x0001c002, - .EmcDllXformAddr5 = 0x00000008, - .EmcDllXformQUse8 = 0x00000000, - .EmcDllXformQUse9 = 0x00000000, - .EmcDllXformQUse10 = 0x00000000, - .EmcDllXformQUse11 = 0x00000000, - .EmcDllXformQUse12 = 0x00000000, - .EmcDllXformQUse13 = 0x00000000, - .EmcDllXformQUse14 = 0x00000000, - .EmcDllXformQUse15 = 0x00000000, - .EmcDliTrimTxDqs0 = 0x00000008, - .EmcDliTrimTxDqs1 = 0x00000008, - .EmcDliTrimTxDqs2 = 0x00000008, - .EmcDliTrimTxDqs3 = 0x00000008, - .EmcDliTrimTxDqs4 = 0x00000008, - .EmcDliTrimTxDqs5 = 0x00000008, - .EmcDliTrimTxDqs6 = 0x00000008, - .EmcDliTrimTxDqs7 = 0x00000008, - .EmcDliTrimTxDqs8 = 0x00000008, - .EmcDliTrimTxDqs9 = 0x00000008, - .EmcDliTrimTxDqs10 = 0x00000008, - .EmcDliTrimTxDqs11 = 0x00000008, - .EmcDliTrimTxDqs12 = 0x00000008, - .EmcDliTrimTxDqs13 = 0x00000008, - .EmcDliTrimTxDqs14 = 0x00000008, - .EmcDliTrimTxDqs15 = 0x00000008, - .EmcDllXformDq0 = 0x0000000a, - .EmcDllXformDq1 = 0x0000000a, - .EmcDllXformDq2 = 0x0000000a, - .EmcDllXformDq3 = 0x0000000a, - .EmcDllXformDq4 = 0x0000000a, - .EmcDllXformDq5 = 0x0000000a, - .EmcDllXformDq6 = 0x0000000a, - .EmcDllXformDq7 = 0x0000000a, - .WarmBootWait = 0x00000001, - .EmcCttTermCtrl = 0x00000802, - .EmcOdtWrite = 0x00000000, - .EmcOdtRead = 0x00000000, - .EmcZcalInterval = 0x00064000, - .EmcZcalWaitCnt = 0x00000058, - .EmcZcalMrwCmd = 0x000a0056, - .EmcMrsResetDll = 0x00000000, - .EmcZcalInitDev0 = 0x840a00ff, - .EmcZcalInitDev1 = 0x440a00ff, - .EmcZcalInitWait = 0x00000001, - .EmcZcalWarmColdBootEnables = 0x00000003, - .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab, - .EmcZqCalDdr3WarmBoot = 0x00000000, - .EmcZcalWarmBootWait = 0x00000001, - .EmcMrsWarmBootEnable = 0x00000001, - .EmcMrsResetDllWait = 0x00000000, - .EmcMrsExtra = 0x00000000, - .EmcWarmBootMrsExtra = 0x00000000, - .EmcEmrsDdr2DllEnable = 0x00000000, - .EmcMrsDdr2DllReset = 0x00000000, - .EmcEmrsDdr2OcdCalib = 0x00000000, - .EmcDdr2Wait = 0x00000000, - .EmcClkenOverride = 0x00000000, - .McDisExtraSnapLevels = 0x00000000, - .EmcExtraRefreshNum = 0x00000002, - .EmcClkenOverrideAllWarmBoot = 0x00000000, - .McClkenOverrideAllWarmBoot = 0x00000000, - .EmcCfgDigDllPeriodWarmBoot = 0x00000003, - .PmcVddpSel = 0x00000001, - .PmcVddpSelWait = 0x00000002, - .PmcDdrPwr = 0x00000003, - .PmcDdrCfg = 0x00001000, - .PmcIoDpd3Req = 0x4ffefef7, - .PmcIoDpd3ReqWait = 0x00000000, - .PmcRegShort = 0x0000330f, - .PmcNoIoPower = 0x00000000, - .PmcPorDpdCtrlWait = 0x00000001, - .EmcXm2CmdPadCtrl = 0x00000220, - .EmcXm2CmdPadCtrl2 = 0x770c0000, - .EmcXm2CmdPadCtrl3 = 0x050c0000, - .EmcXm2CmdPadCtrl4 = 0x00000000, - .EmcXm2CmdPadCtrl5 = 0x00100100, - .EmcXm2DqsPadCtrl = 0x770c1414, - .EmcXm2DqsPadCtrl2 = 0x0120103d, - .EmcXm2DqsPadCtrl3 = 0x65965920, - .EmcXm2DqsPadCtrl4 = 0x00596596, - .EmcXm2DqsPadCtrl5 = 0x00596596, - .EmcXm2DqsPadCtrl6 = 0x65965900, - .EmcXm2DqPadCtrl = 0x770c2990, - .EmcXm2DqPadCtrl2 = 0x00000000, - .EmcXm2DqPadCtrl3 = 0x00000000, - .EmcXm2ClkPadCtrl = 0x77ffc004, - .EmcXm2ClkPadCtrl2 = 0x00000000, - .EmcXm2CompPadCtrl = 0x81f1f008, - .EmcXm2VttGenPadCtrl = 0x07070000, - .EmcXm2VttGenPadCtrl2 = 0x00000000, - .EmcXm2VttGenPadCtrl3 = 0x015ddddd, - .EmcAcpdControl = 0x00000000, - .EmcSwizzleRank0ByteCfg = 0x00001032, - .EmcSwizzleRank0Byte0 = 0x53067142, - .EmcSwizzleRank0Byte1 = 0x73025146, - .EmcSwizzleRank0Byte2 = 0x20136475, - .EmcSwizzleRank0Byte3 = 0x46273150, - .EmcSwizzleRank1ByteCfg = 0x00003210, - .EmcSwizzleRank1Byte0 = 0x73451026, - .EmcSwizzleRank1Byte1 = 0x73025146, - .EmcSwizzleRank1Byte2 = 0x20641735, - .EmcSwizzleRank1Byte3 = 0x42136075, - .EmcDsrVttgenDrv = 0x0000003f, - .EmcTxdsrvttgen = 0x00000000, - .EmcBgbiasCtl0 = 0x00000000, - .McEmemAdrCfg = 0x00000001, - .McEmemAdrCfgDev0 = 0x00080304, - .McEmemAdrCfgDev1 = 0x00080304, - .McEmemAdrCfgBankMask0 = 0x00001248, - .McEmemAdrCfgBankMask1 = 0x00002490, - .McEmemAdrCfgBankMask2 = 0x00000920, - .McEmemAdrCfgBankSwizzle3 = 0x00000001, - .McEmemCfg = 0x00001000, - .McEmemArbCfg = 0x0e00000d, - .McEmemArbOutstandingReq = 0x80000040, - .McEmemArbTimingRcd = 0x00000007, - .McEmemArbTimingRp = 0x00000008, - .McEmemArbTimingRc = 0x0000001b, - .McEmemArbTimingRas = 0x00000012, - .McEmemArbTimingFaw = 0x00000017, - .McEmemArbTimingRrd = 0x00000004, - .McEmemArbTimingRap2Pre = 0x00000004, - .McEmemArbTimingWap2Pre = 0x0000000e, - .McEmemArbTimingR2R = 0x00000004, - .McEmemArbTimingW2W = 0x00000001, - .McEmemArbTimingR2W = 0x00000009, - .McEmemArbTimingW2R = 0x00000009, - .McEmemArbDaTurns = 0x09090104, - .McEmemArbDaCovers = 0x001e141b, - .McEmemArbMisc0 = 0x71ae2a1c, - .McEmemArbMisc1 = 0x70000f02, - .McEmemArbRing1Throttle = 0x001f0000, - .McEmemArbOverride = 0x10000000, - .McEmemArbOverride1 = 0x00000000, - .McEmemArbRsv = 0xff00ff00, - .McClkenOverride = 0x00000000, - .McStatControl = 0x00000000, - .McDisplaySnapRing = 0x00000003, - .McVideoProtectBom = 0xfff00000, - .McVideoProtectBomAdrHi = 0x00000000, - .McVideoProtectSizeMb = 0x00000000, - .McVideoProtectVprOverride = 0xe4bac743, - .McVideoProtectVprOverride1 = 0x00000013, - .McVideoProtectGpuOverride0 = 0x00000000, - .McVideoProtectGpuOverride1 = 0x00000000, - .McSecCarveoutBom = 0xfff00000, - .McSecCarveoutAdrHi = 0x00000000, - .McSecCarveoutSizeMb = 0x00000000, - .McVideoProtectWriteAccess = 0x00000000, - .McSecCarveoutProtectWriteAccess = 0x00000000, - .EmcCaTrainingEnable = 0x00000001, - .EmcCaTrainingTimingCntl1 = 0x09257359, - .EmcCaTrainingTimingCntl2 = 0x00000017, - .SwizzleRankByteEncode = 0x00000008, - .BootRomPatchControl = 0x00000000, - .BootRomPatchData = 0x00000000, - .McMtsCarveoutBom = 0x78000000, - .McMtsCarveoutAdrHi = 0x00000001, - .McMtsCarveoutSizeMb = 0x00000080, - .McMtsCarveoutRegCtrl = 0x00000001, -}, diff --git a/src/mainboard/google/rush_ryu/bct/sdram-samsung-4GB-924.inc b/src/mainboard/google/rush_ryu/bct/sdram-samsung-4GB-924.inc deleted file mode 100644 index 8f19db26a9..0000000000 --- a/src/mainboard/google/rush_ryu/bct/sdram-samsung-4GB-924.inc +++ /dev/null @@ -1,311 +0,0 @@ -{ /* generated from sdram-4GB-924.cfg; do not edit. This is SAMSUNG LPDDR3 */ - .MemoryType = NvBootMemoryType_LpDdr2, - .PllMInputDivider = 0x00000001, - .PllMFeedbackDivider = 0x0000004d, - .PllMStableTime = 0x0000012c, - .PllMSetupControl = 0x00000000, - .PllMSelectDiv2 = 0x00000000, - .PllMPDLshiftPh45 = 0x00000001, - .PllMPDLshiftPh90 = 0x00000001, - .PllMPDLshiftPh135 = 0x00000001, - .PllMKCP = 0x00000000, - .PllMKVCO = 0x00000000, - .EmcBctSpare0 = 0x00000000, - .EmcBctSpare1 = 0x00000000, - .EmcBctSpare2 = 0x00000000, - .EmcBctSpare3 = 0x00000000, - .EmcBctSpare4 = 0x00000000, - .EmcBctSpare5 = 0x00000000, - .EmcBctSpare6 = 0x00000000, - .EmcBctSpare7 = 0x00000000, - .EmcBctSpare8 = 0x00000000, - .EmcBctSpare9 = 0x00000000, - .EmcBctSpare10 = 0x00000000, - .EmcBctSpare11 = 0x00000000, - .EmcClockSource = 0x80000000, - .EmcAutoCalInterval = 0x001fffff, - .EmcAutoCalConfig = 0xa1430000, - .EmcAutoCalConfig2 = 0x00000000, - .EmcAutoCalConfig3 = 0x00000000, - .EmcAutoCalWait = 0x00000190, - .EmcAdrCfg = 0x00000001, - .EmcPinProgramWait = 0x00000000, - .EmcPinExtraWait = 0x00000000, - .EmcTimingControlWait = 0x00000000, - .EmcRc = 0x00000037, - .EmcRfc = 0x00000078, - .EmcRfcSlr = 0x00000000, - .EmcRas = 0x00000026, - .EmcRp = 0x00000010, - .EmcR2r = 0x00000000, - .EmcW2w = 0x00000000, - .EmcR2w = 0x00000010, - .EmcW2r = 0x00000010, - .EmcR2p = 0x00000006, - .EmcW2p = 0x00000017, - .EmcRdRcd = 0x00000010, - .EmcWrRcd = 0x00000010, - .EmcRrd = 0x00000009, - .EmcRext = 0x00000005, - .EmcWext = 0x00000000, - .EmcWdv = 0x00000007, - .EmcWdvMask = 0x00000007, - .EmcQUse = 0x00000011, - .EmcQuseWidth = 0x00000004, - .EmcIbdly = 0x00000000, - .EmcEInput = 0x00000006, - .EmcEInputDuration = 0x00000011, - .EmcPutermExtra = 0x000e0000, - .EmcPutermWidth = 0x00000006, - .EmcPutermAdj = 0x00000000, - .EmcCdbCntl1 = 0x00000000, - .EmcCdbCntl2 = 0x00000000, - .EmcCdbCntl3 = 0x00000000, - .EmcQRst = 0x00000005, - .EmcQSafe = 0x00000018, - .EmcRdv = 0x00000020, - .EmcRdvMask = 0x00000022, - .EmcQpop = 0x00000017, - .EmcCtt = 0x00000000, - .EmcCttDuration = 0x00000006, - .EmcRefresh = 0x00000dd4, - .EmcBurstRefreshNum = 0x00000000, - .EmcPreRefreshReqCnt = 0x00000375, - .EmcPdEx2Wr = 0x00000006, - .EmcPdEx2Rd = 0x00000006, - .EmcPChg2Pden = 0x00000010, - .EmcAct2Pden = 0x00000000, - .EmcAr2Pden = 0x00000001, - .EmcRw2Pden = 0x0000001b, - .EmcTxsr = 0x00000082, - .EmcTxsrDll = 0x00000082, - .EmcTcke = 0x00000007, - .EmcTckesr = 0x0000000e, - .EmcTpd = 0x00000007, - .EmcTfaw = 0x0000002d, - .EmcTrpab = 0x00000014, - .EmcTClkStable = 0x00000003, - .EmcTClkStop = 0x00000003, - .EmcTRefBw = 0x00000f04, - .EmcFbioCfg5 = 0x1363a896, - .EmcFbioCfg6 = 0x00000000, - .EmcFbioSpare = 0x00000000, - .EmcCfgRsv = 0xff00ff00, - .EmcMrs = 0x00000000, - .EmcEmrs = 0x00000000, - .EmcEmrs2 = 0x00000000, - .EmcEmrs3 = 0x00000000, - .EmcMrw1 = 0x00010083, - .EmcMrw2 = 0x0002001c, - .EmcMrw3 = 0x00030001, - .EmcMrw4 = 0x800b0000, - .EmcMrwExtra = 0x00010083, - .EmcWarmBootMrwExtra = 0x0002001c, - .EmcWarmBootExtraModeRegWriteEnable = 0x00000000, - .EmcExtraModeRegWriteEnable = 0x00000000, - .EmcMrwResetCommand = 0x003f00fc, - .EmcMrwResetNInitWait = 0x0000000a, - .EmcMrsWaitCnt = 0x039c0019, - .EmcMrsWaitCnt2 = 0x039c0019, - .EmcCfg = 0xf3300000, - .EmcCfg2 = 0x0000089f, - .EmcCfgPipe = 0x00004080, - .EmcDbg = 0x01000c00, - .EmcCmdQ = 0x10004408, - .EmcMc2EmcQ = 0x06000404, - .EmcDynSelfRefControl = 0x80001c77, - .AhbArbitrationXbarCtrlMemInitDone = 0x00000001, - .EmcCfgDigDll = 0xe00400b9, - .EmcCfgDigDllPeriod = 0x00008000, - .EmcDevSelect = 0x00000000, - .EmcSelDpdCtrl = 0x0004001c, - .EmcDllXformDqs0 = 0x007fc00a, - .EmcDllXformDqs1 = 0x007fc00a, - .EmcDllXformDqs2 = 0x007fc00a, - .EmcDllXformDqs3 = 0x007fc00a, - .EmcDllXformDqs4 = 0x007f800c, - .EmcDllXformDqs5 = 0x00000008, - .EmcDllXformDqs6 = 0x007f800a, - .EmcDllXformDqs7 = 0x007fc00a, - .EmcDllXformDqs8 = 0x007f400a, - .EmcDllXformDqs9 = 0x007f400a, - .EmcDllXformDqs10 = 0x007f400a, - .EmcDllXformDqs11 = 0x007f400a, - .EmcDllXformDqs12 = 0x007f400a, - .EmcDllXformDqs13 = 0x007f400a, - .EmcDllXformDqs14 = 0x007f400a, - .EmcDllXformDqs15 = 0x007f400a, - .EmcDllXformQUse0 = 0x00000000, - .EmcDllXformQUse1 = 0x00000000, - .EmcDllXformQUse2 = 0x00000000, - .EmcDllXformQUse3 = 0x00000000, - .EmcDllXformQUse4 = 0x00000000, - .EmcDllXformQUse5 = 0x00000000, - .EmcDllXformQUse6 = 0x00000000, - .EmcDllXformQUse7 = 0x00000000, - .EmcDllXformAddr0 = 0x00018002, - .EmcDllXformAddr1 = 0x00018002, - .EmcDllXformAddr2 = 0x00000008, - .EmcDllXformAddr3 = 0x00018002, - .EmcDllXformAddr4 = 0x00018002, - .EmcDllXformAddr5 = 0x00000008, - .EmcDllXformQUse8 = 0x00000000, - .EmcDllXformQUse9 = 0x00000000, - .EmcDllXformQUse10 = 0x00000000, - .EmcDllXformQUse11 = 0x00000000, - .EmcDllXformQUse12 = 0x00000000, - .EmcDllXformQUse13 = 0x00000000, - .EmcDllXformQUse14 = 0x00000000, - .EmcDllXformQUse15 = 0x00000000, - .EmcDliTrimTxDqs0 = 0x00000008, - .EmcDliTrimTxDqs1 = 0x00000008, - .EmcDliTrimTxDqs2 = 0x00000008, - .EmcDliTrimTxDqs3 = 0x00000008, - .EmcDliTrimTxDqs4 = 0x00000008, - .EmcDliTrimTxDqs5 = 0x00000008, - .EmcDliTrimTxDqs6 = 0x00000008, - .EmcDliTrimTxDqs7 = 0x00000008, - .EmcDliTrimTxDqs8 = 0x00000008, - .EmcDliTrimTxDqs9 = 0x00000008, - .EmcDliTrimTxDqs10 = 0x00000008, - .EmcDliTrimTxDqs11 = 0x00000008, - .EmcDliTrimTxDqs12 = 0x00000008, - .EmcDliTrimTxDqs13 = 0x00000008, - .EmcDliTrimTxDqs14 = 0x00000008, - .EmcDliTrimTxDqs15 = 0x00000008, - .EmcDllXformDq0 = 0x0000000c, - .EmcDllXformDq1 = 0x0000000c, - .EmcDllXformDq2 = 0x0000000c, - .EmcDllXformDq3 = 0x0000000c, - .EmcDllXformDq4 = 0x0000000c, - .EmcDllXformDq5 = 0x0000000c, - .EmcDllXformDq6 = 0x0000000c, - .EmcDllXformDq7 = 0x0000000c, - .WarmBootWait = 0x00000001, - .EmcCttTermCtrl = 0x00000802, - .EmcOdtWrite = 0x00000000, - .EmcOdtRead = 0x00000000, - .EmcZcalInterval = 0x00064000, - .EmcZcalWaitCnt = 0x00000058, - .EmcZcalMrwCmd = 0x000a0056, - .EmcMrsResetDll = 0x00000000, - .EmcZcalInitDev0 = 0x840a00ff, - .EmcZcalInitDev1 = 0x440a00ff, - .EmcZcalInitWait = 0x00000001, - .EmcZcalWarmColdBootEnables = 0x00000003, - .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab, - .EmcZqCalDdr3WarmBoot = 0x00000000, - .EmcZcalWarmBootWait = 0x00000001, - .EmcMrsWarmBootEnable = 0x00000001, - .EmcMrsResetDllWait = 0x00000000, - .EmcMrsExtra = 0x00000000, - .EmcWarmBootMrsExtra = 0x00000000, - .EmcEmrsDdr2DllEnable = 0x00000000, - .EmcMrsDdr2DllReset = 0x00000000, - .EmcEmrsDdr2OcdCalib = 0x00000000, - .EmcDdr2Wait = 0x00000000, - .EmcClkenOverride = 0x00000000, - .McDisExtraSnapLevels = 0x00000000, - .EmcExtraRefreshNum = 0x00000002, - .EmcClkenOverrideAllWarmBoot = 0x00000000, - .McClkenOverrideAllWarmBoot = 0x00000000, - .EmcCfgDigDllPeriodWarmBoot = 0x00000003, - .PmcVddpSel = 0x00000001, - .PmcVddpSelWait = 0x00000002, - .PmcDdrPwr = 0x00000003, - .PmcDdrCfg = 0x00001000, - .PmcIoDpd3Req = 0x4ffefef7, - .PmcIoDpd3ReqWait = 0x00000000, - .PmcRegShort = 0x0000330f, - .PmcNoIoPower = 0x00000000, - .PmcPorDpdCtrlWait = 0x00000001, - .EmcXm2CmdPadCtrl = 0x00000220, - .EmcXm2CmdPadCtrl2 = 0x770c0000, - .EmcXm2CmdPadCtrl3 = 0x050c0000, - .EmcXm2CmdPadCtrl4 = 0x00000000, - .EmcXm2CmdPadCtrl5 = 0x00100100, - .EmcXm2DqsPadCtrl = 0x770c1414, - .EmcXm2DqsPadCtrl2 = 0x0120103d, - .EmcXm2DqsPadCtrl3 = 0x55555520, - .EmcXm2DqsPadCtrl4 = 0x00596596, - .EmcXm2DqsPadCtrl5 = 0x00596596, - .EmcXm2DqsPadCtrl6 = 0x55555500, - .EmcXm2DqPadCtrl = 0x770c2990, - .EmcXm2DqPadCtrl2 = 0x00000000, - .EmcXm2DqPadCtrl3 = 0x00000000, - .EmcXm2ClkPadCtrl = 0x77ffc004, - .EmcXm2ClkPadCtrl2 = 0x00000000, - .EmcXm2CompPadCtrl = 0x81f1f008, - .EmcXm2VttGenPadCtrl = 0x07070000, - .EmcXm2VttGenPadCtrl2 = 0x00000000, - .EmcXm2VttGenPadCtrl3 = 0x015ddddd, - .EmcAcpdControl = 0x00000000, - .EmcSwizzleRank0ByteCfg = 0x00001032, - .EmcSwizzleRank0Byte0 = 0x53067142, - .EmcSwizzleRank0Byte1 = 0x73025146, - .EmcSwizzleRank0Byte2 = 0x20136475, - .EmcSwizzleRank0Byte3 = 0x46273150, - .EmcSwizzleRank1ByteCfg = 0x00003210, - .EmcSwizzleRank1Byte0 = 0x73451026, - .EmcSwizzleRank1Byte1 = 0x73025146, - .EmcSwizzleRank1Byte2 = 0x20641735, - .EmcSwizzleRank1Byte3 = 0x42136075, - .EmcDsrVttgenDrv = 0x0000003f, - .EmcTxdsrvttgen = 0x00000000, - .EmcBgbiasCtl0 = 0x00000000, - .McEmemAdrCfg = 0x00000001, - .McEmemAdrCfgDev0 = 0x00080304, - .McEmemAdrCfgDev1 = 0x00080304, - .McEmemAdrCfgBankMask0 = 0x00001248, - .McEmemAdrCfgBankMask1 = 0x00002490, - .McEmemAdrCfgBankMask2 = 0x00000920, - .McEmemAdrCfgBankSwizzle3 = 0x00000001, - .McEmemCfg = 0x00001000, - .McEmemArbCfg = 0x0e00000d, - .McEmemArbOutstandingReq = 0x80000040, - .McEmemArbTimingRcd = 0x00000007, - .McEmemArbTimingRp = 0x00000008, - .McEmemArbTimingRc = 0x0000001b, - .McEmemArbTimingRas = 0x00000012, - .McEmemArbTimingFaw = 0x00000017, - .McEmemArbTimingRrd = 0x00000004, - .McEmemArbTimingRap2Pre = 0x00000004, - .McEmemArbTimingWap2Pre = 0x0000000e, - .McEmemArbTimingR2R = 0x00000004, - .McEmemArbTimingW2W = 0x00000001, - .McEmemArbTimingR2W = 0x00000009, - .McEmemArbTimingW2R = 0x00000009, - .McEmemArbDaTurns = 0x09090104, - .McEmemArbDaCovers = 0x001e141b, - .McEmemArbMisc0 = 0x71ae2a1c, - .McEmemArbMisc1 = 0x70000f02, - .McEmemArbRing1Throttle = 0x001f0000, - .McEmemArbOverride = 0x10000000, - .McEmemArbOverride1 = 0x00000000, - .McEmemArbRsv = 0xff00ff00, - .McClkenOverride = 0x00000000, - .McStatControl = 0x00000000, - .McDisplaySnapRing = 0x00000003, - .McVideoProtectBom = 0xfff00000, - .McVideoProtectBomAdrHi = 0x00000000, - .McVideoProtectSizeMb = 0x00000000, - .McVideoProtectVprOverride = 0xe4bac743, - .McVideoProtectVprOverride1 = 0x00000013, - .McVideoProtectGpuOverride0 = 0x00000000, - .McVideoProtectGpuOverride1 = 0x00000000, - .McSecCarveoutBom = 0xfff00000, - .McSecCarveoutAdrHi = 0x00000000, - .McSecCarveoutSizeMb = 0x00000000, - .McVideoProtectWriteAccess = 0x00000000, - .McSecCarveoutProtectWriteAccess = 0x00000000, - .EmcCaTrainingEnable = 0x00000001, - .EmcCaTrainingTimingCntl1 = 0x09257359, - .EmcCaTrainingTimingCntl2 = 0x00000017, - .SwizzleRankByteEncode = 0x00000008, - .BootRomPatchControl = 0x00000000, - .BootRomPatchData = 0x00000000, - .McMtsCarveoutBom = 0x78000000, - .McMtsCarveoutAdrHi = 0x00000001, - .McMtsCarveoutSizeMb = 0x00000080, - .McMtsCarveoutRegCtrl = 0x00000001, -}, diff --git a/src/mainboard/google/rush_ryu/bct/spi.cfg b/src/mainboard/google/rush_ryu/bct/spi.cfg deleted file mode 100644 index a5ded0bd68..0000000000 --- a/src/mainboard/google/rush_ryu/bct/spi.cfg +++ /dev/null @@ -1,31 +0,0 @@ -# Copyright (c) 2013 The Chromium OS Authors. All rights reserved. -# Distributed under the terms of the GNU General Public License v2 - -Version = 0x00130001; -BlockSize = 32768; -PageSize = 2048; -PartitionSize = 4194304; - -DevType[0] = NvBootDevType_Spi; -DeviceParam[0].SpiFlashParams.ReadCommandTypeFast = NV_FALSE; -DeviceParam[0].SpiFlashParams.ClockDivider = 0x16; -DeviceParam[0].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0; -DeviceParam[0].SpiFlashParams.PageSize2kor16k = 0; - -DevType[1] = NvBootDevType_Spi; -DeviceParam[1].SpiFlashParams.ReadCommandTypeFast = NV_FALSE; -DeviceParam[1].SpiFlashParams.ClockDivider = 0x16; -DeviceParam[1].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0; -DeviceParam[1].SpiFlashParams.PageSize2kor16k = 0; - -DevType[2] = NvBootDevType_Spi; -DeviceParam[2].SpiFlashParams.ReadCommandTypeFast = NV_FALSE; -DeviceParam[2].SpiFlashParams.ClockDivider = 0x16; -DeviceParam[2].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0; -DeviceParam[2].SpiFlashParams.PageSize2kor16k = 0; - -DevType[3] = NvBootDevType_Spi; -DeviceParam[3].SpiFlashParams.ReadCommandTypeFast = NV_FALSE; -DeviceParam[3].SpiFlashParams.ClockDivider = 0x16; -DeviceParam[3].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0; -DeviceParam[3].SpiFlashParams.PageSize2kor16k = 0; diff --git a/src/mainboard/google/rush_ryu/board_info.txt b/src/mainboard/google/rush_ryu/board_info.txt deleted file mode 100644 index dd52e9c2bf..0000000000 --- a/src/mainboard/google/rush_ryu/board_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -Vendor name: Google -Board name: Rush Ryu Nvidia Tegra132 board -Category: eval -ROM protocol: SPI -ROM socketed: n -Flashrom support: y diff --git a/src/mainboard/google/rush_ryu/boardid.c b/src/mainboard/google/rush_ryu/boardid.c deleted file mode 100644 index 2c1d4f6070..0000000000 --- a/src/mainboard/google/rush_ryu/boardid.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <boardid.h> -#include <console/console.h> -#include <stdlib.h> - -#include "gpio.h" - -uint8_t board_id(void) -{ - static int id = -1; - - if (id < 0) { - gpio_t gpio[] = {[1] = BD_ID1, [0] = BD_ID0}; /* ID0 is LSB */ - - id = gpio_base3_value(gpio, ARRAY_SIZE(gpio)); - } - - return id; -} diff --git a/src/mainboard/google/rush_ryu/bootblock.c b/src/mainboard/google/rush_ryu/bootblock.c deleted file mode 100644 index 2b80d52fcf..0000000000 --- a/src/mainboard/google/rush_ryu/bootblock.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <bootblock_common.h> -#include <console/console.h> -#include <device/i2c.h> -#include <soc/addressmap.h> -#include <soc/clk_rst.h> -#include <soc/clock.h> -#include <soc/funitcfg.h> -#include <soc/nvidia/tegra/i2c.h> -#include <soc/padconfig.h> - -#include "pmic.h" - -static const struct pad_config uart_console_pads[] = { - /* UARTA: tx and rx. */ - PAD_CFG_SFIO(KB_ROW9, PINMUX_PULL_NONE, UA3), - PAD_CFG_SFIO(KB_ROW10, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, UA3), - /* - * Disable UART2 pads as they are default connected to UARTA controller. - */ - PAD_CFG_UNUSED(UART2_RXD), - PAD_CFG_UNUSED(UART2_TXD), - PAD_CFG_UNUSED(UART2_RTS_N), - PAD_CFG_UNUSED(UART2_CTS_N), -}; - -static const struct pad_config pmic_pads[] = { - PAD_CFG_SFIO(PWR_I2C_SCL, PINMUX_INPUT_ENABLE, I2CPMU), - PAD_CFG_SFIO(PWR_I2C_SDA, PINMUX_INPUT_ENABLE, I2CPMU), -}; - -static const struct pad_config spiflash_pads[] = { - /* mosi, miso, clk, cs0 */ - PAD_CFG_SFIO(GPIO_PG6, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SPI4), - PAD_CFG_SFIO(GPIO_PG7, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SPI4), - PAD_CFG_SFIO(GPIO_PG5, PINMUX_INPUT_ENABLE, SPI4), - PAD_CFG_SFIO(GPIO_PI3, PINMUX_INPUT_ENABLE, SPI4), -}; - -static const struct funit_cfg funits[] = { - /* PMIC on I2C5 (PWR_I2C* pads) at 400kHz. */ - FUNIT_CFG(I2C5, PLLP, 400, pmic_pads, ARRAY_SIZE(pmic_pads)), - /* SPI flash at 33MHz on SPI4 controller. */ - FUNIT_CFG(SBC4, PLLP, 33333, spiflash_pads, ARRAY_SIZE(spiflash_pads)), -}; - -void bootblock_mainboard_early_init(void) -{ - soc_configure_pads(uart_console_pads, ARRAY_SIZE(uart_console_pads)); -} - -static void set_clock_sources(void) -{ - /* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */ - write32(CLK_RST_REG(clk_src_uarta), PLLP << CLK_SOURCE_SHIFT); -} - -static const struct pad_config padcfgs[] = { - /* Board build id bits 1:0 */ - PAD_CFG_GPIO_INPUT(KB_COL4, PINMUX_PULL_NONE), - PAD_CFG_GPIO_INPUT(KB_COL3, PINMUX_PULL_NONE), -}; - -void bootblock_mainboard_init(void) -{ - set_clock_sources(); - - /* Set up controllers and pads to load romstage. */ - soc_configure_funits(funits, ARRAY_SIZE(funits)); - soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs)); - - i2c_init(I2CPWR_BUS); - pmic_init(I2CPWR_BUS); -} diff --git a/src/mainboard/google/rush_ryu/chromeos.c b/src/mainboard/google/rush_ryu/chromeos.c deleted file mode 100644 index 9f4ec6bb7c..0000000000 --- a/src/mainboard/google/rush_ryu/chromeos.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <boardid.h> -#include <boot/coreboot_tables.h> -#include <console/console.h> -#include <ec/google/chromeec/ec.h> -#include <ec/google/chromeec/ec_commands.h> -#include <string.h> -#include <vendorcode/google/chromeos/chromeos.h> - -#include "gpio.h" - -static inline uint32_t get_pwr_btn_polarity(void) -{ - if (board_id() < BOARD_ID_PROTO_3) - return ACTIVE_HIGH; - - return ACTIVE_LOW; -} - -void fill_lb_gpios(struct lb_gpios *gpios) -{ - struct lb_gpio chromeos_gpios[] = { - {WRITE_PROTECT_L, ACTIVE_LOW, gpio_get(WRITE_PROTECT_L), - "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - /* TODO(adurbin): add lid switch */ - {POWER_BUTTON, get_pwr_btn_polarity(), -1, "power"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, - {EC_IN_RW, ACTIVE_HIGH, -1, "EC in RW"}, - {AP_SYS_RESET_L, ACTIVE_LOW, -1, "reset"}, - }; - - lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); -} - -int get_developer_mode_switch(void) -{ - return 0; -} - -int get_recovery_mode_switch(void) -{ - uint32_t ec_events; - - ec_events = google_chromeec_get_events_b(); - return !!(ec_events & - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); -} - -int get_write_protect_state(void) -{ - return !gpio_get(WRITE_PROTECT_L); -} diff --git a/src/mainboard/google/rush_ryu/chromeos.fmd b/src/mainboard/google/rush_ryu/chromeos.fmd deleted file mode 100644 index bd78e09c35..0000000000 --- a/src/mainboard/google/rush_ryu/chromeos.fmd +++ /dev/null @@ -1,27 +0,0 @@ -FLASH@0x0 0x800000 { - WP_RO@0x0 0x300000 { - RO_SECTION@0x0 0x2f0000 { - BOOTBLOCK@0 128K - COREBOOT(CBFS)@0x20000 0x1e0000 - FMAP@0x200000 0x1000 - GBB@0x201000 0xeef00 - RO_FRID@0x2eff00 0x100 - } - RO_VPD@0x2f0000 0x10000 - } - RW_SECTION_A@0x300000 0x278000 { - VBLOCK_A@0x0 0x2000 - FW_MAIN_A(CBFS)@0x2000 0x275f00 - RW_FWID_A@0x277f00 0x100 - } - RW_SHARED@0x578000 0x4000 { - SHARED_DATA@0x0 0x4000 - } - RW_ELOG@0x57c000 0x4000 - RW_SECTION_B@0x580000 0x278000 { - VBLOCK_B@0x0 0x2000 - FW_MAIN_B(CBFS)@0x2000 0x275f00 - RW_FWID_B@0x277f00 0x100 - } - RW_VPD@0x7f8000 0x8000 -} diff --git a/src/mainboard/google/rush_ryu/devicetree.cb b/src/mainboard/google/rush_ryu/devicetree.cb deleted file mode 100644 index 4245444890..0000000000 --- a/src/mainboard/google/rush_ryu/devicetree.cb +++ /dev/null @@ -1,47 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright 2014 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -chip soc/nvidia/tegra132 - device cpu_cluster 0 on - end - - register "display_controller" = "TEGRA_ARM_DISPLAYA" - register "xres" = "2560" - register "yres" = "1800" - - # bits per pixel and color depth - register "framebuffer_bits_per_pixel" = "32" - register "color_depth" = "12" - - # framebuffer resolution - register "display_xres" = "1280" - register "display_yres" = "800" - - register "href_to_sync" = "1" - register "hfront_porch" = "80" - register "hsync_width" = "80" - register "hback_porch" = "80" - - register "vref_to_sync" = "1" - register "vfront_porch" = "4" - register "vsync_width" = "4" - register "vback_porch" = "4" - register "refresh" = "60" - - # kernel driver - register "pixel_clock" = "301620000" - - register "win_opt" = "DSI_ENABLE" -end diff --git a/src/mainboard/google/rush_ryu/gpio.h b/src/mainboard/google/rush_ryu/gpio.h deleted file mode 100644 index cb4ec4d0a1..0000000000 --- a/src/mainboard/google/rush_ryu/gpio.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MAINBOARD_GOOGLE_RUSH_RYU_GPIO_H__ -#define __MAINBOARD_GOOGLE_RUSH_RYU_GPIO_H__ - -#include <gpio.h> -#include <base3.h> - -/* Board ID definitions. */ -enum { - BOARD_REV0 = BASE3(0, 0), - BOARD_REV1 = BASE3(0, 1), - BOARD_REV2 = BASE3(0, Z), - BOARD_REV3 = BASE3(1, 0), - BOARD_REV4 = BASE3(1, 1), - BOARD_REV5 = BASE3(1, Z), - BOARD_REV6 = BASE3(Z, 0), - BOARD_REV7 = BASE3(Z, 1), - BOARD_REV8 = BASE3(Z, Z), - - BOARD_ID_PROTO_0 = BOARD_REV0, - BOARD_ID_PROTO_1 = BOARD_REV1, - BOARD_ID_PROTO_3 = BOARD_REV2, - BOARD_ID_PROTO_4 = BOARD_REV3, - BOARD_ID_EVT = BOARD_REV4, - BOARD_ID_DVT = BOARD_REV5, - BOARD_ID_PVT = BOARD_REV6, - BOARD_ID_MP = BOARD_REV7, -}; - -enum { - /* Board ID related GPIOS. */ - BD_ID0 = GPIO(Q3), - BD_ID1 = GPIO(Q4), - /* LTE modem related GPIOs */ - MODEM_RESET = GPIO(S3), - MODEM_PWR_ON = GPIO(S4), - MDM_DET = GPIO(V1), - /* Warm reset */ - AP_SYS_RESET_L = GPIO(I5), - /* Write Protect */ - SPI_1V8_WP_L = GPIO(R1), - WRITE_PROTECT_L = SPI_1V8_WP_L, - /* Power button - Depending on board id, maybe active high / low */ - BTN_AP_PWR = GPIO(Q0), - POWER_BUTTON = BTN_AP_PWR, - /* EC in RW signal */ - EC_IN_RW = GPIO(U4), - - /* Panel related GPIOs */ - LCD_EN = GPIO(H5), - LCD_RST_L = GPIO(H3), - EN_VDD18_LCD = GPIO(X0), - EN_VDD_LCD = GPIO(BB6), /* P1/P3 board */ -}; - -#endif /* __MAINBOARD_GOOGLE_RUSH_RYU_GPIO_H__ */ diff --git a/src/mainboard/google/rush_ryu/mainboard.c b/src/mainboard/google/rush_ryu/mainboard.c deleted file mode 100644 index 64e01ece30..0000000000 --- a/src/mainboard/google/rush_ryu/mainboard.c +++ /dev/null @@ -1,302 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/mmu.h> -#include <boardid.h> -#include <bootmode.h> -#include <boot/coreboot_tables.h> -#include <cbmem.h> -#include <delay.h> -#include <device/device.h> -#include <device/i2c.h> -#include <elog.h> -#include <memrange.h> -#include <soc/addressmap.h> -#include <soc/clk_rst.h> -#include <soc/clock.h> -#include <soc/funitcfg.h> -#include <soc/nvidia/tegra/i2c.h> -#include <soc/padconfig.h> -#include <soc/nvidia/tegra/dc.h> -#include <soc/display.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include <vendorcode/google/chromeos/cros_vpd.h> -#if IS_ENABLED(CONFIG_CHROMEOS) -#include <vboot_struct.h> -#include <vboot/misc.h> -#include <vboot/vboot_common.h> -#endif - -#include "gpio.h" -#include "pmic.h" - -static const struct pad_config mmcpads[] = { - /* MMC4 (eMMC) */ - PAD_CFG_SFIO(SDMMC4_CLK, PINMUX_INPUT_ENABLE|PINMUX_PULL_DOWN, SDMMC4), - PAD_CFG_SFIO(SDMMC4_CMD, PINMUX_INPUT_ENABLE|PINMUX_PULL_UP, SDMMC4), - PAD_CFG_SFIO(SDMMC4_DAT0, PINMUX_INPUT_ENABLE|PINMUX_PULL_UP, SDMMC4), - PAD_CFG_SFIO(SDMMC4_DAT1, PINMUX_INPUT_ENABLE|PINMUX_PULL_UP, SDMMC4), - PAD_CFG_SFIO(SDMMC4_DAT2, PINMUX_INPUT_ENABLE|PINMUX_PULL_UP, SDMMC4), - PAD_CFG_SFIO(SDMMC4_DAT3, PINMUX_INPUT_ENABLE|PINMUX_PULL_UP, SDMMC4), - PAD_CFG_SFIO(SDMMC4_DAT4, PINMUX_INPUT_ENABLE|PINMUX_PULL_UP, SDMMC4), - PAD_CFG_SFIO(SDMMC4_DAT5, PINMUX_INPUT_ENABLE|PINMUX_PULL_UP, SDMMC4), - PAD_CFG_SFIO(SDMMC4_DAT6, PINMUX_INPUT_ENABLE|PINMUX_PULL_UP, SDMMC4), - PAD_CFG_SFIO(SDMMC4_DAT7, PINMUX_INPUT_ENABLE|PINMUX_PULL_UP, SDMMC4), -}; - -static const struct pad_config audio_codec_pads[] = { - /* H1 is CODEC_RST_L and R2(ROW2) is AUDIO_ENABLE */ - PAD_CFG_GPIO_OUT1(GPIO_PH1, PINMUX_PULL_DOWN), - PAD_CFG_GPIO_OUT1(KB_ROW2, PINMUX_PULL_DOWN), -}; - -static const struct funit_cfg funits[] = { - /* MMC on SDMMC4 controller at 48MHz. */ - FUNIT_CFG(SDMMC4, PLLP, 48000, mmcpads, ARRAY_SIZE(mmcpads)), - /* I2C6 for audio, temp sensor, etc. Enable codec via GPIOs/muxes */ - FUNIT_CFG(I2C6, PLLP, 400, audio_codec_pads, ARRAY_SIZE(audio_codec_pads)), - FUNIT_CFG_USB(USBD), -}; - -/* HACK: For proto boards before proto3, we want to disable ec sw sync */ -static void fix_ec_sw_sync(void) -{ -#if IS_ENABLED(CONFIG_CHROMEOS) - struct vboot_handoff *vh; - - if (board_id() >= BOARD_ID_PROTO_3) - return; - - vh = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); - - if (vh == NULL) { - printk(BIOS_ERR, "No vboot handoff struct found\n"); - return; - } - - VbSharedDataHeader *vb_sd = (VbSharedDataHeader *)vh->shared_data; - vb_sd->flags &= ~VBSD_EC_SOFTWARE_SYNC; -#endif -} - -static const struct pad_config lcd_gpio_padcfgs[] = { - /* LCD_EN */ - PAD_CFG_GPIO_OUT0(GPIO_PH5, PINMUX_PULL_UP), - /* LCD_RST_L */ - PAD_CFG_GPIO_OUT0(GPIO_PH3, PINMUX_PULL_UP), - /* EN_VDD_LCD */ - PAD_CFG_GPIO_OUT0(GPIO_PBB6, PINMUX_PULL_NONE), - /* EN_VDD18_LCD */ - PAD_CFG_GPIO_OUT0(DVFS_PWM, PINMUX_PULL_DOWN), -}; - -static void configure_display_clocks(void) -{ - u32 lclks = CLK_L_HOST1X | CLK_L_DISP1; /* dc */ - u32 hclks = CLK_H_MIPI_CAL | CLK_H_DSI; /* mipi phy, mipi-dsi a */ - u32 uclks = CLK_U_DSIB; /* mipi-dsi b */ - u32 xclks = CLK_X_CLK72MHZ; /* clk src of mipi_cal */ - - clock_enable_clear_reset(lclks, hclks, uclks, 0, 0, xclks); - - /* Give clocks time to stabilize. */ - udelay(IO_STABILIZATION_DELAY); -} - -static int enable_lcd_vdd(void) -{ - uint8_t data; - - /* Set 1.20V to power AVDD_DSI_CSI */ - pmic_write_reg(I2CPWR_BUS, TI65913_LDO5_VOLTAGE, - VSEL_1200, 1); - pmic_write_reg(I2CPWR_BUS, TI65913_LDO5_CTRL, - TI65913_MODE_ACTIVE_ON, 1); - - /* - * Enable VDD_LCD - * - * Use different GPIO based on board id - */ - switch (board_id()) { - case BOARD_ID_PROTO_0: - /* Select PMIC GPIO_6's primary function */ - pmic_read_reg(I2CPWR_BUS, TI65913_PAD2, &data); - pmic_write_reg(I2CPWR_BUS, TI65913_PAD2, - PAD2_GPIO_6_PRIMARY(data), 0); - - /* Set PMIC_GPIO_6 as output */ - pmic_read_reg(I2CPWR_BUS, TI65913_GPIO_DATA_DIR, &data); - pmic_write_reg(I2CPWR_BUS, TI65913_GPIO_DATA_DIR, - TI65913_GPIO_6_OUTPUT, 0); - - /* Set PMIC_GPIO_6 output high */ - pmic_read_reg(I2CPWR_BUS, TI65913_GPIO_DATA_OUT, &data); - pmic_write_reg(I2CPWR_BUS, TI65913_GPIO_DATA_OUT, - TI65913_GPIO_6_HIGH, 1); - break; - case BOARD_ID_PROTO_1: - case BOARD_ID_PROTO_3: - case BOARD_ID_PROTO_4: - case BOARD_ID_EVT: - gpio_set(EN_VDD_LCD, 1); - break; - default: /* unknown board */ - return -1; - } - /* wait for 2ms */ - mdelay(2); - - /* Enable PP1800_LCDIO to panel */ - gpio_set(EN_VDD18_LCD, 1); - /* wait for 1ms */ - mdelay(1); - - /* Set panel EN and RST signals */ - gpio_set(LCD_EN, 1); /* enable */ - /* wait for min 10ms */ - mdelay(10); - gpio_set(LCD_RST_L, 1); /* clear reset */ - /* wait for min 3ms */ - mdelay(3); - - return 0; -} - -static const struct pad_config i2s1_pad[] = { - /* I2S1 */ - PAD_CFG_SFIO(DAP2_SCLK, PINMUX_INPUT_ENABLE, I2S1), - PAD_CFG_SFIO(DAP2_FS, PINMUX_INPUT_ENABLE, I2S1), - PAD_CFG_SFIO(DAP2_DOUT, PINMUX_INPUT_ENABLE, I2S1), - PAD_CFG_SFIO(DAP2_DIN, PINMUX_INPUT_ENABLE | PINMUX_TRISTATE, I2S1), - /* codec MCLK via EXTPERIPH1 */ - PAD_CFG_SFIO(DAP_MCLK1, PINMUX_PULL_NONE, EXTPERIPH1), -}; - -static const struct funit_cfg audio_funit[] = { - /* We need 1.5MHz for I2S1. So we use CLK_M */ - FUNIT_CFG(I2S1, CLK_M, 1500, i2s1_pad, ARRAY_SIZE(i2s1_pad)), -}; - -static int configure_display_blocks(void) -{ - /* set and enable panel related vdd */ - if (enable_lcd_vdd()) - return -1; - - /* enable display related clocks */ - configure_display_clocks(); - - return 0; -} - -/* Audio init: clocks and enables/resets */ -static void setup_audio(void) -{ - /* - * External peripheral 1: audio codec (RT5677) uses 12MHz CLK1 - * NOTE: We can't use a funits struct/call here because EXTPERIPH1/2/3 - * don't have BASE regs or CAR RST/ENA bits. Also, the mux setting for - * EXTPERIPH1/DAP_MCLK1 is rolled into the I2S1 padcfg. - */ - clock_configure_source(extperiph1, CLK_M, 12000); - - soc_configure_funits(audio_funit, ARRAY_SIZE(audio_funit)); - - clock_external_output(1); /* For external RT5677 audio codec. */ - - /* - * Confirmed by NVIDIA hardware team, we need to take ALL audio devices - * connected to AHUB (AUDIO, APBIF, I2S, DAM, AMX, ADX, SPDIF, AFC) out - * of reset and clock-enabled, otherwise reading AHUB devices (in our - * case, I2S/APBIF/AUDIO<XBAR>) will hang. - */ - clock_enable_audio(); -} - -#define AD4567_DEV 0x34 -#define PWR_CTL 0 -#define DAC_CTL 2 -#define SPWDN (1 << 0) -#define DAC_MUTE (1 << 6) -#define DAC_FS (0x7 << 0) -#define SR_32K_48KHZ 0x2 - -static void enable_ad4567_spkr_amp(void) -{ - uint8_t reg_byte; - - if (board_id() >= BOARD_ID_PROTO_3) - return; - /* - * I2C6, device 0x34 is an AD4567 speaker amp on P0/P1. - * It needs to have a couple of regs tweaked to turn it on - * so it can provide audio output to the mono speaker on P0/P1. - */ - i2c_readb(I2C6_BUS, AD4567_DEV, PWR_CTL, ®_byte); - reg_byte &= ~SPWDN; // power up amp - i2c_writeb(I2C6_BUS, AD4567_DEV, PWR_CTL, reg_byte); - - /* The next 2 settings are defaults, but set them anyway */ - i2c_readb(I2C6_BUS, AD4567_DEV, DAC_CTL, ®_byte); - reg_byte &= ~DAC_MUTE; // unmute DAC (default) - reg_byte &= ~DAC_FS; // mask sample rate bits - reg_byte |= SR_32K_48KHZ; // set 32K-48KHz sample rate (default) - i2c_writeb(I2C6_BUS, AD4567_DEV, DAC_CTL, reg_byte); -} - -static void mainboard_init(device_t dev) -{ - soc_configure_funits(funits, ARRAY_SIZE(funits)); - - /* I2C6 bus (audio, etc.) */ - soc_configure_i2c6pad(); - i2c_init(I2C6_BUS); - - setup_audio(); - /* Temp hack for P1 board: Enable speaker amp (powerup, etc.) */ - enable_ad4567_spkr_amp(); - - fix_ec_sw_sync(); - - /* configure panel gpio pads */ - soc_configure_pads(lcd_gpio_padcfgs, ARRAY_SIZE(lcd_gpio_padcfgs)); - - /* if panel needs to bringup */ - if (display_init_required()) - configure_display_blocks(); -} - -void display_startup(device_t dev) -{ - dsi_display_startup(dev); -} - -static void mainboard_enable(device_t dev) -{ - dev->ops->init = &mainboard_init; -} - -struct chip_operations mainboard_ops = { - .name = "rush_ryu", - .enable_dev = mainboard_enable, -}; - -#if IS_ENABLED(CONFIG_CHROMEOS) -void lb_board(struct lb_header *header) -{ - lb_table_add_serialno_from_vpd(header); -} -#endif diff --git a/src/mainboard/google/rush_ryu/memlayout.ld b/src/mainboard/google/rush_ryu/memlayout.ld deleted file mode 100644 index 2c3330651d..0000000000 --- a/src/mainboard/google/rush_ryu/memlayout.ld +++ /dev/null @@ -1,14 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/memlayout.ld> diff --git a/src/mainboard/google/rush_ryu/pmic.c b/src/mainboard/google/rush_ryu/pmic.c deleted file mode 100644 index b3ca14c890..0000000000 --- a/src/mainboard/google/rush_ryu/pmic.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <delay.h> -#include <device/i2c.h> -#include <stdint.h> -#include <stdlib.h> - -#include "pmic.h" -#include "reset.h" - -#define PAGE_ADDR(reg) ((reg >> 8) & 0xff) -#define PAGE_OFFSET(reg) (reg & 0xff) - -struct ti65913_init_reg { - u16 reg; - u8 val; - u8 delay; -}; - -static struct ti65913_init_reg init_list[] = { -//TODO(twarren@nvidia.com): Add slams back to defaults -// {TI65913_SMPS12_VOLTAGE, 0x38, 0}, -// {TI65913_SMPS12_CTRL, 0x01, 1}, -//etc. -}; - -int pmic_read_reg(unsigned bus, uint16_t reg, uint8_t *data) -{ - if (i2c_readb(bus, PAGE_ADDR(reg), PAGE_OFFSET(reg), data)) { - printk(BIOS_ERR, "%s: page = 0x%02X, reg = 0x%02X failed!\n", - __func__, PAGE_ADDR(reg), PAGE_OFFSET(reg)); - return -1; - } - return 0; -} - -void pmic_write_reg(unsigned bus, uint16_t reg, uint8_t val, int delay) -{ - if (i2c_writeb(bus, PAGE_ADDR(reg), PAGE_OFFSET(reg), val)) { - printk(BIOS_ERR, "%s: page = 0x%02X, reg = 0x%02X, " - "value = 0x%02X failed!\n", - __func__, PAGE_ADDR(reg), PAGE_OFFSET(reg), val); - /* Reset the SoC on any PMIC write error */ - cpu_reset(); - } else { - if (delay) - udelay(500); - } -} - -static void pmic_slam_defaults(unsigned bus) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(init_list); i++) { - struct ti65913_init_reg *reg = &init_list[i]; - pmic_write_reg(bus, reg->reg, reg->val, reg->delay); - } -} - -void pmic_init(unsigned bus) -{ - /* Restore PMIC POR defaults, in case kernel changed 'em */ - pmic_slam_defaults(bus); - - /* A44: Set VDD_CPU to 1.0V. */ - pmic_write_reg(bus, TI65913_SMPS12_VOLTAGE, 0x38, 0); - pmic_write_reg(bus, TI65913_SMPS12_CTRL, 0x01, 1); - - printk(BIOS_DEBUG, "PMIC init done\n"); -} diff --git a/src/mainboard/google/rush_ryu/pmic.h b/src/mainboard/google/rush_ryu/pmic.h deleted file mode 100644 index 0f8fbec763..0000000000 --- a/src/mainboard/google/rush_ryu/pmic.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MAINBOARD_GOOGLE_RUSH_RYU_PMIC_H__ -#define __MAINBOARD_GOOGLE_RUSH_RYU_PMIC_H__ - -#include <stdint.h> - -/* A44/Ryu has a TI 65913 PMIC on bus 4 (PWR_I2C) */ -enum { - TI65913_I2C_ADDR_PAGE1 = 0x58, - TI65913_I2C_ADDR_PAGE2 = 0x59 -}; - -enum { - /* Registers in PAGE1 */ - TI65913_SMPS12_CTRL = (TI65913_I2C_ADDR_PAGE1 << 8) | 0x20, - TI65913_SMPS12_TSTEP, - TI65913_SMPS12_FORCE, - TI65913_SMPS12_VOLTAGE, - - TI65913_SMPS3_CTRL, - TI65913_SMPS3_VOLTAGE = (TI65913_I2C_ADDR_PAGE1 << 8) | 0x27, - - TI65913_SMPS45_CTRL = (TI65913_I2C_ADDR_PAGE1 << 8) | 0x28, - TI65913_SMPS45_TSTEP, - TI65913_SMPS45_FORCE, - TI65913_SMPS45_VOLTAGE, - - TI65913_SMPS6_CTRL = (TI65913_I2C_ADDR_PAGE1 << 8) | 0x2C, - TI65913_SMPS6_TSTEP, - TI65913_SMPS6_FORCE, - TI65913_SMPS6_VOLTAGE, - - TI65913_SMPS7_CTRL = (TI65913_I2C_ADDR_PAGE1 << 8) | 0x30, - TI65913_SMPS7_VOLTAGE = (TI65913_I2C_ADDR_PAGE1 << 8) | 0x33, - - TI65913_SMPS8_CTRL = (TI65913_I2C_ADDR_PAGE1 << 8) | 0x34, - TI65913_SMPS8_TSTEP, - TI65913_SMPS8_FORCE, - TI65913_SMPS8_VOLTAGE, - - TI65913_SMPS9_CTRL = (TI65913_I2C_ADDR_PAGE1 << 8) | 0x38, - TI65913_SMPS9_VOLTAGE = (TI65913_I2C_ADDR_PAGE1 << 8) | 0x3B, - - TI65913_SMPS10_CTRL = (TI65913_I2C_ADDR_PAGE1 << 8) | 0x3C, - TI65913_SMPS10_STATUS = (TI65913_I2C_ADDR_PAGE1 << 8) | 0x3F, - - TI65913_LDO1_CTRL = (TI65913_I2C_ADDR_PAGE1 << 8) | 0x50, - TI65913_LDO1_VOLTAGE, - TI65913_LDO2_CTRL, - TI65913_LDO2_VOLTAGE, - TI65913_LDO3_CTRL, - TI65913_LDO3_VOLTAGE, - TI65913_LDO4_CTRL, - TI65913_LDO4_VOLTAGE, - TI65913_LDO5_CTRL, - TI65913_LDO5_VOLTAGE, - TI65913_LDO6_CTRL, - TI65913_LDO6_VOLTAGE, - TI65913_LDO7_CTRL, - TI65913_LDO7_VOLTAGE, - TI65913_LDO8_CTRL, - TI65913_LDO8_VOLTAGE, - TI65913_LDO9_CTRL, - TI65913_LDO9_VOLTAGE, - - TI65913_LDOLN_CTRL = (TI65913_I2C_ADDR_PAGE1 << 8) | 0x62, - TI65913_LDOLN_VOLTAGE, - TI65913_LDOUSB_CTRL, - TI65913_LDOUSB_VOLTAGE, - - TI65913_LDO_CTRL = (TI65913_I2C_ADDR_PAGE1 << 8) | 0x6A, - TI65913_LDO_PD_CTRL1, - TI65913_LDO_PD_CTRL2, - - TI65913_LDO_SHORT_STATUS1 = (TI65913_I2C_ADDR_PAGE1 << 8) | 0x6D, - TI65913_LDO_SHORT_STATUS2, - - TI65913_CLK32KGAUDIO_CTRL = (TI65913_I2C_ADDR_PAGE1 << 8) | 0xD5, - - TI65913_PAD2 = (TI65913_I2C_ADDR_PAGE1 << 8) | 0xFB, - - /* Registers in PAGE2 */ - TI65913_GPIO_DATA_IN = (TI65913_I2C_ADDR_PAGE2 << 8) | 0x80, - TI65913_GPIO_DATA_DIR, - TI65913_GPIO_DATA_OUT, -}; - -/* Voltage selection */ -enum { - VSEL_1200 = 0x07, -}; - -/* - * TI65913_LDO5_CTRL - * TI65913_CLK32KGAUDIO_CTRL - */ -#define TI65913_MODE_ACTIVE_ON (1 << 0) - -/* - * select PRIMARY or SECONDARY function on PAD2 - */ -#define PAD2_GPIO_6_PRIMARY(data) \ - ((data) & ~(1 << 3)) /* clear bit 3 */ -#define PAD2_GPIO_5_SEC_CLK32KGAUDIO(data) \ - (((data) & ~(0x03 << 1)) | (0x01 << 1)) /* bit 2:1 = 01 */ - -/* TI65913_GPIO_DATA_DIR */ -#define TI65913_GPIO_6_OUTPUT (1 << 6) - -/* TI65913_GPIO_DATA_OUT */ -#define TI65913_GPIO_6_HIGH (1 << 6) - -int pmic_read_reg(unsigned bus, uint16_t reg, uint8_t *data); -void pmic_write_reg(unsigned bus, uint16_t reg, uint8_t val, int delay); -void pmic_init(unsigned bus); - -#endif /* __MAINBOARD_GOOGLE_RUSH_RYU_PMIC_H__ */ diff --git a/src/mainboard/google/rush_ryu/reset.c b/src/mainboard/google/rush_ryu/reset.c deleted file mode 100644 index fe94ac8bf1..0000000000 --- a/src/mainboard/google/rush_ryu/reset.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <reset.h> - -#include "gpio.h" - -void hard_reset(void) -{ - gpio_output(AP_SYS_RESET_L, 0); - while(1); -} diff --git a/src/mainboard/google/rush_ryu/romstage.c b/src/mainboard/google/rush_ryu/romstage.c deleted file mode 100644 index e7b120b071..0000000000 --- a/src/mainboard/google/rush_ryu/romstage.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <delay.h> -#include <soc/addressmap.h> -#include <device/i2c.h> -#include <soc/clock.h> -#include <soc/funitcfg.h> -#include <soc/nvidia/tegra/i2c.h> -#include <soc/padconfig.h> -#include <soc/romstage.h> - -#include "gpio.h" -#include "pmic.h" - -static const struct pad_config padcfgs[] = { - /* AP_SYS_RESET_L */ - PAD_CFG_GPIO_OUT1(GPIO_PI5, PINMUX_PULL_UP), - /* WP_L */ - PAD_CFG_GPIO_INPUT(KB_ROW1, PINMUX_PULL_NONE), - /* MODEM_RESET */ - PAD_CFG_GPIO_OUT0(KB_ROW11, PINMUX_PULL_DOWN), - /* MODEM_PWR_ON */ - PAD_CFG_GPIO_OUT0(KB_ROW12, PINMUX_PULL_DOWN), - /* MDM_DET - expected to be pulled down by LTE modem */ - PAD_CFG_GPIO_INPUT(GPIO_PV1, PINMUX_PULL_UP), - /* Power Button - active high / low depending on board id */ - PAD_CFG_GPIO_INPUT(KB_COL0, PINMUX_PULL_UP), - /* BTN_AP_VOLD_L - active low */ - PAD_CFG_GPIO_INPUT(KB_COL6, PINMUX_PULL_UP), - /* BTN_AP_VOLU_L - active low */ - PAD_CFG_GPIO_INPUT(KB_COL7, PINMUX_PULL_UP), -}; - -static const struct pad_config tpm_pads[] = { - PAD_CFG_SFIO(CAM_I2C_SCL, PINMUX_INPUT_ENABLE, I2C3), - PAD_CFG_SFIO(CAM_I2C_SDA, PINMUX_INPUT_ENABLE, I2C3), -}; - -static const struct pad_config ec_i2c_pads[] = { - PAD_CFG_SFIO(GEN2_I2C_SCL, PINMUX_OPEN_DRAIN|PINMUX_INPUT_ENABLE, I2C2), - PAD_CFG_SFIO(GEN2_I2C_SDA, PINMUX_OPEN_DRAIN|PINMUX_INPUT_ENABLE, I2C2), -}; - -static const struct funit_cfg funits[] = { - /* TPM on I2C3 @ 400kHz */ - FUNIT_CFG(I2C3, PLLP, 400, tpm_pads, ARRAY_SIZE(tpm_pads)), - /* EC on I2C2 - pulled to 3.3V @ 100kHz */ - FUNIT_CFG(I2C2, PLLP, 100, ec_i2c_pads, ARRAY_SIZE(ec_i2c_pads)), -}; - -static void lte_modem_init(void) -{ - int mdm_det; - uint8_t data; - - /* A LTE modem is present if MDM_DET is pulled down by the modem */ - mdm_det = gpio_get(MDM_DET); - if (mdm_det == 1) - return; - - printk(BIOS_DEBUG, "Found LTE modem\n"); - - /* Enable PMIC CLK32KGAUDIO to drive CLK_MDM_32K */ - pmic_read_reg(I2CPWR_BUS, TI65913_PAD2, &data); - pmic_write_reg(I2CPWR_BUS, TI65913_PAD2, - PAD2_GPIO_5_SEC_CLK32KGAUDIO(data), 0); - pmic_write_reg(I2CPWR_BUS, TI65913_CLK32KGAUDIO_CTRL, - TI65913_MODE_ACTIVE_ON, 0); - - /* FULL_CARD_POWER_OFF# (A44: MODEM_PWR_ON) and RESET# - * (A44: MODEM_RESET) of the LTE modem are actively low and initially - * pulled down by the pad config. To properly enable the LTE modem, - * de-assert FULL_CARD_POWER_OFF#, wait for at least 10ms, and then - * de-assert RESET#. - */ - gpio_output(MODEM_PWR_ON, 1); - udelay(15000); - gpio_output(MODEM_RESET, 1); -} - -void romstage_mainboard_init(void) -{ - /* Bring up controller interfaces for ramstage loading. */ - soc_configure_funits(funits, ARRAY_SIZE(funits)); - soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs)); - - /* TPM */ - i2c_init(I2C3_BUS); - /* EC */ - i2c_init(I2C2_BUS); - - lte_modem_init(); -} - -void mainboard_configure_pmc(void) -{ -} - -void mainboard_enable_vdd_cpu(void) -{ - /* VDD_CPU is already enabled in bootblock. */ -} diff --git a/src/mainboard/google/rush_ryu/sdram_configs.c b/src/mainboard/google/rush_ryu/sdram_configs.c deleted file mode 100644 index ebea4df6cb..0000000000 --- a/src/mainboard/google/rush_ryu/sdram_configs.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <soc/sdram_configs.h> -#include <stdlib.h> - -static const struct sdram_params sdram_configs[] = { -#include "bct/sdram-samsung-4GB-924.inc" /* ram_code = 00 */ -#include "bct/sdram-hynix-4GB-924.inc" /* ram_code = 01 */ -#include "bct/sdram-micron-4GB-924.inc" /* ram_code = 10 */ -#include "bct/sdram-micron-4GB-528.inc" /* ram_code = 11 */ -}; - -const struct sdram_params *get_sdram_config() -{ - uint32_t ramcode = sdram_get_ram_code(); - - /* - * If we need to apply some special hacks to RAMCODE mapping (ex, by - * board_id), do that now. - */ - - ramcode &= 0x3; /* Only bits 1:0 used on Ryu */ - printk(BIOS_SPEW, "%s: RAMCODE=%d\n", __func__, ramcode); - - if (ramcode >= ARRAY_SIZE(sdram_configs) || - sdram_configs[ramcode].MemoryType == NvBootMemoryType_Unused) { - die("Invalid RAMCODE."); - } - - return &sdram_configs[ramcode]; -} diff --git a/src/mainboard/google/rush_ryu/verstage.c b/src/mainboard/google/rush_ryu/verstage.c deleted file mode 100644 index e555e0ac3d..0000000000 --- a/src/mainboard/google/rush_ryu/verstage.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/addressmap.h> -#include <soc/funitcfg.h> -#include <soc/padconfig.h> -#include <soc/verstage.h> -#include <soc/nvidia/tegra/i2c.h> -#include "gpio.h" -#include "pmic.h" - -static const struct pad_config tpm_pads[] = { - PAD_CFG_SFIO(CAM_I2C_SCL, PINMUX_INPUT_ENABLE, I2C3), - PAD_CFG_SFIO(CAM_I2C_SDA, PINMUX_INPUT_ENABLE, I2C3), -}; - -static const struct pad_config ec_i2c_pads[] = { - PAD_CFG_SFIO(GEN2_I2C_SCL, PINMUX_OPEN_DRAIN|PINMUX_INPUT_ENABLE, I2C2), - PAD_CFG_SFIO(GEN2_I2C_SDA, PINMUX_OPEN_DRAIN|PINMUX_INPUT_ENABLE, I2C2), -}; - -static const struct funit_cfg funits[] = { - /* TPM on I2C3 @ 400kHz */ - FUNIT_CFG(I2C3, PLLP, 400, tpm_pads, ARRAY_SIZE(tpm_pads)), - /* EC on I2C2 - pulled to 3.3V @ 100kHz */ - FUNIT_CFG(I2C2, PLLP, 100, ec_i2c_pads, ARRAY_SIZE(ec_i2c_pads)), -}; - -void verstage_mainboard_init(void) -{ - soc_configure_funits(funits, ARRAY_SIZE(funits)); - - /* TPM */ - i2c_init(I2C3_BUS); - /* EC */ - i2c_init(I2C2_BUS); -} |