diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-04-29 10:28:20 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-01 16:37:13 +0000 |
| commit | 066e61f3ea1f65012b14467412e6b17351c87dc6 (patch) | |
| tree | 0536c4c8d9059f1b765cc2388f6d6974d0486d54 /src | |
| parent | ad87d1c8b9285cfed47b3ec060be520a467189ff (diff) | |
soc/intel/braswell: Fix 16-bit read/write PCI_COMMAND register
Change-Id: Ie213b8c08e2d2b33a1dc1fda632163160d1cd70e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/braswell/lpe.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/braswell/smihandler.c | 8 | ||||
| -rw-r--r-- | src/soc/intel/braswell/southcluster.c | 16 |
3 files changed, 12 insertions, 14 deletions
diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c index 9c4d2b1819..363b57ffa5 100644 --- a/src/soc/intel/braswell/lpe.c +++ b/src/soc/intel/braswell/lpe.c @@ -45,7 +45,7 @@ static void lpe_enable_acpi_mode(struct device *dev) { static const struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ - REG_PCI_OR32(PCI_COMMAND, + REG_PCI_OR16(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INT_DISABLE), /* Enable ACPI mode */ diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index e96f452341..188c14ee42 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -59,7 +59,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { - u32 reg32; + u16 reg16; pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); @@ -69,9 +69,9 @@ static void busmaster_disable_on_bus(int bus) continue; /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~PCI_COMMAND_MASTER; + pci_write_config16(dev, PCI_COMMAND, reg16); /* If this is a bridge, then follow it. */ hdr = pci_read_config8(dev, PCI_HEADER_TYPE); diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 50ff608cc0..9b5784c2b5 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -440,9 +440,9 @@ static void hda_work_around(struct device *dev) */ pci_write_config32(dev, PCI_BASE_ADDRESS_0, TEMP_BASE_ADDRESS); pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0); - pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); write32(gctl, read32(gctl) | 0x1); - pci_write_config8(dev, PCI_COMMAND, 0); + pci_write_config16(dev, PCI_COMMAND, 0); pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); } @@ -526,7 +526,7 @@ static int place_device_in_d3hot(struct device *dev) /* Common PCI device function disable. */ void southcluster_enable_dev(struct device *dev) { - uint32_t reg32; + uint16_t reg16; printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); @@ -537,9 +537,9 @@ void southcluster_enable_dev(struct device *dev) dev_path(dev), slot, func); /* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config16(dev, PCI_COMMAND, reg16); /* Place device in D3Hot */ if (place_device_in_d3hot(dev) < 0) { @@ -552,9 +552,7 @@ void southcluster_enable_dev(struct device *dev) sc_disable_devfn(dev); } else { /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); } } |