mb/prodrive/hermes: Remove overridetree

There's no need to have an overridetree with a single board variant.

TEST=Compare static.c and observe only device order has changed.

Change-Id: I2097e247c27d5d0c5479cb533b477cd490a4c827
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

3 files changed, 193 insertions, 211 deletions

diff --git a/src/mainboard/prodrive/hermes/Kconfig b/src/mainboard/prodrive/hermes/Kconfig
index bdb8e497b2..2fecc06f6d 100644
--- a/src/mainboard/prodrive/hermes/Kconfig
+++ b/src/mainboard/prodrive/hermes/Kconfig
@@ -51,9 +51,6 @@ config MAX_CPUS
 	int
 	default 16
 
-config OVERRIDE_DEVICETREE
-	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
-
 config CONSOLE_POST
 	bool
 	default y
diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb
index cafc81e6ba..69658211f9 100644
--- a/src/mainboard/prodrive/hermes/devicetree.cb
+++ b/src/mainboard/prodrive/hermes/devicetree.cb
@@ -1,4 +1,132 @@
 chip soc/intel/cannonlake
+	# FSP configuration
+
+	register "SataMode" = "0"		# AHCI
+	register "SataSalpSupport" = "0"
+	register "satapwroptimize" = "1"
+	register "SataPortsDevSlp[1]" = "1"	# PCH_M2_SATA_DEVSLP1
+
+	register "SataPortsEnable[0]" = "1"
+	register "SataPortsEnable[1]" = "1"	# depends on SATAXPCIE1
+	register "SataPortsEnable[2]" = "0"	# Not used for SATA
+	register "SataPortsEnable[3]" = "0"	# Not used for SATA
+	register "SataPortsEnable[4]" = "1"
+	register "SataPortsEnable[5]" = "1"
+	register "SataPortsEnable[6]" = "1"
+	register "SataPortsEnable[7]" = "1"
+
+	register "SataPortsHotPlug[0]" = "1"
+	register "SataPortsHotPlug[1]" = "1"
+	register "SataPortsHotPlug[2]" = "0"
+	register "SataPortsHotPlug[3]" = "0"
+	register "SataPortsHotPlug[4]" = "1"
+	register "SataPortsHotPlug[5]" = "1"
+	register "SataPortsHotPlug[6]" = "1"
+	register "SataPortsHotPlug[7]" = "1"
+
+	register "PchHdaDspEnable" = "0"
+	register "PchHdaAudioLinkHda" = "1"
+
+	# Controls the CLKREQ, not the output directly.
+	# Depends on the CLKREQ to CLK gen mapping below
+	register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE"		# BMC, PCIe Slot1, Slot2, Slot4, Slot6
+	register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE"		# PHY3
+	register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE"		# RP9 M2 Slot M x4
+	register "PcieClkSrcUsage[5]" = "PCIE_CLK_FREE"		# RP16 M2 Slot E x1
+	register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcUsage[7]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcUsage[8]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcUsage[9]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcUsage[10]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcUsage[11]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcUsage[12]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcUsage[13]" = "PCIE_CLK_FREE"	# PHY 0, PHY 1, PHY 2, PHY 4
+	register "PcieClkSrcUsage[14]" = "PCIE_CLK_FREE"	# PB
+	register "PcieClkSrcUsage[15]" = "PCIE_CLK_FREE"	# PCIe Slot3
+
+	# Only map M2 CLKREQ to CLK gen
+	register "PcieClkSrcClkReq[4]" = "4"	# M2_M_CLK_REQ_n
+	register "PcieClkSrcClkReq[5]" = "5"	# M2_E_CLK_REQ_n
+
+	# USB OC5-7: not connected
+	register "usb2_ports" = "{
+
+#define HERMES_USB2_CONFIG(pin) { \
+	.enable        = 1, \
+	.ocpin         = (pin), \
+	.tx_bias       = USB2_BIAS_0MV, \
+	.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, \
+	.pre_emp_bias  = USB2_BIAS_28P15MV, \
+	.pre_emp_bit   = USB2_FULL_BIT_PRE_EMP, \
+}
+		[0] = HERMES_USB2_CONFIG(OC0),		/* USB3 rear panel 1 */
+		[1] = HERMES_USB2_CONFIG(OC0),
+		[2] = HERMES_USB2_CONFIG(OC1),		/* USB3 rear panel 2 */
+		[3] = HERMES_USB2_CONFIG(OC1),
+		[4] = HERMES_USB2_CONFIG(OC2),		/* USB3 internal header CN_USB3_HDR */
+		[5] = HERMES_USB2_CONFIG(OC2),
+		[6] = HERMES_USB2_CONFIG(OC3),		/* USB2 internal header USB2_HDR1 */
+		[7] = HERMES_USB2_CONFIG(OC3),
+		[8] = HERMES_USB2_CONFIG(OC4),		/* USB2 internal header USB2_HDR1 */
+		[9] = HERMES_USB2_CONFIG(OC4),
+		[10] = HERMES_USB2_CONFIG(OC_SKIP),	/* BMC */
+		[11] = USB2_PORT_EMPTY,
+		[12] = HERMES_USB2_CONFIG(OC_SKIP),	/* piggy-back */
+		[13] = HERMES_USB2_CONFIG(OC_SKIP),	/* M.2 key E */
+	}"
+
+	# USB Config 2.0/3.0
+	# Enumeration starts at 0
+	# USB 3.0
+	# USB OC0: RP1
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
+
+	# USB OC1: RP2
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)"
+	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)"
+
+	# USB OC2:  Internal Header CN_USB3_HDR
+	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)"
+	register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)"
+
+	# Thermal
+	register "tcc_offset" = "1"     # TCC of 99C
+
+	# Disable S0ix
+	register "s0ix_enable" = "0"
+
+	# Enable Turbo
+	register "eist_enable" = "1"
+
+	register "common_soc_config" = "{
+		.gspi[0] = {
+			.speed_mhz = 1,
+			.early_init = 1,
+		},
+	}"
+
+	# VR Power Delivery Design
+	register "VrPowerDeliveryDesign" = "0x12"
+
+	register "SerialIoDevMode" = "{
+		[PchSerialIoIndexI2C0]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C1]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C2]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C4]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
+		[PchSerialIoIndexSPI0]  = PchSerialIoPci,
+		[PchSerialIoIndexSPI1]  = PchSerialIoDisabled,
+		[PchSerialIoIndexUART0] = PchSerialIoPci,
+		[PchSerialIoIndexUART1] = PchSerialIoPci,
+		[PchSerialIoIndexUART2] = PchSerialIoPci,
+	}"
+
+	register "DisableHeciRetry" = "1"
+
 	device cpu_cluster 0 on
 		device lapic 0 on end
 	end
@@ -14,24 +142,86 @@ chip soc/intel/cannonlake
 		device pci 01.2 on # PEG x4 or disabled / Slot 4
 			smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT4" "SlotDataBusWidth4X"
 		end
+		device pci 02.0 on end	# Integrated Graphics Device
 		device pci 04.0 on  end # SA Thermal device
 		device pci 08.0 on  end # Gaussian Mixture
 		device pci 12.0 on  end # Thermal Subsystem
 		device pci 14.0 on  end # USB xHCI
 		device pci 14.1 off end # USB xDCI (OTG)
 		device pci 14.2 on  end # RAM controller
+		device pci 14.3 on
+			chip drivers/wifi/generic
+				register "wake" = "PME_B0_EN_BIT"
+				device generic 0 on end
+			end
+		end  # CNVi wifi
 		device pci 14.5 off end # SDCard
-
 		device pci 16.0 on  end # Management Engine Interface 1
 		device pci 16.1 on  end # Management Engine Interface 2
 		device pci 16.4 off end # Management Engine Interface 3
 		device pci 17.0 on  end # SATA
-		device pci 1d.6 on	# PCIe root port 15
-			device pci 00.0 on      # Aspeed PCI Bridge
+		# This device does not have any function on CNP-H, but it needs
+		# to be here so that the resource allocator is aware of UART 2.
+		device pci 19.0 hidden end
+		chip soc/intel/common/block/uart
+			device pci 19.2 hidden
+				register "devid" = "PCI_DEVICE_ID_INTEL_CNP_H_UART2"
+			end # UART #2, in ACPI mode
+		end
+		device pci 1b.4 on	# PCIe root port 21 (Slot 1)
+			smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X"
+			register "PcieRpEnable[20]" = "1"
+			register "PcieRpLtrEnable[20]" = "1"
+			register "PcieRpSlotImplemented[20]" = "1"
+			register "PcieRpMaxPayload[20]" = "RpMaxPayload_256"
+			register "PcieRpAdvancedErrorReporting[20]" = "1"
+			register "PcieRpAspm[20]" = "AspmDisabled"
+		end
+		device pci 1c.0 on	# PCIe root port 1 (Slot 3)
+			smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT3" "SlotDataBusWidth4X"
+			register "PcieRpEnable[0]" = "1"
+			register "PcieRpLtrEnable[0]" = "1"
+			register "PcieRpSlotImplemented[0]" = "1"
+			register "PcieRpMaxPayload[0]" = "RpMaxPayload_256"
+			register "PcieRpAdvancedErrorReporting[0]" = "1"
+			register "PcieRpAspm[0]" = "AspmDisabled"
+		end
+		device pci 1c.4 on	# PCIe root port 5 (PHY 3)
+			register "PcieRpEnable[4]" = "1"
+		end
+		device pci 1c.5 on	# PCIe root port 6 (PHY 4)
+			register "PcieRpEnable[5]" = "1"
+		end
+		device pci 1c.6 on	# PCIe root port 7 (PHY 2)
+			register "PcieRpEnable[6]" = "1"
+		end
+		device pci 1c.7 on	# PCIe root port 8 (PHY 1)
+			register "PcieRpEnable[7]" = "1"
+		end
+		device pci 1d.0 on	# PCIe root port 9 (M2 M)
+			smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "M2 M" "SlotDataBusWidth4X"
+			register "PcieRpEnable[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "1"
+		end
+		device pci 1d.5 on	# PCIe root port 14 (PHY 0)
+			register "PcieRpEnable[13]" = "1"
+		end
+		device pci 1d.6 on	# PCIe root port 15 (BMC)
+			device pci 00.0 on	# Aspeed PCI Bridge
 				device pci 00.0 on end  # Aspeed 2500 VGA
 			end
+			register "PcieRpEnable[14]" = "1"
 			register "PcieRpSlotImplemented[14]" = "1"
 		end
+		device pci 1d.7 on	# PCIe root port 16 (M.2 E/CNVi)
+			# Disabled when CNVi is present
+			register "PcieRpEnable[15]" = "1"
+			register "PcieRpSlotImplemented[15]" = "1"
+		end
+		device pci 1e.0 on  end # UART #0
+		device pci 1e.1 on  end # UART #1
+		device pci 1e.2 off end # GSPI #0
+		device pci 1e.3 off end # GSPI #1
 		device pci 1f.0 on	# LPC Interface
 			chip drivers/pc80/tpm
 				device pnp 0c31.0 on end
@@ -44,5 +234,4 @@ chip soc/intel/cannonlake
 		device pci 1f.4 on     end # SMBus
 		device pci 1f.5 on     end # PCH SPI
 	end
-
 end
diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
deleted file mode 100644
index 16ba724e9e..0000000000
--- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
+++ /dev/null
@@ -1,204 +0,0 @@
-chip soc/intel/cannonlake
-
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
-
-	# FSP configuration
-
-	register "SataMode" = "0"		# AHCI
-	register "SataSalpSupport" = "0"
-	register "satapwroptimize" = "1"
-	register "SataPortsDevSlp[1]" = "1"	# PCH_M2_SATA_DEVSLP1
-
-	register "SataPortsEnable[0]" = "1"
-	register "SataPortsEnable[1]" = "1"	# depends on SATAXPCIE1
-	register "SataPortsEnable[2]" = "0"	# Not used for SATA
-	register "SataPortsEnable[3]" = "0"	# Not used for SATA
-	register "SataPortsEnable[4]" = "1"
-	register "SataPortsEnable[5]" = "1"
-	register "SataPortsEnable[6]" = "1"
-	register "SataPortsEnable[7]" = "1"
-
-	register "SataPortsHotPlug[0]" = "1"
-	register "SataPortsHotPlug[1]" = "1"
-	register "SataPortsHotPlug[2]" = "0"
-	register "SataPortsHotPlug[3]" = "0"
-	register "SataPortsHotPlug[4]" = "1"
-	register "SataPortsHotPlug[5]" = "1"
-	register "SataPortsHotPlug[6]" = "1"
-	register "SataPortsHotPlug[7]" = "1"
-
-	register "PchHdaDspEnable" = "0"
-	register "PchHdaAudioLinkHda" = "1"
-
-	# Controls the CLKREQ, not the output directly.
-	# Depends on the CLKREQ to CLK gen mapping below
-	register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE"		# BMC, PCIe Slot1, Slot2, Slot4, Slot6
-	register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE"		# PHY3
-	register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED"
-	register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED"
-	register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE"		# RP9 M2 Slot M x4
-	register "PcieClkSrcUsage[5]" = "PCIE_CLK_FREE"		# RP16 M2 Slot E x1
-	register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED"
-	register "PcieClkSrcUsage[7]" = "PCIE_CLK_NOTUSED"
-	register "PcieClkSrcUsage[8]" = "PCIE_CLK_NOTUSED"
-	register "PcieClkSrcUsage[9]" = "PCIE_CLK_NOTUSED"
-	register "PcieClkSrcUsage[10]" = "PCIE_CLK_NOTUSED"
-	register "PcieClkSrcUsage[11]" = "PCIE_CLK_NOTUSED"
-	register "PcieClkSrcUsage[12]" = "PCIE_CLK_NOTUSED"
-	register "PcieClkSrcUsage[13]" = "PCIE_CLK_FREE"	# PHY 0, PHY 1, PHY 2, PHY 4
-	register "PcieClkSrcUsage[14]" = "PCIE_CLK_FREE"	# PB
-	register "PcieClkSrcUsage[15]" = "PCIE_CLK_FREE"	# PCIe Slot3
-
-	# Only map M2 CLKREQ to CLK gen
-	register "PcieClkSrcClkReq[4]" = "4"	# M2_M_CLK_REQ_n
-	register "PcieClkSrcClkReq[5]" = "5"	# M2_E_CLK_REQ_n
-
-	# USB OC5-7: not connected
-	register "usb2_ports" = "{
-
-#define HERMES_USB2_CONFIG(pin) { \
-	.enable        = 1, \
-	.ocpin         = (pin), \
-	.tx_bias       = USB2_BIAS_0MV, \
-	.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, \
-	.pre_emp_bias  = USB2_BIAS_28P15MV, \
-	.pre_emp_bit   = USB2_FULL_BIT_PRE_EMP, \
-}
-		[0] = HERMES_USB2_CONFIG(OC0),		/* USB3 rear panel 1 */
-		[1] = HERMES_USB2_CONFIG(OC0),
-		[2] = HERMES_USB2_CONFIG(OC1),		/* USB3 rear panel 2 */
-		[3] = HERMES_USB2_CONFIG(OC1),
-		[4] = HERMES_USB2_CONFIG(OC2),		/* USB3 internal header CN_USB3_HDR */
-		[5] = HERMES_USB2_CONFIG(OC2),
-		[6] = HERMES_USB2_CONFIG(OC3),		/* USB2 internal header USB2_HDR1 */
-		[7] = HERMES_USB2_CONFIG(OC3),
-		[8] = HERMES_USB2_CONFIG(OC4),		/* USB2 internal header USB2_HDR1 */
-		[9] = HERMES_USB2_CONFIG(OC4),
-		[10] = HERMES_USB2_CONFIG(OC_SKIP),	/* BMC */
-		[11] = USB2_PORT_EMPTY,
-		[12] = HERMES_USB2_CONFIG(OC_SKIP),	/* piggy-back */
-		[13] = HERMES_USB2_CONFIG(OC_SKIP),	/* M.2 key E */
-	}"
-
-	# USB Config 2.0/3.0
-	# Enumeration starts at 0
-	# USB 3.0
-	# USB OC0: RP1
-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
-
-	# USB OC1: RP2
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)"
-	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)"
-
-	# USB OC2:  Internal Header CN_USB3_HDR
-	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)"
-	register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)"
-
-	# Thermal
-	register "tcc_offset" = "1"     # TCC of 99C
-
-
-	# Disable S0ix
-	register "s0ix_enable" = "0"
-
-	# Enable Turbo
-	register "eist_enable" = "1"
-
-	register "common_soc_config" = "{
-		.gspi[0] = {
-			.speed_mhz = 1,
-			.early_init = 1,
-		},
-	}"
-
-	# VR Power Delivery Design
-	register "VrPowerDeliveryDesign" = "0x12"
-
-	register "SerialIoDevMode" = "{
-		[PchSerialIoIndexI2C0]  = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C1]  = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C2]  = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C4]  = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
-		[PchSerialIoIndexSPI0]  = PchSerialIoPci,
-		[PchSerialIoIndexSPI1]  = PchSerialIoDisabled,
-		[PchSerialIoIndexUART0] = PchSerialIoPci,
-		[PchSerialIoIndexUART1] = PchSerialIoPci,
-		[PchSerialIoIndexUART2] = PchSerialIoPci,
-	}"
-
-	register "DisableHeciRetry" = "1"
-
-	device domain 0 on
-		device pci 02.0 on end	# Integrated Graphics Device
-		device pci 14.3 on
-			chip drivers/wifi/generic
-				register "wake" = "PME_B0_EN_BIT"
-				device generic 0 on end
-			end
-		end  # CNVi wifi
-
-		# This device does not have any function on CNP-H, but it needs
-		# to be here so that the resource allocator is aware of UART 2.
-		device pci 19.0 hidden end
-		chip soc/intel/common/block/uart
-			device pci 19.2 hidden
-				register "devid" = "PCI_DEVICE_ID_INTEL_CNP_H_UART2"
-			end # UART #2, in ACPI mode
-		end
-		device pci 1b.4 on	# PCIe root port 21 (Slot 1)
-			smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X"
-			register "PcieRpEnable[20]" = "1"
-			register "PcieRpLtrEnable[20]" = "1"
-			register "PcieRpSlotImplemented[20]" = "1"
-			register "PcieRpMaxPayload[20]" = "RpMaxPayload_256"
-			register "PcieRpAdvancedErrorReporting[20]" = "1"
-			register "PcieRpAspm[20]" = "AspmDisabled"
-		end
-		device pci 1c.0 on	# PCIe root port 1 (Slot 3)
-			smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT3" "SlotDataBusWidth4X"
-			register "PcieRpEnable[0]" = "1"
-			register "PcieRpLtrEnable[0]" = "1"
-			register "PcieRpSlotImplemented[0]" = "1"
-			register "PcieRpMaxPayload[0]" = "RpMaxPayload_256"
-			register "PcieRpAdvancedErrorReporting[0]" = "1"
-			register "PcieRpAspm[0]" = "AspmDisabled"
-		end
-		device pci 1c.4 on	# PCIe root port 5 (PHY 3)
-			register "PcieRpEnable[4]" = "1"
-		end
-		device pci 1c.5 on	# PCIe root port 6 (PHY 4)
-			register "PcieRpEnable[5]" = "1"
-		end
-		device pci 1c.6 on	# PCIe root port 7 (PHY 2)
-			register "PcieRpEnable[6]" = "1"
-		end
-		device pci 1c.7 on	# PCIe root port 8 (PHY 1)
-			register "PcieRpEnable[7]" = "1"
-		end
-		device pci 1d.0 on	# PCIe root port 9 (M2 M)
-			smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "M2 M" "SlotDataBusWidth4X"
-			register "PcieRpEnable[8]" = "1"
-			register "PcieRpSlotImplemented[8]" = "1"
-		end
-		device pci 1d.5 on	# PCIe root port 14 (PHY 0)
-			register "PcieRpEnable[13]" = "1"
-		end
-		device pci 1d.6 on	# PCIe root port 15 (BMC)
-			register "PcieRpEnable[14]" = "1"
-		end
-		device pci 1d.7 on	# PCIe root port 16 (M.2 E/CNVi)
-			# Disabled when CNVi is present
-			register "PcieRpEnable[15]" = "1"
-			register "PcieRpSlotImplemented[15]" = "1"
-		end
-		device pci 1e.0 on  end # UART #0
-		device pci 1e.1 on  end # UART #1
-		device pci 1e.2 off end # GSPI #0
-		device pci 1e.3 off end # GSPI #1
-	end
-end