diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2024-06-14 17:07:29 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-06-21 15:52:24 +0000 |
| commit | 0395b4b5f274e2cfd1d1073f5d221393d8d8e253 (patch) | |
| tree | 38f0f446781366258034c7184d1e387346e36578 /src | |
| parent | f40f5b6dd5274f02bb0c84d05ed1cf112e1187e6 (diff) | |
mb/emulation/qemu: Configure TSEG size
Configure TSEG size by reading CONFIG_SMM_TSEG_SIZE in romstage.
The remaining Qemu code can already handle the bigger TSEG region.
TEST: Increased TSEG to 8MiB.
Change-Id: I1ae5ac93ecca83ae9c319c666aac844bbd5b259f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/qemu-x86/Kconfig | 5 | ||||
| -rw-r--r-- | src/mainboard/emulation/qemu-q35/romstage.c | 17 |
2 files changed, 22 insertions, 0 deletions
diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index 221a7bae45..e1469d6f1e 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -31,6 +31,11 @@ config CPU_QEMU_X86_TSEG_SMM endchoice +config SMM_TSEG_SIZE + hex + depends on SMM_TSEG + default 0x100000 + config MAX_CPUS int default 32 if SMM_TSEG diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index ff06640bf9..d4700d5fb6 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -7,6 +7,8 @@ #include "q35.h" +#define TSEG_SZ_MASK (3 << 1) + void mainboard_romstage_entry(void) { i82801ix_early_init(); @@ -14,5 +16,20 @@ void mainboard_romstage_entry(void) if (!CONFIG(BOOTBLOCK_CONSOLE)) mainboard_machine_check(); + /* Configure requested TSEG size */ + switch (CONFIG_SMM_TSEG_SIZE) { + case 1 * MiB: + pci_update_config8(HOST_BRIDGE, ESMRAMC, ~TSEG_SZ_MASK, 0 << 1); + break; + case 2 * MiB: + pci_update_config8(HOST_BRIDGE, ESMRAMC, ~TSEG_SZ_MASK, 1 << 1); + break; + case 8 * MiB: + pci_update_config8(HOST_BRIDGE, ESMRAMC, ~TSEG_SZ_MASK, 2 << 1); + break; + default: + printk(BIOS_WARNING, "%s: Unsupported TSEG size: 0x%x\n", __func__, CONFIG_SMM_TSEG_SIZE); + } + cbmem_recovery(0); } |