diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-06-01 22:04:26 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-06-07 18:54:43 +0000 |
| commit | 022c4a490c7af97e7b31636152c8da3464db0056 (patch) | |
| tree | 8e84048f88afb276176d390bb280de49b7de171c /src | |
| parent | 0fddbc75e35d044961393e531a465e4dffee8bf3 (diff) | |
soc/amd/glinda/acpi: use ROOT_BRIDGE macro
Use the ROOT_BRIDGE macro in soc.asl to replace the pci0.asl file. The
soc/amd/common/acpi/lpc.asl file which was included in the now removed
pci0.asl file now gets included in the correct scope in the soc.asl
file.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I373c171f7f4754391012b41d44965561ced4f0b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75595
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/amd/glinda/acpi/pci0.asl | 26 | ||||
| -rw-r--r-- | src/soc/amd/glinda/acpi/soc.asl | 7 |
2 files changed, 6 insertions, 27 deletions
diff --git a/src/soc/amd/glinda/acpi/pci0.asl b/src/soc/amd/glinda/acpi/pci0.asl deleted file mode 100644 index 3f29c335d8..0000000000 --- a/src/soc/amd/glinda/acpi/pci0.asl +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* TODO: Update for Glinda */ - -Device(PCI0) { - Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ - Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ - - /* Operating System Capabilities Method */ - Method(_OSC, 4) { - CreateDWordField(Arg3, 0, CDW1) /* Capabilities dword 1 */ - - /* Check for proper PCI/PCIe UUID */ - If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { - /* Let OS control everything */ - Return (Arg3) - } Else { - CDW1 |= 4 /* Unrecognized UUID */ - Return (Arg3) - } - } - - /* 0:14.3 - LPC */ - #include <soc/amd/common/acpi/lpc.asl> - -} /* End PCI0 scope */ diff --git a/src/soc/amd/glinda/acpi/soc.asl b/src/soc/amd/glinda/acpi/soc.asl index b810a2bdb8..964cad94b5 100644 --- a/src/soc/amd/glinda/acpi/soc.asl +++ b/src/soc/amd/glinda/acpi/soc.asl @@ -2,6 +2,7 @@ /* TODO: Update for Glinda */ +#include <soc/amd/common/acpi/pci_root.asl> #include "globalnvs.asl" Scope(\_SB) { @@ -18,7 +19,11 @@ Scope(\_SB) { #include "mmio.asl" - #include "pci0.asl" + ROOT_BRIDGE(PCI0) + + Scope(PCI0) { + #include <soc/amd/common/acpi/lpc.asl> + } /* End PCI0 scope */ } /* End \_SB scope */ #include <soc/amd/common/acpi/alib.asl> |