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authorKyösti Mälkki <kyosti.malkki@gmail.com>2017-08-29 13:08:43 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2017-08-31 04:48:43 +0000
commitfd77d714f968458670ef7a477996ed61af46650b (patch)
tree208548cd3775f9913c4128bd1d2f286d4301655f /src
parentc87c6e68a3e76fc365a47ccebd280b816750172b (diff)
AGESA f12 vendorcode: Remove unused sources
Change-Id: Ia22c96ee19babb3fc64d57966ea923eb5ec4b48f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Azalia/AzaliaEnv.c81
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Azalia/AzaliaLate.c59
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Azalia/AzaliaMid.c528
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Azalia/AzaliaReset.c77
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Common/AcpiLib.c231
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Common/AcpiLib.h87
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchBiosRamUsage.h67
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchCommon.c47
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchCommonCfg.h1092
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchCommonSmm.c71
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchDef.h444
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchLib.c564
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchPeLib.c196
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Common/MemLib.c144
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Common/PciLib.c94
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Fch.h1949
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/FchPlatform.h117
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/Family/Hudson2/Hudson2GecEnvService.c104
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/Family/Hudson2/Hudson2GecService.c78
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/GecEnv.c65
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/GecLate.c61
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/GecMid.c63
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/GecReset.c83
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c505
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiLateService.c343
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiMidService.c48
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c142
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiEnv.c106
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiLate.c135
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiMid.c64
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiReset.c200
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmEnvService.c265
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmLateService.c170
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmMidService.c248
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/HwmEnv.c75
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/HwmLate.c84
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/HwmMid.c74
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/HwmReset.c77
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Ide/IdeEnv.c120
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Ide/IdeLate.c59
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Ide/IdeMid.c61
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/Family/Hudson2/Hudson2ImcService.c126
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/FchEcEnv.c185
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/FchEcLate.c61
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/FchEcMid.c61
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/FchEcReset.c132
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcEnv.c153
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcLate.c82
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcLib.c279
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcMid.c63
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcReset.c94
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/Family/Hudson2/EnvDefHudson2.c355
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/Family/Hudson2/ResetDefHudson2.c87
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitEnv.c113
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitLate.c93
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitMid.c91
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitReset.c100
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitS3.c94
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchTaskLauncher.c62
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchTaskLauncher.h80
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/InitEnvDef.c170
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/InitResetDef.c63
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Ir/IrEnv.c101
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Ir/IrLate.c60
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Ir/IrMid.c60
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Oem.h141
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Pcib/PcibEnv.c107
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Pcib/PcibLate.c94
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Pcib/PcibMid.c60
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Pcib/PcibReset.c112
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbEnv.c79
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbLate.c75
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbMid.c62
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbReset.c64
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbEnvService.c360
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbResetService.c126
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbService.c47
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppResetService.c123
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppService.c207
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieEnvService.c77
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieService.c46
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppEnv.c562
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppHp.c159
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppLate.c351
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppLib.c193
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppMid.c64
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppReset.c65
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieEnv.c67
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieLate.c61
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieMid.c61
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieReset.c63
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/AhciEnv.c86
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/AhciLate.c61
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/AhciLib.c68
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/AhciMid.c70
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Family/Hudson2/Hudson2SataEnvService.c218
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Family/Hudson2/Hudson2SataResetService.c131
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Family/Hudson2/Hudson2SataService.c681
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Ide2AhciEnv.c86
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Ide2AhciLate.c82
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Ide2AhciLib.c67
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Ide2AhciMid.c76
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/RaidEnv.c105
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/RaidLate.c65
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/RaidLib.c69
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/RaidMid.c74
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataEnv.c105
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataEnvLib.c88
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataIdeEnv.c103
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataIdeLate.c71
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataIdeLib.c46
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataIdeMid.c75
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataLate.c118
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataLib.c260
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataMid.c198
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataReset.c65
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Sd/SdEnv.c102
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Sd/SdLate.c60
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Sd/SdMid.c61
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/LpcEnv.c110
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/LpcLate.c59
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/LpcMid.c60
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/LpcReset.c131
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/SpiEnv.c61
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/SpiLate.c113
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/SpiMid.c61
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/SpiReset.c113
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/EhciEnv.c60
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/EhciLate.c60
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/EhciMid.c159
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/EhciReset.c77
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciEnvService.c44
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciLateService.c47
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciMidService.c179
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciEnvService.c47
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciLateService.c48
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciMidService.c105
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciEnvService.c325
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciLateService.c129
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciMidService.c48
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciResetService.c118
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/OhciEnv.c60
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/OhciLate.c60
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/OhciMid.c214
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/OhciReset.c78
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/UsbEnv.c107
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/UsbLate.c61
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/UsbMid.c68
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/UsbReset.c77
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/XhciEnv.c126
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/XhciLate.c63
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/XhciMid.c70
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/XhciRecovery.c332
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/XhciReset.c81
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c486
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c242
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-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c181
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-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.c117
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-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbCoherentFam10.c162
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbCoherentFam10.h66
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbFam10.c365
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbNonCoherentFam10.c120
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbNonCoherentFam10.h57
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbOptimizationFam10.c221
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-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbSystemFam10.c401
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-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbUtilitiesFam10.c444
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-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatDynamicDiscovery.c782
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-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatGanging.c217
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-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatNoncoherent.c374
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatNoncoherent.h80
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatOptimization.c889
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-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatRouting.c492
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-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatSublinks.c231
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-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatTrafficDistribution.c411
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-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/Features/htIds.c150
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbCoherent.c491
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbCoherent.h177
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbNonCoherent.c141
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbNonCoherent.h61
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbOptimization.c257
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbOptimization.h90
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbUtilities.c334
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbUtilities.h107
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph.c198
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph1.c69
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph2.c70
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph3Line.c75
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph3Triangle.c76
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph4Degenerate.c79
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph4FullyConnected.c82
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph4Kite.c80
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph4Line.c79
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph4Square.c79
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph4Star.c79
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph5FullyConnected.c79
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph5TwistedLadder.c88
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph6DoubloonLower.c74
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph6DoubloonUpper.c74
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph6FullyConnected.c85
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph6TwinTriangles.c91
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph6TwistedLadder.c91
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph7FullyConnected.c77
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph7TwistedLadder.c94
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph8DoubloonM.c75
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph8FullyConnected.c78
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph8Ladder.c95
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph8TwinFullyFourWays.c95
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph8TwistedLadder.c94
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/NDINTLV/mfndi.c238
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/NDINTLV/mfndi.h78
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/OLSPARE/mfspr.c169
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/OLSPARE/mfspr.h79
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mt2.c232
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mt2.h124
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mtot2.c162
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mtot2.h88
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mtspd2.c1115
-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mtspd2.h182
231 files changed, 0 insertions, 36015 deletions
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Azalia/AzaliaEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Azalia/AzaliaEnv.c
deleted file mode 100644
index 84adc69b93..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Azalia/AzaliaEnv.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config FCH HD Audio Controller
- *
- * Init Azalia Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 47028 $ @e \$Date: 2011-02-15 03:00:55 +0800 (Tue, 15 Feb 2011) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#define FILECODE PROC_FCH_AZALIA_AZALIAENV_FILECODE
-//
-// Declaration of local functions
-//
-
-/**
- * FchInitEnvAzalia - Config Azalia controller before PCI
- * emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitEnvAzalia (
- IN VOID *FchDataPtr
- )
-{
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- if ( LocalCfgPtr->Azalia.AzaliaEnable == AzDisable ) {
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEB, AccessWidth8, ~BIT0, 0);
- } else {
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEB, AccessWidth8, ~BIT0, BIT0);
- RwPci ((AZALIA_BUS_DEV_FUN << 16) + FCH_AZ_REG4C, AccessWidth8, ~BIT0, BIT0, StdHeader);
-
- if ( LocalCfgPtr->Azalia.AzaliaMsiEnable) {
- RwPci ((AZALIA_BUS_DEV_FUN << 16) + FCH_AZ_REG44, AccessWidth32, ~BIT8, BIT8, StdHeader);
- RwPci ((AZALIA_BUS_DEV_FUN << 16) + FCH_AZ_REG60, AccessWidth32, ~BIT16, BIT16, StdHeader);
- }
- }
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Azalia/AzaliaLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Azalia/AzaliaLate.c
deleted file mode 100644
index 9d37abb9e0..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Azalia/AzaliaLate.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config FCH HD Audio Controller
- *
- * Init Azalia Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#define FILECODE PROC_FCH_AZALIA_AZALIALATE_FILECODE
-
-/**
- * FchInitLateAzalia - Prepare Azalia controller to boot to OS.
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitLateAzalia (
- IN VOID *FchDataPtr
- )
-{
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Azalia/AzaliaMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Azalia/AzaliaMid.c
deleted file mode 100644
index 9ec9a2cfe0..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Azalia/AzaliaMid.c
+++ /dev/null
@@ -1,528 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config FCH HD Audio Controller
- *
- * Init Azalia Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 47028 $ @e \$Date: 2011-02-15 03:00:55 +0800 (Tue, 15 Feb 2011) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#define FILECODE PROC_FCH_AZALIA_AZALIAMID_FILECODE
-//
-// Declaration of local functions
-//
-VOID
-ConfigureAzaliaPinCmd (
- IN FCH_DATA_BLOCK *FchDataPtr,
- IN UINT32 BAR0,
- IN UINT8 ChannelNum
- );
-
-VOID
-ConfigureAzaliaSetConfigD4Dword (
- IN CODEC_ENTRY *TempAzaliaCodecEntryPtr,
- IN UINT32 ChannelNumDword,
- IN UINT32 BAR0,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * FchInitMidAzalia - Config Azalia controller after PCI
- * emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitMidAzalia (
- IN VOID *FchDataPtr
- )
-{
- UINT8 Data;
- UINT8 Index;
- BOOLEAN EnableAzalia;
- UINT32 PinRouting;
- UINT8 ChannelNum;
- UINT8 AzaliaTempVariableByte;
- UINT16 AzaliaTempVariableWord;
- UINT32 BAR0;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- EnableAzalia = FALSE;
- ChannelNum = 0;
- AzaliaTempVariableByte = 0;
- AzaliaTempVariableWord = 0;
- BAR0 = 0;
-
- if ( LocalCfgPtr->Azalia.AzaliaEnable == AzDisable ) {
- return;
- } else {
- RwPci ((AZALIA_BUS_DEV_FUN << 16) + FCH_AZ_REG04, AccessWidth8, ~BIT1, BIT1, StdHeader);
-
- if ( LocalCfgPtr->Azalia.AzaliaSsid != NULL ) {
- RwPci ((AZALIA_BUS_DEV_FUN << 16) + FCH_AZ_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Azalia.AzaliaSsid, StdHeader);
- }
-
- ReadPci ((AZALIA_BUS_DEV_FUN << 16) + FCH_AZ_REG10, AccessWidth32, &BAR0, StdHeader);
-
- if ( BAR0 != 0 ) {
- if ( BAR0 != 0xFFFFFFFF ) {
- BAR0 &= ~(0x03FFF);
- EnableAzalia = TRUE;
- }
- }
- }
-
- if ( EnableAzalia ) {
- //
- // Get SDIN Configuration
- //
- if ( LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin0 == 2 ) {
- RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG167, AccessWidth8, 0, 0x3E);
- RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG167, AccessWidth8, 0, 0x00);
- } else {
- RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG167, AccessWidth8, 0, 0x0);
- RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG167, AccessWidth8, 0, 0x01);
- }
-
- if ( LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin1 == 2 ) {
- RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG168, AccessWidth8, 0, 0x3E);
- RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG168, AccessWidth8, 0, 0x00);
- } else {
- RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG168, AccessWidth8, 0, 0x0);
- RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG168, AccessWidth8, 0, 0x01);
- }
-
- if ( LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin2 == 2 ) {
- RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG169, AccessWidth8, 0, 0x3E);
- RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG169, AccessWidth8, 0, 0x00);
- } else {
- RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG169, AccessWidth8, 0, 0x0);
- RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG169, AccessWidth8, 0, 0x01);
- }
-
- if ( LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin3 == 2 ) {
- RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG170, AccessWidth8, 0, 0x3E);
- RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG170, AccessWidth8, 0, 0x00);
- } else {
- RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG170, AccessWidth8, 0, 0x0);
- RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG170, AccessWidth8, 0, 0x01);
- }
- //
- // INT#A Azalia resource
- //
- Data = 0x93; /// Azalia APIC index
- LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Data, StdHeader);
- Data = 0x10; /// IRQ16 (INTA#)
- LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Data, StdHeader);
-
- Index = 11;
- do {
- ReadMem ( BAR0 + FCH_AZ_BAR_REG08, AccessWidth8, &AzaliaTempVariableByte);
- AzaliaTempVariableByte |= BIT0;
- WriteMem (BAR0 + FCH_AZ_BAR_REG08, AccessWidth8, &AzaliaTempVariableByte);
- FchStall (1000, StdHeader);
- ReadMem (BAR0 + FCH_AZ_BAR_REG08, AccessWidth8, &AzaliaTempVariableByte);
- Index--;
- } while ((! (AzaliaTempVariableByte & BIT0)) && (Index > 0) );
-
- if ( Index == 0 ) {
- return;
- }
-
- FchStall (1000, StdHeader);
- ReadMem ( BAR0 + FCH_AZ_BAR_REG0E, AccessWidth16, &AzaliaTempVariableWord);
- if ( AzaliaTempVariableWord & 0x0F ) {
-
- //
- //at least one azalia codec found
- //
- //PinRouting = LocalCfgPtr->Azalia.AZALIA_CONFIG.AzaliaSdinPin;
- //new structure need make up PinRouting
- //need adjust later!!!
- //
- PinRouting = 0;
- PinRouting = (UINT32 )LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin3;
- PinRouting <<= 8;
- PinRouting |= (UINT32 )LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin2;
- PinRouting <<= 8;
- PinRouting |= (UINT32 )LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin1;
- PinRouting <<= 8;
- PinRouting |= (UINT32 )LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin0;
-
- do {
- if ( ( ! (PinRouting & BIT0) ) && (PinRouting & BIT1) ) {
- ConfigureAzaliaPinCmd (LocalCfgPtr, BAR0, ChannelNum);
- }
- PinRouting >>= 8;
- ChannelNum++;
- } while ( ChannelNum != 4 );
- } else {
- //
- //No Azalia codec found
- //
- if ( LocalCfgPtr->Azalia.AzaliaEnable != AzEnable ) {
- EnableAzalia = FALSE; ///set flag to disable Azalia
- }
- }
- }
-
- if ( EnableAzalia ) {
- //
- //redo clear reset
- //
- do {
- AzaliaTempVariableWord = 0;
- WriteMem ( BAR0 + FCH_AZ_BAR_REG0C, AccessWidth16, &AzaliaTempVariableWord);
- ReadMem (BAR0 + FCH_AZ_BAR_REG08, AccessWidth8, &AzaliaTempVariableByte);
- AzaliaTempVariableByte &= ~(BIT0);
- WriteMem (BAR0 + FCH_AZ_BAR_REG08, AccessWidth8, &AzaliaTempVariableByte);
- ReadMem (BAR0 + FCH_AZ_BAR_REG08, AccessWidth8, &AzaliaTempVariableByte);
- } while ( AzaliaTempVariableByte & BIT0 );
-
- if ( LocalCfgPtr->Azalia.AzaliaSnoop == 1 ) {
- RwPci ((AZALIA_BUS_DEV_FUN << 16) + FCH_AZ_REG42, AccessWidth8, 0xFF, BIT1 + BIT0, StdHeader);
- }
- } else {
- //
- //disable Azalia controller
- //
- RwPci ((AZALIA_BUS_DEV_FUN << 16) + FCH_AZ_REG04, AccessWidth16, 0, 0, StdHeader);
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEB, AccessWidth8, ~BIT0, 0);
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEB, AccessWidth8, ~BIT0, 0);
- }
-}
-
-/**
- * Pin Config for ALC880, ALC882 and ALC883.
- *
- *
- *
- */
-CODEC_ENTRY AzaliaCodecAlc882Table[] =
-{
- {0x14, 0x01014010},
- {0x15, 0x01011012},
- {0x16, 0x01016011},
- {0x17, 0x01012014},
- {0x18, 0x01A19030},
- {0x19, 0x411111F0},
- {0x1a, 0x01813080},
- {0x1b, 0x411111F0},
- {0x1C, 0x411111F0},
- {0x1d, 0x411111F0},
- {0x1e, 0x01441150},
- {0x1f, 0x01C46160},
- {0xff, 0xffffffff}
-};
-
-/**
- * Pin Config for ALC0262.
- *
- *
- *
- */
-CODEC_ENTRY AzaliaCodecAlc262Table[] =
-{
- {0x14, 0x01014010},
- {0x15, 0x411111F0},
- {0x16, 0x411111F0},
- {0x18, 0x01A19830},
- {0x19, 0x02A19C40},
- {0x1a, 0x01813031},
- {0x1b, 0x02014C20},
- {0x1c, 0x411111F0},
- {0x1d, 0x411111F0},
- {0x1e, 0x0144111E},
- {0x1f, 0x01C46150},
- {0xff, 0xffffffff}
-};
-
-/**
- * Pin Config for ALC0269.
- *
- *
- *
- */
-CODEC_ENTRY AzaliaCodecAlc269Table[] =
-{
- {0x12, 0x99A308F0},
- {0x14, 0x99130010},
- {0x15, 0x0121101F},
- {0x16, 0x99036120},
- {0x18, 0x01A19850},
- {0x19, 0x99A309F0},
- {0x1a, 0x01813051},
- {0x1b, 0x0181405F},
- {0x1d, 0x40134601},
- {0x1e, 0x01442130},
- {0x11, 0x99430140},
- {0x20, 0x0030FFFF},
- {0xff, 0xffffffff}
-};
-
-/**
- * Pin Config for ALC0861.
- *
- *
- *
- */
-CODEC_ENTRY AzaliaCodecAlc861Table[] =
-{
- {0x01, 0x8086C601},
- {0x0B, 0x01014110},
- {0x0C, 0x01813140},
- {0x0D, 0x01A19941},
- {0x0E, 0x411111F0},
- {0x0F, 0x02214420},
- {0x10, 0x02A1994E},
- {0x11, 0x99330142},
- {0x12, 0x01451130},
- {0x1F, 0x411111F0},
- {0x20, 0x411111F0},
- {0x23, 0x411111F0},
- {0xff, 0xffffffff}
-};
-
-/**
- * Pin Config for ALC0889.
- *
- *
- *
- */
-CODEC_ENTRY AzaliaCodecAlc889Table[] =
-{
- {0x11, 0x411111F0},
- {0x14, 0x01014010},
- {0x15, 0x01011012},
- {0x16, 0x01016011},
- {0x17, 0x01013014},
- {0x18, 0x01A19030},
- {0x19, 0x411111F0},
- {0x1a, 0x411111F0},
- {0x1b, 0x411111F0},
- {0x1C, 0x411111F0},
- {0x1d, 0x411111F0},
- {0x1e, 0x01442150},
- {0x1f, 0x01C42160},
- {0xff, 0xffffffff}
-};
-
-/**
- * Pin Config for ADI1984.
- *
- *
- *
- */
-CODEC_ENTRY AzaliaCodecAd1984Table[] =
-{
- {0x11, 0x0221401F},
- {0x12, 0x90170110},
- {0x13, 0x511301F0},
- {0x14, 0x02A15020},
- {0x15, 0x50A301F0},
- {0x16, 0x593301F0},
- {0x17, 0x55A601F0},
- {0x18, 0x55A601F0},
- {0x1A, 0x91F311F0},
- {0x1B, 0x014511A0},
- {0x1C, 0x599301F0},
- {0xff, 0xffffffff}
-};
-
-/**
- * FrontPanel Config table list
- *
- *
- *
- */
-CODEC_ENTRY FrontPanelAzaliaCodecTableList[] =
-{
- {0x19, 0x02A19040},
- {0x1b, 0x02214020},
- {0xff, 0xffffffff}
-};
-
-/**
- * Current HD Audio support codec list
- *
- *
- *
- */
-CODEC_TBL_LIST AzaliaCodecTableList[] =
-{
- {0x010ec0880, &AzaliaCodecAlc882Table[0]},
- {0x010ec0882, &AzaliaCodecAlc882Table[0]},
- {0x010ec0883, &AzaliaCodecAlc882Table[0]},
- {0x010ec0885, &AzaliaCodecAlc882Table[0]},
- {0x010ec0889, &AzaliaCodecAlc889Table[0]},
- {0x010ec0262, &AzaliaCodecAlc262Table[0]},
- {0x010ec0269, &AzaliaCodecAlc269Table[0]},
- {0x010ec0861, &AzaliaCodecAlc861Table[0]},
- {0x011d41984, &AzaliaCodecAd1984Table[0]},
- { (UINT32) 0x0FFFFFFFF, (CODEC_ENTRY*) (UINTN)0x0FFFFFFFF}
-};
-
-/**
- * ConfigureAzaliaPinCmd - Configuration HD Audio PIN Command
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- * @param[in] BAR0 HD Audio BAR0 base address.
- * @param[in] ChannelNum Channel Number.
- *
- */
-VOID
-ConfigureAzaliaPinCmd (
- IN FCH_DATA_BLOCK *FchDataPtr,
- IN UINT32 BAR0,
- IN UINT8 ChannelNum
- )
-{
- UINT32 AzaliaTempVariable;
- UINT32 ChannelNumDword;
- CODEC_TBL_LIST *TempAzaliaOemCodecTablePtr;
- CODEC_ENTRY *TempAzaliaCodecEntryPtr;
-
- if ( (FchDataPtr->Azalia.AzaliaPinCfg) != 1 ) {
- return;
- }
-
- ChannelNumDword = ChannelNum << 28;
- AzaliaTempVariable = 0xF0000;
- AzaliaTempVariable |= ChannelNumDword;
-
- WriteMem (BAR0 + FCH_AZ_BAR_REG60, AccessWidth32, &AzaliaTempVariable);
- FchStall (600, FchDataPtr->StdHeader);
- ReadMem (BAR0 + FCH_AZ_BAR_REG64, AccessWidth32, &AzaliaTempVariable);
-
- if ( ((FchDataPtr->Azalia.AzaliaOemCodecTablePtr) == NULL) || ((FchDataPtr->Azalia.AzaliaOemCodecTablePtr) == ((CODEC_TBL_LIST*) (UINTN)0xFFFFFFFF))) {
- TempAzaliaOemCodecTablePtr = (CODEC_TBL_LIST*) (&AzaliaCodecTableList[0]);
- } else {
- TempAzaliaOemCodecTablePtr = (CODEC_TBL_LIST*) FchDataPtr->Azalia.AzaliaOemCodecTablePtr;
- }
-
- while ( TempAzaliaOemCodecTablePtr->CodecId != 0xFFFFFFFF ) {
- if ( TempAzaliaOemCodecTablePtr->CodecId == AzaliaTempVariable ) {
- break;
- } else {
- ++TempAzaliaOemCodecTablePtr;
- }
- }
-
- if ( TempAzaliaOemCodecTablePtr->CodecId != 0xFFFFFFFF ) {
- TempAzaliaCodecEntryPtr = (CODEC_ENTRY*) TempAzaliaOemCodecTablePtr->CodecTablePtr;
- if ( ((FchDataPtr->Azalia.AzaliaOemCodecTablePtr) == NULL) || ((FchDataPtr->Azalia.AzaliaOemCodecTablePtr) == ((CODEC_TBL_LIST*) (UINTN)0xFFFFFFFF)) ) {
- TempAzaliaCodecEntryPtr = (CODEC_ENTRY*) (TempAzaliaCodecEntryPtr);
- }
-
- ConfigureAzaliaSetConfigD4Dword (TempAzaliaCodecEntryPtr, ChannelNumDword, BAR0, FchDataPtr->StdHeader);
-
- if ( FchDataPtr->Azalia.AzaliaFrontPanel != 1 ) {
- if ( (FchDataPtr->Azalia.AzaliaFrontPanel == 2) || (FchDataPtr->Azalia.FrontPanelDetected == 1) ) {
- if ( ((FchDataPtr->Azalia.AzaliaOemFpCodecTablePtr) == NULL) || ((FchDataPtr->Azalia.AzaliaOemFpCodecTablePtr) == (VOID*) (UINTN)0xFFFFFFFF) ) {
- TempAzaliaCodecEntryPtr = (CODEC_ENTRY*) (&FrontPanelAzaliaCodecTableList[0]);
- } else {
- TempAzaliaCodecEntryPtr = (CODEC_ENTRY*) FchDataPtr->Azalia.AzaliaOemFpCodecTablePtr;
- }
-
- ConfigureAzaliaSetConfigD4Dword (TempAzaliaCodecEntryPtr, ChannelNumDword, BAR0, FchDataPtr->StdHeader);
- }
- }
- }
-}
-
-/**
- * ConfigureAzaliaSetConfigD4Dword - Configuration HD Audio Codec table
- *
- *
- * @param[in] TempAzaliaCodecEntryPtr HD Audio Codec table structure pointer.
- * @param[in] ChannelNumDword HD Audio Channel Number.
- * @param[in] BAR0 HD Audio BAR0 base address.
- * @param[in] StdHeader
- *
- */
-VOID
-ConfigureAzaliaSetConfigD4Dword (
- IN CODEC_ENTRY *TempAzaliaCodecEntryPtr,
- IN UINT32 ChannelNumDword,
- IN UINT32 BAR0,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 TempByte1;
- UINT8 TempByte2;
- UINT8 Index;
- UINT32 TempDword1;
- UINT32 TempDword2;
-
- TempDword1 = 0;
- TempDword2 = 0;
-
- while ( (TempAzaliaCodecEntryPtr->Nid) != 0xFF ) {
- TempByte1 = 0x20;
- if ( (TempAzaliaCodecEntryPtr->Nid) == 0x1 ) {
- TempByte1 = 0x24;
- }
-
- TempDword1 = TempAzaliaCodecEntryPtr->Nid;
- TempDword1 &= 0xff;
- TempDword1 <<= 20;
- TempDword1 |= ChannelNumDword;
- TempDword1 |= (0x700 << 8);
-
- for ( Index = 4; Index > 0; Index-- ) {
- do {
- ReadMem (BAR0 + FCH_AZ_BAR_REG68, AccessWidth32, &TempDword2);
- } while ( (TempDword2 & BIT0) != 0 );
-
- TempByte2 = (UINT8) (( (TempAzaliaCodecEntryPtr->Byte40) >> ((4 - Index) * 8 ) ) & 0xff);
- TempDword1 = (TempDword1 & 0xFFFF0000) + ((TempByte1 - Index) << 8) + TempByte2;
- WriteMem (BAR0 + FCH_AZ_BAR_REG60, AccessWidth32, &TempDword1);
- FchStall (60, StdHeader);
- }
-
- ++TempAzaliaCodecEntryPtr;
- }
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Azalia/AzaliaReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Azalia/AzaliaReset.c
deleted file mode 100644
index 4bc7514105..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Azalia/AzaliaReset.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config FCH HD Audio Controller
- *
- * Init Azalia Controller features (PEI phase).
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#define FILECODE PROC_FCH_AZALIA_AZALIARESET_FILECODE
-
-/**
- * FchInitResetAzalia - Config Azalia controller during Power-On
- *
- *
- *
- * @param[in] FchDataPtr
- *
- */
-VOID
-FchInitResetAzalia (
- IN VOID *FchDataPtr
- )
-{
-}
-
-/**
- * FchInitRecoveryAzalia - Config Azalia controller during
- * Crisis Recovery
- *
- *
- *
- * @param[in] FchDataPtr
- *
- */
-VOID
-FchInitRecoveryAzalia (
- IN VOID *FchDataPtr
- )
-{
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/AcpiLib.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/AcpiLib.c
deleted file mode 100644
index 16705a1293..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/AcpiLib.c
+++ /dev/null
@@ -1,231 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * FCH ACPI lib
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#define FILECODE PROC_FCH_COMMON_ACPILIB_FILECODE
-//
-//
-// Routine Description:
-//
-// Locate ACPI table
-//
-// Arguments:
-//
-// Signature - table signature
-//
-//Returns:
-//
-// pointer to ACPI table
-//
-//
-VOID*
-AcpiLocateTable (
- IN UINT32 Signature
- )
-{
- UINT32 Index;
- UINT32 *RsdPtr;
- UINT32 *Rsdt;
- UINTN TableOffset;
- DESCRIPTION_HEADER *CurrentTable;
-
- RsdPtr = (UINT32*) (UINTN) FCHOEM_ACPI_TABLE_RANGE_LOW;
- Rsdt = NULL;
- do {
- if ( *RsdPtr == ' DSR' && *(RsdPtr + 1) == ' RTP' ) {
- Rsdt = (UINT32*) (UINTN) ((RSDP_HEADER*)RsdPtr)->RsdtAddress;
- break;
- }
- RsdPtr += 4;
- } while ( RsdPtr <= (UINT32*) (UINTN) FCHOEM_ACPI_TABLE_RANGE_HIGH );
-
- if ( Rsdt != NULL && AcpiGetTableCheckSum (Rsdt) == 0 ) {
- for ( Index = 0; Index < (((DESCRIPTION_HEADER*)Rsdt)->Length - sizeof (DESCRIPTION_HEADER)) / 4; Index++ ) {
- TableOffset = *(UINTN*) ((UINT8*)Rsdt + sizeof (DESCRIPTION_HEADER) + Index * 4);
- CurrentTable = (DESCRIPTION_HEADER*)TableOffset;
- if ( CurrentTable->Signature == Signature ) {
- return CurrentTable;
- }
- }
- }
- return NULL;
-}
-
-//
-//
-// Routine Description:
-//
-// Update table CheckSum
-//
-// Arguments:
-//
-// TablePtr - table pointer
-//
-// Returns:
-//
-// none
-//
-//
-VOID
-AcpiSetTableCheckSum (
- IN VOID *TablePtr
- )
-{
- UINT8 CheckSum;
-
- CheckSum = 0;
- ((DESCRIPTION_HEADER*)TablePtr)->CheckSum = 0;
- CheckSum = AcpiGetTableCheckSum (TablePtr);
- ((DESCRIPTION_HEADER*)TablePtr)->CheckSum = (UINT8) (FCHOEM_ACPI_BYTE_CHECHSUM - CheckSum);
-}
-
-//
-//
-// Routine Description:
-//
-// Get table CheckSum - Get ACPI table checksum
-//
-// Arguments:
-//
-// TablePtr - table pointer
-//
-// Returns:
-//
-// none
-//
-//
-UINT8
-AcpiGetTableCheckSum (
- IN VOID *TablePtr
- )
-{
- return GetByteSum (TablePtr, ((DESCRIPTION_HEADER*)TablePtr)->Length);
-}
-
-
-//
-//
-// Routine Description:
-//
-// GetByteSum - Get BYTE checksum value
-//
-// Arguments:
-//
-// DataPtr - table pointer
-// Length - table length
-//
-// Returns:
-//
-// CheckSum - CheckSum value
-//
-//
-UINT8
-GetByteSum (
- IN VOID *DataPtr,
- IN UINT32 Length
- )
-{
- UINT32 Index;
- UINT8 CheckSum;
-
- CheckSum = 0;
- for ( Index = 0; Index < Length; Index++ ) {
- CheckSum = CheckSum + (*((UINT8*)DataPtr + Index));
- }
- return CheckSum;
-}
-
-//
-//
-// Routine Description:
-//
-// GetFchAcpiMmioBase - Get FCH HwAcpi MMIO Base Address
-//
-// Arguments:
-//
-// AcpiMmioBase - HwAcpi MMIO Base Address
-// StdHeader - Amd Stand Header
-//
-// Returns:
-//
-// AcpiMmioBase - HwAcpi MMIO Base Address
-//
-//
-VOID
-GetFchAcpiMmioBase (
- OUT UINT32 *AcpiMmioBase,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 AcpiMmioBaseAddressDword;
-
- ReadPmio (FCH_PMIOA_REG24 + 2, AccessWidth16, &AcpiMmioBaseAddressDword, StdHeader);
- *AcpiMmioBase = AcpiMmioBaseAddressDword << 16;
-}
-
-//
-//
-// Routine Description:
-//
-// GetFchAcpiPmBase - Get FCH HwAcpi PM Base Address
-//
-// Arguments:
-//
-// AcpiPmBase - HwAcpi PM Base Address
-// StdHeader - Amd Stand Header
-//
-// Returns:
-//
-// AcpiPmBase - HwAcpi PM Base Address
-//
-//
-VOID
-GetFchAcpiPmBase (
- OUT UINT16 *AcpiPmBase,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- ReadPmio (FCH_PMIOA_REG60, AccessWidth16, AcpiPmBase, StdHeader);
-}
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/AcpiLib.h b/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/AcpiLib.h
deleted file mode 100644
index 4dc303f4f6..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/AcpiLib.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * FCH ACPI lib
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-///
-/// RSDP - ACPI 2.0 table RSDP
-///
-typedef struct _RSDP_HEADER {
- UINT64 Signature; ///< RSDP signature "RSD PTR"
- UINT8 CheckSum; ///< checksum of the first 20 bytes
- UINT8 OEMID[6]; ///< OEM ID
- UINT8 Revision; ///< 0 for APCI 1.0, 2 for ACPI 2.0
- UINT32 RsdtAddress; ///< physical address of RSDT
- UINT32 Length; ///< total length of RSDP (including extended part)
- UINT64 XsdtAddress; ///< physical address of XSDT
- UINT8 ExtendedCheckSum; ///< chechsum of whole table
- UINT8 Reserved[3]; ///< Reserved
-} RSDP_HEADER;
-
-///
-/// DESCRIPTION_HEADER - ACPI common table header
-///
-typedef struct _DESCRIPTION_HEADER {
- UINT32 Signature; ///< ACPI signature (4 ASCII characters)
- UINT32 Length; ///< Length of table, in bytes, including header
- UINT8 Revision; ///< ACPI Specification minor version #
- UINT8 CheckSum; ///< To make sum of entire table == 0
- UINT8 OemId[6]; ///< OEM identification
- UINT8 OemTableId[8]; ///< OEM table identification
- UINT32 OemRevision; ///< OEM revision number
- UINT32 CreatorId; ///< ASL compiler vendor ID
- UINT32 CreatorRevision; ///< ASL compiler revision number
-} DESCRIPTION_HEADER;
-
-///
-/// _AcpiRegWrite - ACPI MMIO register R/W structure
-///
-typedef struct _ACPI_REG_WRITE {
- UINT8 MmioBase; /// MmioBase: Index of Fch block (For instance GPIO_BASE:0x01 SMI_BASE:0x02)
- UINT8 MmioReg; /// MmioReg : Register index
- UINT8 DataAndMask; /// DataANDMask : AND Register Data
- UINT8 DataOrMask; /// DataOrMask : Or Register Data
-} ACPI_REG_WRITE;
-
-VOID* AcpiLocateTable (IN UINT32 Signature);
-VOID AcpiSetTableCheckSum (IN VOID *TablePtr);
-UINT8 AcpiGetTableCheckSum (IN VOID *TablePtr);
-UINT8 GetByteSum (IN VOID *DataPtr, IN UINT32 Length);
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchBiosRamUsage.h b/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchBiosRamUsage.h
deleted file mode 100644
index be90192872..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchBiosRamUsage.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * FCH BIOS Ram usage
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#ifndef _FCH_BIOS_RAM_USAGE_H_
-#define _FCH_BIOS_RAM_USAGE_H_
-
-#define RESTORE_MEMORY_CONTROLLER_START 0
-#define XHCI_REGISTER_BAR00 0xD0
-#define XHCI_REGISTER_BAR01 0xD1
-#define XHCI_REGISTER_BAR02 0xD2
-#define XHCI_REGISTER_BAR03 0xD3
-#define XHCI_REGISTER_04H 0xD4
-#define XHCI_REGISTER_0CH 0xD5
-#define XHCI_REGISTER_3CH 0xD6
-#define XHCI1_REGISTER_BAR00 0xE0
-#define XHCI1_REGISTER_BAR01 0xE1
-#define XHCI1_REGISTER_BAR02 0xE2
-#define XHCI1_REGISTER_BAR03 0xE3
-#define XHCI1_REGISTER_04H 0xE4
-#define XHCI1_REGISTER_0CH 0xE5
-#define XHCI1_REGISTER_3CH 0xE6
-#define RTC_WORKAROUND_DATA_START 0xF0
-#define BOOT_TIME_FLAG_SEC 0xF8
-#define BOOT_TIME_FLAG_INT19 0xFC
-
-#endif
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchCommon.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchCommon.c
deleted file mode 100644
index 7c4fe8143d..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchCommon.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * FCH common
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "heapManager.h"
-#define FILECODE PROC_FCH_COMMON_FCHCOMMON_FILECODE
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchCommonCfg.h b/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchCommonCfg.h
deleted file mode 100644
index 03b3a22e75..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchCommonCfg.h
+++ /dev/null
@@ -1,1092 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * FCH Function Support Definition
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 49891 $ @e \$Date: 2011-03-30 15:45:37 +0800 (Wed, 30 Mar 2011) $
- *
- */
-/*;********************************************************************************
-;
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*********************************************************************************/
-#ifndef _FCH_COMMON_CFG_H_
-#define _FCH_COMMON_CFG_H_
-
-
-//-----------------------------------------------------------------------------
-// FCH DEFINITIONS AND MACROS
-//-----------------------------------------------------------------------------
-
-//
-// FCH Component Data Structure Definitions
-//
-
-/// PCI_ADDRESS - PCI access structure
-#define PCI_ADDRESS(bus, dev, func, reg) \
- (UINT32) ( (((UINT32)bus) << 24) + (((UINT32)dev) << 19) + (((UINT32)func) << 16) + ((UINT32)reg) )
-
-///
-/// - Byte Register R/W structure
-///
-typedef struct _REG8_MASK {
- UINT8 RegIndex; /// RegIndex - Reserved
- UINT8 AndMask; /// AndMask - Reserved
- UINT8 OrMask; /// OrMask - Reserved
-} REG8_MASK;
-
-
-///
-/// PCIE Reset Block
-///
-typedef enum {
- NbBlock, ///< Reset for NB PCIE
- FchBlock ///< Reset for FCH GPP
-} RESET_BLOCK;
-
-///
-/// PCIE Reset Operation
-///
-typedef enum {
- DeassertReset, ///< DeassertRese - Deassert reset
- AssertReset ///< AssertReset - Assert reset
-} RESET_OP;
-
-
-
-///
-/// SD structure
-///
-typedef struct {
- SD_MODE SdConfig; ///< SD Mode configuration
- /// @li <b>00</b> - Disabled
- /// @li <b>00</b> - AMDA, set 24,18,16, default
- /// @li <b>01</b> - DMA clear 24, 16, set 18
- /// @li <b>10</b> - PIO clear 24,18,16
- ///
- UINT8 SdSpeed; ///< SD Speed
- /// @li <b>0</b> - Low speed clear 17
- /// @li <b>1</b> - High speed, set 17, default
- ///
- UINT8 SdBitWidth; ///< SD Bit Width
- /// @li <b>0</b> - 32BIT clear 23
- /// @li <b>1</b> - 64BIT, set 23,default
- ///
-} FCH_SD;
-
-///
-/// CODEC_ENTRY - Fch HD Audio OEM Codec structure
-///
-typedef struct _CODEC_ENTRY {
- UINT8 Nid; /// Nid - Reserved
- UINT32 Byte40; /// Byte40 - Reserved
-} CODEC_ENTRY;
-
-///
-/// CODEC_TBL_LIST - Fch HD Audio Codec table list
-///
-typedef struct _CODEC_TBL_LIST {
- UINT32 CodecId; /// CodecID - Codec ID
- CODEC_ENTRY* CodecTablePtr; /// CodecTablePtr - Codec table pointer
-} CODEC_TBL_LIST;
-
-///
-/// AZALIA_PIN - HID Azalia or GPIO define structure.
-///
-typedef struct _AZALIA_PIN {
- UINT8 AzaliaSdin0; ///< AzaliaSdin0
- /// @par
- /// @li <b>00</b> - GPIO PIN
- /// @li <b>10</b> - As a Azalia SDIN pin
-
- UINT8 AzaliaSdin1; ///< AzaliaSdin1
- /// @par
- /// SDIN1 is define at BIT2 & BIT3
- /// @li <b>00</b> - GPIO PIN
- /// @li <b>10</b> - As a Azalia SDIN pin
-
- UINT8 AzaliaSdin2; ///< AzaliaSdin2
- /// @par
- /// SDIN2 is define at BIT4 & BIT5
- /// @li <b>00</b> - GPIO PIN
- /// @li <b>10</b> - As a Azalia SDIN pin
-
- UINT8 AzaliaSdin3; ///< AzaliaSdin3
- /// @par
- /// SDIN3 is define at BIT6 & BIT7
- /// @li <b>00</b> - GPIO PIN
- /// @li <b>10</b> - As a Azalia SDIN pin
-} AZALIA_PIN;
-
-///
-/// Azalia structure
-///
-typedef struct {
- HDA_CONFIG AzaliaEnable; ///< AzaliaEnable - Azalia function configuration
- BOOLEAN AzaliaMsiEnable; ///< AzaliaMsiEnable - Azalia MSI capability
- UINT32 AzaliaSsid; ///< AzaliaSsid - Azalia Subsystem ID
- UINT8 AzaliaPinCfg; ///< AzaliaPinCfg - Azalia Controller SDIN pin Configuration
- /// @par
- /// @li <b>0</b> - disable
- /// @li <b>1</b> - enable
-
- UINT8 AzaliaFrontPanel; ///< AzaliaFrontPanel - Azalia Controller Front Panel Configuration
- /// @par
- /// Support Front Panel configuration
- /// @li <b>0</b> - Auto
- /// @li <b>1</b> - disable
- /// @li <b>2</b> - enable
-
- UINT8 FrontPanelDetected; ///< FrontPanelDetected - Force Azalia Controller Front Panel Configuration
- /// @par
- /// Force Front Panel configuration
- /// @li <b>0</b> - Not Detected
- /// @li <b>1</b> - Detected
-
- UINT8 AzaliaSnoop; ///< AzaliaSnoop - Azalia Controller Snoop feature Configuration
- /// @par
- /// Azalia Controller Snoop feature Configuration
- /// @li <b>0</b> - disable
- /// @li <b>1</b> - enable
-
- UINT8 AzaliaDummy; /// AzaliaDummy - Reserved */
-
- AZALIA_PIN AzaliaConfig; /// AzaliaConfig - Azaliz Pin Configuration
-
-///
-/// AZOEMTBL - Azalia Controller OEM Codec Table Pointer
-///
- CODEC_TBL_LIST *AzaliaOemCodecTablePtr; /// AzaliaOemCodecTablePtr - Oem Azalia Codec Table Pointer
-
-///
-/// AZOEMFPTBL - Azalia Controller Front Panel OEM Table Pointer
-///
- VOID *AzaliaOemFpCodecTablePtr; /// AzaliaOemFpCodecTablePtr - Oem Front Panel Codec Table Pointer
-} FCH_AZALIA;
-
-///
-/// SPI structure
-///
-typedef struct {
- BOOLEAN LpcMsiEnable; ///< LPC MSI capability
- UINT32 LpcSsid; ///< LPC Subsystem ID
- UINT32 RomBaseAddress; ///< SpiRomBaseAddress
- /// @par
- /// SPI ROM BASE Address
- ///
- UINT8 SpiSpeed; ///< SpiSpeed - Spi Frequency
- /// @par
- /// SPI Speed [1.0] - the clock speed for non-fast read command
- /// @li <b>00</b> - 66Mhz
- /// @li <b>01</b> - 33Mhz
- /// @li <b>10</b> - 22Mhz
- /// @li <b>11</b> - 16.5Mhz
- ///
- UINT8 SpiFastSpeed; ///< FastSpeed - Spi Fast Speed feature
- /// @par
- /// TBD
- ///
- UINT8 WriteSpeed; ///< WriteSpeed - Spi Write Speed
- /// @par
- /// TBD
- ///
- UINT8 SpiMode; ///< SpiMode - Spi Mode Setting
- /// @par
- /// @li <b>101</b> - Qual-io 1-4-4
- /// @li <b>100</b> - Dual-io 1-2-2
- /// @li <b>011</b> - Qual-io 1-1-4
- /// @li <b>010</b> - Dual-io 1-1-2
- /// @li <b>111</b> - FastRead
- /// @li <b>110</b> - Normal
- ///
- UINT8 AutoMode; ///< AutoMode - Spi Auto Mode
- /// @par
- /// SPI Auto Mode
- /// @li <b>0</b> - Disabled
- /// @li <b>1</b> - Enabled
- ///
- UINT8 SpiBurstWrite; ///< SpiBurstWrite - Spi Burst Write Mode
- /// @par
- /// SPI Burst Write
- /// @li <b>0</b> - Disabled
- /// @li <b>1</b> - Enabled
-} FCH_SPI;
-
-
-///
-/// IDE structure
-///
-typedef struct {
- BOOLEAN IdeEnable; ///< IDE function switch
- BOOLEAN IdeMsiEnable; ///< IDE MSI capability
- UINT32 IdeSsid; ///< IDE controller Subsystem ID
-} FCH_IDE;
-
-///
-/// IR Structure
-///
-typedef struct {
- IR_CONFIG IrConfig; ///< IrConfig
-} FCH_IR;
-
-
-///
-/// PCI Bridge Structure
-///
-typedef struct {
- BOOLEAN PcibMsiEnable; ///< PCI-PCI Bridge MSI capability
- UINT32 PcibSsid; ///< PCI-PCI Bridge Subsystem ID
- UINT8 PciClks; ///< 33MHz PCICLK0/1/2/3 Enable, bits [0:3] used
- /// @li <b>0</b> - disable
- /// @li <b>1</b> - enable
- ///
- UINT16 PcibClkStopOverride; ///< PCIB_CLK_Stop Override
- BOOLEAN PcibClockRun; ///< Enable the auto clkrun functionality
- /// @li <b>0</b> - disable
- /// @li <b>1</b> - enable
- ///
-} FCH_PCIB;
-
-
-///
-/// - SATA Phy setting structure
-///
-typedef struct _SATA_PHY_SETTING {
- UINT16 PhyCoreControlWord; /// PhyCoreControlWord - Reserved
- UINT32 PhyFineTuneDword; /// PhyFineTuneDword - Reserved
-} SATA_PHY_SETTING;
-
-///
-/// SATA main setting structure
-///
-typedef struct _SATA_ST {
- UINT8 SataModeReg; ///< SataModeReg - Sata Controller Mode
- BOOLEAN SataEnable; ///< SataEnable - Sata Controller Function
- /// @par
- /// Sata Controller
- /// @li <b>0</b> - disable
- /// @li <b>1</b> - enable
- ///
- UINT8 Sata6AhciCap; ///< Sata6AhciCap - Reserved */
- BOOLEAN SataSetMaxGen2; ///< SataSetMaxGen2 - Set Sata Max Gen2 mode
- /// @par
- /// Sata Controller Set to Max Gen2 mode
- /// @li <b>0</b> - disable
- /// @li <b>1</b> - enable
- ///
- BOOLEAN IdeEnable; ///< IdeEnable - Ide Controller Mode
- /// @par
- /// Sata IDE Controller set to Combined Mode
- /// @li <b>0</b> - disable
- /// @li <b>1</b> - enable
- ///
- UINT8 SataClkMode; /// SataClkMode - Reserved
-} SATA_ST;
-
-///
-/// SATA_PORT_ST - SATA PORT structure
-///
-typedef struct _SATA_PORT_ST {
- UINT8 SataPortReg; ///< SATA Port bit map - bits[0:7] for ports 0 ~ 7
- /// @li <b>0</b> - disable
- /// @li <b>1</b> - enable
- ///
- BOOLEAN Port0; ///< PORT0 - 0:disable, 1:enable
- BOOLEAN Port1; ///< PORT1 - 0:disable, 1:enable
- BOOLEAN Port2; ///< PORT2 - 0:disable, 1:enable
- BOOLEAN Port3; ///< PORT3 - 0:disable, 1:enable
- BOOLEAN Port4; ///< PORT4 - 0:disable, 1:enable
- BOOLEAN Port5; ///< PORT5 - 0:disable, 1:enable
- BOOLEAN Port6; ///< PORT6 - 0:disable, 1:enable
- BOOLEAN Port7; ///< PORT7 - 0:disable, 1:enable
-} SATA_PORT_ST;
-
-///
-///< _SATA_PORT_MD - Force Each PORT to GEN1/GEN2 mode
-///
-typedef struct _SATA_PORT_MD {
- UINT16 SataPortMode; ///< SATA Port GEN1/GEN2 mode bit map - bits [0:15] for ports 0 ~ 7
- UINT8 Port0; ///< PORT0 - set BIT0 to GEN1, BIT1 - PORT0 set to GEN2
- UINT8 Port1; ///< PORT1 - set BIT2 to GEN1, BIT3 - PORT1 set to GEN2
- UINT8 Port2; ///< PORT2 - set BIT4 to GEN1, BIT5 - PORT2 set to GEN2
- UINT8 Port3; ///< PORT3 - set BIT6 to GEN1, BIT7 - PORT3 set to GEN2
- UINT8 Port4; ///< PORT4 - set BIT8 to GEN1, BIT9 - PORT4 set to GEN2
- UINT8 Port5; ///< PORT5 - set BIT10 to GEN1, BIT11 - PORT5 set to GEN2
- UINT8 Port6; ///< PORT6 - set BIT12 to GEN1, BIT13 - PORT6 set to GEN2
- UINT8 Port7; ///< PORT7 - set BIT14 to GEN1, BIT15 - PORT7 set to GEN2
-} SATA_PORT_MD;
-///
-/// SATA structure
-///
-typedef struct {
- BOOLEAN SataMsiEnable; ///< SATA MSI capability
- UINT32 SataIdeSsid; ///< SATA IDE mode SSID
- UINT32 SataRaidSsid; ///< SATA RAID mode SSID
- UINT32 SataRaid5Ssid; ///< SATA RAID 5 mode SSID
- UINT32 SataAhciSsid; ///< SATA AHCI mode SSID
-
- SATA_ST SataMode; /// SataMode - Reserved
- SATA_CLASS SataClass; ///< SataClass - SATA Controller mode [2:0]
- UINT8 SataIdeMode; ///< SataIdeMode - Sata IDE Controller mode
- /// @par
- /// @li <b>0</b> - Legacy IDE mode
- /// @li <b>1</b> - Native IDE mode
- ///
- UINT8 SataDisUnusedIdePChannel; ///< SataDisUnusedIdePChannel-Disable Unused IDE Primary Channel
- /// @par
- /// @li <b>0</b> - Channel Enable
- /// @li <b>1</b> - Channel Disable
- ///
- UINT8 SataDisUnusedIdeSChannel; ///< SataDisUnusedIdeSChannel - Disable Unused IDE Secondary Channel
- /// @par
- /// @li <b>0</b> - Channel Enable
- /// @li <b>1</b> - Channel Disable
- ///
- UINT8 IdeDisUnusedIdePChannel; ///< IdeDisUnusedIdePChannel-Disable Unused IDE Primary Channel
- /// @par
- /// @li <b>0</b> - Channel Enable
- /// @li <b>1</b> - Channel Disable
- ///
- UINT8 IdeDisUnusedIdeSChannel; ///< IdeDisUnusedIdeSChannel-Disable Unused IDE Secondary Channel
- /// @par
- /// @li <b>0</b> - Channel Enable
- /// @li <b>1</b> - Channel Disable
- ///
- UINT8 SataOptionReserved; /// SataOptionReserved - Reserved
-
- SATA_PORT_ST SataEspPort; ///< SataEspPort - SATA port is external accessible on a signal only connector (eSATA:)
-
- SATA_PORT_ST SataPortPower; ///< SataPortPower - Port Power configuration
-
- SATA_PORT_MD SataPortMd; ///< SataPortMd - Port Mode
-
- UINT8 SataAggrLinkPmCap; /// SataAggrLinkPmCap - 0:OFF 1:ON
- UINT8 SataPortMultCap; /// SataPortMultCap - 0:OFF 1:ON
- UINT8 SataClkAutoOff; /// SataClkAutoOff - AutoClockOff 0:Disabled, 1:Enabled
- UINT8 SataPscCap; /// SataPscCap 1:Enable PSC, 0:Disable PSC capability
- UINT8 BiosOsHandOff; /// BiosOsHandOff - Reserved
- UINT8 SataFisBasedSwitching; /// SataFisBasedSwitching - Reserved
- UINT8 SataCccSupport; /// SataCccSupport - Reserved
- UINT8 SataSscCap; /// SataSscCap - 1:Enable, 0:Disable SSC capability
- UINT8 SataMsiCapability; /// SataMsiCapability 0:Hidden 1:Visible
- UINT8 SataForceRaid; /// SataForceRaid 0:No function 1:Force RAID
- UINT8 SataInternal100Spread; /// SataInternal100Spread - Reserved
- UINT8 SataDebugDummy; /// SataDebugDummy - Reserved
- UINT8 SataTargetSupport8Device; /// SataTargetSupport8Device - Reserved
- UINT8 SataDisableGenericMode; /// SataDisableGenericMode - Reserved
- BOOLEAN SataAhciEnclosureManagement; /// SataAhciEnclosureManagement - Reserved
- UINT8 SataSgpio0; /// SataSgpio0 - Reserved
- UINT8 SataSgpio1; /// SataSgpio1 - Reserved
- UINT8 SataPhyPllShutDown; /// SataPhyPllShutDown - Reserved
- BOOLEAN SataHotRemovalEnh; /// SataHotRemovalEnh - Reserved
-
- SATA_PORT_ST SataHotRemovalEnhPort; ///< SataHotRemovalEnhPort - Hot Remove
-
- BOOLEAN SataOobDetectionEnh; /// SataOobDetectionEnh - TRUE
- BOOLEAN SataPowerSavingEnh; /// SataPowerSavingEnh - TRUE
- UINT8 SataMemoryPowerSaving; /// SataMemoryPowerSaving - 0-3 Default [3]
- UINT32 TempMmio; /// TempMmio - Reserved
-} FCH_SATA;
-
-
-//
-// IMC Message Register Software Interface
-//
-#define CPU_MISC_BUS_DEV_FUN ((0x18 << 3) + 3)
-
-#define MSG_SYS_TO_IMC 0x80
-#define Fun_80 0x80
-#define Fun_81 0x81
-#define Fun_82 0x82
-#define Fun_83 0x83
-#define Fun_84 0x84
-#define Fun_85 0x85
-#define Fun_86 0x86
-#define Fun_87 0x87
-#define Fun_88 0x88
-#define Fun_89 0x89
-#define Fun_90 0x90
-#define MSG_IMC_TO_SYS 0x81
-#define MSG_REG0 0x82
-#define MSG_REG1 0x83
-#define MSG_REG2 0x84
-#define MSG_REG3 0x85
-#define MSG_REG4 0x86
-#define MSG_REG5 0x87
-#define MSG_REG6 0x88
-#define MSG_REG7 0x89
-#define MSG_REG8 0x8A
-#define MSG_REG9 0x8B
-#define MSG_REGA 0x8C
-#define MSG_REGB 0x8D
-#define MSG_REGC 0x8E
-#define MSG_REGD 0x8F
-
-#define DISABLED 0
-#define ENABLED 1
-
-
-
-///
-/// EC structure
-///
-typedef struct _FCH_EC {
- UINT8 MsgFun81Zone0MsgReg0; ///<Thermal zone
- UINT8 MsgFun81Zone0MsgReg1; ///<Thermal zone
- UINT8 MsgFun81Zone0MsgReg2; ///<Thermal zone control byte 1
- UINT8 MsgFun81Zone0MsgReg3; ///<Thermal zone control byte 2
- UINT8 MsgFun81Zone0MsgReg4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
- UINT8 MsgFun81Zone0MsgReg5; ///<Hysteresis information
- UINT8 MsgFun81Zone0MsgReg6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
- UINT8 MsgFun81Zone0MsgReg7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located.
- UINT8 MsgFun81Zone0MsgReg8; ///<Fan PWM stepping rate in unit of PWM level percentage
- UINT8 MsgFun81Zone0MsgReg9; ///<Fan PWM ramping rate in 5ms unit
-//
-// EC LDN9 function 81 zone 1
-//
- UINT8 MsgFun81Zone1MsgReg0; ///<Thermal zone
- UINT8 MsgFun81Zone1MsgReg1; ///<Thermal zone
- UINT8 MsgFun81Zone1MsgReg2; ///<Thermal zone control byte 1
- UINT8 MsgFun81Zone1MsgReg3; ///<Thermal zone control byte 2
- UINT8 MsgFun81Zone1MsgReg4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
- UINT8 MsgFun81Zone1MsgReg5; ///<Hysteresis information
- UINT8 MsgFun81Zone1MsgReg6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
- UINT8 MsgFun81Zone1MsgReg7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located.
- UINT8 MsgFun81Zone1MsgReg8; ///<Fan PWM stepping rate in unit of PWM level percentage
- UINT8 MsgFun81Zone1MsgReg9; ///<Fan PWM ramping rate in 5ms unit
-//
-//EC LDN9 function 81 zone 2
-//
- UINT8 MsgFun81Zone2MsgReg0; ///<Thermal zone
- UINT8 MsgFun81Zone2MsgReg1; ///<Thermal zone
- UINT8 MsgFun81Zone2MsgReg2; ///<Thermal zone control byte 1
- UINT8 MsgFun81Zone2MsgReg3; ///<Thermal zone control byte 2
- UINT8 MsgFun81Zone2MsgReg4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
- UINT8 MsgFun81Zone2MsgReg5; ///<Hysteresis information
- UINT8 MsgFun81Zone2MsgReg6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
- UINT8 MsgFun81Zone2MsgReg7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located.
- UINT8 MsgFun81Zone2MsgReg8; ///<Fan PWM stepping rate in unit of PWM level percentage
- UINT8 MsgFun81Zone2MsgReg9; ///<Fan PWM ramping rate in 5ms unit
-//
-//EC LDN9 function 81 zone 3
-//
- UINT8 MsgFun81Zone3MsgReg0; ///<Thermal zone
- UINT8 MsgFun81Zone3MsgReg1; ///<Thermal zone
- UINT8 MsgFun81Zone3MsgReg2; ///<Thermal zone control byte 1
- UINT8 MsgFun81Zone3MsgReg3; ///<Thermal zone control byte 2
- UINT8 MsgFun81Zone3MsgReg4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
- UINT8 MsgFun81Zone3MsgReg5; ///<Hysteresis information
- UINT8 MsgFun81Zone3MsgReg6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
- UINT8 MsgFun81Zone3MsgReg7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located.
- UINT8 MsgFun81Zone3MsgReg8; ///<Fan PWM stepping rate in unit of PWM level percentage
- UINT8 MsgFun81Zone3MsgReg9; ///<Fan PWM ramping rate in 5ms unit
-//
-//EC LDN9 function 83 zone 0
-//
- UINT8 MsgFun83Zone0MsgReg0; ///<Thermal zone
- UINT8 MsgFun83Zone0MsgReg1; ///<Thermal zone
- UINT8 MsgFun83Zone0MsgReg2; ///<_AC0
- UINT8 MsgFun83Zone0MsgReg3; ///<_AC1
- UINT8 MsgFun83Zone0MsgReg4; ///<_AC2
- UINT8 MsgFun83Zone0MsgReg5; ///<_AC3
- UINT8 MsgFun83Zone0MsgReg6; ///<_AC4
- UINT8 MsgFun83Zone0MsgReg7; ///<_AC5
- UINT8 MsgFun83Zone0MsgReg8; ///<_AC6
- UINT8 MsgFun83Zone0MsgReg9; ///<_AC7
- UINT8 MsgFun83Zone0MsgRegA; ///<_CRT
- UINT8 MsgFun83Zone0MsgRegB; ///<_PSV
-//
-//EC LDN9 function 83 zone 1
-//
- UINT8 MsgFun83Zone1MsgReg0; ///<Thermal zone
- UINT8 MsgFun83Zone1MsgReg1; ///<Thermal zone
- UINT8 MsgFun83Zone1MsgReg2; ///<_AC0
- UINT8 MsgFun83Zone1MsgReg3; ///<_AC1
- UINT8 MsgFun83Zone1MsgReg4; ///<_AC2
- UINT8 MsgFun83Zone1MsgReg5; ///<_AC3
- UINT8 MsgFun83Zone1MsgReg6; ///<_AC4
- UINT8 MsgFun83Zone1MsgReg7; ///<_AC5
- UINT8 MsgFun83Zone1MsgReg8; ///<_AC6
- UINT8 MsgFun83Zone1MsgReg9; ///<_AC7
- UINT8 MsgFun83Zone1MsgRegA; ///<_CRT
- UINT8 MsgFun83Zone1MsgRegB; ///<_PSV
-//
-//EC LDN9 function 85 zone 0
-//
- UINT8 MsgFun85Zone0MsgReg0; ///<Thermal zone
- UINT8 MsgFun85Zone0MsgReg1; ///<Thermal zone
- UINT8 MsgFun85Zone0MsgReg2; ///<AL0 PWM level in percentage (0 - 100%)
- UINT8 MsgFun85Zone0MsgReg3; ///<AL1 PWM level in percentage (0 - 100%)
- UINT8 MsgFun85Zone0MsgReg4; ///<AL2 PWM level in percentage (0 - 100%)
- UINT8 MsgFun85Zone0MsgReg5; ///<AL3 PWM level in percentage (0 - 100%)
- UINT8 MsgFun85Zone0MsgReg6; ///<AL4 PWM level in percentage (0 - 100%)
- UINT8 MsgFun85Zone0MsgReg7; ///<AL5 PWM level in percentage (0 - 100%)
- UINT8 MsgFun85Zone0MsgReg8; ///<AL6 PWM level in percentage (0 - 100%)
- UINT8 MsgFun85Zone0MsgReg9; ///<AL7 PWM level in percentage (0 - 100%)
-//
-//EC LDN9 function 85 zone 1
-//
- UINT8 MsgFun85Zone1MsgReg0; ///<Thermal zone
- UINT8 MsgFun85Zone1MsgReg1; ///<Thermal zone
- UINT8 MsgFun85Zone1MsgReg2; ///<AL0 PWM level in percentage (0 - 100%)
- UINT8 MsgFun85Zone1MsgReg3; ///<AL1 PWM level in percentage (0 - 100%)
- UINT8 MsgFun85Zone1MsgReg4; ///<AL2 PWM level in percentage (0 - 100%)
- UINT8 MsgFun85Zone1MsgReg5; ///<AL3 PWM level in percentage (0 - 100%)
- UINT8 MsgFun85Zone1MsgReg6; ///<AL4 PWM level in percentage (0 - 100%)
- UINT8 MsgFun85Zone1MsgReg7; ///<AL5 PWM level in percentage (0 - 100%)
- UINT8 MsgFun85Zone1MsgReg8; ///<AL6 PWM level in percentage (0 - 100%)
- UINT8 MsgFun85Zone1MsgReg9; ///<AL7 PWM level in percentage (0 - 100%)
-//
-//EC LDN9 function 89 TEMPIN channel 0
-//
- UINT8 MsgFun89Zone0MsgReg0; ///<Thermal zone
- UINT8 MsgFun89Zone0MsgReg1; ///<Thermal zone
- UINT8 MsgFun89Zone0MsgReg2; ///<At DWORD bit 0-7
- UINT8 MsgFun89Zone0MsgReg3; ///<At DWORD bit 15-8
- UINT8 MsgFun89Zone0MsgReg4; ///<At DWORD bit 23-16
- UINT8 MsgFun89Zone0MsgReg5; ///<At DWORD bit 31-24
- UINT8 MsgFun89Zone0MsgReg6; ///<Ct DWORD bit 0-7
- UINT8 MsgFun89Zone0MsgReg7; ///<Ct DWORD bit 15-8
- UINT8 MsgFun89Zone0MsgReg8; ///<Ct DWORD bit 23-16
- UINT8 MsgFun89Zone0MsgReg9; ///<Ct DWORD bit 31-24
- UINT8 MsgFun89Zone0MsgRegA; ///<Mode bit 0-7
-//
-//EC LDN9 function 89 TEMPIN channel 1
-//
- UINT8 MsgFun89Zone1MsgReg0; ///<Thermal zone
- UINT8 MsgFun89Zone1MsgReg1; ///<Thermal zone
- UINT8 MsgFun89Zone1MsgReg2; ///<At DWORD bit 0-7
- UINT8 MsgFun89Zone1MsgReg3; ///<At DWORD bit 15-8
- UINT8 MsgFun89Zone1MsgReg4; ///<At DWORD bit 23-16
- UINT8 MsgFun89Zone1MsgReg5; ///<At DWORD bit 31-24
- UINT8 MsgFun89Zone1MsgReg6; ///<Ct DWORD bit 0-7
- UINT8 MsgFun89Zone1MsgReg7; ///<Ct DWORD bit 15-8
- UINT8 MsgFun89Zone1MsgReg8; ///<Ct DWORD bit 23-16
- UINT8 MsgFun89Zone1MsgReg9; ///<Ct DWORD bit 31-24
- UINT8 MsgFun89Zone1MsgRegA; ///<Mode bit 0-7
-//
-//EC LDN9 function 89 TEMPIN channel 2
-//
- UINT8 MsgFun89Zone2MsgReg0; ///<Thermal zone
- UINT8 MsgFun89Zone2MsgReg1; ///<Thermal zone
- UINT8 MsgFun89Zone2MsgReg2; ///<At DWORD bit 0-7
- UINT8 MsgFun89Zone2MsgReg3; ///<At DWORD bit 15-8
- UINT8 MsgFun89Zone2MsgReg4; ///<At DWORD bit 23-16
- UINT8 MsgFun89Zone2MsgReg5; ///<At DWORD bit 31-24
- UINT8 MsgFun89Zone2MsgReg6; ///<Ct DWORD bit 0-7
- UINT8 MsgFun89Zone2MsgReg7; ///<Ct DWORD bit 15-8
- UINT8 MsgFun89Zone2MsgReg8; ///<Ct DWORD bit 23-16
- UINT8 MsgFun89Zone2MsgReg9; ///<Ct DWORD bit 31-24
- UINT8 MsgFun89Zone2MsgRegA; ///<Mode bit 0-7
-//
-//EC LDN9 function 89 TEMPIN channel 3
-//
- UINT8 MsgFun89Zone3MsgReg0; ///<Thermal zone
- UINT8 MsgFun89Zone3MsgReg1; ///<Thermal zone
- UINT8 MsgFun89Zone3MsgReg2; ///<At DWORD bit 0-7
- UINT8 MsgFun89Zone3MsgReg3; ///<At DWORD bit 15-8
- UINT8 MsgFun89Zone3MsgReg4; ///<At DWORD bit 23-16
- UINT8 MsgFun89Zone3MsgReg5; ///<At DWORD bit 31-24
- UINT8 MsgFun89Zone3MsgReg6; ///<Ct DWORD bit 0-7
- UINT8 MsgFun89Zone3MsgReg7; ///<Ct DWORD bit 15-8
- UINT8 MsgFun89Zone3MsgReg8; ///<Ct DWORD bit 23-16
- UINT8 MsgFun89Zone3MsgReg9; ///<Ct DWORD bit 31-24
- UINT8 MsgFun89Zone3MsgRegA; ///<Mode bit 0-7
-//
-//EC LDN9 function 89 TEMPIN channel 4
-//
- UINT8 MsgFun89Zone4MsgReg0; ///<Thermal zone
- UINT8 MsgFun89Zone4MsgReg1; ///<Thermal zone
- UINT8 MsgFun89Zone4MsgReg2; ///<At DWORD bit 0-7
- UINT8 MsgFun89Zone4MsgReg3; ///<At DWORD bit 15-8
- UINT8 MsgFun89Zone4MsgReg4; ///<At DWORD bit 23-16
- UINT8 MsgFun89Zone4MsgReg5; ///<At DWORD bit 31-24
- UINT8 MsgFun89Zone4MsgReg6; ///<Ct DWORD bit 0-7
- UINT8 MsgFun89Zone4MsgReg7; ///<Ct DWORD bit 15-8
- UINT8 MsgFun89Zone4MsgReg8; ///<Ct DWORD bit 23-16
- UINT8 MsgFun89Zone4MsgReg9; ///<Ct DWORD bit 31-24
- UINT8 MsgFun89Zone4MsgRegA; ///<Mode bit 0-7
-} FCH_EC;
-
-///
-/// IMC structure
-///
-typedef struct _FCH_IMC {
- UINT8 ImcEnable; ///< ImcEnable - IMC Enable
- UINT8 ImcEnabled; ///< ImcEnabled - IMC Enable
- UINT8 ImcSureBootTimer; ///< ImcSureBootTimer - IMc SureBootTimer function
- FCH_EC EcStruct; ///< EC structure
- UINT8 ImcEnableOverWrite; ///< OverWrite IMC with the EC structure
- /// @li <b>0</b> - disable
- /// @li <b>1</b> - enable
- ///
-} FCH_IMC;
-
-
-///
-/// Hpet structure
-///
-typedef struct {
- BOOLEAN HpetEnable; ///< HPET function switch
- UINT8 HpetTimer; ///< HpetTimer - South Bridge Hpet Timer Configuration
- /// @par
- /// @li <b>0</b> - disable
- /// @li <b>1</b> - enable
-
- BOOLEAN HpetMsiDis; ///< HpetMsiDis - South Bridge HPET MSI Configuration
- /// @par
- /// @li <b>1</b> - disable
- /// @li <b>0</b> - enable
-
- UINT32 HpetBase; ///< HpetBase
- /// @par
- /// HPET Base address
-} FCH_HPET;
-
-
-///
-/// GCPU related parameters
-///
-typedef struct {
- UINT8 AcDcMsg; ///< Send a message to CPU to indicate the power mode (AC vs battery)
- /// @li <b>1</b> - disable
- /// @li <b>0</b> - enable
-
- UINT8 TimerTickTrack; ///< Send a message to CPU to indicate the latest periodic timer interval
- /// @li <b>1</b> - disable
- /// @li <b>0</b> - enable
-
- UINT8 ClockInterruptTag; ///< Mark the periodic timer interrupt
- /// @li <b>1</b> - disable
- /// @li <b>0</b> - enable
-
- UINT8 OhciTrafficHanding; ///< Cause CPU to break out from C state when USB OHCI has pending traffic
- /// @li <b>1</b> - disable
- /// @li <b>0</b> - enable
-
- UINT8 EhciTrafficHanding; ///< Cause CPU to break out from C state when USB EHCI has pending traffic
- /// @li <b>1</b> - disable
- /// @li <b>0</b> - enable
-
- UINT8 GcpuMsgCMultiCore; ///< Track of CPU C state by monitoring each core's C state message
- /// @li <b>1</b> - disable
- /// @li <b>0</b> - enable
-
- UINT8 GcpuMsgCStage; ///< Enable the FCH C state coordination logic
- /// @li <b>1</b> - disable
- /// @li <b>0</b> - enable
-} FCH_GCPU;
-
-
-///
-/// MISC structure
-///
-typedef struct {
- BOOLEAN NativePcieSupport; /// PCIe NativePcieSupport - Debug function. 1:Enabled, 0:Disabled
- BOOLEAN S3Resume; /// S3Resume - Flag of ACPI S3 Resume.
- BOOLEAN RebootRequired; /// RebootRequired - Flag of Reboot system is required.
- UINT8 FchVariant; /// FchVariant - FCH Variant value.
- UINT8 Cg2Pll; ///< CG2 PLL - 0:disable, 1:enable
-} FCH_MISC;
-
-
-///
-/// SDB structure
-///
-typedef struct {
- BOOLEAN SerialDebugBusEnable; /// Serial Debug Bus - 1:Enabled, 0:Disabled
-} FCH_SERIALDB;
-
-
-///
-/// SMBus structure
-///
-typedef struct {
- UINT32 SmbusSsid; ///< SMBUS controller Subsystem ID
-} FCH_SMBUS;
-
-
-///
-/// Acpi structure
-///
-typedef struct {
- UINT16 Smbus0BaseAddress; ///< Smbus0BaseAddress
- /// @par
- /// Smbus BASE Address
- ///
- UINT16 Smbus1BaseAddress; ///< Smbus1BaseAddress
- /// @par
- /// Smbus1 (ASF) BASE Address
- ///
- UINT16 SioPmeBaseAddress; ///< SioPmeBaseAddress
- /// @par
- /// SIO PME BASE Address
- ///
- UINT32 WatchDogTimerBase; ///< WatchDogTimerBase
- /// @par
- /// Watch Dog Timer Address
- ///
- UINT16 AcpiPm1EvtBlkAddr; ///< AcpiPm1EvtBlkAddr
- /// @par
- /// ACPI PM1 event block Address
- ///
- UINT16 AcpiPm1CntBlkAddr; ///< AcpiPm1CntBlkAddr
- /// @par
- /// ACPI PM1 Control block Address
- ///
- UINT16 AcpiPmTmrBlkAddr; ///< AcpiPmTmrBlkAddr
- /// @par
- /// ACPI PM timer block Address
- ///
- UINT16 CpuControlBlkAddr; ///< CpuControlBlkAddr
- /// @par
- /// ACPI CPU control block Address
- ///
- UINT16 AcpiGpe0BlkAddr; ///< AcpiGpe0BlkAddr
- /// @par
- /// ACPI GPE0 block Address
- ///
- UINT16 SmiCmdPortAddr; ///< SmiCmdPortAddr
- /// @par
- /// SMI command port Address
- ///
- UINT16 AcpiPmaCntBlkAddr; ///< AcpiPmaCntBlkAddr
- /// @par
- /// ACPI PMA Control block Address
- ///
- BOOLEAN AnyHt200MhzLink; ///< AnyHt200MhzLink
- /// @par
- /// HT Link Speed on 200MHz option for each CPU specific LDTSTP# (Force enable)
- ///
- BOOLEAN SpreadSpectrum; ///< SpreadSpectrum
- /// @par
- /// Spread Spectrum function
- /// @li <b>0</b> - disable
- /// @li <b>1</b> - enable
- ///
- POWER_FAIL PwrFailShadow; ///< PwrFailShadow = PM_Reg: 5Bh [3:0]
- /// @par
- /// @li <b>00</b> - Always off
- /// @li <b>01</b> - Always on
- /// @li <b>11</b> - Use previous
- ///
- UINT8 StressResetMode; ///< StressResetMode 01-10
- /// @li <b>00</b> - Disabed
- /// @li <b>01</b> - Io Write 0x64 with 0xfe
- /// @li <b>10</b> - Io Write 0xcf9 with 0x06
- /// @li <b>11</b> - Io Write 0xcf9 with 0x0e
- ///
- BOOLEAN MtC1eEnable; /// MtC1eEnable - Enable MtC1e
- VOID* OemProgrammingTablePtr; /// Pointer of ACPI OEM table
-} FCH_ACPI;
-
-
-///
-/// HWM temp parameter structure
-///
-typedef struct _FCH_HWM_TEMP_PAR {
- UINT16 At; ///< At
- UINT16 Ct; ///< Ct
- UINT8 Mode; ///< Mode BIT0:HiRatio BIT1:HiCurrent
-} FCH_HWM_TEMP_PAR;
-
-///
-/// HWM Current structure
-///
-typedef struct _FCH_HWM_CUR {
- UINT16 FanSpeed[5]; ///< FanSpeed - fan Speed
- UINT16 Temperature[5]; ///< Temperature - temperature
- UINT16 Voltage[8]; ///< Voltage - voltage
-} FCH_HWM_CUR;
-
-///
-/// HWM fan control structure
-///
-typedef struct _FCH_HWM_FAN_CTR {
- UINT8 InputControlReg00; /// Fan Input Control register, PM2 offset [0:4]0
- UINT8 ControlReg01; /// Fan control register, PM2 offset [0:4]1
- UINT8 FreqReg02; /// Fan frequency register, PM2 offset [0:4]2
- UINT8 LowDutyReg03; /// Low Duty register, PM2 offset [0:4]3
- UINT8 MedDutyReg04; /// Med Duty register, PM2 offset [0:4]4
- UINT8 MultiplierReg05; /// Multiplier register, PM2 offset [0:4]5
- UINT16 LowTempReg06; /// Low Temp register, PM2 offset [0:4]6
- UINT16 MedTempReg08; /// Med Temp register, PM2 offset [0:4]8
- UINT16 HighTempReg0A; /// High Temp register, PM2 offset [0:4]A
- UINT8 LinearRangeReg0C; /// Linear Range register, PM2 offset [0:4]C
- UINT8 LinearHoldCountReg0D; /// Linear Hold Count register, PM2 offset [0:4]D
-} FCH_HWM_FAN_CTR;
-
-///
-/// Hwm structure
-///
-typedef struct _FCH_HWM {
- UINT8 HwMonitorEnable; ///< HwMonitorEnable
- UINT32 HwmControl; ///< hwmControl
- /// @par
- /// HWM control configuration
- /// @li <b>0</b> - HWM is Enabled
- /// @li <b>1</b> - IMC is Enabled
- ///
- UINT8 FanSampleFreqDiv; ///< Sampling rate of Fan Speed
- /// @li <b>00</b> - Base(22.5KHz)
- /// @li <b>01</b> - Base(22.5KHz)/2
- /// @li <b>10</b> - Base(22.5KHz)/4
- /// @li <b>11</b> - Base(22.5KHz)/8
- ///
- UINT8 HwmFchtsiAutoPoll; ///< TSI Auto Polling
- /// @li <b>0</b> - disable
- /// @li <b>1</b> - enable
- ///
- UINT16 HwmCalibrationFactor; /// Calibration Factor
- FCH_HWM_CUR HwmCurrent; /// HWM Current structure
- FCH_HWM_CUR HwmCurrentRaw; /// HWM Current Raw structure
- FCH_HWM_TEMP_PAR HwmTempPar[5]; /// HWM Temp parameter structure
- FCH_HWM_FAN_CTR HwmFanControl[5]; /// HWM Fan Control structure
-} FCH_HWM;
-
-
-///
-/// Gec structure
-///
-typedef struct {
- BOOLEAN GecEnable; ///< GecEnable - GEC function switch
- UINT32 LpcSsid; /// LPC SSID
- UINT8 GecPhyStatus; /// GEC PHY Status
- UINT8 GecPowerPolicy; /// GEC Power Policy
- /// @li <b>00</b> - GEC is powered down in S3 and S5
- /// @li <b>01</b> - GEC is powered down only in S5
- /// @li <b>10</b> - GEC is powered down only in S3
- /// @li <b>11</b> - GEC is never powered down
- ///
- UINT8 GecDebugBus; /// GEC Debug Bus
- /// @li <b>0</b> - disable
- /// @li <b>1</b> - enable
- ///
- UINT32 GecShadowRomBase; ///< GecShadowRomBase
- /// @par
- /// GEC (NIC) SHADOWROM BASE Address
- ///
- VOID *PtrDynamicGecRomAddress; /// Pointer of Dynamic GEC ROM Address
-} FCH_GEC;
-
-
-///
-/// _ABTblEntry - AB link register table R/W structure
-///
-typedef struct _AB_TBL_ENTRY {
- UINT8 RegType; /// RegType : AB Register Type (ABCFG, AXCFG and so on)
- UINT32 RegIndex; /// RegIndex : AB Register Index
- UINT32 RegMask; /// RegMask : AB Register Mask
- UINT32 RegData; /// RegData : AB Register Data
-} AB_TBL_ENTRY;
-
-///
-/// AB structure
-///
-typedef struct {
- BOOLEAN AbMsiEnable; ///< ABlink MSI capability
- UINT8 UmiPhyPllPowerDown; /// UMI PHY PLL Power Down - 0:disable, 1:enable
- UINT8 ALinkClkGateOff; /// Alink Clock Gate-Off function - 0:disable, 1:enable *KR
- UINT8 BLinkClkGateOff; /// Blink Clock Gate-Off function - 0:disable, 1:enable *KR
- UINT8 AbClockGating; /// AB Clock Gating - 0:disable, 1:enable *KR
- UINT8 GppClockGating; /// GPP Clock Gating - 0:disable, 1:enable
- UINT8 UmiL1TimerOverride; /// UMI L1 inactivity timer overwrite value
- UINT8 UmiLinkWidth; /// UMI Link Width
- UINT8 UmiDynamicSpeedChange; /// UMI Dynamic Speed Change - 0:disable, 1:enable
- UINT8 PcieRefClockOverClocking; /// PCIe Ref Clock OverClocking value
- UINT8 UmiGppTxDriverStrength; /// UMI GPP TX Driver Strength
- BOOLEAN NbSbGen2; /// UMI link Gen2 - 0:Gen1, 1:Gen2
- UINT8 PcieOrderRule; /// PCIe Order Rule - 0:disable, 1:enable *KR AB Posted Pass Non-Posted
- UINT8 SlowSpeedAbLinkClock; /// Slow Speed AB Link Clock - 0:disable, 1:enable *KR
- UINT8 ResetCpuOnSyncFlood; /// Reset Cpu On Sync Flood - 0:disable, 1:enable *KR
- BOOLEAN AbDmaMemoryWrtie3264B; /// AB DMA Memory Write 32/64 BYTE Support *KR only
- BOOLEAN AbMemoryPowerSaving; /// AB Memory Power Saving *KR only
- BOOLEAN SbgDmaMemoryWrtie3264ByteCount; /// SBG DMA Memory Write 32/64 BYTE Count Support *KR only
- BOOLEAN SbgMemoryPowerSaving; /// SBG Memory Power Saving *KR only
-} FCH_AB;
-
-
-/**
- * PCIE_CAP_ID - PCIe Cap ID
- *
- */
-#define PCIE_CAP_ID 0x10
-
-///
-/// FCH_GPP_PORT_CONFIG - Fch GPP port config structure
-///
-typedef struct {
- BOOLEAN PortPresent; ///< Port connection
- /// @par
- /// @li <b>0</b> - Port doesn't have slot. No need to train the link
- /// @li <b>1</b> - Port connection defined and needs to be trained
- ///
- BOOLEAN PortDetected; ///< Link training status
- /// @par
- /// @li <b>0</b> - EP not detected
- /// @li <b>1</b> - EP detected
- ///
- BOOLEAN PortIsGen2; ///< Port link speed configuration
- /// @par
- /// @li <b>00</b> - Auto
- /// @li <b>01</b> - Forced GEN1
- /// @li <b>10</b> - Forced GEN2
- /// @li <b>11</b> - Reserved
- ///
- BOOLEAN PortHotPlug; ///< Support hot plug?
- /// @par
- /// @li <b>0</b> - No support
- /// @li <b>1</b> - support
- ///
- UINT8 PortMisc; /// PortMisc - Reserved
-} FCH_GPP_PORT_CONFIG;
-
-///
-/// GPP structure
-///
-typedef struct {
- FCH_GPP_PORT_CONFIG PortCfg[4]; /// GPP port configuration structure
- GPP_LINKMODE GppLinkConfig; ///< GppLinkConfig - PCIE_GPP_Enable[3:0]
- /// @li <b>0000</b> - Port ABCD -> 4:0:0:0
- /// @li <b>0010</b> - Port ABCD -> 2:2:0:0
- /// @li <b>0011</b> - Port ABCD -> 2:1:1:0
- /// @li <b>0100</b> - Port ABCD -> 1:1:1:1
- ///
- UINT8 GppFoundGfxDev; ///< Gpp Found Gfx Device
- /// @li <b>0</b> - Not found
- /// @li <b>1</b> - Found
- ///
- UINT8 GppGen2; ///< GPP Gen2 - 0:disable, 1:enable
- UINT8 GppGen2Strap; ///< GPP Gen2 Strap - 0:disable, 1:enable, FCH itself uses this
- UINT8 GppMemWrImprove; ///< GPP Memory Write Improve - 0:disable, 1:enable
- BOOLEAN GppFunctionEnable; ///< GPP Function - 0:disable, 1:enable
- UINT8 GppUnhidePorts; ///< GPP Unhide Ports - 0:disable, 1:enable
- UINT8 GppPortAspm; ///< GppPortAspm - ASPM state for all GPP ports
- /// @li <b>01</b> - Disabled
- /// @li <b>01</b> - L0s
- /// @li <b>10</b> - L1
- /// @li <b>11</b> - L0s + L1
- ///
- UINT8 GppLaneReversal; ///< GPP Lane Reversal - 0:disable, 1:enable
- UINT8 GppPhyPllPowerDown; ///< GPP PHY PLL Power Down - 0:disable, 1:enable
- UINT8 GppDynamicPowerSaving; ///< GPP Dynamic Power Saving - 0:disable, 1:enable
- UINT8 PcieAer; ///< PcieAer - Advanced Error Report: 0/1-disable/enable
- UINT8 PcieRas; ///< PCIe RAS - 0:disable, 1:enable
- UINT8 PcieCompliance; ///< PCIe Compliance - 0:disable, 1:enable
- UINT8 PcieSoftwareDownGrade; ///< PCIe Software Down Grade
- UINT8 GppHardwareDownGrade; /// GppHardwareDownGrade - Gpp HW Down Grade function 0:Disable, 1-4: portA-D
- BOOLEAN GppToggleReset; ///< Toggle GPP core reset
-} FCH_GPP;
-
-
-///
-/// FCH USB sturcture
-///
-typedef struct {
- BOOLEAN Ohci1Enable; ///< OHCI1 controller enable
- BOOLEAN Ohci2Enable; ///< OHCI2 controller enable
- BOOLEAN Ohci3Enable; ///< OHCI3 controller enable
- BOOLEAN Ohci4Enable; ///< OHCI4 controller enable
- BOOLEAN Ehci1Enable; ///< EHCI1 controller enable
- BOOLEAN Ehci2Enable; ///< EHCI2 controller enable
- BOOLEAN Ehci3Enable; ///< EHCI3 controller enable
- BOOLEAN Xhci0Enable; ///< XHCI0 controller enable
- BOOLEAN Xhci1Enable; ///< XHCI1 controller enable
- BOOLEAN UsbMsiEnable; ///< USB MSI capability
- UINT32 OhciSsid; ///< OHCI SSID
- UINT32 Ohci4Ssid; ///< OHCI 4 SSID
- UINT32 EhciSsid; ///< EHCI SSID
- UINT32 XhciSsid; ///< XHCI SSID
- BOOLEAN UsbPhyPowerDown; ///< USB PHY Power Down - 0:disable, 1:enable
-} FCH_USB;
-
-
-/// Private: FCH_DATA_BLOCK_RESET
-typedef struct _FCH_RESET_DATA_BLOCK {
- AMD_CONFIG_PARAMS *StdHeader; ///< Header structure
- FCH_RESET_INTERFACE *FchReset; ///< Reset interface
-
- BOOLEAN NbSbGen2; ///< NB SB Gen2 - TRUE:GEN2, FALSE:GEN1
- UINT8 FastSpeed; ///< SPI Fast Speed - 0:disable, 1:enable
- UINT8 WriteSpeed; ///< SPI Write Speed
- UINT8 Mode; ///< SPI Mode
- /// @li <b>101</b> - Qual-io 1-4-4
- /// @li <b>100</b> - Dual-io 1-2-2
- /// @li <b>011</b> - Qual-io 1-1-4
- /// @li <b>010</b> - Dual-io 1-1-2
- /// @li <b>111</b> - FastRead
- /// @li <b>110</b> - Normal
- ///
- UINT8 AutoMode; ///< SPI Auto Mode - 0:disable, 1:enable
- UINT8 BurstWrite; ///< SPI Burst Write - 0:disable, 1:enable
- BOOLEAN Sata6AhciCap; ///< SATA 6 AHCI Capability - TRUE:enable, FALSE:disable
- UINT8 Cg2Pll; ///< CG2 PLL - 0:disable, 1:enable
- BOOLEAN EcKbd; ///< EC KBD - 0:disable, 1:enable
- BOOLEAN LegacyFree; ///< Legacy Free - 0:disable, 1:enable
- BOOLEAN SataSetMaxGen2; ///< SATA enable maximum GEN2
- UINT8 SataClkMode; ///< SATA reference clock selector and divider
- UINT8 SataModeReg; ///< Output: SATAConfig PMIO:0xDA
- BOOLEAN SataInternal100Spread; ///< SATA internal 100MHz spread ON/OFF
- UINT8 SpiSpeed; ///< SPI NormSpeed: 00-66MHz, 01-33MHz, 10-22MHz, 11-16.5MHz
- BOOLEAN EcChannel0; ///< Enable EC channel 0
- BOOLEAN SerialDebugBusEnable; ///< SDB Enable
- BOOLEAN GppToggleReset; ///< Toggle GPP core reset
-} FCH_RESET_DATA_BLOCK;
-
-
-/// Private: FCH_DATA_BLOCK
-typedef struct _FCH_DATA_BLOCK {
- AMD_CONFIG_PARAMS *StdHeader; ///< Header structure
-
- FCH_ACPI HwAcpi; ///< ACPI structure
- FCH_AB Ab; ///< AB structure
- FCH_GPP Gpp; ///< GPP structure
- FCH_USB Usb; ///< USB structure
- FCH_SATA Sata; ///< SATA structure
- FCH_SMBUS Smbus; ///< SMBus structure
- FCH_IDE Ide; ///< IDE structure
- FCH_AZALIA Azalia; ///< Azalia structure
- FCH_SPI Spi; ///< SPI structure
- FCH_PCIB Pcib; ///< PCIB structure
- FCH_GEC Gec; ///< GEC structure
- FCH_SD Sd; ///< SD structure
- FCH_HWM Hwm; ///< Hardware Moniter structure
- FCH_IR Ir; ///< IR structure
- FCH_HPET Hpet; ///< HPET structure
- FCH_GCPU Gcpu; ///< GCPU structure
- FCH_IMC Imc; ///< IMC structure
- FCH_SERIALDB SerialDb; ///< Serial Debug structure
- FCH_MISC Misc; ///< MISC structure
-} FCH_DATA_BLOCK;
-
-
-#endif
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchCommonSmm.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchCommonSmm.c
deleted file mode 100644
index e971abef14..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchCommonSmm.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * FCH common SMM
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#define FILECODE PROC_FCH_COMMON_FCHCOMMONSMM_FILECODE
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * FchSmmAcpiOn - Config Fch during ACPI_ON
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchSmmAcpiOn (
- IN FCH_DATA_BLOCK *FchDataPtr
- )
-{
- //
- // Commented the following code since we need to leave the IRQ1/12 filtering enabled always as per latest
- // recommendation. This is required to fix the keyboard stuck issue when playing games under Windows
- //
-
- //
- // Disable Power Button SMI
- //
- RwMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGAC, AccessWidth8, ~(BIT6), 0);
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchDef.h b/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchDef.h
deleted file mode 100644
index 32230f4fd8..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchDef.h
+++ /dev/null
@@ -1,444 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * FCH routine definition
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 45638 $ @e \$Date: 2011-01-20 03:17:37 +0800 (Thu, 20 Jan 2011) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#ifndef _FCH_DEF_H_
-#define _FCH_DEF_H_
-
-
-UINT32 ReadAlink (IN UINT32 Index, IN AMD_CONFIG_PARAMS *StdHeader);
-VOID WriteAlink (IN UINT32 Index, IN UINT32 Data, IN AMD_CONFIG_PARAMS *StdHeader);
-VOID RwAlink (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
-VOID ReadMem (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *ValuePtr);
-VOID WriteMem (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *ValuePtr);
-VOID RwMem (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data);
-VOID ReadPci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
-VOID WritePci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
-VOID RwPci (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data, IN AMD_CONFIG_PARAMS *StdHeader);
-VOID ProgramPciByteTable (IN REG8_MASK* pPciByteTable, IN UINT16 dwTableSize, IN AMD_CONFIG_PARAMS *StdHeader);
-VOID ProgramFchAcpiMmioTbl (IN ACPI_REG_WRITE *pAcpiTbl, IN AMD_CONFIG_PARAMS *StdHeader);
-VOID GetChipSysMode (IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
-BOOLEAN IsImcEnabled (IN AMD_CONFIG_PARAMS *StdHeader);
-VOID ReadPmio (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
-VOID WritePmio (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
-VOID RwPmio (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
-VOID ReadPmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
-VOID WritePmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
-VOID RwPmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
-VOID ReadBiosram (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
-VOID WriteBiosram (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
-VOID GetFchAcpiMmioBase (OUT UINT32 *AcpiMmioBase, IN AMD_CONFIG_PARAMS *StdHeader);
-VOID GetFchAcpiPmBase (OUT UINT16 *AcpiPmBase, IN AMD_CONFIG_PARAMS *StdHeader);
-
-///
-/// Fch Ab Routines
-///
-/// Pei Phase
-///
-VOID FchInitResetAb (IN VOID* FchDataPtr);
-VOID FchProgramAbPowerOnReset (IN VOID* FchDataPtr);
-///
-/// Dxe Phase
-///
-VOID FchInitEnvAb (IN VOID* FchDataPtr);
-VOID FchInitEnvAbSpecial (IN VOID* FchDataPtr);
-VOID FchInitMidAb (IN VOID* FchDataPtr);
-VOID FchInitLateAb (IN VOID* FchDataPtr);
-///
-/// Other Public Routines
-///
-VOID FchInitEnvAbLinkInit (IN VOID* FchDataPtr);
-BOOLEAN IsUmiOneLaneGen1Mode (IN AMD_CONFIG_PARAMS *StdHeader);
-
-///
-/// Fch Pcie Routines
-///
-/// Pei Phase
-///
-VOID FchInitResetPcie (IN VOID* FchDataPtr);
-///
-/// Dxe Phase
-///
-VOID FchInitEnvPcie (IN VOID* FchDataPtr);
-VOID FchInitMidPcie (IN VOID* FchDataPtr);
-VOID FchInitLatePcie (IN VOID* FchDataPtr);
-VOID ProgramPcieNativeMode (IN VOID* FchDataPtr);
-
-///
-/// Fch Gpp Routines
-///
-/// Pei Phase
-///
-VOID FchInitResetGpp (IN VOID* FchDataPtr);
-VOID ProgramFchGppInitReset (IN VOID *FchDataPtr);
-VOID FchResetPcie (IN RESET_BLOCK ResetBlock, IN RESET_OP ResetOp, IN AMD_CONFIG_PARAMS *StdHeader);
-
-///
-/// Dxe Phase
-///
-VOID FchInitEnvGpp (IN VOID* FchDataPtr);
-VOID FchInitMidGpp (IN VOID* FchDataPtr);
-VOID FchInitLateGpp (IN VOID* FchDataPtr);
-
-///
-/// Other Public Routines
-///
-VOID ProgramGppTogglePcieReset (IN BOOLEAN DoToggling, IN AMD_CONFIG_PARAMS *StdHeader);
-VOID FchGppForceGen1 (IN VOID* FchDataPtr, IN CONST UINT8 ActivePorts);
-VOID FchGppForceGen2 (IN VOID* FchDataPtr, IN CONST UINT8 ActivePorts);
-VOID FchGppDynamicPowerSaving (IN VOID* FchDataPtr );
-UINT8 GppPortPollingLtssm (IN VOID* FchDataPtr, IN UINT8 ActivePorts, IN BOOLEAN IsGen2);
-
-
-
-///
-/// Fch Azalia Routines
-///
-/// Pei Phase
-///
-VOID FchInitResetAzalia (IN VOID *FchDataPtr);
-VOID FchInitRecoveryAzalia (IN VOID *FchDataPtr);
-///
-/// Dxe Phase
-///
-VOID FchInitEnvAzalia (IN VOID *FchDataPtr);
-VOID FchInitMidAzalia (IN VOID *FchDataPtr);
-VOID FchInitLateAzalia (IN VOID *FchDataPtr);
-
-
-///
-/// Fch GEC Routines
-///
-/// Pei Phase
-///
-VOID FchInitResetGec (IN VOID* FchDataPtr);
-VOID FchInitRecoveryGec (IN VOID* FchDataPtr);
-///
-/// Dxe Phase
-///
-VOID FchInitEnvGec (IN VOID* FchDataPtr);
-VOID FchInitMidGec (IN VOID* FchDataPtr);
-VOID FchInitLateGec (IN VOID* FchDataPtr);
-///
-/// Other Public Routines
-///
-VOID FchInitGecController (IN VOID* FchDataPtr);
-VOID FchSwInitGecBootRom (IN VOID* FchDataPtr);
-
-///
-/// Fch HwAcpi Routines
-///
-/// Pei Phase
-///
-VOID FchInitResetHwAcpiP (IN VOID *FchDataPtr);
-VOID FchInitResetHwAcpi (IN VOID *FchDataPtr);
-VOID FchInitRecoveryHwAcpi (IN VOID *FchDataPtr);
-VOID ProgramFchHwAcpiResetP (IN VOID *FchDataPtr);
-///
-/// Dxe Phase
-///
-VOID FchInitEnvHwAcpiP (IN VOID *FchDataPtr);
-VOID FchInitEnvHwAcpi (IN VOID *FchDataPtr);
-VOID ProgramEnvPFchAcpiMmio (IN VOID *FchDataPtr);
-VOID ProgramFchEnvHwAcpiPciReg (IN VOID *FchDataPtr);
-VOID ProgramSpecificFchInitEnvAcpiMmio (IN VOID *FchDataPtr);
-VOID ProgramFchEnvSpreadSpectrum (IN VOID *FchDataPtr);
-VOID FchInitMidHwAcpi (IN VOID *FchDataPtr);
-VOID FchInitLateHwAcpi (IN VOID *FchDataPtr);
-
-///
-/// Other Public Routines
-///
-VOID HpetInit (IN VOID *FchDataPtr);
-VOID C3PopupSetting (IN VOID *FchDataPtr);
-VOID MtC1eEnable (IN VOID *FchDataPtr);
-VOID GcpuRelatedSetting (IN VOID *FchDataPtr);
-VOID StressResetModeLate (IN VOID *FchDataPtr);
-
-///
-/// Fch Hwm Routines
-///
-/// Pei Phase
-///
-VOID FchInitResetHwm (IN VOID* FchDataPtr);
-VOID FchInitRecoveryHwm (IN VOID* FchDataPtr);
-///
-/// Dxe Phase
-///
-VOID FchInitEnvHwm (IN VOID* FchDataPtr);
-VOID FchInitMidHwm (IN VOID* FchDataPtr);
-VOID FchInitLateHwm (IN VOID* FchDataPtr);
-///
-/// Other Public Routines
-///
-VOID HwmInitRegister (IN VOID* FchDataPtr);
-VOID HwmProcessParameter (IN VOID* FchDataPtr);
-VOID HwmSetRegister (IN VOID* FchDataPtr);
-VOID HwmGetCalibrationFactor (IN VOID* FchDataPtr);
-VOID HwmFchtsiAutoPolling (IN VOID* FchDataPtr);
-VOID HwmGetRawData (IN VOID* FchDataPtr);
-VOID HwmCaculate (IN VOID* FchDataPtr);
-VOID HwmFchtsiAutoPollingOff (IN VOID* FchDataPtr);
-VOID FchECfancontrolservice (IN VOID* FchDataPtr);
-
-
-///
-/// Fch Ide Routines
-///
-VOID FchInitEnvIde (IN VOID* FchDataPtr);
-VOID FchInitMidIde (IN VOID* FchDataPtr);
-VOID FchInitLateIde (IN VOID* FchDataPtr);
-
-
-///
-/// Fch Imc Routines
-///
-/// Pei Phase
-///
-VOID FchInitResetImc (IN VOID *FchDataPtr);
-VOID FchInitRecoveryImc (IN VOID *FchDataPtr);
-VOID FchInitResetEc (IN VOID *FchDataPtr);
-VOID FchInitRecoveryEc (IN VOID *FchDataPtr);
-///
-/// Dxe Phase
-///
-VOID FchInitEnvImc (IN VOID *FchDataPtr);
-VOID FchInitMidImc (IN VOID *FchDataPtr);
-VOID FchInitLateImc (IN VOID *FchDataPtr);
-VOID FchInitEnvEc (IN VOID *FchDataPtr);
-VOID FchInitMidEc (IN VOID *FchDataPtr);
-VOID FchInitLateEc (IN VOID *FchDataPtr);
-///
-/// Other Public Routines
-///
-VOID EnterEcConfig (IN AMD_CONFIG_PARAMS *StdHeader);
-VOID ExitEcConfig (IN AMD_CONFIG_PARAMS *StdHeader);
-VOID ReadEc8 (IN UINT8 Address, IN UINT8* Value, IN AMD_CONFIG_PARAMS *StdHeader);
-VOID WriteEc8 (IN UINT8 Address, IN UINT8* Value, IN AMD_CONFIG_PARAMS *StdHeader);
-VOID RwEc8 (IN UINT8 Address, IN UINT8 AndMask, IN UINT8 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
-VOID WriteECmsg (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader);
-VOID ReadECmsg (IN UINT8 Address, IN UINT8 OpFlag, OUT VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader);
-VOID WaitForEcLDN9MailboxCmdAck (IN AMD_CONFIG_PARAMS *StdHeader);
-
-VOID ImcSleep (IN VOID *FchDataPtr);
-VOID ImcEnableSurebootTimer (IN VOID *FchDataPtr);
-VOID ImcDisarmSurebootTimer (IN VOID *FchDataPtr);
-VOID ImcDisableSurebootTimer (IN VOID *FchDataPtr);
-VOID ImcWakeup (IN VOID *FchDataPtr);
-VOID ImcIdle (IN VOID *FchDataPtr);
-BOOLEAN ValidateImcFirmware (IN VOID *FchDataPtr);
-VOID SoftwareToggleImcStrapping (IN VOID *FchDataPtr);
-
-
-///
-/// Fch Ir Routines
-///
-/// Dxe Phase
-///
-VOID FchInitEnvIr (IN VOID* FchDataPtr);
-VOID FchInitMidIr (IN VOID* FchDataPtr);
-VOID FchInitLateIr (IN VOID* FchDataPtr);
-
-///
-/// Fch Pcib Routines
-///
-/// Pei Phase
-///
-VOID FchInitResetPcib (IN VOID* FchDataPtr);
-VOID FchInitRecoveryPcib (IN VOID* FchDataPtr);
-///
-/// Dxe Phase
-///
-VOID FchInitEnvPcib (IN VOID* FchDataPtr);
-VOID FchInitMidPcib (IN VOID* FchDataPtr);
-VOID FchInitLatePcib (IN VOID* FchDataPtr);
-
-
-///
-/// Fch SATA Routines
-///
-/// Pei Phase
-///
-VOID FchInitResetSata (IN VOID *FchDataPtr);
-VOID FchInitResetSataProgram (IN VOID *FchDataPtr);
-///
-/// Dxe Phase
-///
-VOID FchInitMidSata (IN VOID *FchDataPtr);
-VOID FchInitEnvSata (IN VOID *FchDataPtr);
-VOID FchInitEnvProgramSataPciRegs (IN VOID *FchDataPtr);
-VOID FchInitMidProgramSataRegs (IN VOID *FchDataPtr);
-VOID FchInitLateProgramSataRegs (IN VOID *FchDataPtr);
-
-VOID FchInitLateSata (IN VOID *FchDataPtr);
-VOID FchInitEnvSataIde (IN VOID *FchDataPtr);
-VOID FchInitMidSataIde (IN VOID *FchDataPtr);
-VOID FchInitLateSataIde (IN VOID *FchDataPtr);
-VOID FchInitEnvSataAhci (IN VOID *FchDataPtr);
-VOID FchInitMidSataAhci (IN VOID *FchDataPtr);
-VOID FchInitLateSataAhci (IN VOID *FchDataPtr);
-VOID FchInitEnvSataRaid (IN VOID *FchDataPtr);
-VOID FchInitMidSataRaid (IN VOID *FchDataPtr);
-VOID FchInitLateSataRaid (IN VOID *FchDataPtr);
-VOID FchInitEnvSataIde2Ahci (IN VOID *FchDataPtr);
-VOID FchInitMidSataIde2Ahci (IN VOID *FchDataPtr);
-VOID FchInitLateSataIde2Ahci (IN VOID *FchDataPtr);
-
-VOID SataAhciSetDeviceNumMsi (IN VOID *FchDataPtr);
-VOID SataRaidSetDeviceNumMsi (IN VOID *FchDataPtr);
-VOID SataIde2AhciSetDeviceNumMsi (IN VOID *FchDataPtr);
-VOID SataSetIrqIntResource (IN VOID *FchDataPtr, IN AMD_CONFIG_PARAMS *StdHeader);
-VOID SataBar5setting (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr);
-VOID SataEnableWriteAccess (IN AMD_CONFIG_PARAMS *StdHeader);
-VOID SataDisableWriteAccess (IN AMD_CONFIG_PARAMS *StdHeader);
-VOID SataSetDeviceNumMsi (IN VOID *FchDataPtr);
-VOID FchSataSetDeviceNumMsi (IN VOID *FchDataPtr);
-VOID ShutdownUnconnectedSataPortClock (IN VOID *FchDataPtr, IN UINT32 Bar5);
-VOID FchShutdownUnconnectedSataPortClock (IN VOID *FchDataPtr, IN UINT32 Bar5);
-VOID SataDriveDetection (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr);
-VOID FchSataDriveDetection (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr);
-VOID FchSataGpioInitial (IN VOID *FchDataPtr);
-VOID SataBar5RegSet (IN VOID *FchDataPtr);
-VOID SataSetPortGenMode (IN VOID *FchDataPtr);
-VOID FchSataSetPortGenMode (IN VOID *FchDataPtr);
-VOID FchProgramSataPhy (IN AMD_CONFIG_PARAMS *StdHeader);
-VOID FchSataDriveFpga (IN VOID *FchDataPtr);
-
-///
-/// FCH USB Controller Public Function
-///
-/// Pei Phase
-///
-VOID FchInitResetUsb (IN VOID *FchDataPtr);
-VOID FchInitRecoveryUsb (IN VOID *FchDataPtr);
-VOID FchInitResetOhci (IN VOID *FchDataPtr);
-VOID FchInitRecoveryOhci (IN VOID *FchDataPtr);
-VOID FchInitResetEhci (IN VOID *FchDataPtr);
-VOID FchInitRecoveryEhci (IN VOID *FchDataPtr);
-VOID FchInitResetXhci (IN VOID *FchDataPtr);
-VOID FchInitRecoveryXhci (IN VOID *FchDataPtr);
-VOID FchInitResetXhciProgram (IN VOID *FchDataPtr);
-///
-/// Dxe Phase
-///
-VOID FchInitEnvUsb (IN VOID *FchDataPtr);
-VOID FchInitMidUsb (IN VOID *FchDataPtr);
-VOID FchInitLateUsb (IN VOID *FchDataPtr);
-VOID FchInitEnvUsbOhci (IN VOID *FchDataPtr);
-VOID FchInitMidUsbOhci (IN VOID *FchDataPtr);
-VOID FchInitLateUsbOhci (IN VOID *FchDataPtr);
-VOID FchInitEnvUsbEhci (IN VOID *FchDataPtr);
-VOID FchInitMidUsbEhci (IN VOID *FchDataPtr);
-VOID FchInitLateUsbEhci (IN VOID *FchDataPtr);
-VOID FchInitEnvUsbXhci (IN VOID *FchDataPtr);
-VOID FchInitMidUsbXhci (IN VOID *FchDataPtr);
-VOID FchInitLateUsbXhci (IN VOID *FchDataPtr);
-VOID FchInitMidUsbOhci1 (IN VOID *FchDataPtr);
-VOID FchInitMidUsbOhci2 (IN VOID *FchDataPtr);
-VOID FchInitMidUsbOhci3 (IN VOID *FchDataPtr);
-VOID FchInitMidUsbOhci4 (IN VOID *FchDataPtr);
-VOID FchInitMidUsbEhci1 (IN FCH_DATA_BLOCK *FchDataPtr);
-VOID FchInitMidUsbEhci2 (IN FCH_DATA_BLOCK *FchDataPtr);
-VOID FchInitMidUsbEhci3 (IN FCH_DATA_BLOCK *FchDataPtr);
-///
-/// Other Public Routines
-///
-VOID SetUsbEnableReg (IN FCH_DATA_BLOCK *FchDataPtr);
-VOID FchOhciInitAfterPciInit (IN UINT32 Value, IN FCH_DATA_BLOCK* FchDataPtr);
-VOID FchEhciInitAfterPciInit (IN UINT32 Value, IN FCH_DATA_BLOCK* FchDataPtr);
-VOID FchXhciInitBeforePciInit (IN FCH_DATA_BLOCK* FchDataPtr);
-VOID FchXhciInitIndirectReg (IN AMD_CONFIG_PARAMS *StdHeader);
-VOID FchInitLateUsbXhciProgram (IN VOID *FchDataPtr);
-///
-/// Fch Sd Routines
-///
-VOID FchInitEnvSd (IN VOID *FchDataPtr);
-VOID FchInitMidSd (IN VOID *FchDataPtr);
-VOID FchInitLateSd (IN VOID *FchDataPtr);
-
-///
-/// Fch Spi Routines
-///
-/// Pei Phase
-///
-VOID FchInitResetSpi (IN VOID *FchDataPtr);
-VOID FchInitRecoverySpi (IN VOID *FchDataPtr);
-VOID FchInitResetLpc (IN VOID *FchDataPtr);
-VOID FchInitRecoveryLpc (IN VOID *FchDataPtr);
-///
-/// Dxe Phase
-///
-VOID FchInitEnvSpi (IN VOID *FchDataPtr);
-VOID FchInitMidSpi (IN VOID *FchDataPtr);
-VOID FchInitLateSpi (IN VOID *FchDataPtr);
-VOID FchInitEnvLpc (IN VOID *FchDataPtr);
-VOID FchInitMidLpc (IN VOID *FchDataPtr);
-VOID FchInitLateLpc (IN VOID *FchDataPtr);
-///
-/// Other Public Routines
-///
-VOID FchSpiUnlock (IN VOID *FchDataPtr);
-VOID FchSpiLock (IN VOID *FchDataPtr);
-
-/*--------------------------- Documentation Pages ---------------------------*/
-VOID FchStall (IN UINT32 uSec, IN AMD_CONFIG_PARAMS *StdHeader);
-VOID CimFchStall (IN UINT32 uSec, IN AMD_CONFIG_PARAMS *StdHeader);
-VOID FchReset (IN AMD_CONFIG_PARAMS *StdHeader);
-VOID OutPort80 (IN UINT32 pcode, IN AMD_CONFIG_PARAMS *StdHeader);
-VOID OutPort1080 (IN UINT32 pcode, IN AMD_CONFIG_PARAMS *StdHeader);
-VOID GetEfuseStatus (IN VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader);
-VOID TurnOffCG2 (OUT VOID);
-VOID BackUpCG2 (OUT VOID);
-VOID FchCopyMem (IN VOID* pDest, IN VOID* pSource, IN UINTN Length);
-VOID* GetRomSigPtr (IN UINTN* RomSigPtr, IN AMD_CONFIG_PARAMS *StdHeader);
-VOID RwXhciIndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
-VOID AcLossControl (IN UINT8 AcLossControlValue);
-VOID FchVgaInit (OUT VOID);
-VOID RecordFchConfigPtr (IN UINT32 FchConfigPtr);
-VOID ValidateFchVariant (IN VOID *FchDataPtr);
-VOID RecordSmiStatus (IN AMD_CONFIG_PARAMS *StdHeader);
-BOOLEAN IsGCPU (IN VOID *FchDataPtr);
-BOOLEAN IsExternalClockMode (IN VOID *FchDataPtr);
-BOOLEAN IsLpcRom (OUT VOID);
-
-#endif
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchLib.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchLib.c
deleted file mode 100644
index 838fa9fe50..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchLib.c
+++ /dev/null
@@ -1,564 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * FCH IO access common routine
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 45638 $ @e \$Date: 2011-01-20 03:17:37 +0800 (Thu, 20 Jan 2011) $
- *
- */
-/*;********************************************************************************
-;
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*********************************************************************************/
-#include "FchPlatform.h"
-#define FILECODE PROC_FCH_COMMON_FCHLIB_FILECODE
-
-/**< FchStall - Reserved */
-VOID
-FchStall (
- IN UINT32 uSec,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT16 timerAddr;
- UINT32 startTime;
- UINT32 elapsedTime;
-
- LibAmdMemRead (AccessWidth16, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG64), &timerAddr, StdHeader);
- if ( timerAddr == 0 ) {
- uSec = uSec / 2;
- while ( uSec != 0 ) {
- LibAmdIoRead (AccessWidth8, FCHOEM_IO_DELAY_PORT, (UINT8 *) (&startTime), StdHeader);
- uSec--;
- }
- } else {
- LibAmdIoRead (AccessWidth32, timerAddr, &startTime, StdHeader);
- for ( ;; ) {
- LibAmdIoRead (AccessWidth32, timerAddr, &elapsedTime, StdHeader);
- if ( elapsedTime < startTime ) {
- elapsedTime = elapsedTime + FCH_MAX_TIMER - startTime;
- } else {
- elapsedTime = elapsedTime - startTime;
- }
- if ( (elapsedTime * FCHOEM_ELAPSED_TIME_UNIT / FCHOEM_ELAPSED_TIME_DIVIDER) > uSec ) {
- break;
- }
- }
- }
-}
-
-/**< cimFchStall - Reserved */
-VOID
-CimFchStall (
- IN UINT32 uSec,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT16 timerAddr;
- UINT32 startTime;
- UINT32 elapsedTime;
-
- LibAmdMemRead (AccessWidth16, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG64), &timerAddr, StdHeader);
- if ( timerAddr == 0 ) {
- uSec = uSec / 2;
- while ( uSec != 0 ) {
- LibAmdIoRead (AccessWidth8, FCHOEM_IO_DELAY_PORT, (UINT8*)&elapsedTime, StdHeader);
- uSec--;
- }
- } else {
- LibAmdIoRead (AccessWidth32, timerAddr, &startTime, StdHeader);
- for ( ;; ) {
- LibAmdIoRead (AccessWidth32, timerAddr, &elapsedTime, StdHeader);
- if ( elapsedTime < startTime ) {
- elapsedTime = elapsedTime + FCH_MAX_TIMER - startTime;
- } else {
- elapsedTime = elapsedTime - startTime;
- }
- if ( (elapsedTime * FCHOEM_ELAPSED_TIME_UNIT / FCHOEM_ELAPSED_TIME_DIVIDER) > uSec ) {
- break;
- }
- }
- }
-}
-
-/**< FchReset - Reserved */
-VOID
-FchReset (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 PciRstValue;
-
- PciRstValue = 0x06;
- LibAmdIoWrite (AccessWidth8, FCH_PCIRST_BASE_IO, &PciRstValue, StdHeader);
-}
-
-/**< outPort80 - Reserved */
-VOID
-OutPort80 (
- IN UINT32 pcode,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- LibAmdIoWrite (AccessWidth8, FCHOEM_OUTPUT_DEBUG_PORT, &pcode, StdHeader);
- return;
-}
-
-/**< outPort1080 - Reserved */
-VOID
-OutPort1080 (
- IN UINT32 pcode,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- LibAmdIoWrite (AccessWidth32, 0x1080, &pcode, StdHeader);
- return;
-}
-
-/**< FchCopyMem - Reserved */
-VOID
-FchCopyMem (
- IN VOID* pDest,
- IN VOID* pSource,
- IN UINTN Length
- )
-{
- UINTN i;
- UINT8 *Ptr;
- UINT8 *Source;
- Ptr = (UINT8*)pDest;
- Source = (UINT8*)pSource;
- for (i = 0; i < Length; i++) {
- *Ptr = *Source;
- Source++;
- Ptr++;
- }
-}
-
-/** GetRomSigPtr - Reserved **/
-VOID*
-GetRomSigPtr (
- IN UINTN *RomSigPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 RomPtr;
- UINT32 RomSig;
- UINT16 MswAddr;
-
- *RomSigPtr = 0;
- MswAddr = 0xFFF0;
- do {
- RomPtr = (MswAddr << 16) + FCH_ROMSIG_BASE_IO;
- LibAmdMemRead (AccessWidth32, (UINT64) RomPtr, &RomSig, StdHeader);
- if (RomSig == FCH_ROMSIG_SIGNATURE) {
- *RomSigPtr = RomPtr;
- break;
- }
- MswAddr <<= 1;
- } while (MswAddr != 0xFE00);
- return RomSigPtr;
-}
-
-/** RwXhciIndReg - Reserved **/
-VOID
-RwXhciIndReg (
- IN UINT32 Index,
- IN UINT32 AndMask,
- IN UINT32 OrMask,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 RevReg;
- PCI_ADDR PciAddress;
-
- PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x48;
- LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader);
- PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x4C;
- RevReg = ~AndMask;
- LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader);
-
- PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x48;
- LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader);
- PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x4C;
- RevReg = ~AndMask;
- LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader);
-}
-
-/** AcLossControl - Reserved **/
-VOID
-AcLossControl (
- IN UINT8 AcLossControlValue
- )
-{
- AcLossControlValue &= 0x03;
- AcLossControlValue |= BIT2;
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5B, AccessWidth8, 0xF0, AcLossControlValue);
-}
-
-/** RecordFchConfigPtr - Reserved **/
-VOID
-RecordFchConfigPtr (
- IN UINT32 FchConfigPtr
- )
-{
- RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x08, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 0) & 0xFF) );
- RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x09, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 8) & 0xFF) );
- RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0A, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 16) & 0xFF) );
- RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0B, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 24) & 0xFF) );
-}
-
-/** ReadAlink - Reserved **/
-UINT32
-ReadAlink (
- IN UINT32 Index,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Data;
- LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader);
- LibAmdIoRead (AccessWidth32, ALINK_ACCESS_DATA, &Data, StdHeader);
- //Clear Index
- Index = 0;
- LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader);
- return Data;
-}
-
-/** WriteAlink - Reserved **/
-VOID
-WriteAlink (
- IN UINT32 Index,
- IN UINT32 Data,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader);
- LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_DATA, &Data, StdHeader);
- //Clear Index
- Index = 0;
- LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader);
-}
-
-/** RwAlink - Reserved **/
-VOID
-RwAlink (
- IN UINT32 Index,
- IN UINT32 AndMask,
- IN UINT32 OrMask,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 AccessType;
-
- AccessType = Index & 0xE0000000;
- if (AccessType == (AXINDC << 29)) {
- WriteAlink ((FCH_AX_INDXC_REG30 | AccessType), Index & 0x1FFFFFFF, StdHeader);
- Index = FCH_AX_DATAC_REG34 | AccessType;
- } else if (AccessType == (AXINDP << 29)) {
- WriteAlink ((FCH_AX_INDXP_REG38 | AccessType), Index & 0x1FFFFFFF, StdHeader);
- Index = FCH_AX_DATAP_REG3C | AccessType;
- }
- WriteAlink (Index, ReadAlink (Index, StdHeader) & AndMask | OrMask, StdHeader);
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Read PMIO
- *
- *
- *
- * @param[in] Address - PMIO Offset value
- * @param[in] OpFlag - Access sizes
- * @param[in] Value - Read Data Buffer
- * @param[in] StdHeader
- *
- */
-VOID
-ReadPmio (
- IN UINT8 Address,
- IN UINT8 OpFlag,
- IN VOID *Value,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 i;
-
- OpFlag = OpFlag & 0x7f;
- OpFlag = 1 << (OpFlag - 1);
- for (i = 0; i < OpFlag; i++) {
- LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD6, &Address, StdHeader);
- Address++;
- LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGCD7, (UINT8 *)Value + i, StdHeader);
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Write PMIO
- *
- *
- *
- * @param[in] Address - PMIO Offset value
- * @param[in] OpFlag - Access sizes
- * @param[in] Value - Write Data Buffer
- * @param[in] StdHeader
- *
- */
-VOID
-WritePmio (
- IN UINT8 Address,
- IN UINT8 OpFlag,
- IN VOID *Value,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 i;
-
- OpFlag = OpFlag & 0x7f;
- OpFlag = 1 << (OpFlag - 1);
- for (i = 0; i < OpFlag; i++) {
- LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD6, &Address, StdHeader);
- Address++;
- LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD7, (UINT8 *)Value + i, StdHeader);
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * RwPmio - Read/Write PMIO
- *
- *
- *
- * @param[in] Address - PMIO Offset value
- * @param[in] OpFlag - Access sizes
- * @param[in] AndMask - Data And Mask 32 bits
- * @param[in] OrMask - Data OR Mask 32 bits
- * @param[in] StdHeader
- *
- */
-VOID
-RwPmio (
- IN UINT8 Address,
- IN UINT8 OpFlag,
- IN UINT32 AndMask,
- IN UINT32 OrMask,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Result;
-
- ReadPmio (Address, OpFlag, &Result, StdHeader);
- Result = (Result & AndMask) | OrMask;
- WritePmio (Address, OpFlag, &Result, StdHeader);
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Read PMIO2
- *
- *
- *
- * @param[in] Address - PMIO2 Offset value
- * @param[in] OpFlag - Access sizes
- * @param[in] Value - Read Data Buffer
- * @param[in] StdHeader
- *
- */
-VOID
-ReadPmio2 (
- IN UINT8 Address,
- IN UINT8 OpFlag,
- IN VOID *Value,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 i;
-
- OpFlag = OpFlag & 0x7f;
- OpFlag = 1 << (OpFlag - 1);
- for ( i = 0; i < OpFlag; i++ ) {
- LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD0, &Address, StdHeader);
- Address++;
- LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGCD1, (UINT8 *) Value + i, StdHeader);
- }
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Write PMIO 2
- *
- *
- *
- * @param[in] Address - PMIO2 Offset value
- * @param[in] OpFlag - Access sizes
- * @param[in] Value - Write Data Buffer
- * @param[in] StdHeader
- *
- */
-VOID
-WritePmio2 (
- IN UINT8 Address,
- IN UINT8 OpFlag,
- IN VOID *Value,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 i;
-
- OpFlag = OpFlag & 0x7f;
- OpFlag = 1 << (OpFlag - 1);
-
- for ( i = 0; i < OpFlag; i++ ) {
- LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD0, &Address, StdHeader);
- Address++;
- LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD1, (UINT8 *) Value + i, StdHeader);
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * RwPmio2 - Read/Write PMIO2
- *
- *
- *
- * @param[in] Address - PMIO2 Offset value
- * @param[in] OpFlag - Access sizes
- * @param[in] AndMask - Data And Mask 32 bits
- * @param[in] OrMask - Data OR Mask 32 bits
- * @param[in] StdHeader
- *
- */
-VOID
-RwPmio2 (
- IN UINT8 Address,
- IN UINT8 OpFlag,
- IN UINT32 AndMask,
- IN UINT32 OrMask,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Result;
-
- ReadPmio2 (Address, OpFlag, &Result, StdHeader);
- Result = (Result & AndMask) | OrMask;
- WritePmio2 (Address, OpFlag, &Result, StdHeader);
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Read BIOSRAM
- *
- *
- *
- * @param[in] Address - BIOSRAM Offset value
- * @param[in] OpFlag - Access sizes
- * @param[in] Value - Read Data Buffer
- * @param[in] StdHeader
- *
- */
-VOID
-ReadBiosram (
- IN UINT8 Address,
- IN UINT8 OpFlag,
- IN VOID *Value,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 i;
-
- OpFlag = OpFlag & 0x7f;
- OpFlag = 1 << (OpFlag - 1);
- for (i = 0; i < OpFlag; i++) {
- LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD4, &Address, StdHeader);
- Address++;
- LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGCD5, (UINT8 *)Value + i, StdHeader);
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Write BIOSRAM
- *
- *
- *
- * @param[in] Address - BIOSRAM Offset value
- * @param[in] OpFlag - Access sizes
- * @param[in] Value - Write Data Buffer
- * @param[in] StdHeader
- *
- */
-VOID
-WriteBiosram (
- IN UINT8 Address,
- IN UINT8 OpFlag,
- IN VOID *Value,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 i;
-
- OpFlag = OpFlag & 0x7f;
- OpFlag = 1 << (OpFlag - 1);
- for (i = 0; i < OpFlag; i++) {
- LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD4, &Address, StdHeader);
- Address++;
- LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD5, (UINT8 *)Value + i, StdHeader);
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Record SMI Status
- *
- *
- * @param[in] StdHeader
- *
- */
-VOID
-RecordSmiStatus (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINTN Index;
- UINT8 SwSmiValue;
-
- ACPIMMIO8 (0xfed80320) |= 0x01;
- for ( Index = 0; Index < 20; Index++ ) {
- ACPIMMIO8 (0xfed10020 + Index) = ACPIMMIO8 (0xfed80280 + Index);
- }
- LibAmdIoRead (AccessWidth8, 0xB0, &SwSmiValue, StdHeader);
- ACPIMMIO8 (0xfed10040) = SwSmiValue;
-} \ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchPeLib.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchPeLib.c
deleted file mode 100644
index 0e191c1bbe..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchPeLib.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * FCH IO access common routine
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*;********************************************************************************
-;
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*********************************************************************************/
-
-#include "FchPlatform.h"
-#define FILECODE PROC_FCH_COMMON_FCHPELIB_FILECODE
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * ProgramPciByteTable - Program PCI register by table (8 bits data)
- *
- *
- *
- * @param[in] pPciByteTable - Table data pointer
- * @param[in] dwTableSize - Table length
- * @param[in] StdHeader
- *
- */
-VOID
-ProgramPciByteTable (
- IN REG8_MASK *pPciByteTable,
- IN UINT16 dwTableSize,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 i;
- UINT8 dbBusNo;
- UINT8 dbDevFnNo;
- UINT8 Or8;
- UINT8 Mask8;
- PCI_ADDR PciAddress;
-
- dbBusNo = pPciByteTable->RegIndex;
- dbDevFnNo = pPciByteTable->AndMask;
- pPciByteTable++;
-
- for ( i = 1; i < dwTableSize; i++ ) {
- if ( (pPciByteTable->RegIndex == 0xFF) && (pPciByteTable->AndMask == 0xFF) && (pPciByteTable->OrMask == 0xFF) ) {
- pPciByteTable++;
- dbBusNo = pPciByteTable->RegIndex;
- dbDevFnNo = pPciByteTable->AndMask;
- pPciByteTable++;
- i++;
- } else {
- PciAddress.AddressValue = (dbBusNo << 20) + (dbDevFnNo << 12) + pPciByteTable->RegIndex;
- Or8 = pPciByteTable->OrMask;
- Mask8 = ~pPciByteTable->AndMask;
- LibAmdPciRMW (AccessWidth8, PciAddress, &Or8, &Mask8, StdHeader);
- pPciByteTable++;
- }
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * ProgramFchAcpiMmioTbl - Program FCH ACPI MMIO register by table (8 bits data)
- *
- *
- *
- * @param[in] pAcpiTbl - Table data pointer
- * @param[in] StdHeader
- *
- */
-VOID
-ProgramFchAcpiMmioTbl (
- IN ACPI_REG_WRITE *pAcpiTbl,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 i;
- UINT8 Or8;
- UINT8 Mask8;
- UINT32 ddtempVar;
-
- if (pAcpiTbl != NULL) {
- if ((pAcpiTbl->MmioReg == 0) && (pAcpiTbl->MmioBase == 0) && (pAcpiTbl->DataAndMask == 0xB0) && (pAcpiTbl->DataOrMask == 0xAC)) {
- // Signature Checking
- pAcpiTbl++;
- for ( i = 1; pAcpiTbl->MmioBase < 0x1D; i++ ) {
- ddtempVar = ACPI_MMIO_BASE | (pAcpiTbl->MmioBase) << 8 | pAcpiTbl->MmioReg;
- Or8 = pAcpiTbl->DataOrMask;
- Mask8 = ~pAcpiTbl->DataAndMask;
- LibAmdMemRMW (AccessWidth8, (UINT64) ddtempVar, &Or8, &Mask8, StdHeader);
- pAcpiTbl++;
- }
- }
- }
-}
-
-/**
- * GetChipSysMode - Get Chip status
- *
- *
- * @param[in] Value - Return Chip strap status
- * StrapStatus [15.0] - Hudson-2 chip Strap Status
- * @li <b>0001</b> - Not USED FWH
- * @li <b>0002</b> - Not USED LPC ROM
- * @li <b>0004</b> - EC enabled
- * @li <b>0008</b> - Reserved
- * @li <b>0010</b> - Internal Clock mode
- * @param[in] StdHeader
- *
- */
-VOID
-GetChipSysMode (
- IN VOID *Value,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- LibAmdMemRead (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80), Value, StdHeader);
-}
-
-/**
- * IsImcEnabled - Is IMC Enabled
- * @retval TRUE for IMC Enabled; FALSE for IMC Disabled
- */
-BOOLEAN
-IsImcEnabled (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 dbSysConfig;
- GetChipSysMode (&dbSysConfig, StdHeader);
- if (dbSysConfig & ChipSysEcEnable) {
- return TRUE;
- } else {
- return FALSE;
- }
-}
-
-
-/**
- * GetEfuseStatue - Get Efuse status
- *
- *
- * @param[in] Value - Return Chip strap status
- * @param[in] StdHeader
- *
- */
-VOID
-GetEfuseStatus (
- IN VOID *Value,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 Or8;
- UINT8 Mask8;
-
- Or8 = BIT5;
- Mask8 = BIT5;
- LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8), &Or8, &Mask8, StdHeader);
- LibAmdMemWrite (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD8), Value, StdHeader);
- LibAmdMemRead (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD8 + 1), Value, StdHeader);
- Or8 = 0;
- Mask8 = BIT5;
- LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8), &Or8, &Mask8, StdHeader);
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/MemLib.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/MemLib.c
deleted file mode 100644
index f478365f64..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/MemLib.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * FCH memory access lib
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 46093 $ @e \$Date: 2011-01-28 11:39:58 +0800 (Fri, 28 Jan 2011) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Ids.h"
-#define FILECODE PROC_FCH_COMMON_MEMLIB_FILECODE
-
-
-/**
- * ReadMem - Read FCH BAR Memory
- *
- * @param[in] Address - Memory BAR address
- * @param[in] OpFlag - Access width
- * @param[in] *ValuePtr - In/Out value pointer
- *
- */
-VOID
-ReadMem (
- IN UINT32 Address,
- IN UINT8 OpFlag,
- IN VOID *ValuePtr
- )
-{
- OpFlag = OpFlag & 0x7f;
-
- switch ( OpFlag ) {
- case AccessWidth8:
- *((UINT8*)ValuePtr) = *((UINT8*) ((UINTN)Address));
- break;
-
- case AccessWidth16:
- *((UINT16*)ValuePtr) = *((UINT16*) ((UINTN)Address));
- break;
-
- case AccessWidth32:
- *((UINT32*)ValuePtr) = *((UINT32*) ((UINTN)Address));
- break;
-
- default:
- ASSERT (FALSE);
- break;
- }
-}
-
-/**
- * WriteMem - Write FCH BAR Memory
- *
- * @param[in] Address - Memory BAR address
- * @param[in] OpFlag - Access width
- * @param[in] *ValuePtr - In/Out Value pointer
- *
- */
-VOID
-WriteMem (
- IN UINT32 Address,
- IN UINT8 OpFlag,
- IN VOID *ValuePtr
- )
-{
- OpFlag = OpFlag & 0x7f;
-
- switch ( OpFlag ) {
- case AccessWidth8 :
- *((UINT8*) ((UINTN)Address)) = *((UINT8*)ValuePtr);
- break;
-
- case AccessWidth16:
- *((UINT16*) ((UINTN)Address)) = *((UINT16*)ValuePtr);
- break;
-
- case AccessWidth32:
- *((UINT32*) ((UINTN)Address)) = *((UINT32*)ValuePtr);
- break;
-
- default:
- ASSERT (FALSE);
- break;
- }
-}
-
-/**
- * RwMem - Read & Write FCH BAR Memory
- *
- * @param[in] Address - Memory BAR address
- * @param[in] OpFlag - Access width
- * @param[in] Mask - Mask Value of data
- * @param[in] Data - Write data
- *
- */
-VOID
-RwMem (
- IN UINT32 Address,
- IN UINT8 OpFlag,
- IN UINT32 Mask,
- IN UINT32 Data
- )
-{
- UINT32 Result;
-
- ReadMem (Address, OpFlag, &Result);
- Result = (Result & Mask) | Data;
- WriteMem (Address, OpFlag, &Result);
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/PciLib.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/PciLib.c
deleted file mode 100644
index 0c3678690a..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Common/PciLib.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * FCH PCI access lib
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#define FILECODE PROC_FCH_COMMON_PCILIB_FILECODE
-
-VOID
-ReadPci (
- IN UINT32 Address,
- IN UINT8 OpFlag,
- IN VOID* Value,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- PCI_ADDR PciAddress;
-
- PciAddress.AddressValue = ((Address >> 4) & ~0xFFF) + (Address & 0xFFF);
- LibAmdPciRead ((ACCESS_WIDTH) OpFlag, PciAddress, Value, StdHeader);
-}
-
-
-VOID
-WritePci (
- IN UINT32 Address,
- IN UINT8 OpFlag,
- IN VOID *Value,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- PCI_ADDR PciAddress;
-
- PciAddress.AddressValue = ((Address >> 4) & ~0xFFF) + (Address & 0xFFF);
- LibAmdPciWrite ((ACCESS_WIDTH) OpFlag, PciAddress, Value, StdHeader);
-}
-
-
-VOID
-RwPci (
- IN UINT32 Address,
- IN UINT8 OpFlag,
- IN UINT32 Mask,
- IN UINT32 Data,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- PCI_ADDR PciAddress;
- UINT32 rMask;
-
- PciAddress.AddressValue = ((Address >> 4) & ~0xFFF) + (Address & 0xFFF);
- rMask = ~Mask;
- LibAmdPciRMW ((ACCESS_WIDTH) OpFlag, PciAddress, &Data, &rMask, StdHeader);
-}
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Fch.h b/src/vendorcode/amd/agesa/f12/Proc/Fch/Fch.h
deleted file mode 100644
index fb87827246..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Fch.h
+++ /dev/null
@@ -1,1949 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * FCH registers definition
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 49891 $ @e \$Date: 2011-03-30 15:45:37 +0800 (Wed, 30 Mar 2011) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#define FCH_REVISION "0.0.0.0"
-#define FCH_ID "YUBAA00"
-#define FCH_VERSION 0x0000
-
-
-/*--------------------------- Documentation Pages ---------------------------*/
-/**
- * @page FCH_INIT_RESET_Page FCH_INIT_RESET
- * @section FCH_INIT_RESET Interface Call
- * @par
- * Initialize structure referenced by FCH_RESET_DATA_BLOCK to default recommended value.
- * @subsection FCH_INIT_RESET_CallIn Call Prototype
- * @par
- * AGESA_STATUS FchInitReset (IN AMD_RESET_PARAMS *ResetParams);
- * @subsection FCH_INIT_RESET_CallOut Prepare for Callout
- * @par
- * Not Applicable (Not necessary for the current implementation)
- * @subsection FCH_INIT_RESET_Config Prepare for Configuration Data.
- * @par
- * <TABLE border="0">
- * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSmbus0BaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSmbus1BaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSioPmeBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgWatchDogTimerBase </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgGecShadowRomBase </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSpiRomBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiPm1EvtBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiPm1CntBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiPmTmrBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgCpuControlBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiGpe0BlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSmiCmdPortAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiPmaCntBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- * <TR><TD class="indexkey" width=380> FCH_RESET_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
- * <TR><TD class="indexkey" width=380> FCH_RESET_INTERFACE::IdeEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
- * </TABLE>
- *
- */
-
-/*--------------------------- Documentation Pages ---------------------------*/
-/**
- * @page FCH_INIT_ENV_Page FCH_INIT_ENV
- * @section FCH_INIT_ENV Interface Call
- * @par
- * Initialize structure referenced by FCH_DATA_BLOCK to default recommended value.
- * @subsection FCH_INIT_ENV_CallIn Call Prototype
- * @par
- * AGESA_STATUS FchInitEnv (IN AMD_ENV_PARAMS *EnvParams);
- * @subsection FCH_INIT_ENV_CallOut Prepare for Callout
- * @par
- * Not Applicable (Not necessary for the current implementation)
- * @subsection FCH_INIT_ENV_Config Prepare for Configuration Data.
- * @par
- * <TABLE border="0">
- * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SdConfig </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
- * <TR><TD class="indexkey" width=380> FCH_INTERFACE::AzaliaController </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
- * <TR><TD class="indexkey" width=380> FCH_INTERFACE::IrConfig </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
- * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
- * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
- * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataIdeMode </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
- * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci1Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
- * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci2Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
- * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci3Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
- * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci4Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
- * <TR><TD class="indexkey" width=380> FCH_INTERFACE::XhciSwitch </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
- * </TABLE>
- *
- */
-
-/*--------------------------- Documentation Pages ---------------------------*/
-/**
- * @page FCH_INIT_MID_Page FCH_INIT_MID
- * @section FCH_INIT_MID Interface Call
- * @par
- * Initialize structure referenced by FCH_DATA_BLOCK to default recommended value.
- * @subsection FCH_INIT_MID_CallIn Call Prototype
- * @par
- * AGESA_STATUS FchInitMid (IN AMD_MID_PARAMS *MidParams);
- * @subsection FCH_INIT_MID_CallOut Prepare for Callout
- * @par
- * Not Applicable (Not necessary for the current implementation)
- * @subsection FCH_INIT_MID_Config Prepare for Configuration Data.
- * @par
- * <TABLE border="0">
- * <TR><TD class="indexkey" width=380> FCH_INTERFACE::AzaliaController </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
- * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
- * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
- * <TR><TD class="indexkey" width=380> FCH_INTERFACE::IdeEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
- * <TR><TD class="indexkey" width=380> FCH_INTERFACE::XhciSwitch </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
- * </TABLE>
- *
- */
-
-/*--------------------------- Documentation Pages ---------------------------*/
-/**
- * @page FCH_INIT_LATE_Page FCH_INIT_LATE
- * @section FCH_INIT_LATE Interface Call
- * @par
- * Initialize structure referenced by FCH_DATA_BLOCK to default recommended value.
- * @subsection FCH_INIT_LATE_CallIn Call Prototype
- * @par
- * AGESA_STATUS FchInitLate (IN AMD_S3SAVE_PARAMS *LateParams);
- * @subsection FCH_INIT_LATE_CallOut Prepare for Callout
- * @par
- * Not Applicable (Not necessary for the current implementation)
- * @subsection FCH_INIT_LATE_Config Prepare for Configuration Data.
- * @par
- * <TABLE border="0">
- * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
- * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
- * <TR><TD class="indexkey" width=380> FCH_INTERFACE::XhciSwitch </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
- * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSpiRomBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- * </TABLE>
- *
- */
-
-/*--------------------------- Documentation Pages ---------------------------*/
-/**
- * @page FCH_INIT_S3_EARLY_RESTORE_Page FCH_INIT_S3_EARLY_RESTORE
- * @section FCH_INIT_S3_EARLY_RESTORE Interface Call
- * @par
- * Initialize structure referenced by FCH_DATA_BLOCK to default recommended value.
- * @subsection FCH_INIT_S3_EARLY_RESTORE_CallIn Call Prototype
- * @par
- * VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr);
- * @subsection FCH_INIT_S3_EARLY_RESTORE_CallOut Prepare for Callout
- * @par
- * Not Applicable (Not necessary for the current implementation)
- * @subsection FCH_INIT_S3_EARLY_RESTORE_Config Prepare for Configuration Data.
- * @par
- * <TABLE border="0">
- * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SdConfig </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
- * <TR><TD class="indexkey" width=380> FCH_INTERFACE::AzaliaController </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
- * <TR><TD class="indexkey" width=380> FCH_INTERFACE::IrConfig </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
- * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
- * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
- * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataIdeMode </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
- * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci1Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
- * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci2Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
- * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci3Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
- * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci4Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
- * <TR><TD class="indexkey" width=380> FCH_INTERFACE::XhciSwitch </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
- * </TABLE>
- *
- */
-
-/*--------------------------- Documentation Pages ---------------------------*/
-/**
- * @page FCH_INIT_S3_LATE_RESTORE_Page FCH_INIT_S3_LATE_RESTORE
- * @section FCH_INIT_S3_LATE_RESTORE Interface Call
- * @par
- * Initialize structure referenced by FCH_DATA_BLOCK to default recommended value.
- * @subsection FCH_INIT_S3_LATE_RESTORE_CallIn Call Prototype
- * @par
- * VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr);
- * @subsection FCH_INIT_S3_LATE_RESTORE_CallOut Prepare for Callout
- * @par
- * Not Applicable (Not necessary for the current implementation)
- * @subsection FCH_INIT_S3_LATE_RESTORE_Config Prepare for Configuration Data.
- * @par
- * <TABLE border="0">
- * <TR><TD class="indexkey" width=380> FCH_INTERFACE::AzaliaController </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
- * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
- * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
- * <TR><TD class="indexkey" width=380> FCH_INTERFACE::IdeEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
- * <TR><TD class="indexkey" width=380> FCH_INTERFACE::XhciSwitch </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
- * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSpiRomBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
- * </TABLE>
- *
- */
-
-/*--------------------------- Documentation Pages ---------------------------*/
-/**
- * @page FCH_SMM_SERVICE_Page FCH_SMM_SERVICE
- * @section FCH_SMM_SERVICE Interface Call
- * Initialize structure referenced by FCHCFG to default recommended value.
- * @subsection FCH_SMM_SERVICE_CallIn Call Prototype
- * @par
- * FchSmmService ((FCHCFG*)pConfig) (Followed PH Interface)
- * @subsection FCH_SMM_SERVICE_CallID Service ID
- * @par
- * <TABLE border="0">
- * <TR><TD class="indexkey" width=380> FCH_SMM_SERVICE --> 0x00010060 </TD></TR>
- * </TABLE>
- * @subsection FCH_SMM_SERVICE_CallOut Prepare for Callout
- * @par
- * Not Applicable (Not necessary for the current implementation)
- * @subsection FCH_SMM_SERVICE_Config Prepare for Configuration Data.
- * @par
- * Not necessary on current implementation
- *
- */
-#define FCH_SMM_SERVICE 0x00010060
-/*--------------------------- Documentation Pages ---------------------------*/
-/**
- * @page FCH_SMM_ACPION_Page FCH_SMM_ACPION
- * @section FCH_SMM_ACPION Interface Call
- * Initialize structure referenced by FCHCFG to default recommended value.
- * @subsection FCH_SMM_ACPION_CallIn Call Prototype
- * @par
- * FchSmmAcpiOn ((FCHCFG*)pConfig) (Followed PH Interface)
- * @subsection FCH_SMM_ACPION_CallID Service ID
- * @par
- * <TABLE border="0">
- * <TR><TD class="indexkey" width=380> FCH_SMM_ACPION --> 0x00010061 </TD></TR>
- * </TABLE>
- * @subsection FCH_SMM_ACPION_CallOut Prepare for Callout
- * @par
- * Not Applicable (Not necessary for the current implementation)
- * @subsection FCH_SMM_ACPION_Config Prepare for Configuration Data.
- * @par
- * Not necessary on current implementation
- *
- */
-#define FCH_SMM_ACPION 0x00010061
-
-#ifndef OEM_CALLBACK_BASE
- #define OEM_CALLBACK_BASE 0x00010100
-#endif
-
-//0x00 - 0x0F callback functions are reserved for bootblock
-#define SATA_PHY_PROGRAMMING OEM_CALLBACK_BASE + 0x10
-#define PULL_UP_PULL_DOWN_SETTINGS OEM_CALLBACK_BASE + 0x20
-/*--------------------------- Documentation Pages ---------------------------*/
-/**
- * @page CB_SBGPP_RESET_ASSERT_Page CB_SBGPP_RESET_ASSERT
- * @section CB_SBGPP_RESET_ASSERT Interface Call
- * Initialize structure referenced by FCHCFG to default recommended value.
- * @subsection CB_SBGPP_RESET_ASSERT_CallID Service ID
- * @par
- * <TABLE border="0">
- * <TR><TD class="indexkey" width=380> CB_SBGPP_RESET_ASSERT --> 0x00010130 </TD></TR>
- * </TABLE>
- * @subsection CB_SBGPP_RESET_ASSERT_Config Prepare for Configuration Data.
- * @par
- * Not necessary on current implementation
- *
- */
-#define CB_SBGPP_RESET_ASSERT OEM_CALLBACK_BASE + 0x30
-/*--------------------------- Documentation Pages ---------------------------*/
-/**
- * @page CB_SBGPP_RESET_DEASSERT_Page CB_SBGPP_RESET_DEASSERT
- * @section CB_SBGPP_RESET_DEASSERT Interface Call
- * Initialize structure referenced by FCHCFG to default recommended value.
- * @subsection CB_SBGPP_RESET_DEASSERT _CallID Service ID
- * @par
- * <TABLE border="0">
- * <TR><TD class="indexkey" width=380> CB_SBGPP_RESET_DEASSERT --> 0x00010131 </TD></TR>
- * </TABLE>
- * @subsection CB_SBGPP_RESET_DEASSERT _Config Prepare for Configuration Data.
- * @par
- * Not necessary on current implementation
- *
- */
-#define CB_SBGPP_RESET_DEASSERT OEM_CALLBACK_BASE + 0x31
-
-#define CFG_ADDR_PORT 0xCF8
-#define CFG_DATA_PORT 0xCFC
-
-#define ALINK_ACCESS_INDEX 0x0CD8
-#define ALINK_ACCESS_DATA ALINK_ACCESS_INDEX + 4
-
-/*------------------------------------------------------------------
-; I/O Base Address - Should be set by host BIOS
-;------------------------------------------------------------------ */
-#define DELAY_PORT 0x0E0
-
-/*------------------------------------------------------------------
-; DEBUG_PORT = 8-bit I/O Port Address for POST Code Display
-;------------------------------------------------------------------ */
-// ASIC VendorID and DeviceIDs
-#define AMD_FCH_VID 0x1022
-#define FCH_DEVICE_ID 0x780B
-#define FCH_SATA_VID AMD_FCH_VID // Dev 17 Func 0
-#define FCH_SATA_DID 0x7800
-#define FCH_SATA_AHCI_DID 0x7801
-#define FCH_SATA_RAID_DID 0x7802
-#define FCH_SATA_RAID5_DID 0x7803
-#define FCH_SATA_AMDAHCI_DID 0x7804
-#define FCH_USB_OHCI_VID AMD_FCH_VID // Dev 18 Func 0, Dev 19 Func 0
-#define FCH_USB_OHCI_DID 0x7807
-#define FCH_USB_EHCI_VID AMD_FCH_VID // Dev 18 Func 2, Dev 19 Func 2
-#define FCH_USB_EHCI_DID 0x7808
-#define FCH_USB_XHCI_VID AMD_FCH_VID // Dev 10 Func 0, Dev 10 Func 1
-#define FCH_USB_XHCI_DID 0x7812
-#define FCH_SMBUS_VID AMD_FCH_VID // Dev 20 Func 0
-#define FCH_SMBUS_DID 0x780B
-#define FCH_IDE_VID AMD_FCH_VID // Dev 20 Func 1
-#define FCH_IDE_DID 0x780C
-#define FCH_AZALIA_VID AMD_FCH_VID // Dev 20 Func 2
-#define FCH_AZALIA_DID 0x780D
-#define FCH_LPC_VID AMD_FCH_VID // Dev 20 Func 3
-#define FCH_LPC_DID 0x780E
-#define FCH_PCIB_VID AMD_FCH_VID // Dev 20 Func 4
-#define FCH_PCIB_DID 0x780F
-#define FCH_USB_OHCIF_VID AMD_FCH_VID // dev 20 Func 5
-#define FCH_USB_OHCIF_DID 0x7809
-#define FCH_NIC_VID 0x14E4 // Dev 20 Func 6
-#define FCH_NIC_DID 0x1699
-#define FCH_SD_VID AMD_FCH_VID // Dev 20 Func 7
-#define FCH_SD_DID 0x7806
-
-//FCH Variant
-#define FCH_Variant_EFUSE_LOCATION 0x1E // EFUSE bit 240-247
-
-#define FCH_M2 0x01
-#define FCH_M3 0x03
-#define FCH_M3T 0x07
-#define FCH_D2 0x0F
-#define FCH_D3 0x1F
-#define FCH_D4 0x3F
-
-
-//Misc
-#define R_FCH_ACPI_PM1_STATUS 0x00
-#define R_FCH_ACPI_PM1_ENABLE 0x02
-#define R_FCH_ACPI_PM_CONTROL 0x04
-#define R_FCH_ACPI_EVENT_STATUS 0x20
-#define R_FCH_ACPI_EVENT_ENABLE 0x24
-#define R_FCH_PM_ACPI_PMA_CNT_BLK_LO 0x2C
-
-//#define SATA_BUS_DEV_FUN_FPGA 0x228
-#define SATA_BUS_DEV_FUN ((0x11 << 3) + 0)
-#define FCH_SATA1_BUS 0
-#define FCH_SATA1_DEV 17
-#define FCH_SATA1_FUNC 0
-
-#define FC_BUS_DEV_FUN ((0x11 << 3) + 1)
-#define FCH_XHCI_BUS 0
-#define FCH_XHCI_DEV 16
-#define FCH_XHCI_FUNC 0
-#define USB_XHCI_BUS_DEV_FUN ((FCH_XHCI_DEV << 3) + FCH_XHCI_FUNC)
-#define FCH_XHCI1_BUS 0
-#define FCH_XHCI1_DEV 16
-#define FCH_XHCI1_FUNC 1
-#define USB_XHCI1_BUS_DEV_FUN ((FCH_XHCI1_DEV << 3) + FCH_XHCI1_FUNC)
-#define USB1_OHCI_BUS_DEV_FUN ((0x12 << 3) + 0) // PORT 0-4
-#define FCH_OHCI1_BUS 0
-#define FCH_OHCI1_DEV 18
-#define FCH_OHCI1_FUNC 0
-#define USB2_OHCI_BUS_DEV_FUN ((0x13 << 3) + 0) // PORT 5-9
-#define FCH_OHCI2_BUS 0
-#define FCH_OHCI2_DEV 19
-#define FCH_OHCI2_FUNC 0
-#define USB3_OHCI_BUS_DEV_FUN ((0x16 << 3) + 0) // PORT 10-13
-#define FCH_OHCI3_BUS 0
-#define FCH_OHCI3_DEV 22
-#define FCH_OHCI3_FUNC 0
-#define USB1_EHCI_BUS_DEV_FUN ((0x12 << 3) + 2) // PORT 0-4
-#define FCH_EHCI1_BUS 0
-#define FCH_EHCI1_DEV 18
-#define FCH_EHCI1_FUNC 2
-#define USB2_EHCI_BUS_DEV_FUN ((0x13 << 3) + 2) // PORT 5-9
-#define FCH_EHCI2_BUS 0
-#define FCH_EHCI2_DEV 19
-#define FCH_EHCI2_FUNC 2
-#define USB3_EHCI_BUS_DEV_FUN ((0x16 << 3) + 2) // PORT 10-13
-#define FCH_EHCI3_BUS 0
-#define FCH_EHCI3_DEV 22
-#define FCH_EHCI3_FUNC 2
-#define SMBUS_BUS_DEV_FUN ((0x14 << 3) + 0)
-#define FCH_ISA_BUS 0
-#define FCH_ISA_DEV 20
-#define FCH_ISA_FUNC 0
-#define IDE_BUS_DEV_FUN ((0x14 << 3) + 1)
-#define FCH_IDE_BUS 0
-#define FCH_IDE_DEV 20
-#define FCH_IDE_FUNC 1
-#define AZALIA_BUS_DEV_FUN ((0x14 << 3) + 2)
-#define FCH_AZALIA_BUS 0
-#define FCH_AZALIA_DEV 20
-#define FCH_AZALIA_FUNC 2
-#define LPC_BUS_DEV_FUN ((0x14 << 3) + 3)
-#define FCH_LPC_BUS 0
-#define FCH_LPC_DEV 20
-#define FCH_LPC_FUNC 3
-#define PCIB_BUS_DEV_FUN ((0x14 << 3) + 4) // P2P in SB700
-#define FCH_PCI_BUS 0
-#define FCH_PCI_DEV 20
-#define FCH_PCI_FUNC 4
-#define USB4_OHCI_BUS_DEV_FUN ((0x14 << 3) + 5) // PORT FL0 - FL1
-#define FCH_OHCI4_BUS 0
-#define FCH_OHCI4_DEV 20
-#define FCH_OHCI4_FUNC 5
-//Gigabyte Ethernet Controller
-#define GEC_BUS_DEV_FUN ((0x14 << 3) + 6)
-#define FCH_GBEC_BUS 0
-#define FCH_GBEC_DEV 20
-#define FCH_GBEC_FUNC 6
-
-#define SD_BUS_DEV_FUN ((0x14 << 3) + 7) // SD Controller
-#define SD_PCI_BUS 0
-#define SD_PCI_DEV 20
-#define SD_PCI_FUNC 7
-#define SD_PCI_REGA4 0xA4
-#define SD_PCI_REGB0 0xB0
-
-
-#define FCH_GPP_BUS 0
-#define FCH_GPP_DEV 21
-#define FCH_GPP_FUNC 0
-#define GPP0_BUS_DEV_FUN ((0x15 << 3) + 0) // GPP P2P bridge PORT0
-#define GPP1_BUS_DEV_FUN ((0x15 << 3) + 1) // GPP P2P bridge PORT1
-#define GPP2_BUS_DEV_FUN ((0x15 << 3) + 2) // GPP P2P bridge PORT2
-#define GPP3_BUS_DEV_FUN ((0x15 << 3) + 3) // GPP P2P bridge PORT3
-
-#define ACPI_MMIO_BASE 0xFED80000
-#define FCH_CFG_BASE 0x000 // DWORD
-#define GPIO_BASE 0x100 // BYTE
-#define SMI_BASE 0x200 // DWORD
-#define PMIO_BASE 0x300 // DWORD
-#define PMIO2_BASE 0x400 // BYTE
-#define BIOS_RAM_BASE 0x500 // BYTE
-#define CMOS_RAM_BASE 0x600 // BYTE
-#define CMOS_BASE 0x700 // BYTE
-#define ASF_BASE 0x900 // DWORD
-#define SMBUS_BASE 0xA00 // DWORD
-#define WATCHDOG_BASE 0xB00 //
-#define HPET_BASE 0xC00 // DWORD
-#define IOMUX_BASE 0xD00 // BYTE
-#define MISC_BASE 0xE00
-#define SERIAL_DEBUG_BASE 0x1000
-#define GFX_DAC_BASE 0x1400
-#define CEC_BASE 0x1800
-#define XHCI_BASE 0x1C00
-
-
-// RegSpace field (AB_INDEX[31:29]
-#define AXINDC 0 // AXINDC
-#define AXINDP 2 // AXINDP
-#define ABCFG 6 // ABCFG
-#define AXCFG 4 // AXCFG
-#define RCINDXC 1 // PCIEIND
-#define RCINDXP 3 // PCIEIND_P
-
-#define SBTEMP_BUS 8
-#define GPP_DEV_NUM 21 //
-#define MAX_GPP_PORTS 4
-
-#define PCIE_FORCE_GEN1_EFUSE_LOCATION 0x14 // EFUSE bit 160
-//
-// ABCFG Registers
-//
-#define FCH_ABCFG_REG00 0x00 // VENDOR ID
-#define FCH_ABCFG_REG08 0x08 // REVISION ID
-#define FCH_ABCFG_REG40 0x40 // BL_EVENTCNT0LO
-#define FCH_ABCFG_REG44 0x44 // BL_EVENTCNT1LO
-#define FCH_ABCFG_REG48 0x48 // BL_EVENTCNTSEL
-#define FCH_ABCFG_REG4A 0x4A // BL_EVENTCNT0HI
-#define FCH_ABCFG_REG4B 0x4B // BL_EVENTCNT1HI
-#define FCH_ABCFG_REG4C 0x4C // BL_EVENTCNTCTL
-#define FCH_ABCFG_REG50 0x50 // MISCCTL_50
-#define FCH_ABCFG_REG54 0x54 // MISCCTL_54
-#define FCH_ABCFG_REG58 0x58 // BL RAB CONTROL
-
-#define FCH_ABCFG_REG60 0x60 // LINKWIDTH_CTL
-#define FCH_ABCFG_REG64 0x64 // LINKWIDTH_UP_INTERVAL
-#define FCH_ABCFG_REG68 0x68 // LINKWIDTH_DN_INVERVAL
-#define FCH_ABCFG_REG6C 0x6C // LINKWIDTH_UPSTREAM_DWORDS
-#define FCH_ABCFG_REG70 0x70 // LINKWIDTH_DOWNSTREAM_DWORDS
-#define FCH_ABCFG_REG74 0x74 // LINKWIDTH_THRESHOLD_INCREASE
-#define FCH_ABCFG_REG78 0x78 // LINKWIDTH_THRESHOLD_DECREASE
-
-#define FCH_ABCFG_REG80 0x80 // BL DMA PREFETCH CONTROL
-#define FCH_ABCFG_REG88 0x88 //
-#define FCH_ABCFG_REG8C 0x8C //
-#define FCH_ABCFG_REG90 0x90 // BIF CONTROL 0
-#define FCH_ABCFG_REG94 0x94 // MSI CONTROL
-#define FCH_ABCFG_REG98 0x98 // BIF CONTROL 1
-#define FCH_ABCFG_REG9C 0x9C // MISCCTL_9C
-#define FCH_ABCFG_REGA0 0xA0 // BIF PHY CONTROL ENABLE
-#define FCH_ABCFG_REGA4 0xA4 // BIF PHY CONTROL A4
-#define FCH_ABCFG_REGA8 0xA8 // BIF PHY CONTROL A8
-#define FCH_ABCFG_REGB0 0xB0 // HYPERFLASH-PCIE PORT MAPPING
-#define FCH_ABCFG_REGB4 0xB4 //
-#define FCH_ABCFG_REGC0 0xC0 // PCIE_GPP_ENABLE
-#define FCH_ABCFG_REGC4 0xC4 // PCIE_P2P_INT_MAP
-#define FCH_ABCFG_REGD0 0xD0 // MCTP_VDM_TX_FIFO_DATA
-#define FCH_ABCFG_REGD4 0xD4 // MCTP_VMD_TX_CONTROL
-#define FCH_ABCFG_REGE0 0xE0 // MCTP_VDM_RX_FIFO_DATA
-#define FCH_ABCFG_REGE4 0xE4 // MCTP_VDM_RX_FIFO_STATUS
-#define FCH_ABCFG_REGEC 0xEC // MCTP_VDM_CONTROL
-#define FCH_ABCFG_REGF0 0xF0 // GPP_UPSTREAM_CONTROL
-#define FCH_ABCFG_REGF4 0xF4 // GPP_SYSTEM_ERROR_CONTROL
-#define FCH_ABCFG_REGFC 0xFC // FCH_TRAP_CONTROL
-#define FCH_ABCFG_REG100 0x100 // FCH_TRAP0_ADDRL
-#define FCH_ABCFG_REG104 0x104 // FCH_TRAP0_ADDRH
-#define FCH_ABCFG_REG108 0x108 // FCH_TRAP0_CMD
-#define FCH_ABCFG_REG10C 0x10C // FCH_TRAP1_DATA
-#define FCH_ABCFG_REG110 0x110 // FCH_TRAP1_ADDRL
-#define FCH_ABCFG_REG114 0x114 // FCH_TRAP1_ADDRH
-#define FCH_ABCFG_REG118 0x118 // FCH_TRAP1_CMD
-#define FCH_ABCFG_REG11C 0x11C // FCH_TRAP1_DATA
-#define FCH_ABCFG_REG120 0x120 // FCH_TRAP2_ADDRL
-#define FCH_ABCFG_REG124 0x124 // FCH_TRAP2_ADDRH
-#define FCH_ABCFG_REG128 0x128 // FCH_TRAP2_CMD
-#define FCH_ABCFG_REG12C 0x12C // FCH_TRAP2_DATA
-#define FCH_ABCFG_REG130 0x130 // FCH_TRAP3_ADDRL
-#define FCH_ABCFG_REG134 0x134 // FCH_TRAP3_ADDRH
-#define FCH_ABCFG_REG138 0x138 // FCH_TRAP3_CMD
-#define FCH_ABCFG_REG13C 0x13C // FCH_TRAP3_DATA
-#define FCH_ABCFG_REG208 0x208 // KR New
-#define FCH_ABCFG_REG300 0x300 // MCTP_VDM_RX_SMI_CONTROL
-#define FCH_ABCFG_REG310 0x310 // BIF_GPP_STRAP_SYSTEM_0
-#define FCH_ABCFG_REG314 0x314 // BIF_GPP_STRAP_SYSTEM_1
-#define FCH_ABCFG_REG31C 0x31C // BIF_GPP_STRAP_LINK_CONTROL_0
-#define FCH_ABCFG_REG320 0x320 // BIF_GPP_STRAP_LINK_CONTROL_LANE_A
-#define FCH_ABCFG_REG324 0x324 // BIF_GPP_STRAP_LINK_CONTROL_LANE_B
-#define FCH_ABCFG_REG328 0x328 // BIF_GPP_STRAP_LINK_CONTROL_LANE_C
-#define FCH_ABCFG_REG32C 0x32C // BIF_GPP_STRAP_LINK_CONTROL_LANE_D
-#define FCH_ABCFG_REG330 0x330 // BIF_GPP_STRAP_BIF_0
-#define FCH_ABCFG_REG334 0x334 // BIF_GPP_STRAP_BIF_1
-#define FCH_ABCFG_REG338 0x338 // BIF_GPP_STRAP_BIF_2
-#define FCH_ABCFG_REG340 0x340 // BIF_GPP_STRAP_BIF_LANE_A
-#define FCH_ABCFG_REG344 0x344 // BIF_GPP_STRAP_BIF_LANE_B
-#define FCH_ABCFG_REG348 0x348 // BIF_GPP_STRAP_BIF_LANE_C
-#define FCH_ABCFG_REG34C 0x34C // BIF_GPP_STRAP_BIF_LANE_D
-#define FCH_ABCFG_REG350 0x350 // BIF_GPP_STRAP_PHY_LOGICAL _0
-#define FCH_ABCFG_REG354 0x354 // BIF_GPP_STRAP_PHY_LOGICAL _1
-#define FCH_ABCFG_REG404 0x404 // GPP0_SHADOW_COMMAND
-#define FCH_ABCFG_REG418 0x418 // GPP0_SHADOW_BUS_NUMBER
-#define FCH_ABCFG_REG41C 0x41C // GPP0_SHADOW_IO_LIMIT_BASE
-#define FCH_ABCFG_REG420 0x420 // GPP0_SHADOW_MEM_LIMIT_BASE
-#define FCH_ABCFG_REG424 0x424 // GPP0_SHADOW_PREF_MEM_LIMIT_BASE
-#define FCH_ABCFG_REG428 0x428 // GPP0_SHADOW_PREF_MEM_BASE_UPPER
-#define FCH_ABCFG_REG42C 0x42C // GPP0_SHADOW_PREF_MEM_LIMIT_UPPER
-#define FCH_ABCFG_REG430 0x430 // GPP0_SHADOW_IO_LIMIT_BASE_UPPER
-#define FCH_ABCFG_REG43C 0x43C // GPP0_SHADOW_BRIDGE_CONTROL
-#define FCH_ABCFG_REG444 0x444 // GPP1_SHADOW_COMMAND
-#define FCH_ABCFG_REG458 0x458 // GPP1_SHADOW_BUS_NUMBER
-#define FCH_ABCFG_REG45C 0x45C // GPP1_SHADOW_IO_LIMIT_BASE
-#define FCH_ABCFG_REG460 0x460 // GPP1_SHADOW_MEM_LIMIT_BASE
-#define FCH_ABCFG_REG464 0x464 // GPP1_SHADOW_PREF_MEM_LIMIT_BASE
-#define FCH_ABCFG_REG468 0x468 // GPP1_SHADOW_PREF_MEM_BASE_UPPER
-#define FCH_ABCFG_REG46C 0x46C // GPP1_SHADOW_PREF_MEM_LIMIT_UPPER
-#define FCH_ABCFG_REG470 0x470 // GPP1_SHADOW_IO_LIMIT_BASE_UPPER
-#define FCH_ABCFG_REG47C 0x47C // GPP1_SHADOW_BRIDGE_CONTROL
-#define FCH_ABCFG_REG484 0x484 // GPP2_SHADOW_COMMAND
-#define FCH_ABCFG_REG498 0x498 // GPP2_SHADOW_BUS_NUMBER
-#define FCH_ABCFG_REG49C 0x49C // GPP2_SHADOW_IO_LIMIT_BASE
-#define FCH_ABCFG_REG4A0 0x4A0 // GPP2_SHADOW_MEM_LIMIT_BASE
-#define FCH_ABCFG_REG4A4 0x4A4 // GPP2_SHADOW_PREF_MEM_LIMIT_BASE
-#define FCH_ABCFG_REG4A8 0x4A8 // GPP2_SHADOW_PREF_MEM_BASE_UPPER
-#define FCH_ABCFG_REG4AC 0x4AC // GPP2_SHADOW_PREF_MEM_LIMIT_UPPER
-#define FCH_ABCFG_REG4B0 0x4B0 // GPP2_SHADOW_IO_LIMIT_BASE_UPPER
-#define FCH_ABCFG_REG4BC 0x4BC // GPP2_SHADOW_BRIDGE_CONTROL
-#define FCH_ABCFG_REG4C4 0x4C4 // GPP3_SHADOW_COMMAND
-#define FCH_ABCFG_REG4D8 0x4D8 // GPP3_SHADOW_BUS_NUMBER
-#define FCH_ABCFG_REG4DC 0x4DC // GPP3_SHADOW_IO_LIMIT_BASE
-#define FCH_ABCFG_REG4E0 0x4E0 // GPP3_SHADOW_MEM_LIMIT_BASE
-#define FCH_ABCFG_REG4E4 0x4E4 // GPP3_SHADOW_PREF_MEM_LIMIT_BASE
-#define FCH_ABCFG_REG4E8 0x4E8 // GPP3_SHADOW_PREF_MEM_BASE_UPPER
-#define FCH_ABCFG_REG4EC 0x4EC // GPP3_SHADOW_PREF_MEM_LIMIT_UPPER
-#define FCH_ABCFG_REG4F0 0x4F0 // GPP3_SHADOW_IO_LIMIT_BASE_UPPER
-#define FCH_ABCFG_REG4FC 0x4FC // GPP3_SHADOW_BRIDGE_CONTROL
-#define FCH_ABCFG_REG10040 0x10040 // AL_EVENTCNT0LO
-#define FCH_ABCFG_REG10044 0x10044 // AL_EVENTCNT1LO
-#define FCH_ABCFG_REG10048 0x10048 // AL_EVENTCNTSEL
-#define FCH_ABCFG_REG1004A 0x1004A // AL_EVENTCNT0HI
-#define FCH_ABCFG_REG1004B 0x1004B // AL_EVENTCNT1HI
-#define FCH_ABCFG_REG1004C 0x1004C // AL_EVENTCNTCTL
-#define FCH_ABCFG_REG10050 0x10050 // MISCCTL_10050
-#define FCH_ABCFG_REG10054 0x10054 // AL_ARB_CTL
-#define FCH_ABCFG_REG10056 0x10056 // AL_CLK_CTL
-#define FCH_ABCFG_REG10058 0x10058 // AL RAB CONTROL
-#define FCH_ABCFG_REG1005C 0x1005C // AL MLT CONTROL
-#define FCH_ABCFG_REG10060 0x10060 // AL DMA PREFETCH ENABLE
-#define FCH_ABCFG_REG10064 0x10064 // AL DMA PREFETCH FLUSH CONTROL
-#define FCH_ABCFG_REG10068 0x10068 // AL PREFETCH LIMIT
-#define FCH_ABCFG_REG1006C 0x1006C // AL DMA PREFETCH CONTROL
-#define FCH_ABCFG_REG10070 0x10070 // MISCCTL_10070
-#define FCH_ABCFG_REG10080 0x10080 // CLKMUXSTATUS
-#define FCH_ABCFG_REG10090 0x10090 // BIF CONTROL 0
-#define FCH_ABCFG_REG1009C 0x1009C // MISCCTL_1009C
-
-//
-// RCINDX_P Registers
-//
-#define FCH_RCINDXP_REG01 0x01 | RCINDXP << 29 // PCIEP_SCRATCH
-#define FCH_RCINDXP_REG02 0x02 | RCINDXP << 29 //
-#define FCH_RCINDXP_REG10 0x10 | RCINDXP << 29 //
-#define FCH_RCINDXP_REG20 0x20 | RCINDXP << 29 // PCIE_TX_CNTL
-#define FCH_RCINDXP_REG21 0x21 | RCINDXP << 29 // PCIE_TX_REQUESTER_ID
-#define FCH_RCINDXP_REG50 0x50 | RCINDXP << 29 // PCIE_P_PORT_LANE_STATUS
-#define FCH_RCINDXP_REG6A 0x6A | RCINDXP << 29 //
-#define FCH_RCINDXP_REG70 0x70 | RCINDXP << 29 // PCIE_RX_CNTL
-#define FCH_RCINDXP_REGA0 0xA0 | RCINDXP << 29 // PCIE_LC_CNTL
-#define FCH_RCINDXP_REGA1 0xA1 | RCINDXP << 29 // PCIE_LC_TRAINING_CNTL
-#define FCH_RCINDXP_REGA2 0xA2 | RCINDXP << 29 //
-#define FCH_RCINDXP_REGA4 0xA4 | RCINDXP << 29 //
-#define FCH_RCINDXP_REGA5 0xA5 | RCINDXP << 29 // PCIE_LC_STATE0
-#define FCH_RCINDXP_REGC0 0xC0 | RCINDXP << 29 //
-
-//
-// RCINDX_C Registers
-//
-#define FCH_RCINDXC_REG02 0x02 | RCINDXC << 29 // PCIE_HW_DEBUG
-#define FCH_RCINDXC_REG10 0x10 | RCINDXC << 29 // PCIE_CNTL
-#define FCH_RCINDXC_REGC1 0xC1 | RCINDXC << 29 //
-
-//
-// AXINDC Registers
-//
-#define FCH_AX_INDXC_REG02 0x02 // PCIEP_HW_DEBUG
-#define FCH_AX_INDXC_REG10 0x10
-#define FCH_AX_INDXC_REG30 0x30
-#define FCH_AX_DATAC_REG34 0x34
-#define FCH_AX_INDXP_REG38 0x38
-#define FCH_AX_DATAP_REG3C 0x3C
-#define FCH_AX_INDXC_REG40 0x40 | AXINDC << 29
-#define FCH_AX_INDXC_REGA4 0xA4 | AXINDC << 29
-
-#define FCH_AX_INDXP_REG02 0x02 | AXINDP << 29
-#define FCH_AX_INDXP_REGA0 0xA0 | AXINDP << 29
-#define FCH_AX_INDXP_REGA4 0xA4 | AXINDP << 29
-#define FCH_AX_INDXP_REGB1 0xB1 | AXINDP << 29
-
-#define FCH_AX_CFG_REG68 0x68 | AXCFG << 29
-#define FCH_AX_CFG_REG88 0x88 | AXCFG << 29
-
-#define FCH_AB_REG04 0x04
-#define FCH_AB_REG40 0x40
-
-#define RC_INDXC_REG40 0x40 | RCINDXC << 29
-#define RC_INDXC_REG65 0x65 | RCINDXC << 29
-#define RC_INDXC_REGC0 0xC0 | RCINDXC << 29
-
-//Sata Port Configuration
-#define SIX_PORTS 0
-#define FOUR_PORTS 1
-
-#define SATA_EFUSE_LOCATION 0x10 // EFUSE bit 133
-#define SATA_FIS_BASE_EFUSE_LOC 0x15 // EFUSE bit 169
-#define SATA_EFUSE_BIT 0x20 //
-#define FCH_SATA_REG00 0x000 // Vendor ID - R- 16 bits
-#define FCH_SATA_REG02 0x002 // Device ID - RW -16 bits
-#define FCH_SATA_REG04 0x004 // PCI Command - RW - 16 bits
-#define FCH_SATA_REG06 0x006 // PCI Status - RW - 16 bits
-#define FCH_SATA_REG08 0x008 // Revision ID/PCI Class Code - R - 32 bits - Offset: 08
-#define FCH_SATA_REG0C 0x00C // Cache Line Size - R/W - 8bits
-#define FCH_SATA_REG0D 0x00D // Latency Timer - RW - 8 bits
-#define FCH_SATA_REG0E 0x00E // Header Type - R - 8 bits
-#define FCH_SATA_REG0F 0x00F // BIST - R - 8 bits
-#define FCH_SATA_REG10 0x010 // Base Address Register 0 - RW - 32 bits
-#define FCH_SATA_REG14 0x014 // Base Address Register 1 - RW- 32 bits
-#define FCH_SATA_REG18 0x018 // Base Address Register 2 - RW - 32 bits
-#define FCH_SATA_REG1C 0x01C // Base Address Register 3 - RW - 32 bits
-#define FCH_SATA_REG20 0x020 // Base Address Register 4 - RW - 32 bits
-#define FCH_SATA_REG24 0x024 // Base Address Register 5 - RW - 32 bits
-#define FCH_SATA_REG2C 0x02C // Subsystem Vendor ID - R - 16 bits
-#define FCH_SATA_REG2D 0x02D // Subsystem ID - R - 16 bits
-#define FCH_SATA_REG30 0x030 // Expansion ROM Base Address - 32 bits
-#define FCH_SATA_REG34 0x034 // Capabilities Pointer - R - 32 bits
-#define FCH_SATA_REG3C 0x03C // Interrupt Line - RW - 8 bits
-#define FCH_SATA_REG3D 0x03D // Interrupt Pin - R - 8 bits
-#define FCH_SATA_REG3E 0x03E // Min Grant - R - 8 bits
-#define FCH_SATA_REG3F 0x03F // Max Latency - R - 8 bits
-#define FCH_SATA_REG40 0x040 // Configuration - RW - 32 bits
-#define FCH_SATA_REG44 0x044 // Software Data Register - RW - 32 bits
-#define FCH_SATA_REG48 0x048
-#define FCH_SATA_REG4C 0x04C
-#define FCH_SATA_REG50 0x050 // Message Capability - R - 16 bits
-#define FCH_SATA_REG52 0x052 // Message Control - R/W - 16 bits
-#define FCH_SATA_REG54 0x054 // Message Address - R/W - 32 bits
-#define FCH_SATA_REG58 0x058 // Message Data - R/W - 16 bits
-#define FCH_SATA_REG5C 0x05C // RAMBIST Control Register - R/W - 8 bits
-#define FCH_SATA_REG5D 0x05D // RAMBIST Status0 Register - R - 8 bits
-#define FCH_SATA_REG5E 0x05E // RAMBIST Status1 Register - R - 8 bits
-#define FCH_SATA_REG60 0x060 // Power Management Capabilities - R - 32 bits
-#define FCH_SATA_REG64 0x064 // Power Management Control + Status - RW - 32 bits
-#define FCH_SATA_REG68 0x068 // MSI Program - R/W - 8 bits
-#define FCH_SATA_REG69 0x069 // PCI Burst Timer - R/W - 8 bits
-#define FCH_SATA_REG70 0x070 // PCI Bus Master - IDE0 - RW - 32 bits
-#define FCH_SATA_REG74 0x074 // PRD Table Address - IDE0 - RW - 32 bits
-#define FCH_SATA_REG78 0x078 // PCI Bus Master - IDE1 - RW - 32 bits
-#define FCH_SATA_REG7C 0x07C // PRD Table Address - IDE1 - RW - 32 bits
-#define FCH_SATA_REG80 0x080 // Data Transfer Mode - IDE0 - RW - 32 bits
-#define FCH_SATA_REG84 0x084 // Data Transfer Mode - IDE1 - RW - 32 bits
-#define FCH_SATA_REG86 0x086 // PY Global Control
-#define FCH_SATA_REG87 0x087
-#define FCH_SATA_REG88 0x088 // PHY Port0 Control - Port0 PY fine tune (0:23)
-#define FCH_SATA_REG8A 0x08A
-#define FCH_SATA_REG8C 0x08C // PHY Port1 Control - Port0 PY fine tune (0:23)
-#define FCH_SATA_REG8E 0x08E
-#define FCH_SATA_REG90 0x090 // PHY Port2 Control - Port0 PY fine tune (0:23)
-#define FCH_SATA_REG92 0x092
-#define FCH_SATA_REG94 0x094 // PHY Port3 Control - Port0 PY fine tune (0:23)
-#define FCH_SATA_REG96 0x096
-#define FCH_SATA_REG98 0x098 // EEPROM Memory Address - Command + Status - RW - 32 bits
-#define FCH_SATA_REG9C 0x09C // EEPROM Memory Data - RW - 32 bits
-#define FCH_SATA_REGA0 0x0A0 //
-#define FCH_SATA_REGA4 0x0A4 //
-#define FCH_SATA_REGA5 0x0A5 //;
-#define FCH_SATA_REGA8 0x0A8 //
-#define FCH_SATA_REGAD 0x0AD //;
-#define FCH_SATA_REGB0 0x0B0 // IDE1 Task File Configuration + Status - RW - 32 bits
-#define FCH_SATA_REGB5 0x0B5 //;
-#define FCH_SATA_REGBD 0x0BD //;
-#define FCH_SATA_REGC0 0x0C0 // BA5 Indirect Address - RW - 32 bits
-#define FCH_SATA_REGC4 0x0C4 // BA5 Indirect Access - RW - 32 bits
-
-#define FCH_SATA_BAR5_REG00 0x000 // PCI Bus Master - IDE0 - RW - 32 bits
-#define FCH_SATA_BAR5_REG04 0x004 // PRD Table Address - IDE0 - RW - 32 bits
-#define FCH_SATA_BAR5_REG08 0x008 // PCI Bus Master - IDE1 - RW - 32 bits
-#define FCH_SATA_BAR5_REG0C 0x00C // PRD Table Address - IDE1 - RW - 32 bits
-#define FCH_SATA_BAR5_REG10 0x010 // PCI Bus Master2 - IDE0 - RW - 32 bits
-#define FCH_SATA_BAR5_REG1C 0x01C
-#define FCH_SATA_BAR5_REG18 0x018 // PCI Bus Master2 - IDE1 - RW - 32 bits
-#define FCH_SATA_BAR5_REG20 0x020 // PRD Address - IDE0 - RW - 32 bits
-#define FCH_SATA_BAR5_REG24 0x024 // PCI Bus Master Byte Count - IDE0- RW - 32 bits
-#define FCH_SATA_BAR5_REG28 0x028 // PRD Address - IDE1 - RW - 32 bits
-#define FCH_SATA_BAR5_REG2C 0x02C // PCI Bus Master Byte Count - IDE1 - RW - 32 bits
-#define FCH_SATA_BAR5_REG40 0x040 // FIFO Valid Byte Count and Control - IDE0 - RW - 32 bits
-#define FCH_SATA_BAR5_REG44 0x044 // FIFO Valid Byte Count and Control - IDE1 - RW - 32 bits
-#define FCH_SATA_BAR5_REG48 0x048 // System Configuration Status - Command - RW - 32 bits
-#define FCH_SATA_BAR5_REG4C 0x04C // System Software Data Register - RW - 32 bits
-#define FCH_SATA_BAR5_REG50 0x050 // FLAS Memory Address - Command + Status - RW - 32 bits
-#define FCH_SATA_BAR5_REG54 0x054 // FLAS Memory Data - RW - 32 bits
-#define FCH_SATA_BAR5_REG58 0x058 // EEPROM Memory Address - Command + Status - RW - 32 bits
-#define FCH_SATA_BAR5_REG5C 0x05C // EEPROM Memory Data - RW - 32 bits
-#define FCH_SATA_BAR5_REG60 0x060 // FIFO Port - IDE0 - RW - 32 bits
-#define FCH_SATA_BAR5_REG68 0x068 // FIFO Pointers1- IDE0 - RW - 32 bits
-#define FCH_SATA_BAR5_REG6C 0x06C // FIFO Pointers2- IDE0 - RW - 32 bits
-#define FCH_SATA_BAR5_REG70 0x070 // FIFO Port - IDE1- RW - 32 bits
-#define FCH_SATA_BAR5_REG78 0x078 // FIFO Pointers1- IDE1- RW - 32 bits
-#define FCH_SATA_BAR5_REG7C 0x07C // FIFO Pointers2- IDE1- RW - 32 bits
-#define FCH_SATA_BAR5_REG80 0x080 // IDE0 Task File Register 0- RW - 32 bits
-#define FCH_SATA_BAR5_REG84 0x084 // IDE0 Task File Register 1- RW - 32 bits
-#define FCH_SATA_BAR5_REG88 0x088 // IDE0 Task File Register 2- RW - 32 bits
-#define FCH_SATA_BAR5_REG8C 0x08C // IDE0 Read Data - RW - 32 bits
-#define FCH_SATA_BAR5_REG90 0x090 // IDE0 Task File Register 0 - Command Buffering - RW - 32 bits
-#define FCH_SATA_BAR5_REG94 0x094 // IDE0 Task File Register 1 - Command Buffering - RW - 32 bits
-#define FCH_SATA_BAR5_REG9C 0x09C // IDE0 Virtual DMA/PIO Read Byte Count - RW - 32 bits
-#define FCH_SATA_BAR5_REGA0 0x0A0 // IDE0 Task File Configuration + Status - RW - 32 bits
-#define FCH_SATA_BAR5_REGB4 0x0B4 // Data Transfer Mode -IDE0 - RW - 32 bits
-#define FCH_SATA_BAR5_REGC0 0x0C0 // IDE1 Task File Register 0 - RW - 32 bits
-#define FCH_SATA_BAR5_REGC4 0x0C4 // IDE1 Task File Register 1 - RW - 32 bits
-#define FCH_SATA_BAR5_REGC8 0x0C8 // IDE1 Task File Register 2 - RW - 32 bits
-#define FCH_SATA_BAR5_REGCC 0x0CC // Read/Write Data - RW - 32 bits
-#define FCH_SATA_BAR5_REGD0 0x0D0 // IDE1 Task File Register 0 - Command Buffering - RW - 32 bits
-#define FCH_SATA_BAR5_REGD4 0x0D4 // IDE1 Task File Register 1 - Command Buffering - RW - 32 bits
-#define FCH_SATA_BAR5_REGDC 0x0DC // IDE1 Virtual DMA/PIO Read Byte Count - RW - 32 bits
-#define FCH_SATA_BAR5_REGE0 0x0E0 // IDE1 Task File Configuration + Status - RW - 32 bits
-#define FCH_SATA_BAR5_REGF4 0x0F4 // Data Transfer Mode - IDE1 - RW - 32 bits
-#define FCH_SATA_BAR5_REGF8 0x0F8 // PORT Configuration
-#define FCH_SATA_BAR5_REGFC 0x0FC
-#define FCH_SATA_BAR5_REG100 0x0100 // Serial ATA SControl - RW - 32 bits - [Offset: 100h (channel 1) / 180
-#define FCH_SATA_BAR5_REG104 0x0104 // Serial ATA Sstatus - RW - 32 bits - [Offset: 104h (channel 1) / 184h (cannel
-#define FCH_SATA_BAR5_REG108 0x0108 // Serial ATA Serror - RW - 32 bits - [Offset: 108h (channel 1) / 188h (cannel
-#define FCH_SATA_BAR5_REG10C 0x010C // Serial ATA Sdevice - RW - 32 bits - [Offset: 10Ch (channel 1) / 18Ch (cannel
-#define FCH_SATA_BAR5_REG144 0x0144 // Serial ATA PY Configuration - RW - 32 bits
-#define FCH_SATA_BAR5_REG148 0x0148 // SIEN - RW - 32 bits - [Offset: 148 (channel 1) / 1C8 (cannel 2)]
-#define FCH_SATA_BAR5_REG14C 0x014C // SFISCfg - RW - 32 bits - [Offset: 14C (channel 1) / 1CC (cannel 2)]
-#define FCH_SATA_BAR5_REG120 0x0120 //
-#define FCH_SATA_BAR5_REG128 0x0128 // Port Serial ATA Status
-#define FCH_SATA_BAR5_REG12C 0x012C // Port Serial ATA Control
-#define FCH_SATA_BAR5_REG130 0x0130
-#define FCH_SATA_BAR5_REG1B0 0x01B0
-#define FCH_SATA_BAR5_REG230 0x0230
-#define FCH_SATA_BAR5_REG2B0 0x02B0
-#define FCH_SATA_BAR5_REG330 0x0330
-#define FCH_SATA_BAR5_REG3B0 0x03B0
-#define FCH_SATA_BAR5_REG430 0x0430
-#define FCH_SATA_BAR5_REG4B0 0x04B0
-//
-// USB XHCI Device 0x7812
-// Device 16 (0x10) Func 0/1
-//
-#define XHCI_EFUSE_LOCATION 0x18 // EFUSE bit 192, 193
-#define FCH_XHCI_REG48 0x48 // Port Force Reset - RW (800)
-#define FCH_XHCI_REG4C 0x4C // MSI - RW (800)
-//
-// USB OHCI Device 0x7807
-// Device 18 (0x11)/Device 19 (0x12)/Device 22 (0x16) Func 0
-// Device 20 (0x14) Func 5 (FL) 0x7809
-//
-#define FCH_OHCI_REG00 0x00 // Device/Vendor ID - R (0x43971002)
-#define FCH_OHCI_REG04 0x04 // Command - RW
-#define FCH_OHCI_REG06 0x06 // Status - R
-#define FCH_OHCI_REG08 0x08 // Revision ID/Class Code - R
-#define FCH_OHCI_REG0C 0x0C // Miscellaneous - RW
-#define FCH_OHCI_REG10 0x10 // Bar_OCI - RW
-#define FCH_OHCI_REG2C 0x2C // Subsystem Vendor ID/ Subsystem ID - RW
-#define FCH_OHCI_REG34 0x34 // Capability Pointer - R
-#define FCH_OHCI_REG3C 0x3C // Interrupt Line - RW
-#define FCH_OHCI_REG3D 0x3D // Interrupt Line - RW
-#define FCH_OHCI_REG40 0x40 // Config Timers - RW
-#define FCH_OHCI_REG42 0x42 // Port Disable Control - RW (800)
-#define FCH_OHCI_REG46 0x46 // USB PHY Battery Charger - RW (800)
-#define FCH_OHCI_REG48 0x48 // Port Force Reset - RW (800)
-#define FCH_OHCI_REG4C 0x4C // MSI - RW (800)
-#define FCH_OHCI_REG50 0x50 // Misc Control - RW
-#define FCH_OHCI_REG51 0x51
-#define FCH_OHCI_REG52 0x52
-#define FCH_OHCI_REG58 0x58 // Over Current Control - RW
-#define FCH_OHCI_REG5C 0x5C // Over Current Control - RW
-#define FCH_OHCI_REG60 0x60 // Serial Bus Release Number - RW
-#define FCH_OHCI_REG68 0x68 // Over Current PME Enable - RW
-#define FCH_OHCI_REG74 0x74 // Target Timeout Control - RW
-#define FCH_OHCI_REG80 0x80 //
-#define FCH_OHCI_REGD0 0x0D0 // MSI Control - RW
-#define FCH_OHCI_REGD4 0x0D4 // MSI Address - RW
-#define FCH_OHCI_REGD8 0x0D8 // MSI Data - RW
-#define FCH_OHCI_REGE4 0x0E4 // HT MSI Support
-#define FCH_OHCI_REGF0 0x0F0 // Function Level Reset Capability
-#define FCH_OHCI_REGF4 0x0F4 // Function Level Reset Control
-
-#define FCH_OHCI_BAR_REG00 0x00 // cRevision - R
-#define FCH_OHCI_BAR_REG04 0x04 // cControl
-#define FCH_OHCI_BAR_REG08 0x08 // cCommandStatus
-#define FCH_OHCI_BAR_REG0C 0x0C // cInterruptStatus RW
-#define FCH_OHCI_BAR_REG10 0x10 // cInterruptEnable
-#define FCH_OHCI_BAR_REG14 0x14 // cInterruptDisable
-#define FCH_OHCI_BAR_REG18 0x18 // HcCCA
-#define FCH_OHCI_BAR_REG1C 0x1C // cPeriodCurrentED
-#define FCH_OHCI_BAR_REG20 0x20 // HcControleadED
-#define FCH_OHCI_BAR_REG24 0x24 // cControlCurrentED RW
-#define FCH_OHCI_BAR_REG28 0x28 // HcBulkeadED
-#define FCH_OHCI_BAR_REG2C 0x2C // cBulkCurrentED- RW
-#define FCH_OHCI_BAR_REG30 0x30 // HcDoneead
-#define FCH_OHCI_BAR_REG34 0x34 // cFmInterval
-#define FCH_OHCI_BAR_REG38 0x38 // cFmRemaining
-#define FCH_OHCI_BAR_REG3C 0x3C // cFmNumber
-#define FCH_OHCI_BAR_REG40 0x40 // cPeriodicStart
-#define FCH_OHCI_BAR_REG44 0x44 // HcLSThresold
-#define FCH_OHCI_BAR_REG48 0x48 // HcRDescriptorA
-#define FCH_OHCI_BAR_REG4C 0x4C // HcRDescriptorB
-#define FCH_OHCI_BAR_REG50 0x50 // HcRStatus
-#define FCH_OHCI_BAR_REG54 0x54 // HcRhPortStatus (800)
-#define FCH_OHCI_BAR_REG58 0x58 // HcRhPortStatus NPD (800)
-#define FCH_OHCI_BAR_REGF0 0xF0 // OHCI Loop Back feature Support (800)
-
-//
-// USB EHCI Device 0x7808
-// Device 18 (0x11)/Device 19 (0x12)/Device 22 (0x16) Func 2
-//
-#define FCH_EHCI_REG00 0x00 // DEVICE/VENDOR ID - R
-#define FCH_EHCI_REG04 0x04 // Command - RW
-#define FCH_EHCI_REG06 0x06 // Status - R
-#define FCH_EHCI_REG08 0x08 // Revision ID/Class Code - R
-#define FCH_EHCI_REG0C 0x0C // Miscellaneous - RW
-#define FCH_EHCI_REG10 0x10 // BAR - RW
-#define FCH_EHCI_REG2C 0x2C // Subsystem ID/Subsystem Vendor ID - RW
-#define FCH_EHCI_REG34 0x34 // Capability Pointer - R
-#define FCH_EHCI_REG3C 0x3C // Interrupt Line - RW
-#define FCH_EHCI_REG3D 0x3D // Interrupt Line - RW
-#define FCH_EHCI_REG40 0x40 // Config Timers - RW
-#define FCH_EHCI_REG4C 0x4C // MSI - RW
-#define FCH_EHCI_REG50 0x50 // EHCI Misc Control - RW
-#define FCH_EHCI_REG54 0x54 // EHCI Misc Control - RW
-#define FCH_EHCI_REG60 0x60 // SBRN - R
-#define FCH_EHCI_REG61 0x61 // FLADJ - RW
-#define FCH_EHCI_REG62 0x62 // PORTWAKECAP - RW
-#define FCH_EHCI_REGC0 0x0C0 // PME control - RW (800)
-#define FCH_EHCI_REGC4 0x0C4 // PME Data /Status - RW (800)
-#define FCH_EHCI_REGD0 0x0D0 // MSI Control - RW
-#define FCH_EHCI_REGD4 0x0D4 // MSI Address - RW
-#define FCH_EHCI_REGD8 0x0D8 // MSI Data - RW
-#define FCH_EHCI_REGE4 0x0E4 // EHCI Debug Port Support - RW (800)
-#define FCH_EHCI_REGF0 0x0F0 // Function Level Reset Capability - R (800)
-#define FCH_EHCI_REGF4 0x0F4 // Function Level Reset Capability - R (800)
-
-#define FCH_EHCI_BAR_REG00 0x00 // CAPLENGT - R
-#define FCH_EHCI_BAR_REG02 0x002 // CIVERSION- R
-#define FCH_EHCI_BAR_REG04 0x004 // CSPARAMS - R
-#define FCH_EHCI_BAR_REG08 0x008 // CCPARAMS - R
-#define FCH_EHCI_BAR_REG0C 0x00C // CSP-PORTROUTE - R
-
-#define FCH_EHCI_BAR_REG20 0x020 // USBCMD - RW - 32 bits
-#define FCH_EHCI_BAR_REG24 0x024 // USBSTS - RW - 32 bits
-#define FCH_EHCI_BAR_REG28 0x028 // USBINTR -RW - 32 bits
-#define FCH_EHCI_BAR_REG2C 0x02C // FRINDEX -RW - 32 bits
-#define FCH_EHCI_BAR_REG30 0x030 // CTRLDSSEGMENT -RW - 32 bits
-#define FCH_EHCI_BAR_REG34 0x034 // PERIODICLISTBASE -RW - 32 bits
-#define FCH_EHCI_BAR_REG38 0x038 // ASYNCLISTADDR -RW - 32 bits
-#define FCH_EHCI_BAR_REG60 0x060 // CONFIGFLAG -RW - 32 bits
-#define FCH_EHCI_BAR_REG64 0x064 // PORTSC (1-N_PORTS) -RW - 32 bits
-#define FCH_EHCI_BAR_REGA0 0x0A0 // DebugPort MISC Control - RW - 32 bits (800)
-#define FCH_EHCI_BAR_REGA4 0x0A4 // Packet Buffer Threshold Values - RW - 32 bits
-#define FCH_EHCI_BAR_REGA8 0x0A8 // USB PHY Status 0 - R
-#define FCH_EHCI_BAR_REGAC 0x0AC // USB PHY Status 1 - R
-#define FCH_EHCI_BAR_REGB0 0x0B0 // USB PHY Status 2 - R
-#define FCH_EHCI_BAR_REGB4 0x0B4 // UTMI Control - RW (800)
-#define FCH_EHCI_BAR_REGB8 0x0B8 // Loopback Test
-#define FCH_EHCI_BAR_REGBC 0x0BC // EHCI MISC Control
-#define FCH_EHCI_BAR_REGC0 0x0C0 // USB PHY Calibration
-#define FCH_EHCI_BAR_REGC4 0x0C4 // USB Common PHY Control
-#define FCH_EHCI_BAR_REGC8 0x0C8 // EHCI Debug Purpose
-#define FCH_EHCI_BAR_REGCC 0x0CC // Ehci Spare 1 (800) **
-#define FCH_EHCI_BAR_REG100 0x100 // USB debug port
-
-//
-// FCH CFG device 0x780B
-// Device 20 (0x14) Func 0
-//
-#define FCH_CFG_REG00 0x000 // VendorID - R
-#define FCH_CFG_REG02 0x002 // DeviceID - R
-#define FCH_CFG_REG04 0x004 // Command- RW
-#define FCH_CFG_REG05 0x005 // Command- RW
-#define FCH_CFG_REG06 0x006 // STATUS- RW
-#define FCH_CFG_REG08 0x008 // Revision ID/Class Code- R
-#define FCH_CFG_REG0A 0x00A //
-#define FCH_CFG_REG0B 0x00B //
-#define FCH_CFG_REG0C 0x00C // Cache Line Size- R
-#define FCH_CFG_REG0D 0x00D // Latency Timer- R
-#define FCH_CFG_REG0E 0x00E // Header Type- R
-#define FCH_CFG_REG0F 0x00F // BIST- R
-#define FCH_CFG_REG10 0x010 // Base Address 0- R
-#define FCH_CFG_REG11 0x011 //;
-#define FCH_CFG_REG12 0x012 //;
-#define FCH_CFG_REG13 0x013 //;
-#define FCH_CFG_REG14 0x014 // Base Address 1- R
-#define FCH_CFG_REG18 0x018 // Base Address 2- R
-#define FCH_CFG_REG1C 0x01C // Base Address 3- R
-#define FCH_CFG_REG20 0x020 // Base Address 4- R
-#define FCH_CFG_REG24 0x024 // Base Address 5- R
-#define FCH_CFG_REG28 0x028 // Cardbus CIS Pointer- R
-#define FCH_CFG_REG2C 0x02C // Subsystem Vendor ID- W
-#define FCH_CFG_REG2E 0x02E // Subsystem ID- W
-#define FCH_CFG_REG30 0x030 // Expansion ROM Base Address - R
-#define FCH_CFG_REG34 0x034 // Capability Pointer - R (800) default changed as 0x00
-#define FCH_CFG_REG3C 0x03C // Interrupt Line - R
-#define FCH_CFG_REG3D 0x03D // Interrupt Pin - R
-#define FCH_CFG_REG3E 0x03E // Min_Gnt - R
-#define FCH_CFG_REG3F 0x03F // Max_Lat - R
-#define FCH_CFG_REG90 0x090 // Smbus Base Address - R
-#define FCH_CFG_REG9C 0x09C // SBResourceMMIO_BASE
-
-//
-// FCH SATA IDE device
-// Device 20 (0x14) Func 1
-//
-
-#define FCH_IDE_REG00 0x00 // Vendor ID
-#define FCH_IDE_REG02 0x02 // Device ID
-#define FCH_IDE_REG04 0x04 // Command
-#define FCH_IDE_REG06 0x06 // Status
-#define FCH_IDE_REG08 0x08 // Revision ID/Class Code
-#define FCH_IDE_REG09 0x09 // Class Code
-#define FCH_IDE_REG2C 0x2C // Subsystem ID and Subsystem Vendor ID
-#define FCH_IDE_REG40 0x40 // Configuration - RW - 32 bits
-#define FCH_IDE_REG34 0x34
-#define FCH_IDE_REG62 0x62 // IDE Internal Control
-#define FCH_IDE_REG63 0x63 // IDE Internal Control
-//
-// FCH AZALIA device 0x780D
-// Device 20 (0x14) Func 2
-//
-#define ATI_AZALIA_ExtBlk_Addr 0x0F8
-#define ATI_AZALIA_ExtBlk_DATA 0x0FC
-
-#define FCH_AZ_REG00 0x00 // Vendor ID - R
-#define FCH_AZ_REG02 0x02 // Device ID - R/W
-#define FCH_AZ_REG04 0x04 // PCI Command
-#define FCH_AZ_REG06 0x06 // PCI Status - R/W
-#define FCH_AZ_REG08 0x08 // Revision ID
-#define FCH_AZ_REG09 0x09 // Programming Interface
-#define FCH_AZ_REG0A 0x0A // Sub Class Code
-#define FCH_AZ_REG0B 0x0B // Base Class Code
-#define FCH_AZ_REG0C 0x0C // Cache Line Size - R/W
-#define FCH_AZ_REG0D 0x0D // Latency Timer
-#define FCH_AZ_REG0E 0x0E // Header Type
-#define FCH_AZ_REG0F 0x0F // BIST
-#define FCH_AZ_REG10 0x10 // Lower Base Address Register
-#define FCH_AZ_REG14 0x14 // Upper Base Address Register
-#define FCH_AZ_REG2C 0x2C // Subsystem Vendor ID
-#define FCH_AZ_REG2D 0x2D // Subsystem ID
-#define FCH_AZ_REG34 0x34 // Capabilities Pointer
-#define FCH_AZ_REG3C 0x3C // Interrupt Line
-#define FCH_AZ_REG3D 0x3D // Interrupt Pin
-#define FCH_AZ_REG3E 0x3E // Minimum Grant
-#define FCH_AZ_REG3F 0x3F // Maximum Latency
-#define FCH_AZ_REG40 0x40 // Misc Control 1
-#define FCH_AZ_REG42 0x42 // Misc Control 2 Register
-#define FCH_AZ_REG43 0x43 // Misc Control 3 Register
-#define FCH_AZ_REG44 0x44 // Interrupt Pin Control Register
-#define FCH_AZ_REG46 0x46 // Debug Control Register
-#define FCH_AZ_REG4C 0x4C
-#define FCH_AZ_REG50 0x50 // Power Management Capability ID
-#define FCH_AZ_REG52 0x52 // Power Management Capabilities
-#define FCH_AZ_REG54 0x54 // Power Management Control/Status
-#define FCH_AZ_REG60 0x60 // MSI Capability ID
-#define FCH_AZ_REG62 0x62 // MSI Message Control
-#define FCH_AZ_REG64 0x64 // MSI Message Lower Address
-#define FCH_AZ_REG68 0x68 // MSI Message Upper Address
-#define FCH_AZ_REG6C 0x6C // MSI Message Data
-
-#define FCH_AZ_BAR_REG00 0x00 // Global Capabilities - R
-#define FCH_AZ_BAR_REG02 0x02 // Minor Version - R
-#define FCH_AZ_BAR_REG03 0x03 // Major Version - R
-#define FCH_AZ_BAR_REG04 0x04 // Output Payload Capability - R
-#define FCH_AZ_BAR_REG06 0x06 // Input Payload Capability - R
-#define FCH_AZ_BAR_REG08 0x08 // Global Control - R/W
-#define FCH_AZ_BAR_REG0C 0x0C // Wake Enable - R/W
-#define FCH_AZ_BAR_REG0E 0x0E // State Change Status - R/W
-#define FCH_AZ_BAR_REG10 0x10 // Global Status - R/W
-#define FCH_AZ_BAR_REG18 0x18 // Output Stream Payload Capability - R
-#define FCH_AZ_BAR_REG1A 0x1A // Input Stream Payload Capability - R
-#define FCH_AZ_BAR_REG20 0x20 // Interrupt Control - R/W
-#define FCH_AZ_BAR_REG24 0x24 // Interrupt Status - R/W
-#define FCH_AZ_BAR_REG30 0x30 // Wall Clock Counter - R
-#define FCH_AZ_BAR_REG38 0x38 // Stream Synchronization - R/W
-#define FCH_AZ_BAR_REG40 0x40 // CORB Lower Base Address - R/W
-#define FCH_AZ_BAR_REG44 0x44 // CORB Upper Base Address - RW
-#define FCH_AZ_BAR_REG48 0x48 // CORB Write Pointer - R/W
-#define FCH_AZ_BAR_REG4A 0x4A // CORB Read Pointer - R/W
-#define FCH_AZ_BAR_REG4C 0x4C // CORB Control - R/W
-#define FCH_AZ_BAR_REG4D 0x4D // CORB Status - R/W
-#define FCH_AZ_BAR_REG4E 0x4E // CORB Size - R/W
-#define FCH_AZ_BAR_REG50 0x50 // RIRB Lower Base Address - RW
-#define FCH_AZ_BAR_REG54 0x54 // RIRB Upper Address - RW
-#define FCH_AZ_BAR_REG58 0x58 // RIRB Write Pointer - RW
-#define FCH_AZ_BAR_REG5A 0x5A // RIRB Response Interrupt Count - R/W
-#define FCH_AZ_BAR_REG5C 0x5C // RIRB Control - R/W
-#define FCH_AZ_BAR_REG5D 0x5D // RIRB Status - R/W
-#define FCH_AZ_BAR_REG5E 0x5E // RIRB Size - R/W
-#define FCH_AZ_BAR_REG60 0x60 // Immediate Command Output Interface - R/W
-#define FCH_AZ_BAR_REG64 0x64 // Immediate Command Input Interface - R/W
-#define FCH_AZ_BAR_REG68 0x68 // Immediate Command Input Interface - R/W
-#define FCH_AZ_BAR_REG70 0x70 // DMA Position Lower Base Address - R/W
-#define FCH_AZ_BAR_REG74 0x74 // DMA Position Upper Base Address - R/W
-#define FCH_AZ_BAR_REG2030 0x2030 // Wall Clock Counter Alias - R
-
-//
-// FCH LPC Device 0x780E
-// Device 20 (0x14) Func 3
-//
-#define FCH_LPC_REG00 0x00 // VID- R
-#define FCH_LPC_REG02 0x02 // DID- R
-#define FCH_LPC_REG04 0x04 // CMD- RW
-#define FCH_LPC_REG06 0x06 // STATUS- RW
-#define FCH_LPC_REG08 0x08 // Revision ID/Class Code - R
-#define FCH_LPC_REG0C 0x0C // Cache Line Size - R
-#define FCH_LPC_REG0D 0x0D // Latency Timer - R
-#define FCH_LPC_REG0E 0x0E // Header Type - R
-#define FCH_LPC_REG0F 0x0F // BIST- R
-#define FCH_LPC_REG10 0x10 // Base Address Reg 0- RW*
-#define FCH_LPC_REG2C 0x2C // Subsystem ID & Subsystem Vendor ID - Wo/Ro
-#define FCH_LPC_REG34 0x34 // Capabilities Pointer - Ro
-#define FCH_LPC_REG40 0x40 // PCI Control - RW
-#define FCH_LPC_REG44 0x44 // IO Port Decode Enable Register 1- RW
-#define FCH_LPC_REG45 0x45 // IO Port Decode Enable Register 2- RW
-#define FCH_LPC_REG46 0x46 // IO Port Decode Enable Register 3- RW
-#define FCH_LPC_REG47 0x47 // IO Port Decode Enable Register 4- RW
-#define FCH_LPC_REG48 0x48 // IO/Mem Port Decode Enable Register 5- RW
-#define FCH_LPC_REG49 0x49 // LPC Sync Timeout Count - RW
-#define FCH_LPC_REG4A 0x4A // IO/Mem Port Decode Enable Register 6- RW
-#define FCH_LPC_REG4C 0x4C // Memory Range Register - RW
-#define FCH_LPC_REG50 0x50 // Rom Protect 0 - RW
-#define FCH_LPC_REG54 0x54 // Rom Protect 1 - RW
-#define FCH_LPC_REG58 0x58 // Rom Protect 2 - RW
-#define FCH_LPC_REG5C 0x5C // Rom Protect 3 - RW
-#define FCH_LPC_REG60 0x60 // PCI Memory Start Address of LPC Target Cycles -
-#define FCH_LPC_REG62 0x62 // PCI Memory End Address of LPC Target Cycles -
-#define FCH_LPC_REG64 0x64 // PCI IO base Address of Wide Generic Port - RW
-#define FCH_LPC_REG65 0x65
-#define FCH_LPC_REG66 0x66
-#define FCH_LPC_REG67 0x67
-#define FCH_LPC_REG68 0x68 // LPC ROM Address Range 1 (Start Address) - RW
-#define FCH_LPC_REG69 0x69
-#define FCH_LPC_REG6A 0x6A // LPC ROM Address Range 1 (End Address) - RW
-#define FCH_LPC_REG6B 0x6B
-#define FCH_LPC_REG6C 0x6C // LPC ROM Address Range 2 (Start Address)- RW
-#define FCH_LPC_REG6D 0x6D
-#define FCH_LPC_REG6E 0x6E // LPC ROM Address Range 2 (End Address) - RW
-#define FCH_LPC_REG6F 0x6F
-#define FCH_LPC_REG70 0x70 // Firmware ub Select - RW*
-#define FCH_LPC_REG71 0x71
-#define FCH_LPC_REG72 0x72
-#define FCH_LPC_REG73 0x73
-#define FCH_LPC_REG74 0x74 // Alternative Wide IO Range Enable- W/R
-#define FCH_LPC_REG78 0x78 // Miscellaneous Control Bits- W/R
-#define FCH_LPC_REG7C 0x7C // TPM (trusted plant form module) reg- W/R
-#define FCH_LPC_REG9C 0x9C
-#define FCH_LPC_REG80 0x80 // MSI Capability Register- R
-#define FCH_LPC_REGA0 0x0A0 // SPI base address
-#define FCH_LPC_REGA1 0x0A1 // SPI base address
-#define FCH_LPC_REGA2 0x0A2 // SPI base address
-#define FCH_LPC_REGA3 0x0A3 // SPI base address
-#define FCH_LPC_REGA4 0x0A4
-#define FCH_LPC_REGBA 0x0BA // EcControl
-#define FCH_LPC_REGBB 0x0BB // HostControl
-#define FCH_LPC_REGCC 0x0CC // AutoRomCfg
-
-//
-// FCH PCIB 0x780F
-// Device 20 (0x14) Func 4
-//
-#define FCH_PCIB_REG04 0x04 // Command
-#define FCH_PCIB_REG0D 0x0D // Primary Master Latency Timer
-#define FCH_PCIB_REG1B 0x1B // Secondary Latency Timer
-#define FCH_PCIB_REG1C 0x1C // IO Base
-#define FCH_PCIB_REG1D 0x1D // IO Limit
-#define FCH_PCIB_REG40 0x40 // CPCTRL
-#define FCH_PCIB_REG42 0x42 // CLKCTRL
-#define FCH_PCIB_REG48 0x48 //
-#define FCH_PCIB_REG4A 0x4A // PCICLK Enable Bits
-#define FCH_PCIB_REG4B 0x4B // Misc Control
-#define FCH_PCIB_REG4C 0x4C // AutoClockRun Control
-#define FCH_PCIB_REG50 0x50 // Dual Address Cycle Enable and PCIB_CLK_Stop Override
-#define FCH_PCIB_REG65 0x65 // Misc Control
-#define FCH_PCIB_REG66 0x66 // Misc Control
-//
-// FCH GEC 0x14E4 0x1699
-// Device 20 (0x14) Func 6
-//
-#define FCH_GEC_REG10 0x10 // GEC BAR
-//
-// FCH MMIO Base (SMI)
-// offset : 0x200
-//
-#define FCH_SMI_REG00 0x00 // EventStatus
-#define FCH_SMI_REG04 0x04 // EventEnable
-#define FCH_SMI_REG08 0x08 // SciTrig
-#define FCH_SMI_REG0C 0x0C // SciLevl
-#define FCH_SMI_REG10 0x10 // SmiSciStatus
-#define FCH_SMI_REG14 0x14 // SmiSciEn
-#define FCH_SMI_REG18 0x18 // ForceSciEn
-#define FCH_SMI_REG1C 0x1C // SciRwData
-#define FCH_SMI_REG3C 0x3C // DataErrorStatus
-#define FCH_SMI_REG20 0x20 // SciS0En
-#define FCH_SMI_Gevent0 0x40 // SciMap0
-#define FCH_SMI_Gevent1 0x41 // SciMap1
-#define FCH_SMI_Gevent2 0x42 // SciMap2
-#define FCH_SMI_Gevent3 0x43 // SciMap3
-#define FCH_SMI_Gevent4 0x44 // SciMap4
-#define FCH_SMI_Gevent5 0x45 // SciMap5
-#define FCH_SMI_Gevent6 0x46 // SciMap6
-#define FCH_SMI_Gevent7 0x47 // SciMap7
-#define FCH_SMI_Gevent8 0x48 // SciMap8
-#define FCH_SMI_Gevent9 0x49 // SciMap9
-#define FCH_SMI_Gevent10 0x4A // SciMap10
-#define FCH_SMI_Gevent11 0x4B // SciMap11
-#define FCH_SMI_Gevent12 0x4C // SciMap12
-#define FCH_SMI_Gevent13 0x4D // SciMap13
-#define FCH_SMI_Gevent14 0x4E // SciMap14
-#define FCH_SMI_Gevent15 0x4F // SciMap15
-#define FCH_SMI_Gevent16 0x50 // SciMap16
-#define FCH_SMI_Gevent17 0x51 // SciMap17
-#define FCH_SMI_Gevent18 0x52 // SciMap18
-#define FCH_SMI_Gevent19 0x53 // SciMap19
-#define FCH_SMI_Gevent20 0x54 // SciMap20
-#define FCH_SMI_Gevent21 0x55 // SciMap21
-#define FCH_SMI_Gevent22 0x56 // SciMap22
-#define FCH_SMI_Gevent23 0x57 // SciMap23
-#define FCH_SMI_Usbwakup0 0x58 // SciMap24
-#define FCH_SMI_Usbwakup1 0x59 // SciMap25
-#define FCH_SMI_Usbwakup2 0x5A // SciMap26
-#define FCH_SMI_Usbwakup3 0x5B // SciMap27
-#define FCH_SMI_SBGppPme0 0x5C // SciMap28
-#define FCH_SMI_SBGppPme1 0x5D // SciMap29
-#define FCH_SMI_SBGppPme2 0x5E // SciMap30
-#define FCH_SMI_SBGppPme3 0x5F // SciMap31
-#define FCH_SMI_SBGppHp0 0x60 // SciMap32
-#define FCH_SMI_SBGppHp1 0x61 // SciMap33
-#define FCH_SMI_SBGppHp2 0x62 // SciMap34
-#define FCH_SMI_SBGppHp3 0x63 // SciMap35
-#define FCH_SMI_AzaliaPme 0x64 // SciMap36
-#define FCH_SMI_SataGevent0 0x65 // SciMap37
-#define FCH_SMI_SataGevent1 0x66 // SciMap38
-#define FCH_SMI_GecPme 0x67 // SciMap39
-#define FCH_SMI_IMCGevent0 0x68 // SciMap40
-#define FCH_SMI_IMCGevent1 0x69 // SciMap41
-#define FCH_SMI_CIRPme 0x6A // SciMap42
-#define FCH_SMI_WakePinGevent 0x6B // SciMap43
-#define FCH_SMI_FanThGevent 0x6C // SciMap44 //FanThermalGevent
-#define FCH_SMI_ASFMasterIntr 0x6D // SciMap45
-#define FCH_SMI_ASFSlaveIntr 0x6E // SciMap46
-#define FCH_SMI_SMBUS0 0x6F // SciMap47
-#define FCH_SMI_TWARN 0x70 // SciMap48
-#define FCH_SMI_TMI 0x71 // SciMap49 // TrafficMonitorIntr
-#define FCH_SMI_iLLB 0x72 // SciMap50
-#define FCH_SMI_PowerButton 0x73 // SciMap51
-#define FCH_SMI_ProcHot 0x74 // SciMap52
-#define FCH_SMI_APUHwAssertion 0x75 // SciMap53
-#define FCH_SMI_APUSciAssertion 0x76 // SciMap54
-#define FCH_SMI_RAS 0x77 // SciMap55
-#define FCH_SMI_xHC0Pme 0x78 // SciMap56
-#define FCH_SMI_xHC1Pme 0x79 // SciMap57
-
-// Empty from 0x72-0x7F
-//#Define FCH_SMI_REG7C 0x7F // SciMap63 ***
-
-#define FCH_SMI_REG80 0x80 // SmiStatus0
-#define FCH_SMI_REG84 0x84 // SmiStatus1
-#define FCH_SMI_REG88 0x88 // SmiStatus2
-#define FCH_SMI_REG8C 0x8C // SmiStatus3
-#define FCH_SMI_REG90 0x90 // SmiStatus4
-#define FCH_SMI_REG94 0x94 // SmiPointer
-#define FCH_SMI_REG96 0x96 // SmiTimer
-#define FCH_SMI_REG98 0x98 // SmiTrig
-#define FCH_SMI_REG9C 0x9C // SmiTrig
-#define FCH_SMI_REGA0 0xA0
-#define FCH_SMI_REGA1 0xA1
-#define FCH_SMI_REGA2 0xA2
-#define FCH_SMI_REGA3 0xA3
-#define FCH_SMI_REGA4 0xA4
-#define FCH_SMI_REGA5 0xA5
-#define FCH_SMI_REGA6 0xA6
-#define FCH_SMI_REGA7 0xA7
-#define FCH_SMI_REGA8 0xA8
-#define FCH_SMI_REGA9 0xA9
-#define FCH_SMI_REGAA 0xAA
-#define FCH_SMI_REGAB 0xAB
-#define FCH_SMI_REGAC 0xAC
-#define FCH_SMI_REGAD 0xAD
-#define FCH_SMI_REGAE 0xAE
-#define FCH_SMI_REGAF 0xAF
-#define FCH_SMI_REGB0 0xB0
-#define FCH_SMI_REGB1 0xB1
-#define FCH_SMI_REGB2 0xB2
-#define FCH_SMI_REGB3 0xB3
-#define FCH_SMI_REGB4 0xB4
-#define FCH_SMI_REGB5 0xB5
-#define FCH_SMI_REGB6 0xB6
-#define FCH_SMI_REGB7 0xB7
-#define FCH_SMI_REGB8 0xB8
-#define FCH_SMI_REGB9 0xB9
-#define FCH_SMI_REGBA 0xBA
-#define FCH_SMI_REGBB 0xBB
-#define FCH_SMI_REGBC 0xBC
-#define FCH_SMI_REGBD 0xBD
-#define FCH_SMI_REGBE 0xBE
-#define FCH_SMI_REGBF 0xBF
-#define FCH_SMI_REGC0 0xC0
-#define FCH_SMI_REGC1 0xC1
-#define FCH_SMI_REGC2 0xC2
-#define FCH_SMI_REGC3 0xC3
-#define FCH_SMI_REGC4 0xC4
-#define FCH_SMI_REGC5 0xC5
-#define FCH_SMI_REGC6 0xC6
-#define FCH_SMI_REGC7 0xC7
-#define FCH_SMI_REGC8 0xC8
-#define FCH_SMI_REGCA 0xCA // IoTrapping1
-#define FCH_SMI_REGCC 0xCC // IoTrapping2
-#define FCH_SMI_REGCE 0xCE // IoTrapping3
-#define FCH_SMI_REGD0 0xD0 // MemTrapping0
-#define FCH_SMI_REGD4 0xD4 // MemRdOvrData0
-#define FCH_SMI_REGD8 0xD8 // MemTrapping1
-#define FCH_SMI_REGDC 0xDC // MemRdOvrData1
-#define FCH_SMI_REGE0 0xE0 // MemTrapping2
-#define FCH_SMI_REGE4 0xE4 // MemRdOvrData2
-#define FCH_SMI_REGE8 0xE8 // MemTrapping3
-#define FCH_SMI_REGEC 0xEC // MemRdOvrData3
-#define FCH_SMI_REGF0 0xF0 // CfgTrapping0
-#define FCH_SMI_REGF4 0xF4 // CfgTrapping1
-#define FCH_SMI_REGF8 0xF8 // CfgTrapping2
-#define FCH_SMI_REGFC 0xFC // CfgTrapping3
-
-//
-// FCH MMIO Base (PMIO)
-// offset : 0x300
-//
-#define FCH_PMIOA_REG00 0x00 // ISA Decode
-#define FCH_PMIOA_REG04 0x04 // ISA Control
-#define FCH_PMIOA_REG08 0x08 // PCI Control
-#define FCH_PMIOA_REG0C 0x0C // StpClkSmaf
-#define FCH_PMIOA_REG10 0x10 // RetryDetect
-#define FCH_PMIOA_REG14 0x14 // StuckDetect
-#define FCH_PMIOA_REG20 0x20 // BiosRamEn
-#define FCH_PMIOA_REG24 0x24 // AcpiMmioEn
-#define FCH_PMIOA_REG28 0x28 // AsfEn
-#define FCH_PMIOA_REG2C 0x2C // Smbus0En
-#define FCH_PMIOA_REG2E 0x2E // Smbus0Sel
-#define FCH_PMIOA_REG34 0x34 // IoApicEn
-#define FCH_PMIOA_REG3C 0x3C // SmartVoltEn
-#define FCH_PMIOA_REG40 0x40 // SmartVolt2En
-#define FCH_PMIOA_REG44 0x44 // BootTimerEn
-#define FCH_PMIOA_REG48 0x48 // WatchDogTimerEn
-#define FCH_PMIOA_REG4C 0x4C // WatchDogTimerConfig
-#define FCH_PMIOA_REG50 0x50 // HPETEn
-#define FCH_PMIOA_REG54 0x54 // SerialIrqConfig
-#define FCH_PMIOA_REG56 0x56 // RtcControl
-#define FCH_PMIOA_REG58 0x58 // VRT_T1
-#define FCH_PMIOA_REG59 0x59 // VRT_T2
-#define FCH_PMIOA_REG5A 0x5A // IntruderControl
-#define FCH_PMIOA_REG5B 0x5B // RtcShadow
-#define FCH_PMIOA_REG5C 0x5C
-#define FCH_PMIOA_REG5D 0x5D
-#define FCH_PMIOA_REG5E 0x5E // RtcExtIndex
-#define FCH_PMIOA_REG5F 0x5F // RtcExtData
-#define FCH_PMIOA_REG60 0x60 // AcpiPm1EvtBlk
-#define FCH_PMIOA_REG62 0x62 // AcpiPm1CntBlk
-#define FCH_PMIOA_REG64 0x64 // AcpiPmTmrBlk
-#define FCH_PMIOA_REG66 0x66 // P_CNTBlk
-#define FCH_PMIOA_REG68 0x68 // AcpiGpe0Blk
-#define FCH_PMIOA_REG6A 0x6A // AcpiSmiCmd
-#define FCH_PMIOA_REG6C 0x6C // AcpiPm2CntBlk
-#define FCH_PMIOA_REG6E 0x6E // AcpiPmaCntBlk
-#define FCH_PMIOA_REG74 0x74 // AcpiConfig
-#define FCH_PMIOA_REG78 0x78 // WakeIoAddr
-#define FCH_PMIOA_REG7A 0x7A // HaltCountEn
-#define FCH_PMIOA_REG7C 0x7C // C1eWrPortAdr
-#define FCH_PMIOA_REG7E 0x7E // CStateEn
-#define FCH_PMIOA_REG80 0x80 // BreakEvent
-#define FCH_PMIOA_REG84 0x84 // AutoArbEn
-#define FCH_PMIOA_REG88 0x88 // CStateControl
-#define FCH_PMIOA_REG89 0x89 //
-#define FCH_PMIOA_REG8C 0x8C // StpClkHoldTime
-#define FCH_PMIOA_REG8E 0x8E // PopUpEndTime
-#define FCH_PMIOA_REG90 0x90 // C4Control
-#define FCH_PMIOA_REG94 0x94 // CStateTiming0
-#define FCH_PMIOA_REG96 0x96 //
-#define FCH_PMIOA_REG97 0x97 //
-#define FCH_PMIOA_REG98 0x98 // CStateTiming1
-#define FCH_PMIOA_REG99 0x99 //
-#define FCH_PMIOA_REG9B 0x9B //
-#define FCH_PMIOA_REG9C 0x9C // C2Count
-#define FCH_PMIOA_REG9D 0x9D // C3Count
-#define FCH_PMIOA_REG9E 0x9E // C4Count
-#define FCH_PMIOA_REGA0 0xA0 // MessageCState
-#define FCH_PMIOA_REGA4 0xA4 //
-#define FCH_PMIOA_REGA8 0xA8 // TrafficMonitorIdleTime
-#define FCH_PMIOA_REGAA 0xAA // TrafficMonitorIntTime
-#define FCH_PMIOA_REGAC 0xAC // TrafficMonitorTrafficCount
-#define FCH_PMIOA_REGAE 0xAE // TrafficMonitorIntrCount
-#define FCH_PMIOA_REGB0 0xB0 // TrafficMonitorTimeTick
-#define FCH_PMIOA_REGB4 0xB4 // FidVidControl
-#define FCH_PMIOA_REGB6 0xB6 // TPRESET1
-#define FCH_PMIOA_REGB7 0xB7 // Tpreset1b
-#define FCH_PMIOA_REGB8 0xB8 // TPRESET2
-#define FCH_PMIOA_REGB9 0xB9 // Test0
-#define FCH_PMIOA_REGBA 0xBA // S_StateControl
-#define FCH_PMIOA_REGBB 0xBB //
-#define FCH_PMIOA_REGBC 0xBC // ThrottlingControl
-#define FCH_PMIOA_REGBE 0xBE // ResetControl
-#define FCH_PMIOA_REGBF 0xBF // ResetControl
-#define FCH_PMIOA_REGC0 0xC0 // S5Status
-#define FCH_PMIOA_REGC2 0xC2 // ResetStatus
-#define FCH_PMIOA_REGC4 0xC4 // ResetCommand
-#define FCH_PMIOA_REGC5 0xC5 // CF9Shadow
-#define FCH_PMIOA_REGC6 0xC6 // HTControl
-#define FCH_PMIOA_REGC8 0xC8 // Misc
-#define FCH_PMIOA_REGCC 0xCC // IoDrvSth
-#define FCH_PMIOA_REGD0 0xD0 // CLKRunEn
-#define FCH_PMIOA_REGD2 0xD2 // PmioDebug
-#define FCH_PMIOA_REGD3 0xD3 // SD
-#define FCH_PMIOA_REGD6 0xD6 // IMCGating
-#define FCH_PMIOA_REGD8 0xD8 // MiscIndex
-#define FCH_PMIOA_REGD9 0xD9 // MiscData
-#define FCH_PMIOA_REGDA 0xDA // SataConfig
-#define FCH_PMIOA_REGDC 0xDC // HyperFlashConfig
-#define FCH_PMIOA_REGDE 0xDE // ABConfig
-#define FCH_PMIOA_REGE0 0xE0 // ABRegBar
-#define FCH_PMIOA_REGE6 0xE6 // FcEn
-#define FCH_PMIOA_REGE7 0xE7
-#define FCH_PMIOA_REGEA 0xEA // PcibConfig
-#define FCH_PMIOA_REGEB 0xEB // AzEn
-#define FCH_PMIOA_REGEC 0xEC // LpcGating
-#define FCH_PMIOA_REGED 0xED // UsbGating
-#define FCH_PMIOA_REGEE 0xEE // UsbCntrl
-#define FCH_PMIOA_REGEF 0xEF // UsbEnable
-#define FCH_PMIOA_REGF0 0xF0 // UsbControl
-#define FCH_PMIOA_REGF3 0xF3 // UsbDebug
-#define FCH_PMIOA_REGF6 0xF6 // GecEn
-#define FCH_PMIOA_REGF8 0xF8 // GecConfig
-#define FCH_PMIOA_REGFC 0xFC // TraceMemoryEn
-
-//
-// FCH MMIO Base (PMIO2)
-// offset : 0x400
-//
-#define FCH_PMIO2_REG00 0x00 // Fan0InputControl
-#define FCH_PMIO2_REG01 0x01 // Fan0Control
-#define FCH_PMIO2_REG02 0x02 // Fan0Freq
-#define FCH_PMIO2_REG03 0x03 // LowDuty0
-#define FCH_PMIO2_REG04 0x04 // MidDuty0
-
-#define FCH_PMIO2_REG10 0x00 // Fan1InputControl
-#define FCH_PMIO2_REG11 0x01 // Fan1Control
-#define FCH_PMIO2_REG12 0x02 // Fan1Freq
-#define FCH_PMIO2_REG13 0x03 // LowDuty1
-#define FCH_PMIO2_REG14 0x04 // MidDuty1
-
-#define FCH_PMIO2_REG63 0x63 // SampleFreqDiv
-#define FCH_PMIO2_REG69 0x69 // Fan0 Speed
-#define FCH_PMIO2_REG95 0x95 // Temperature
-#define FCH_PMIO2_REGB8 0xB8 // Voltage
-#define FCH_PMIO2_REGEA 0xEA // Hwm_Calibration
-
-#define FCH_PMIO2_REG92 0x92 //
-#define FCH_PMIO2_REGF8 0xF8 // VoltageSamleSel
-#define FCH_PMIO2_REGF9 0xF9 // TempSampleSel
-
-#define FCH_PMIO2_REG 0xFC // TraceMemoryEn
-
-
-//
-// FCH MMIO Base (GPIO/IoMux)
-// offset : 0x100/0xD00
-//
-/*
-GPIO from 0 ~ 67, (GEVENT 0-23) 128 ~ 150, 160 ~ 226.
-*/
-#define FCH_GPIO_REG00 0x00
-#define FCH_GPIO_REG06 0x06
-#define FCH_GPIO_REG09 0x09
-#define FCH_GPIO_REG10 0x0A
-#define FCH_GPIO_REG17 0x11
-#define FCH_GPIO_REG21 0x15
-#define FCH_GPIO_REG28 0x1C
-#define FCH_GPIO_REG32 0x20
-#define FCH_GPIO_REG33 0x21
-#define FCH_GPIO_REG34 0x22
-#define FCH_GPIO_REG35 0x23
-#define FCH_GPIO_REG36 0x24
-#define FCH_GPIO_REG37 0x25
-#define FCH_GPIO_REG38 0x26
-#define FCH_GPIO_REG39 0x27
-#define FCH_GPIO_REG40 0x28
-#define FCH_GPIO_REG41 0x29
-#define FCH_GPIO_REG42 0x2A
-#define FCH_GPIO_REG43 0x2B
-#define FCH_GPIO_REG44 0x2C
-#define FCH_GPIO_REG45 0x2D
-#define FCH_GPIO_REG46 0x2E
-#define FCH_GPIO_REG47 0x2F
-#define FCH_GPIO_REG48 0x30
-#define FCH_GPIO_REG49 0x31
-#define FCH_GPIO_REG50 0x32
-#define FCH_GPIO_REG51 0x33
-#define FCH_GPIO_REG52 0x34
-#define FCH_GPIO_REG53 0x35
-#define FCH_GPIO_REG54 0x36
-#define FCH_GPIO_REG55 0x37
-#define FCH_GPIO_REG56 0x38
-#define FCH_GPIO_REG57 0x39
-#define FCH_GPIO_REG58 0x3A
-#define FCH_GPIO_REG59 0x3B
-#define FCH_GPIO_REG60 0x3C
-#define FCH_GPIO_REG61 0x3D
-#define FCH_GPIO_REG62 0x3E
-#define FCH_GPIO_REG63 0x3F
-#define FCH_GPIO_REG64 0x40
-#define FCH_GPIO_REG65 0x41
-#define FCH_GPIO_REG66 0x42
-#define FCH_GPIO_REG67 0x43
-
-#define FCH_GEVENT_REG00 0x60
-#define FCH_GEVENT_REG01 0x61
-#define FCH_GEVENT_REG02 0x62
-#define FCH_GEVENT_REG03 0x63
-#define FCH_GEVENT_REG04 0x64
-#define FCH_GEVENT_REG05 0x65
-#define FCH_GEVENT_REG06 0x66
-#define FCH_GEVENT_REG07 0x67
-#define FCH_GEVENT_REG08 0x68
-#define FCH_GEVENT_REG09 0x69
-#define FCH_GEVENT_REG10 0x6A
-#define FCH_GEVENT_REG11 0x6B
-#define FCH_GEVENT_REG12 0x6C
-#define FCH_GEVENT_REG13 0x6D
-#define FCH_GEVENT_REG14 0x6E
-#define FCH_GEVENT_REG15 0x6F
-#define FCH_GEVENT_REG16 0x70
-#define FCH_GEVENT_REG17 0x71
-#define FCH_GEVENT_REG18 0x72
-#define FCH_GEVENT_REG19 0x73
-#define FCH_GEVENT_REG20 0x74
-#define FCH_GEVENT_REG21 0x75
-#define FCH_GEVENT_REG22 0x76
-#define FCH_GEVENT_REG23 0x77
-// S5-DOMAIN GPIO
-#define FCH_GPIO_REG160 0xA0
-#define FCH_GPIO_REG161 0xA1
-#define FCH_GPIO_REG162 0xA2
-#define FCH_GPIO_REG163 0xA3
-#define FCH_GPIO_REG164 0xA4
-#define FCH_GPIO_REG165 0xA5
-#define FCH_GPIO_REG166 0xA6
-#define FCH_GPIO_REG167 0xA7
-#define FCH_GPIO_REG168 0xA8
-#define FCH_GPIO_REG169 0xA9
-#define FCH_GPIO_REG170 0xAA
-#define FCH_GPIO_REG171 0xAB
-#define FCH_GPIO_REG172 0xAC
-#define FCH_GPIO_REG173 0xAD
-#define FCH_GPIO_REG174 0xAE
-#define FCH_GPIO_REG175 0xAF
-#define FCH_GPIO_REG176 0xB0
-#define FCH_GPIO_REG177 0xB1
-#define FCH_GPIO_REG178 0xB2
-#define FCH_GPIO_REG179 0xB3
-#define FCH_GPIO_REG180 0xB4
-#define FCH_GPIO_REG181 0xB5
-#define FCH_GPIO_REG182 0xB6
-#define FCH_GPIO_REG183 0xB7
-#define FCH_GPIO_REG184 0xB8
-#define FCH_GPIO_REG185 0xB9
-#define FCH_GPIO_REG186 0xBA
-#define FCH_GPIO_REG187 0xBB
-#define FCH_GPIO_REG188 0xBC
-#define FCH_GPIO_REG189 0xBD
-#define FCH_GPIO_REG190 0xBE
-#define FCH_GPIO_REG191 0xBF
-#define FCH_GPIO_REG192 0xC0
-#define FCH_GPIO_REG193 0xC1
-#define FCH_GPIO_REG194 0xC2
-#define FCH_GPIO_REG195 0xC3
-#define FCH_GPIO_REG196 0xC4
-#define FCH_GPIO_REG197 0xC5
-#define FCH_GPIO_REG198 0xC6
-#define FCH_GPIO_REG199 0xC7
-#define FCH_GPIO_REG200 0xC8
-#define FCH_GPIO_REG201 0xC9
-#define FCH_GPIO_REG202 0xCA
-#define FCH_GPIO_REG203 0xCB
-#define FCH_GPIO_REG204 0xCC
-#define FCH_GPIO_REG205 0xCD
-#define FCH_GPIO_REG206 0xCE
-#define FCH_GPIO_REG207 0xCF
-#define FCH_GPIO_REG208 0xD0
-#define FCH_GPIO_REG209 0xD1
-#define FCH_GPIO_REG210 0xD2
-#define FCH_GPIO_REG211 0xD3
-#define FCH_GPIO_REG212 0xD4
-#define FCH_GPIO_REG213 0xD5
-#define FCH_GPIO_REG214 0xD6
-#define FCH_GPIO_REG215 0xD7
-#define FCH_GPIO_REG216 0xD8
-#define FCH_GPIO_REG217 0xD9
-#define FCH_GPIO_REG218 0xDA
-#define FCH_GPIO_REG219 0xDB
-#define FCH_GPIO_REG220 0xDC
-#define FCH_GPIO_REG221 0xDD
-#define FCH_GPIO_REG222 0xDE
-#define FCH_GPIO_REG223 0xDF
-#define FCH_GPIO_REG224 0xF0
-#define FCH_GPIO_REG225 0xF1
-#define FCH_GPIO_REG226 0xF2
-#define FCH_GPIO_REG227 0xF3
-#define FCH_GPIO_REG228 0xF4
-
-//
-// FCH MMIO Base (SMBUS)
-// offset : 0xA00
-//
-#define FCH_SMBUS_REG12 0x12 // I2CbusConfig
-
-//
-// FCH MMIO Base (MISC)
-// offset : 0xE00
-//
-#define FCH_MISC_REG00 0x00 // ClkCntrl0
-/*
-FCH_MISC_REG00 EQU 000h
- ClkCntrl0 EQU 0FFFFFFFFh
-*/
-#define FCH_MISC_REG04 0x04 // ClkCntrl1
-/*
-FCH_MISC_REG04 EQU 004h
- ClkCntrl1 EQU 0FFFFFFFFh
-*/
-#define FCH_MISC_REG08 0x08 // ClkCntrl2
-/*
-FCH_MISC_REG08 EQU 008h
- ClkCntrl2 EQU 0FFFFFFFFh
-*/
-#define FCH_MISC_REG0C 0x0C // ClkCntrl3
-/*
-FCH_MISC_REG0C EQU 00Ch
- ClkCntrl3 EQU 0FFFFFFFFh
-*/
-#define FCH_MISC_REG10 0x10 // ClkCntrl4
-/*
-FCH_MISC_REG10 EQU 010h
- ClkCntrl4 EQU 0FFFFFFFFh
-*/
-#define FCH_MISC_REG14 0x14 // ClkCntrl5
-/*
-FCH_MISC_REG14 EQU 014h
- ClkCntrl5 EQU 0FFFFFFFFh
-*/
-#define FCH_MISC_REG18 0x18 // ClkCntrl6
-/*
-FCH_MISC_REG18 EQU 018h
- ClkCntrl6 EQU 0FFFFFFFFh
-*/
-#define FCH_MISC_REG30 0x30 // OscFreqCounter
-/*
-FCH_MISC_REG30 EQU 030h
- OscCounter EQU 0FFFFFFFFh ; The 32bit register shows the number of OSC clock per second.
-*/
-#define FCH_MISC_REG34 0x34 // HpetClkPeriod
-/*
-FCH_MISC_REG34 EQU 034h
- HpetClkPeriod EQU 0FFFFFFFFh ; default - 0x429B17Eh (14.31818M).
-*/
-#define FCH_MISC_REG40 0x40 // MiscCntrl for clock only
-#define FCH_MISC_REG41 0x41 // MiscCntr2
-#define FCH_MISC_REG42 0x42 // MiscCntr3
-#define FCH_MISC_REG50 0x50 //
-/*
-FCH_MISC_REG40 EQU 040h
-*/
-
-#define FCH_MISC_REG80 0x80 /**< FCH_MISC_REG80
- * @par
- * StrapStatus [15.0] - FCH chip Strap Status
- * @li <b>0001</b> - Not USED FWH
- * @li <b>0002</b> - Not USED LPC ROM
- * @li <b>0004</b> - EC enabled
- * @li <b>0008</b> - Reserved
- * @li <b>0010</b> - Internal Clock mode
- */
-#define FCH_MISC_REGB6 0xB6 //
-
-#define ChipSysNotUseFWHRom 0x0001 // EcPwm3 pad
-#define ChipSysNotUseLpcRom 0x0002 // Inverted version from EcPwm2 pad (default - 1)
- // Note: Both EcPwm3 and EcPwm2 straps pins are used to select boot ROM type.
-#define ChipSysEcEnable 0x0004 // Enable Embedded Controller (EC)
-#define ChipSysBootFailTmrEn 0x0008 // Enable Watchdog function
-#define ChipSysIntClkGen 0x0010 // Select 25Mhz crystal clock or 100Mhz PCI-E clock **
-
-#define FCH_MISC_REG84 0x84 // StrapOverride
-/*
-FCH_MISC_REG84 EQU 084h
- Override FWHDisableStrap EQU BIT0 ; Override FWHDiableStrap value from external pin.
- Override UseLpcRomStrap EQU BIT1 ; Override UseLpcRomStrap value from external pin.
- Override EcEnableStrap EQU BIT2 ; Override EcEnableStrap value from external pin.
- Override BootFailTmrEnStrap EQU BIT3 ; Override BootFailTmrEnStrap value from external pin.
- Override DefaultModeStrap EQU BIT5 ; Override DefaultModeStrap value from external pin.
- Override I2CRomStrap EQU BIT7 ; Override I2CRomStrap value from external pin.
- Override ILAAutorunEnBStrap EQU BIT8 ; Override ILAAutorunEnBStrap value from external pin.
- Override FcPllBypStrap EQU BIT9 ; Override FcPllBypStrap value from external pin.
- Override PciPllBypStrap EQU BIT10 ; Override PciPllBypStrap value from external pin.
- Override ShortResetStrap EQU BIT11 ; Override ShortResetStrap value from external pin.
- Override FastBif2ClkStrap EQU BIT13 ; Override FastBif2ClkStrap value from external pin
- PciRomBootStrap EQU BIT15 ; Override PCI Rom Boot Strap value from external pin
- BlinkSlowModestrap EQU BIT16 ; Override Blink Slow mode (100Mhz) from external pin
- ClkGenStrap EQU BIT17 ; Override CLKGEN from external pin.
- BIF_GEN2_COMPL_Strap EQU BIT18 ; Override BIF_ GEN2_COMPLIANCE strap from external pin.
- StrapOverrideEn EQU BIT31 ; Enable override strapping feature.
-*/
-#define FCH_MISC_REGC0 0xC0 // CPU_Pstate0
-/*
-FCH_MISC_REGC0 EQU 0C0h
- Core0_PState EQU BIT0+BIT1+BIT2 ; 000: P0 001: P1 010: P2 011: P3 100: P4 101: P5 110: P6 111: P7
- Core1_PState EQU BIT4+BIT5+BIT6
- Core2_PState EQU BIT8+BIT9+BIT10
- Core3_PState EQU BIT12+BIT13+BIT14
- Core4_PState EQU BIT16++BIT17+BIT18
- Core5_PState EQU BIT20+BIT21+BIT22
- Core6_PState EQU BIT24+BIT25+BIT26
- Core7_PState EQU BIT28+BIT29+BIT30
-*/
-#define FCH_MISC_REGC4 0xC4 // CPU_Pstate1
-/*
-FCH_MISC_REGC4 EQU 0C4h
- Core8_PState EQU BIT0+BIT1+BIT2 ; 000: P0 001: P1 010: P2 011: P3 100: P4 101: P5 110: P6 111: P7
- Core9_PState EQU BIT4+BIT5+BIT6
- Core10_PState EQU BIT8+BIT9+BIT10
- Core11_PState EQU BIT12+BIT13+BIT14
- Core12_PState EQU BIT16++BIT17+BIT18
- Core13_PState EQU BIT20+BIT21+BIT22
- Core14_PState EQU BIT24+BIT25+BIT26
- Core15_PState EQU BIT28+BIT29+BIT30
-*/
-#define FCH_MISC_REGD0 0xD0 // CPU_Cstate0
-/*
-FCH_MISC_REGD0 EQU 0D0h
- Core0_CState EQU BIT0+BIT1+BIT2 ; 000: C0 001: C1 010: C2 011: C3 100: C4 101: C5 110: C6 111: C7
- Core1_CState EQU BIT4+BIT5+BIT6
- Core2_CState EQU BIT8+BIT9+BIT10
- Core3_CState EQU BIT12+BIT13+BIT14
- Core4_CState EQU BIT16++BIT17+BIT18
- Core5_CState EQU BIT20+BIT21+BIT22
- Core6_CState EQU BIT24+BIT25+BIT26
- Core7_CState EQU BIT28+BIT29+BIT30
-*/
-#define FCH_MISC_REGD4 0xD4 // CPU_Cstate1
-/*
-FCH_MISC_REGD4 EQU 0D4h
- Core8_CState EQU BIT0+BIT1+BIT2 ; 000: C0 001: C1 010: C2 011: C3 100: C4 101: C5 110: C6 111: C7
- Core9_CState EQU BIT4+BIT5+BIT6
- Core10_CState EQU BIT8+BIT9+BIT10
- Core11_CState EQU BIT12+BIT13+BIT14
- Core12_CState EQU BIT16++BIT17+BIT18
- Core13_CState EQU BIT20+BIT21+BIT22
- Core14_CState EQU BIT24+BIT25+BIT26
- Core15_CState EQU BIT28+BIT29+BIT30
-*/
-#define FCH_MISC_REGF0 0xF0 // SataPortSts
-/*
-FCH_MISC_REGF0 EQU 0F0h
- Port0Sts EQU BIT0 ; The selected status of Port 0.
- Port1Sts EQU BIT1 ; The selected status of Port 1
- Port2Sts EQU BIT2 ; The selected status of Port 2.
- Port3Sts EQU BIT3 ; The selected status of Port 3
- Port4Sts EQU BIT4 ; The selected status of Port 4.
- Port5Sts EQU BIT5 ; The selected status of Port 5
- SataPortSel EQU BIT24+BIT25 ; 00 - Select "led" for Port 0 to 5
- ; 01 - Select "delete" for Port 0 to 5
- ; 10 - Select "err" for Port 0 to 5
- ; 11 - Select "led" for Port 0 to 5
-*/
-
-//
-// FCH MMIO Base (SERIAL_DEBUG_BASE)
-// offset : 0x1000
-//
-#define FCH_SDB_REG00 0x00 //
-#define FCH_SDB_REG74 0x74
-
-#define FCH_RTC_REG00 0x00 // Seconds - RW
-#define FCH_RTC_REG01 0x01 // Seconds Alarm - RW
-#define FCH_RTC_REG02 0x02 // Minutes - RW
-#define FCH_RTC_REG03 0x03 // Minutes Alarm - RW
-#define FCH_RTC_REG04 0x04 // ours - RW
-#define FCH_RTC_REG05 0x05 // ours Alarm- RW
-#define FCH_RTC_REG06 0x06 // Day of Week - RW
-#define FCH_RTC_REG07 0x07 // Date of Mont - RW
-#define FCH_RTC_REG08 0x08 // Mont - RW
-#define FCH_RTC_REG09 0x09 // Year - RW
-#define FCH_RTC_REG0A 0x0A // Register A - RW
-#define FCH_RTC_REG0B 0x0B // Register B - RW
-#define FCH_RTC_REG0C 0x0C // Register C - R
-#define FCH_RTC_REG0D 0x0D // DateAlarm - RW
-#define FCH_RTC_REG32 0x32 // AltCentury - RW
-#define FCH_RTC_REG48 0x48 // Century - RW
-#define FCH_RTC_REG50 0x50 // Extended RAM Address Port - RW
-#define FCH_RTC_REG53 0x53 // Extended RAM Data Port - RW
-#define FCH_RTC_REG7E 0x7E // RTC Time Clear - RW
-#define FCH_RTC_REG7F 0x7F // RTC RAM Enable - RW
-
-#define FCH_ECMOS_REG00 0x00 // scratch - reg
-//;BIT0=0 AsicDebug is enabled
-//;BIT1=0 SLT S3 runs
-#define FCH_ECMOS_REG01 0x01
-#define FCH_ECMOS_REG02 0x02
-#define FCH_ECMOS_REG03 0x03
-#define FCH_ECMOS_REG04 0x04
-#define FCH_ECMOS_REG05 0x05
-#define FCH_ECMOS_REG06 0x06
-#define FCH_ECMOS_REG07 0x07
-#define FCH_ECMOS_REG08 0x08 // save 32BIT Physical address of Config structure
-#define FCH_ECMOS_REG09 0x09
-#define FCH_ECMOS_REG0A 0x0A
-#define FCH_ECMOS_REG0B 0x0B
-
-#define FCH_ECMOS_REG0C 0x0C //;save MODULE_ID
-#define FCH_ECMOS_REG0D 0x0D //;Reserve for NB
-
-#define FCH_IOMAP_REG00 0x000 // Dma_C 0
-#define FCH_IOMAP_REG02 0x002 // Dma_C 1
-#define FCH_IOMAP_REG04 0x004 // Dma_C 2
-#define FCH_IOMAP_REG06 0x006 // Dma_C 3
-#define FCH_IOMAP_REG08 0x008 // Dma_Status
-#define FCH_IOMAP_REG09 0x009 // Dma_WriteRest
-#define FCH_IOMAP_REG0A 0x00A // Dma_WriteMask
-#define FCH_IOMAP_REG0B 0x00B // Dma_WriteMode
-#define FCH_IOMAP_REG0C 0x00C // Dma_Clear
-#define FCH_IOMAP_REG0D 0x00D // Dma_MasterClr
-#define FCH_IOMAP_REG0E 0x00E // Dma_ClrMask
-#define FCH_IOMAP_REG0F 0x00F // Dma_AllMask
-#define FCH_IOMAP_REG20 0x020 // IntrCntrlReg1
-#define FCH_IOMAP_REG21 0x021 // IntrCntrlReg2
-#define FCH_IOMAP_REG40 0x040 // TimerC0
-#define FCH_IOMAP_REG41 0x041 // TimerC1
-#define FCH_IOMAP_REG42 0x042 // TimerC2
-#define FCH_IOMAP_REG43 0x043 // Tmr1CntrlWord
-#define FCH_IOMAP_REG61 0x061 // Nmi_Status
-#define FCH_IOMAP_REG70 0x070 // Nmi_Enable
-#define FCH_IOMAP_REG71 0x071 // RtcDataPort
-#define FCH_IOMAP_REG72 0x072 // AlternatRtcAddrPort
-#define FCH_IOMAP_REG73 0x073 // AlternatRtcDataPort
-#define FCH_IOMAP_REG80 0x080 // Dma_Page_Reserved0
-#define FCH_IOMAP_REG81 0x081 // Dma_PageC2
-#define FCH_IOMAP_REG82 0x082 // Dma_PageC3
-#define FCH_IOMAP_REG83 0x083 // Dma_PageC1
-#define FCH_IOMAP_REG84 0x084 // Dma_Page_Reserved1
-#define FCH_IOMAP_REG85 0x085 // Dma_Page_Reserved2
-#define FCH_IOMAP_REG86 0x086 // Dma_Page_Reserved3
-#define FCH_IOMAP_REG87 0x087 // Dma_PageC0
-#define FCH_IOMAP_REG88 0x088 // Dma_Page_Reserved4
-#define FCH_IOMAP_REG89 0x089 // Dma_PageC6
-#define FCH_IOMAP_REG8A 0x08A // Dma_PageC7
-#define FCH_IOMAP_REG8B 0x08B // Dma_PageC5
-#define FCH_IOMAP_REG8C 0x08C // Dma_Page_Reserved5
-#define FCH_IOMAP_REG8D 0x08D // Dma_Page_Reserved6
-#define FCH_IOMAP_REG8E 0x08E // Dma_Page_Reserved7
-#define FCH_IOMAP_REG8F 0x08F // Dma_Refres
-#define FCH_IOMAP_REG92 0x092 // FastInit
-#define FCH_IOMAP_REGA0 0x0A0 // IntrCntrl2Reg1
-#define FCH_IOMAP_REGA1 0x0A1 // IntrCntrl2Reg2
-#define FCH_IOMAP_REGC0 0x0C0 // Dma2_C4Addr
-#define FCH_IOMAP_REGC2 0x0C2 // Dma2_C4Cnt
-#define FCH_IOMAP_REGC4 0x0C4 // Dma2_C5Addr
-#define FCH_IOMAP_REGC6 0x0C6 // Dma2_C5Cnt
-#define FCH_IOMAP_REGC8 0x0C8 // Dma2_C6Addr
-#define FCH_IOMAP_REGCA 0x0CA // Dma2_C6Cnt
-#define FCH_IOMAP_REGCC 0x0CC // Dma2_C7Addr
-#define FCH_IOMAP_REGCE 0x0CE // Dma2_C7Cnt
-#define FCH_IOMAP_REGD0 0x0D0 // Dma_Status
-#define FCH_IOMAP_REGD2 0x0D2 // Dma_WriteRest
-#define FCH_IOMAP_REGD4 0x0D4 // Dma_WriteMask
-#define FCH_IOMAP_REGD6 0x0D6 // Dma_WriteMode
-#define FCH_IOMAP_REGD8 0x0D8 // Dma_Clear
-#define FCH_IOMAP_REGDA 0x0DA // Dma_Clear
-#define FCH_IOMAP_REGDC 0x0DC // Dma_ClrMask
-#define FCH_IOMAP_REGDE 0x0DE // Dma_ClrMask
-#define FCH_IOMAP_REGF0 0x0F0 // NCP_Error
-#define FCH_IOMAP_REG40B 0x040B // DMA1_Extend
-#define FCH_IOMAP_REG4D0 0x04D0 // IntrEdgeControl
-#define FCH_IOMAP_REG4D6 0x04D6 // DMA2_Extend
-#define FCH_IOMAP_REGC00 0x0C00 // Pci_Intr_Index
-#define FCH_IOMAP_REGC01 0x0C01 // Pci_Intr_Data
-#define FCH_IOMAP_REGC14 0x0C14 // Pci_Error
-#define FCH_IOMAP_REGC50 0x0C50 // CMIndex
-#define FCH_IOMAP_REGC51 0x0C51 // CMData
-#define FCH_IOMAP_REGC52 0x0C52 // GpmPort
-#define FCH_IOMAP_REGC6F 0x0C6F // Isa_Misc
-#define FCH_IOMAP_REGCD0 0x0CD0 // PMio2_Index
-#define FCH_IOMAP_REGCD1 0x0CD1 // PMio2_Data
-#define FCH_IOMAP_REGCD4 0x0CD4 // BIOSRAM_Index
-#define FCH_IOMAP_REGCD5 0x0CD5 // BIOSRAM_Data
-#define FCH_IOMAP_REGCD6 0x0CD6 // PM_Index
-#define FCH_IOMAP_REGCD7 0x0CD7 // PM_Data
-#define FCH_IOMAP_REGCF9 0x0CF9 // CF9Rst reg
-
-
-#define FCH_SPI_MMIO_REG00 0x00 //SPI_
-#define FCH_SPI_MMIO_REG0C 0x0C //SPI_Cntrl1 Register
-#define FCH_SPI_MMIO_REG1C 0x1C //
-
-#define FCH_SPI_MODE_FAST 0x7 //
-#define FCH_SPI_MODE_NORMAL 0x6 //
-#define FCH_SPI_MODE_QUAL_144 0x5 //
-#define FCH_SPI_MODE_QUAL_122 0x4 //
-#define FCH_SPI_MODE_QUAL_114 0x3 //
-#define FCH_SPI_MODE_QUAL_112 0x2 //
-
-#define AMD_NB_REG78 0x78
-#define AMD_NB_SCRATCH AMD_NB_REG78
-#define MailBoxPort 0x3E
-
-#define MAX_LT_POLLINGS 0x4000
-
-
-#define ACPIMMIO32(x) (*(UINT32*)(UINTN)(x))
-#define ACPIMMIO16(x) (*(UINT16*)(UINTN)(x))
-#define ACPIMMIO8(x) (*(UINT8*)(UINTN)(x))
-
-#define XHCI_ACPI_MMIO_AMD_REG00 0x00
-#define U3PLL_LOCK BIT7
-#define U3PLL_RESET BIT8
-#define U3PHY_RESET BIT9
-#define U3CORE_RESET BIT10
-#define XHC0_FUNC_RESET BIT11
-#define XHC1_FUNC_RESET BIT12
-
-#define XHCI_ACPI_MMIO_AMD_REG04 0x04
-#define XHCI_ACPI_MMIO_AMD_REG08 0x08
-#define XHCI_ACPI_MMIO_AMD_REG20 0x20
-#define XHCI_ACPI_MMIO_AMD_REG90 0x90 // adaptation timer settings
-#define XHCI_ACPI_MMIO_AMD_REG98 0x98
-#define XHCI_ACPI_MMIO_AMD_REGA0 0xA0 // BAR 0
-#define XHCI_ACPI_MMIO_AMD_REGA4 0xA4 // BAR 1
-#define XHCI_ACPI_MMIO_AMD_REGA8 0xA8 // BAR 2
-#define XHCI_ACPI_MMIO_AMD_REGB0 0xB0 // SPI_Valid_Base.
-#define XHCI_ACPI_MMIO_AMD_REGC0 0xC0 // Firmware starting offset for coping
-#define XHCI_ACPI_MMIO_AMD_REGB4 0xB4
-#define XHCI_ACPI_MMIO_AMD_REGD0 0xD0
-
-#define FCH_XHCI_REG48 0x48 // XHCI IND_REG Index registers
-#define FCH_XHCI_REG4C 0x4C // XHCI IND_REG Data registers
-
-#define FCH_XHCI_IND60_BASE 0x40000000 //
-
-#define FCH_XHCI_IND60_REG00 FCH_XHCI_IND60_BASE + 0x00 //
-#define FCH_XHCI_IND60_REG04 FCH_XHCI_IND60_BASE + 0x04 //
-#define FCH_XHCI_IND60_REG08 FCH_XHCI_IND60_BASE + 0x08 //
-#define FCH_XHCI_IND60_REG0C FCH_XHCI_IND60_BASE + 0x0C //
-
-
-#define FCH_XHCI_IND_REG00 0x00 //
-#define FCH_XHCI_IND_REG04 0x04 //
-#define FCH_XHCI_IND_REG94 0x94 // adaptation mode settings
-#define FCH_XHCI_IND_REG98 0x98 // CR phase and frequency filter settings
-#define FCH_XHCI_IND_REGD4 0xD4 // adaptation mode settings
-#define FCH_XHCI_IND_REGD8 0xD8 // CR phase and frequency filter settings
-
-#define SPI_HEAD_LENGTH 0x0E
-#define SPI_BAR0_VLD 0x01
-#define SPI_BASE0 (0x00 << 7)
-#define SPI_BAR1_VLD (0x01 << 8)
-#define SPI_BASE1 (SPI_HEAD_LENGTH << 10)
-#define SPI_BAR2_VLD (0x01 << 16)
-#define SPI_BASE2(x) ((SPI_HEAD_LENGTH + ACPIMMIO16(x)) << 18)
-
-#define FW_TO_SIGADDR_OFFSET 0x0C
-#define BCD_ADDR_OFFSET 0x02
-#define BCD_SIZE_OFFSET 0x04
-#define FW_ADDR_OFFSET 0x06
-#define FW_SIZE_OFFSET 0x08
-#define ACD_ADDR_OFFSET 0x0A
-#define ACD_SIZE_OFFSET 0x0C
-
-#define PKT_DATA_REG ACPI_MMIO_BASE + GFX_DAC_BASE + 0x00
-#define PKT_LEN_REG ACPI_MMIO_BASE + GFX_DAC_BASE + 0x14
-#define PKT_CTRL_REG ACPI_MMIO_BASE + GFX_DAC_BASE + 0x15
-#define EFUS_DAC_ADJUSTMENT_CONTROL 0x850A8
-#define BGADJ 0x1F
-#define DACADJ 0x1B
-#define EFUS_DAC_ADJUSTMENT_CONTROL_DATA (BGADJ + (DACADJ << 8) + BIT16 )
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/FchPlatform.h b/src/vendorcode/amd/agesa/f12/Proc/Fch/FchPlatform.h
deleted file mode 100644
index edfbfe94b2..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/FchPlatform.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * FCH platform definition
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 48055 $ @e \$Date: 2011-03-03 10:33:13 +0800 (Thu, 03 Mar 2011) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#ifndef _FCH_PLATFORM_H_
-#define _FCH_PLATFORM_H_
-
-#define MAX_SATA_PORTS 8
-
-#include "AGESA.h"
-
-#ifndef FCHOEM_ACPI_RESTORE_SWSMI
- #define FCHOEM_BEFORE_PCI_RESTORE_SWSMI 0xD3
- #define FCHOEM_AFTER_PCI_RESTORE_SWSMI 0xD4
- #define FCHOEM_ENABLE_ACPI_SWSMI 0xA0
- #define FCHOEM_DISABLE_ACPI_SWSMI 0xA1
-#endif
-
-#ifndef FCHOEM_SPI_UNLOCK_SWSMI
- #define FCHOEM_SPI_UNLOCK_SWSMI 0xAA
-#endif
-#ifndef FCHOEM_SPI_LOCK_SWSMI
- #define FCHOEM_SPI_LOCK_SWSMI 0xAB
-#endif
-
-#ifndef FCHOEM_ACPI_TABLE_RANGE_LOW
- #define FCHOEM_ACPI_TABLE_RANGE_LOW 0xE0000
-#endif
-
-#ifndef FCHOEM_ACPI_TABLE_RANGE_HIGH
- #define FCHOEM_ACPI_TABLE_RANGE_HIGH 0xFFFF0
-#endif
-
-#ifndef FCHOEM_ACPI_BYTE_CHECHSUM
- #define FCHOEM_ACPI_BYTE_CHECHSUM 0x100
-#endif
-
-#ifndef FCHOEM_IO_DELAY_PORT
- #define FCHOEM_IO_DELAY_PORT 0x80
-#endif
-
-#ifndef FCHOEM_OUTPUT_DEBUG_PORT
- #define FCHOEM_OUTPUT_DEBUG_PORT 0x80
-#endif
-
-#define FCH_PCIRST_BASE_IO 0xCF9
-#define FCH_PCI_RESET_COMMAND06 0x06
-#define FCH_PCI_RESET_COMMAND0E 0x0E
-#define FCH_KBDRST_BASE_IO 0x64
-#define FCH_KBC_RESET_COMMAND 0xFE
-#define FCH_ROMSIG_BASE_IO 0x20000
-#define FCH_ROMSIG_SIGNATURE 0x55AA55AA
-#define FCH_MAX_TIMER 0xFFFFFFFF
-#define FCH_GEC_INTERNAL_REG 0x6804
-#define FCH_HPET_REG_MASK 0xFFFFF800
-#define FCH_FAKE_USB_BAR_ADDRESS 0x58830000
-
-
-#ifndef FCHOEM_ELAPSED_TIME_UNIT
- #define FCHOEM_ELAPSED_TIME_UNIT 28
-#endif
-
-#ifndef FCHOEM_ELAPSED_TIME_DIVIDER
- #define FCHOEM_ELAPSED_TIME_DIVIDER 100
-#endif
-
-#include "Fch.h"
-#include "amdlib.h"
-#include "FchCommonCfg.h"
-#include "AcpiLib.h"
-#include "FchDef.h"
-#include "OEM.h"
-#include "FchBiosRamUsage.h"
-#include "AmdFch.h"
-
-extern BUILD_OPT_CFG UserOptions;
-
-#endif // _FCH_PLATFORM_H_
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/Family/Hudson2/Hudson2GecEnvService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/Family/Hudson2/Hudson2GecEnvService.c
deleted file mode 100644
index aadb7bfb0b..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/Family/Hudson2/Hudson2GecEnvService.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config FCH GEC controller
- *
- * Init GEC features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 46088 $ @e \$Date: 2011-01-28 11:24:26 +0800 (Fri, 28 Jan 2011) $
- *
- */
-/*;********************************************************************************
-;
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*********************************************************************************/
-
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_GEC_FAMILY_HUDSON2_HUDSON2GECENVSERVICE_FILECODE
-
-/**
- * FchInitGecController - Config GEC controller
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitGecController (
- IN VOID *FchDataPtr
- )
-{
- UINT8 FchSBGecDebugBus;
- UINT8 FchSBGecPwr;
- FCH_DATA_BLOCK *LocalCfgPtr;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
-
- FchSBGecDebugBus = (UINT8) LocalCfgPtr->Gec.GecDebugBus;
- FchSBGecPwr = (UINT8) LocalCfgPtr->Gec.GecPowerPolicy;
-
- if ( LocalCfgPtr->Misc.Cg2Pll == 1 ) {
- LocalCfgPtr->Gec.GecEnable = 1;
- }
-
- if ( LocalCfgPtr->Gec.GecEnable == 0) {
- //
- // GEC Enabled
- //
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF6, AccessWidth8, ~BIT0, 0x00);
- } else {
- //
- // GEC Disabled
- //
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF6, AccessWidth8, ~BIT0, BIT0);
- //return; ///return if GEC controller is disabled.
- }
-
- RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GEVENT_REG11, AccessWidth8, 0, 0x00);
- RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GEVENT_REG21, AccessWidth8, 0, 0x01);
- RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG166, AccessWidth8, 0, 0x01);
- RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG181, AccessWidth8, 0, 0x01);
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF8, AccessWidth8, ~(BIT5 + BIT6), (UINT8) ((FchSBGecPwr) << 5));
-
- if ( FchSBGecDebugBus == 1) {
- //
- // GEC Debug Bus Enabled
- //
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF6, AccessWidth8, ~BIT3, BIT3);
- } else {
- //
- // GEC Debug Bus Disabled
- //
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF6, AccessWidth8, ~BIT3, 0x00);
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/Family/Hudson2/Hudson2GecService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/Family/Hudson2/Hudson2GecService.c
deleted file mode 100644
index c9dc253077..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/Family/Hudson2/Hudson2GecService.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config FCH GEC controller
- *
- * Init GEC features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*;********************************************************************************
-;
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*********************************************************************************/
-
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_GEC_FAMILY_HUDSON2_HUDSON2GECSERVICE_FILECODE
-
-/**
- * FchSwInitGecBootRom - Config GEC Boot ROM by Platform define
- * ROM address
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchSwInitGecBootRom (
- IN VOID *FchDataPtr
- )
-{
- VOID* GecRomAddress;
- VOID* GecShadowRomAddress;
- UINT32 Temp;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- if ( !LocalCfgPtr->Gec.PtrDynamicGecRomAddress == NULL ) {
- GecRomAddress = LocalCfgPtr->Gec.PtrDynamicGecRomAddress;
- GecShadowRomAddress = (VOID*) (UINTN) LocalCfgPtr->Gec.GecShadowRomBase;
- FchCopyMem (GecShadowRomAddress, GecRomAddress, 0x100);
- ReadPci ((GEC_BUS_DEV_FUN << 16) + FCH_GEC_REG10, AccessWidth32, &Temp, StdHeader);
- Temp = Temp & 0xFFFFFFF0;
- RwMem (Temp + FCH_GEC_INTERNAL_REG, AccessWidth32, 0, BIT0 + BIT29);
- }
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/GecEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/GecEnv.c
deleted file mode 100644
index 99a7287aa5..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/GecEnv.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config FCH GEC controller
- *
- * Init GEC features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*;********************************************************************************
-;
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*********************************************************************************/
-
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_GEC_GECENV_FILECODE
-
-extern VOID FchInitGecController (IN VOID* FchDataPtr);
-/**
- * FchInitEnvGec - Config GEC controller before PCI emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitEnvGec (
- IN VOID *FchDataPtr
- )
-{
- FchInitGecController (FchDataPtr);
-}
-
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/GecLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/GecLate.c
deleted file mode 100644
index fae66c1528..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/GecLate.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config FCH GEC controller
- *
- * Init GEC features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*;********************************************************************************
-;
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*********************************************************************************/
-
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_GEC_GECLATE_FILECODE
-
-/**
- * FchInitLateGec - Prepare GEC controller to boot to OS.
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitLateGec (
- IN VOID *FchDataPtr
- )
-{
-}
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/GecMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/GecMid.c
deleted file mode 100644
index 8188d824b2..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/GecMid.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config FCH GEC controller
- *
- * Init GEC features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*;********************************************************************************
-;
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*********************************************************************************/
-
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_GEC_GECMID_FILECODE
-
-extern VOID FchSwInitGecBootRom (IN VOID* FchDataPtr);
-
-/**
- * FchInitMidGec - Config GEC controller after PCI emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitMidGec (
- IN VOID *FchDataPtr
- )
-{
- FchSwInitGecBootRom (FchDataPtr);
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/GecReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/GecReset.c
deleted file mode 100644
index 78f15491c9..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/GecReset.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config FCH GEC controller
- *
- * Init Gec Controller features (PEI phase).
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_GEC_GECRESET_FILECODE
-
-/**
- * FchInitResetGec - Config Gec controller during Power-On
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitResetGec (
- IN VOID *FchDataPtr
- )
-{
- //
- // Init Gec SHADOW Rom Base Address
- //
- RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG9C, AccessWidth32, 0, \
- UserOptions.CfgGecShadowRomBase + 1, ((FCH_RESET_DATA_BLOCK *) FchDataPtr)->StdHeader);
-}
-
-/**
- * FchInitRecoveryGec - Config Gec controller during Crisis
- * Recovery
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitRecoveryGec (
- IN VOID *FchDataPtr
- )
-{
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c
deleted file mode 100644
index eec95c0a6d..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c
+++ /dev/null
@@ -1,505 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch HwAcpi controller
- *
- * Init HwAcpi Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 49633 $ @e \$Date: 2011-03-26 06:52:29 +0800 (Sat, 26 Mar 2011) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "amdlib.h"
-#include "cpuServices.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPIENVSERVICE_FILECODE
-
-#define AMD_CPUID_APICID_LPC_BID 0x00000001 // Local APIC ID, Logical Processor Count, Brand ID
-
-/**
- * FchInitEnvHwAcpiMmioTable - Fch ACPI MMIO initial
- * during POST.
- *
- */
-ACPI_REG_WRITE FchHudson2InitEnvHwAcpiMmioTable[] =
-{
- {00, 00, 0xB0, 0xAC}, /// Signature
-
- //
- // HPET workaround
- //
- {PMIO_BASE >> 8, FCH_PMIOA_REG54 + 3, 0xFC, BIT0 + BIT1},
- {PMIO_BASE >> 8, FCH_PMIOA_REG54 + 2, 0x7F, BIT7},
- {PMIO_BASE >> 8, FCH_PMIOA_REG54 + 2, 0x7F, 0x00},
- //
- // Enable Hudson-2 A12 ACPI bits at PMIO 0xC0 [30, 10:3]
- // ClrAllStsInThermalEvent 3 Set to 1 to allow ASF remote power down/power cycle, Thermal event, Fan slow event to clear all the Gevent status and enabled bits. The bit should be set to 1 all the time.
- // UsbGoodClkDlyEn 4 Set to 1 to delay de-assertion of Usb clk by 6 Osc clk. The bit should be set to 1 all the time.
- // ForceNBCPUPwr 5 Set to 1 to force CPU pwrGood to be toggled along with NB pwrGood.
- // MergeUsbPerReq 6 Set to 1 to merge usb perdical traffic into usb request as one of break event.
- // IMCWatchDogRstEn 7 Set to 1 to allow IMC watchdog timer to reset entire acpi block. The bit should be set to 1 when IMC is enabled.
- // GeventStsFixEn 8 1: Gevent status is not reset by its enable bit. 0: Gevent status is reset by its enable bit.
- // PmeTimerFixEn 9 Set to 1 to reset Pme Timer when going to sleep state.
- // UserRst2EcEn 10 Set to 1 to route user reset event to Ec. The bit should be set to 1 when IMC is enabled.
- // Smbus0ClkSEn 30 Set to 1 to enable SMBus0 controller clock stretch support.
- //
- {PMIO_BASE >> 8, FCH_PMIOA_REGC4, ~BIT2, BIT2},
- {PMIO_BASE >> 8, FCH_PMIOA_REGC0, 0, 0xF9},
- {PMIO_BASE >> 8, FCH_PMIOA_REGC0 + 1, 0x04, 0x07},
- //
- // RtcSts 19-17 RTC_STS set only in Sleep State.
- // GppPme 20 Set to 1 to enable PME request from SB GPP.
- // Pcireset 22 Set to 1 to allow SW to reset PCIe.
- //
- {PMIO_BASE >> 8, FCH_PMIOA_REGC2, 0x20, 0x58},
- {PMIO_BASE >> 8, FCH_PMIOA_REGC2 + 1, 0, 0x40},
- {PMIO_BASE >> 8, FCH_PMIOA_REGC2, ~(BIT4), BIT4},
-
- {PMIO_BASE >> 8, FCH_PMIOA_REGCC, 0xF8, 0x01},
- {PMIO_BASE >> 8, FCH_PMIOA_REG74, 0x00, BIT0 + BIT1 + BIT2 + BIT4},
- {PMIO_BASE >> 8, FCH_PMIOA_REG74 + 3, ~BIT5, 0},
- {PMIO_BASE >> 8, FCH_PMIOA_REGDE + 1, ~(BIT0 + BIT1), BIT0 + BIT1},
- {PMIO_BASE >> 8, FCH_PMIOA_REGDE, ~BIT4, BIT4},
- {PMIO_BASE >> 8, FCH_PMIOA_REGBA, ~BIT3, BIT3},
- {PMIO_BASE >> 8, FCH_PMIOA_REGBA + 1, ~BIT6, BIT6},
- {PMIO_BASE >> 8, FCH_PMIOA_REGBC, ~BIT1, BIT1},
- {PMIO_BASE >> 8, FCH_PMIOA_REGED, ~(BIT0 + BIT1), 0},
- {PMIO_BASE >> 8, FCH_PMIOA_REGDC, 0x7C, BIT0}, /// Hiding Flash Controller PM_IO 0xDC[7] = 0x0 & PM_IO 0xDC [1:0]=0x01
- {PMIO_BASE >> 8, FCH_PMIOA_REGBF, ~BIT0, 0},
- {PMIO_BASE >> 8, FCH_PMIOA_REGBE, ~BIT0, BIT0},
-
- {SMI_BASE >> 8, FCH_SMI_Gevent1, 0, 1},
- {SMI_BASE >> 8, FCH_SMI_Gevent3, 0, 3},
- {SMI_BASE >> 8, FCH_SMI_Gevent4, 0, 4},
- {SMI_BASE >> 8, FCH_SMI_Gevent5, 0, 5},
- {SMI_BASE >> 8, FCH_SMI_Gevent6, 0, 6},
- {SMI_BASE >> 8, FCH_SMI_Gevent23, 0, 23},
- {SMI_BASE >> 8, FCH_SMI_xHC0Pme, 0, 11},
- {SMI_BASE >> 8, FCH_SMI_xHC1Pme, 0, 11},
- {SMI_BASE >> 8, FCH_SMI_Usbwakup0, 0, 11},
- {SMI_BASE >> 8, FCH_SMI_Usbwakup1, 0, 11},
- {SMI_BASE >> 8, FCH_SMI_Usbwakup2, 0, 11},
- {SMI_BASE >> 8, FCH_SMI_Usbwakup3, 0, 11},
- {SMI_BASE >> 8, FCH_SMI_IMCGevent0, 0, 12},
- {SMI_BASE >> 8, FCH_SMI_FanThGevent, 0, 13},
- {SMI_BASE >> 8, FCH_SMI_SBGppPme0, 0, 15},
- {SMI_BASE >> 8, FCH_SMI_SBGppPme1, 0, 16},
- {SMI_BASE >> 8, FCH_SMI_SBGppPme2, 0, 17},
- {SMI_BASE >> 8, FCH_SMI_SBGppPme3, 0, 18},
- {SMI_BASE >> 8, FCH_SMI_GecPme, 0, 19},
- {SMI_BASE >> 8, FCH_SMI_CIRPme, 0, 28},
- {SMI_BASE >> 8, FCH_SMI_Gevent8, 0, 24},
- {SMI_BASE >> 8, FCH_SMI_AzaliaPme, 0, 27},
- {SMI_BASE >> 8, FCH_SMI_SataGevent0, 0, 30},
- {SMI_BASE >> 8, FCH_SMI_SataGevent1, 0, 31},
- {SMI_BASE >> 8, FCH_SMI_REG08, 0xE7, 0},
- {SMI_BASE >> 8, FCH_SMI_REG0C + 2, ~BIT3, BIT3},
- {SMI_BASE >> 8, FCH_SMI_TWARN, 0, 9},
- {SMI_BASE >> 8, FCH_SMI_REG3C, 0, BIT6},
- {SMI_BASE >> 8, FCH_SMI_REG84 + 2, 0, BIT7},
-
- //
- // CG PLL CMOX Clock Driver Setting for power saving
- //
- {MISC_BASE >> 8, FCH_MISC_REG18 + 0x06, 0, 0xE0},
- {MISC_BASE >> 8, FCH_MISC_REG18 + 0x07, 0, 0x1F},
-
- {MISC_BASE >> 8, FCH_MISC_REG50 + 3, ~BIT5, BIT5},
- {MISC_BASE >> 8, FCH_MISC_REG50 + 2, ~BIT3, BIT3},
- //{SERIAL_DEBUG_BASE >> 8, FCH_SDB_REG74, 0, 0},
- {0xFF, 0xFF, 0xFF, 0xFF},
-};
-
-/**
- * FchHudson2InitEnvHwAcpiPciTable - PCI device registers initial
- * during early POST.
- *
- */
-REG8_MASK FchHudson2InitEnvHwAcpiPciTable[] =
-{
- //
- // SMBUS Device (Bus 0, Dev 20, Func 0)
- //
- {0x00, SMBUS_BUS_DEV_FUN, 0},
- {FCH_CFG_REG10, 0X00, (FCH_VERSION & 0xFF)}, ///Program the version information
- {FCH_CFG_REG11, 0X00, (FCH_VERSION >> 8)},
- {0xFF, 0xFF, 0xFF},
-};
-
-
-/**
- * ProgramPFchAcpiMmio - Config HwAcpi MMIO registers
- * Acpi S3 resume won't execute this procedure (POST only)
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-ProgramEnvPFchAcpiMmio (
- IN VOID *FchDataPtr
- )
-{
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- ProgramFchAcpiMmioTbl ((ACPI_REG_WRITE*) (&FchHudson2InitEnvHwAcpiMmioTable[0]), StdHeader);
-}
-
-/**
- * ProgramFchEnvHwAcpiPciReg - Config HwAcpi PCI controller
- * before PCI emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-ProgramFchEnvHwAcpiPciReg (
- IN VOID *FchDataPtr
- )
-{
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- //
- // FCH CFG programming
- //
- // Make BAR registers of smbus visible.
- //
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8 + 1, AccessWidth8, ~BIT6, 0);
-
- //
- //Early post initialization of pci config space
- //
- ProgramPciByteTable ((REG8_MASK*) (&FchHudson2InitEnvHwAcpiPciTable[0]), sizeof (FchHudson2InitEnvHwAcpiPciTable) / sizeof (REG8_MASK), StdHeader);
-
- if ( LocalCfgPtr->Smbus.SmbusSsid != NULL ) {
- RwPci ((SMBUS_BUS_DEV_FUN << 16) + FCH_CFG_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Smbus.SmbusSsid, StdHeader);
- }
-
- //
- //Make BAR registers of smbus invisible.
- //
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8 + 1, AccessWidth8, ~BIT6, BIT6);
-}
-
-/**
- * FchVgaInit - Config VGA CODEC
- *
- * @param[in] VOID empty
- *
- */
-VOID
-FchVgaInit (
- OUT VOID
- )
-{
- //
- // Cobia_Nutmeg_DP-VGA Electrical SI validation_Lower RGB Luminance level BGADJ=0x1F & DACADJ=0x1B
- //
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC4, AccessWidth8, 0xff, BIT5 );
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD8, AccessWidth8, 0x00, 0x17 );
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD9, AccessWidth8, 0x00, ((BGADJ << 2) + (((DACADJ & 0xf0) >> 4) & 0x3)));
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD8, AccessWidth8, 0x00, 0x16 );
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD9, AccessWidth8, 0x0f, ((DACADJ & 0x0f) << 4));
-
- *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x00))) = (0x08 << 4) + (UINT8) ((EFUS_DAC_ADJUSTMENT_CONTROL >> 16) & 0xff);
- *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x01))) = (UINT8) ((EFUS_DAC_ADJUSTMENT_CONTROL >> 8) & 0xff);
- *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x02))) = (UINT8) ((EFUS_DAC_ADJUSTMENT_CONTROL >> 0) & 0xff);
- *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x03))) = (UINT8) (0x03);
- *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x04))) = (UINT8) (((EFUS_DAC_ADJUSTMENT_CONTROL_DATA) >> 0) & 0xff);
- *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x05))) = (UINT8) (((EFUS_DAC_ADJUSTMENT_CONTROL_DATA) >> 8) & 0xff);
- *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x06))) = (UINT8) (((EFUS_DAC_ADJUSTMENT_CONTROL_DATA) >> 16) & 0xff);
- *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x07))) = (UINT8) (((EFUS_DAC_ADJUSTMENT_CONTROL_DATA) >> 24) & 0xff);
- *((UINT8*) ((UINTN)(PKT_LEN_REG))) = 0x08;
- *((UINT8*) ((UINTN)(PKT_CTRL_REG))) = 0x01;
-}
-
-/**
- * ProgramSpecificFchInitEnvAcpiMmio - Config HwAcpi MMIO before
- * PCI emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-ProgramSpecificFchInitEnvAcpiMmio (
- IN VOID *FchDataPtr
- )
-{
- CPUID_DATA CpuId;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
- //
- // Set ASF SMBUS master function enabled here (temporary)
- //
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG28, AccessWidth16, ~(BIT0 + BIT2), BIT0 + BIT2);
-
-#ifdef ACPI_SLEEP_TRAP
- //
- // Set SLP_TYPE as SMI event
- //
- RwMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0, AccessWidth8, ~(BIT2 + BIT3), BIT2);
-
- //
- // Disabled SLP function for S1/S3/S4/S5
- //
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBE, AccessWidth8, ~BIT5, 0x00);
-
- //
- // Set S state transition disabled (BIT0) force ACPI to send SMI message when writing to SLP_TYP Acpi register. (BIT1)
- //
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG08 + 3, AccessWidth8, ~(BIT0 + BIT1), BIT1);
-
- //
- // Enabled Global Smi ( BIT7 clear as 0 to enable )
- //
- RwMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG98 + 3 , AccessWidth8, ~BIT7, 0x00);
-#endif
-
- //
- // Set Stutter timer settings
- //
- LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuId, StdHeader);
-
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80 + 1, AccessWidth8, ~(BIT3 + BIT4), BIT3 + BIT4);
-
- //
- // Set LDTSTP# duration to 10us for Specific CPU, or when HT link is 200MHz
- //
- if ((LocalCfgPtr->HwAcpi.AnyHt200MhzLink) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x100080) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x100090) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x1000A0)) {
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG94, AccessWidth8, 0, 0x0A);
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80 + 3, AccessWidth8, 0xFE, 0x28);
- } else {
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG94, AccessWidth8, 0, 0x01);
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80 + 3, AccessWidth8, 0xFE, 0x20);
- }
-
- if (!IsImcEnabled (StdHeader)) {
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD2, AccessWidth8, 0xFF, BIT3);
- }
-
- //
- // SSC will provide better jitter margin
- //
- RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x13, AccessWidth8, 0xFC, 0x01);
- //
- // Ac Loss Control
- //
- AcLossControl ((UINT8) LocalCfgPtr->HwAcpi.PwrFailShadow);
- //
- //FCH VGA Init
- //
- FchVgaInit ();
-
- //
- // Set ACPIMMIO by OEM Input table
- //
- ProgramFchAcpiMmioTbl ((ACPI_REG_WRITE *) (LocalCfgPtr->HwAcpi.OemProgrammingTablePtr), StdHeader);
-}
-
-/**
- * ValidateFchVariant - Validate FCH Variant
- *
- *
- *
- * @param[in] FchDataPtr
- *
- */
-VOID
-ValidateFchVariant (
- IN VOID *FchDataPtr
- )
-{
- UINT8 XhciEfuse;
- UINT8 PcieEfuse;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- switch ( LocalCfgPtr->Misc.FchVariant ) {
- case FCH_M3T:
- //Disable Devices for M3T
- LocalCfgPtr->Gec.GecEnable = 1;
- LocalCfgPtr->Hwm.HwMonitorEnable = 0;
- LocalCfgPtr->Sd.SdConfig = 0;
- LocalCfgPtr->Ir.IrConfig = 0;
- break;
-
- default:
- break;
- }
-
- // add Efuse checking for Xhci enable/disable
- XhciEfuse = XHCI_EFUSE_LOCATION;
- GetEfuseStatus (&XhciEfuse, StdHeader);
- if ((XhciEfuse & (BIT0 + BIT1)) == (BIT0 + BIT1)) {
- LocalCfgPtr->Usb.Xhci0Enable = 0;
- LocalCfgPtr->Usb.Xhci1Enable = 0;
- }
-
- // add Efuse checking for PCIE Gen2 enable
- PcieEfuse = PCIE_FORCE_GEN1_EFUSE_LOCATION;
- GetEfuseStatus (&PcieEfuse, StdHeader);
- if ( PcieEfuse & BIT0 ) {
- LocalCfgPtr->Gpp.GppGen2 = 0;
- }
-}
-
-/**
- * IsExternalClockMode - Is External Clock Mode?
- *
- *
- * @retval TRUE or FALSE
- *
- */
-BOOLEAN
-IsExternalClockMode (
- IN VOID *FchDataPtr
- )
-{
- UINT8 MISC80;
- ReadMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80, AccessWidth8, &MISC80);
- return ( (BOOLEAN) ((MISC80 & BIT4) == 0) );
-}
-
-
-/**
- * ProgramFchEnvSpreadSpectrum - Config SpreadSpectrum before
- * PCI emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-ProgramFchEnvSpreadSpectrum (
- IN VOID *FchDataPtr
- )
-{
- UINT8 PortStatus;
- UINT8 FchSpreadSpectrum;
-
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- FchSpreadSpectrum = LocalCfgPtr->HwAcpi.SpreadSpectrum;
-
- if ( FchSpreadSpectrum ) {
- RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x40, AccessWidth32, (UINT32) (~(0x1 << 25)), (0x1 << 25));
- RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccessWidth32, (UINT32) (~(0x1 << 0)), (0x0 << 0));
- RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x18, AccessWidth32, (UINT32) (~(0x7FF << 5)), (0x418 << 5));
- RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x18, AccessWidth32, (UINT32) (~(0xF << 16)), (0x0 << 16));
- RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccessWidth32, (UINT32) (~(0xFFFF << 8)), (0x828F << 8));
- RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccessWidth32, (UINT32) (~(0xFF << 0)), (0xA8 << 0));
- RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x1C, AccessWidth32, (UINT32) (~(0x3F << 0)), (0x0 << 0));
- RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccessWidth32, (UINT32) (~(0xF << 28)), (0x1 << 28));
- RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccessWidth32, (UINT32) (~(0x1 << 7)), (0x0 << 8));
- RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccessWidth32, (UINT32) (~(0x1 << 8)), (0x1 << 8));
- RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccessWidth32, (UINT32) (~(0x3 << 24)), (0x1 << 24));
-
- RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG08, AccessWidth8, 0xFE, 0x01);
- } else {
- RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG08, AccessWidth8, 0xFE, 0x00);
- }
-
- //
- // PLL 100Mhz Reference Clock Buffer setting for internal clock generator mode (BIT5)
- // OSC Clock setting for internal clock generator mode (BIT6)
- //
- GetChipSysMode (&PortStatus, StdHeader);
- if ( ((PortStatus & ChipSysIntClkGen) == ChipSysIntClkGen) ) {
- RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG04 + 1, AccessWidth8, ~(BIT5 + BIT6), BIT5 + BIT6);
- }
-}
-
-/**
- * TurnOffCG2
- *
- *
- * @retval VOID
- *
- */
-VOID
-TurnOffCG2 (
- OUT VOID
- )
-{
- RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x40, AccessWidth8, ~BIT6, 0);
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGDA, AccessWidth8, 0x0F, 0xA0);
- RwMem (ACPI_MMIO_BASE + IOMUX_BASE + 0x41, AccessWidth8, ~(BIT1 + BIT0), (BIT1 + BIT0));
- RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x41, AccessWidth8, ~( BIT4), (BIT4));
- RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x41, AccessWidth8, ~(BIT6), (BIT6));
- RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccessWidth8, ~BIT6, BIT6);
- RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x1C, AccessWidth8, ~BIT6, BIT6);
-}
-
-/**
- * BackUpCG2
- *
- *
- * @retval VOID
- *
- */
-VOID
-BackUpCG2 (
- OUT VOID
- )
-{
- UINT8 Byte;
- ReadMem (ACPI_MMIO_BASE + MISC_BASE + 0x1C, AccessWidth8, &Byte);
- if (Byte & BIT6) {
- RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x41, AccessWidth8, ~(BIT6), (0));
- }
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiLateService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiLateService.c
deleted file mode 100644
index 3c55ac649b..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiLateService.c
+++ /dev/null
@@ -1,343 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch HwAcpi controller
- *
- * Init HwAcpi Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 46093 $ @e \$Date: 2011-01-28 11:39:58 +0800 (Fri, 28 Jan 2011) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuServices.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPILATESERVICE_FILECODE
-
-#define AMD_CPUID_APICID_LPC_BID 0x00000001 // Local APIC ID, Logical Processor Count, Brand ID
-
-/**
- * HpetInit - Program Fch HPET function
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-HpetInit (
- IN VOID *FchDataPtr
- )
-{
- DESCRIPTION_HEADER *HpetTable;
- UINT8 FchHpetTimer;
- UINT8 FchHpetMsiDis;
- FCH_DATA_BLOCK *LocalCfgPtr;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- FchHpetTimer = (UINT8) LocalCfgPtr->Hpet.HpetTimer;
- FchHpetMsiDis = (UINT8) LocalCfgPtr->Hpet.HpetMsiDis;
-
- HpetTable = NULL;
- if ( FchHpetTimer == TRUE ) {
- //
- //Program the HPET BAR address
- //
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG50, AccessWidth32, FCH_HPET_REG_MASK, LocalCfgPtr->Hpet.HpetBase);
-
- //
- //Enabling decoding of HPET MMIO
- //Enable HPET MSI support
- //Enable High Precision Event Timer (also called Multimedia Timer) interrupt
- //
- if ( FchHpetMsiDis == FALSE ) {
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG50, AccessWidth32, FCH_HPET_REG_MASK, BIT0 + BIT1 + BIT2 + BIT3 + BIT4);
-#ifdef FCH_TIMER_TICK_INTERVAL_WA
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG50, AccessWidth32, FCH_HPET_REG_MASK, BIT0 + BIT1);
-#endif
- } else {
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG50, AccessWidth32, FCH_HPET_REG_MASK, BIT0 + BIT1);
- }
-
- } else {
- if ( ! (LocalCfgPtr->Misc.S3Resume) ) {
- HpetTable = (DESCRIPTION_HEADER*) AcpiLocateTable ('TEPH');
- }
- if ( HpetTable != NULL ) {
- HpetTable->Signature = 'HPET';
- }
- }
-}
-
-/**
- * C3PopupSetting - Program Fch C state function
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-C3PopupSetting (
- IN VOID *FchDataPtr
- )
-{
- UINT32 Value;
-
- //
- // C-State and VID/FID Change
- //
-
- GetActiveCoresInGivenSocket (0, &Value, ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader);
-
-#define NON_SUPPORT_PREVIOUS_C3 TRUE
-#ifndef NON_SUPPORT_PREVIOUS_C3
-
- if (Value > 1) {
- //
- //PM 0x80[2]=1, For system with dual core CPU, set this bit to 1 to automatically clear BM_STS when the C3 state is being initiated.
- //PM 0x80[1]=1, For system with dual core CPU, set this bit to 1 and BM_STS will cause C3 to wakeup regardless of BM_RLD
- //PM 0x7E[6]=1, Enable pop-up for C3. For internal bus mastering or BmReq# from the NB, the FCH will de-assert
- //LDTSTP# (pop-up) to allow DMA traffic, then assert LDTSTP# again after some idle time.
- //
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth8, ~(BIT1 + BIT2), (BIT1 + BIT2));
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7E, AccessWidth8, ~BIT6, BIT6);
- }
-
- //
- //PM 0x80 [8] = 0 for system with NB
- //Note: North bridge has AllowLdtStop built for both display and PCIE traffic to wake up the HT link.
- //BmReq# needs to be ignored otherwise may cause LDTSTP# not to toggle.
- //PM_IO 0x80[3]=1, Ignore BM_STS_SET message from NB
- //
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, ~(BIT9 + BIT8 + BIT7 + BIT4 + BIT3 + BIT2 + BIT1 + BIT0), 0x21F);
-
- //
- //LdtStartTime = 10h for minimum LDTSTP# de-assertion duration of 16us in StutterMode. This is to guarantee that
- //the HT link has been safely reconnected before it can be disconnected again. If C3 pop-up is enabled, the 16us also
- //serves as the minimum idle time before LDTSTP# can be asserted again. This allows DMA to finish before the HT
- //link is disconnected.
- //
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG94 + 2, AccessWidth8, 0, 0x10);
-
- //
- //This setting provides 16us delay before the assertion of LDTSTOP# when C3 is entered. The
- //delay will allow USB DMA to go on in a continuous manner
- //
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG98 + 1, AccessWidth8, 0, 0x10);
-
- //
- // ASIC info
- //
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7C, AccessWidth8, 0, 0x85);
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7C + 1, AccessWidth8, 0, 0x01);
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7E + 1, AccessWidth8, ~(BIT7 + BIT5), BIT7 + BIT5);
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG88 + 1, AccessWidth8, ~BIT4, BIT4);
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG98 + 3, AccessWidth8, 0, 0x10);
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGB4 + 1, AccessWidth8, 0, 0x0B);
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG88, AccessWidth8, ~(BIT4 + BIT5), BIT4 + BIT5);
-#else
- // C-State and VID/FID Change
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG88, AccessWidth8, ~(BIT5), BIT5);
-
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, ~(BIT2), BIT2);
-
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, ~(BIT1), BIT1);
-
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7E, AccessWidth8, ~(BIT6), BIT6);
-
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG94, AccessWidth8, 0, 0x01);
-
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG89, AccessWidth8, ~BIT4, BIT4);
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG88, AccessWidth8, ~BIT4, BIT4);
-
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG9B, AccessWidth8, ~(BIT6 + BIT5 + BIT4), BIT4);
-
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG9B, AccessWidth8, ~(BIT1 + BIT0), 0);
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG96, AccessWidth8, 0, 0x10);
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG99, AccessWidth8, 0, 0x10);
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG8E, AccessWidth8, 0, 0x80);
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG97, AccessWidth8, ~(BIT1 + BIT0), 0);
-
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, ~(BIT4), BIT4);
-
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, ~(BIT9), BIT9);
-
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, ~(BIT7), 0);
-#endif
-
-}
-
-/**
- * GcpuRelatedSetting - Program Gcpu C related function
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-GcpuRelatedSetting (
- IN VOID *FchDataPtr
- )
-{
- UINT8 FchAcDcMsg;
- UINT8 FchTimerTickTrack;
- UINT8 FchClockInterruptTag;
- UINT8 FchOhciTrafficHanding;
- UINT8 FchEhciTrafficHanding;
- UINT8 FchGcpuMsgCMultiCore;
- UINT8 FchGcpuMsgCStage;
- UINT32 Value;
- FCH_DATA_BLOCK *LocalCfgPtr;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
-
- FchAcDcMsg = (UINT8) LocalCfgPtr->Gcpu.AcDcMsg;
- FchTimerTickTrack = (UINT8) LocalCfgPtr->Gcpu.TimerTickTrack;
- FchClockInterruptTag = (UINT8) LocalCfgPtr->Gcpu.ClockInterruptTag;
- FchOhciTrafficHanding = (UINT8) LocalCfgPtr->Gcpu.OhciTrafficHanding;
- FchEhciTrafficHanding = (UINT8) LocalCfgPtr->Gcpu.EhciTrafficHanding;
- FchGcpuMsgCMultiCore = (UINT8) LocalCfgPtr->Gcpu.GcpuMsgCMultiCore;
- FchGcpuMsgCStage = (UINT8) LocalCfgPtr->Gcpu.GcpuMsgCStage;
-
- ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGA0, AccessWidth32, &Value);
- Value = Value & 0xC07F00A0;
-
- if ( FchAcDcMsg ) {
- Value = Value | BIT0;
- }
-
- if ( FchTimerTickTrack ) {
- Value = Value | BIT1;
- }
-
- if ( FchClockInterruptTag ) {
- Value = Value | BIT10;
- }
-
- if ( FchOhciTrafficHanding ) {
- Value = Value | BIT13;
- }
-
- if ( FchEhciTrafficHanding ) {
- Value = Value | BIT15;
- }
-
- if ( FchGcpuMsgCMultiCore ) {
- Value = Value | BIT23;
- }
-
- if ( FchGcpuMsgCMultiCore ) {
- Value = (Value | (BIT6 + BIT4 + BIT3 + BIT2));
- }
-
- WriteMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGA0, AccessWidth32, &Value);
-}
-
-/**
- * MtC1eEnable - Program Mt C1E Enable Function
- *
- *
- *
- * @param[in] FchDataPtr
- *
- */
-VOID
-MtC1eEnable (
- IN VOID *FchDataPtr
- )
-{
- FCH_DATA_BLOCK *LocalCfgPtr;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
-
- if ( LocalCfgPtr->HwAcpi.MtC1eEnable ) {
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7A, AccessWidth16, ~ BIT15, BIT15);
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7A, AccessWidth16, ~ (BIT3 + BIT2 + BIT1 + BIT0), 0x01);
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, ~ BIT13, BIT13);
- }
-}
-
-/**
- * StressResetModeLate - Stress Reset Mode
- *
- *
- *
- * @param[in] FchDataPtr
- *
- */
-VOID
-StressResetModeLate (
- IN VOID *FchDataPtr
- )
-{
- UINT8 ResetValue;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- switch ( LocalCfgPtr->HwAcpi.StressResetMode ) {
- case 0:
- return;
- case 1:
- ResetValue = FCH_KBC_RESET_COMMAND;
- LibAmdIoWrite (AccessWidth8, FCH_KBDRST_BASE_IO, &ResetValue, StdHeader);
- break;
- case 2:
- ResetValue = FCH_PCI_RESET_COMMAND06;
- LibAmdIoWrite (AccessWidth8, FCH_PCIRST_BASE_IO, &ResetValue, StdHeader);
- break;
- case 3:
- ResetValue = FCH_PCI_RESET_COMMAND0E;
- LibAmdIoWrite (AccessWidth8, FCH_PCIRST_BASE_IO, &ResetValue, StdHeader);
- break;
- case 4:
- LocalCfgPtr->HwAcpi.StressResetMode = 3;
- return;
- default:
- ASSERT (FALSE);
- return;
- }
- while (LocalCfgPtr->HwAcpi.StressResetMode) {
- }
-}
-
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiMidService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiMidService.c
deleted file mode 100644
index 1c522bdaaa..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiMidService.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch HwAcpi controller
- *
- * Init HwAcpi Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "amdlib.h"
-#include "cpuServices.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPIMIDSERVICE_FILECODE
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c
deleted file mode 100644
index ab1568752d..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch HwAcpi controller
- *
- * Init Spread Spectrum features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "amdlib.h"
-#include "cpuServices.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2SSSERVICE_FILECODE
-
-/**
- * FchInitResetAcpiMmioTable - Fch ACPI MMIO initial
- * during the power on stage.
- *
- *
- *
- *
- */
-ACPI_REG_WRITE FchInitResetAcpiMmioTable[] =
-{
- {00, 00, 0xB0, 0xAC}, /// Signature
- {MISC_BASE >> 8, FCH_MISC_REG41, 0x1F, 0x40}, //keep Auxiliary_14Mclk_Sel [12]
- //
- // USB 3.0 Reference Clock MISC_REG 0x40 [4] = 0 Enable spread-spectrum reference clock.
- //
- {MISC_BASE >> 8, FCH_MISC_REG40, 0xEF, 0x00},
-
- {PMIO_BASE >> 8, FCH_PMIOA_REG5D, 0x00, BIT0},
- {PMIO_BASE >> 8, FCH_PMIOA_REGD2, 0xCF, BIT4 + BIT5},
- {SMBUS_BASE >> 8, FCH_SMBUS_REG12, 0x00, BIT0},
- {PMIO_BASE >> 8, FCH_PMIOA_REG28, 0xFF, BIT0},
- {PMIO_BASE >> 8, FCH_PMIOA_REG44 + 3, 0x67, BIT7}, /// Disable Boot timer
- {PMIO_BASE >> 8, FCH_PMIOA_REG48, 0xFF, BIT0},
- {PMIO_BASE >> 8, FCH_PMIOA_REG00, 0xFF, 0x0E},
- {PMIO_BASE >> 8, FCH_PMIOA_REG00 + 2, 0xFF, 0x40},
- {PMIO_BASE >> 8, FCH_PMIOA_REG00 + 3, 0xFF, 0x08},
- {PMIO_BASE >> 8, FCH_PMIOA_REG34, 0xEF, BIT0 + BIT1},
- {PMIO_BASE >> 8, FCH_PMIOA_REGEC, 0xFD, BIT1},
- {PMIO_BASE >> 8, FCH_PMIOA_REG08, 0xFE, BIT2 + BIT4},
- {PMIO_BASE >> 8, FCH_PMIOA_REG08 + 1, 0xFF, BIT0},
- {PMIO_BASE >> 8, FCH_PMIOA_REG54, 0x00, BIT4 + BIT6 + BIT7},
- {PMIO_BASE >> 8, FCH_PMIOA_REG04 + 3, 0xFD, BIT1},
- {PMIO_BASE >> 8, FCH_PMIOA_REG74, 0xF6, BIT0 + BIT3},
- {PMIO_BASE >> 8, FCH_PMIOA_REGF0, ~BIT2, 0x00},
-
- //
- // GEC I/O Termination Setting
- // PM_Reg 0xF6 = Power-on default setting
- // PM_Reg 0xF7 = Power-on default setting
- // PM_Reg 0xF8 = 0x6C
- // PM_Reg 0xF9 = 0x21
- // PM_Reg 0xFA = 0x00 Hudson-2 A12 GEC I/O Pad settings for 3.3V CMOS
- //
- {PMIO_BASE >> 8, FCH_PMIOA_REGF8, 0x00, 0x6C},
- {PMIO_BASE >> 8, FCH_PMIOA_REGF8 + 1, 0x00, 0x07},
- {PMIO_BASE >> 8, FCH_PMIOA_REGF8 + 2, 0x00, 0x00},
- //
- // GEC -end
- //
-
- {PMIO_BASE >> 8, FCH_PMIOA_REGC4, 0xee, 0x04}, /// Release NB_PCIE_RST
- {PMIO_BASE >> 8, FCH_PMIOA_REGC0 + 2, 0xBF, 0x40},
- {PMIO_BASE >> 8, FCH_PMIOA_REGBE, 0xDF, BIT5},
-
- //
- // Enabling ClkRun Function
- //
- {PMIO_BASE >> 8, FCH_PMIOA_REGBB, 0xFF, BIT2},
- {PMIO_BASE >> 8, FCH_PMIOA_REGD0, ~BIT2, 0},
-
- {0xFF, 0xFF, 0xFF, 0xFF},
-};
-
-/**
- * ProgramFchHwAcpiResetP - Config SpreadSpectrum before PCI
- * emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-ProgramFchHwAcpiResetP (
- IN VOID *FchDataPtr
- )
-{
- FCH_RESET_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
- StdHeader = &((AMD_RESET_PARAMS *)FchDataPtr)->StdHeader;
-
- //Reset USB, BSOD 9F on Cobia Hudson 2 A12 during S4/S5 loop tests
- RwPmio (0xD3, AccessWidth8, ~BIT4, 0, StdHeader);
- RwPmio (0xD3, AccessWidth8, ~BIT4, BIT4, StdHeader);
-
- if ( LocalCfgPtr->Cg2Pll == 1 ) {
- TurnOffCG2 ();
- LocalCfgPtr->SataClkMode = 0x0a;
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiEnv.c
deleted file mode 100644
index e1e89d3d74..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiEnv.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch HwAcpi controller
- *
- * Init HwAcpi Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "amdlib.h"
-#include "cpuServices.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_HWACPI_HWACPIENV_FILECODE
-
-extern VOID ProgramEnvPFchAcpiMmio (IN VOID *FchDataPtr);
-extern VOID ProgramFchEnvHwAcpiPciReg (IN VOID *FchDataPtr);
-extern VOID ProgramSpecificFchInitEnvAcpiMmio (IN VOID *FchDataPtr);
-extern VOID ProgramFchEnvSpreadSpectrum (IN VOID *FchDataPtr);
-extern VOID ValidateFchVariant (IN VOID *FchDataPtr);
-
-/**
- * FchInitEnvHwAcpiP - Config HwAcpi controller preliminary
- * (Special)
- * Acpi S3 resume won't execute this procedure (POST only)
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitEnvHwAcpiP (
- IN VOID *FchDataPtr
- )
-{
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- RecordFchConfigPtr ( (UINT32) ((UINTN) (LocalCfgPtr)));
-
- ValidateFchVariant (LocalCfgPtr);
-
- ProgramEnvPFchAcpiMmio (FchDataPtr);
-
- ProgramFchEnvSpreadSpectrum (FchDataPtr);
-
-}
-
-/**
- * FchInitEnvHwAcpi - Config HwAcpi controller before PCI
- * emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitEnvHwAcpi (
- IN VOID *FchDataPtr
- )
-{
- ProgramFchEnvHwAcpiPciReg (FchDataPtr);
-
- //
- // FCH Specific Function programming
- //
- ProgramSpecificFchInitEnvAcpiMmio (FchDataPtr);
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiLate.c
deleted file mode 100644
index f68916e749..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiLate.c
+++ /dev/null
@@ -1,135 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch HwAcpi controller
- *
- * Init HwAcpi Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "amdlib.h"
-#include "cpuServices.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_HWACPI_HWACPILATE_FILECODE
-
-#define AMD_CPUID_APICID_LPC_BID 0x00000001 // Local APIC ID, Logical Processor Count, Brand ID
-
-extern VOID HpetInit (IN VOID *FchDataPtr);
-extern VOID C3PopupSetting (IN VOID *FchDataPtr);
-extern VOID GcpuRelatedSetting (IN VOID *FchDataPtr);
-extern VOID StressResetModeLate (IN VOID *FchDataPtr);
-
-/**
- * FchInitLateHwAcpi - Prepare HwAcpi controller to boot to OS.
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitLateHwAcpi (
- IN VOID *FchDataPtr
- )
-{
- FCH_DATA_BLOCK *LocalCfgPtr;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
-
- HpetInit (LocalCfgPtr);
-
- if ( IsGCPU (LocalCfgPtr) ) {
- GcpuRelatedSetting (LocalCfgPtr);
- } else {
- C3PopupSetting (LocalCfgPtr);
- }
-
- // Mt C1E Enable
- MtC1eEnable (LocalCfgPtr);
-
- if (LocalCfgPtr->SerialDb.SerialDebugBusEnable == 1 ) {
- RwMem (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + FCH_SDB_REG00, AccessWidth8, 0xFF, 0x05);
- }
-
- StressResetModeLate (LocalCfgPtr);
-}
-
-/**
- * IsGCPU - Is Gcpu Cpu?
- *
- *
- * @retval TRUE or FALSE
- *
- */
-BOOLEAN
-IsGCPU (
- IN VOID *FchDataPtr
- )
-{
- UINT8 ExtendedFamily;
- UINT8 ExtendedModel;
- UINT8 BaseFamily;
- UINT8 BaseModel;
- UINT8 Stepping;
- UINT8 Family;
- UINT8 Model;
- CPUID_DATA CpuId;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuId, StdHeader);
-
- ExtendedFamily = (UINT8) ((CpuId.EAX_Reg >> 20) & 0xff);
- ExtendedModel = (UINT8) ((CpuId.EAX_Reg >> 16) & 0xf);
- BaseFamily = (UINT8) ((CpuId.EAX_Reg >> 8) & 0xf);
- BaseModel = (UINT8) ((CpuId.EAX_Reg >> 4) & 0xf);
- Stepping = (UINT8) ((CpuId.EAX_Reg >> 0) & 0xf);
- Family = BaseFamily + ExtendedFamily;
- Model = (ExtendedModel << 4) + BaseModel;
-
- if ( (Family == 0x12) || \
- (Family == 0x14) || \
- (Family == 0x16) || \
- ((Family == 0x15) && ((Model == 0x10) || (Model == 0x30))) ) {
- return TRUE;
- } else {
- return FALSE;
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiMid.c
deleted file mode 100644
index 1087ad3819..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiMid.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch HwAcpi controller
- *
- * Init HwAcpi Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "amdlib.h"
-#include "cpuServices.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_HWACPI_HWACPIMID_FILECODE
-
-/**
- * FchInitMidHwAcpi - Config HwAcpi controller after PCI
- * emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitMidHwAcpi (
- IN VOID *FchDataPtr
- )
-{
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiReset.c
deleted file mode 100644
index e1f8c60511..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiReset.c
+++ /dev/null
@@ -1,200 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch HwAcpi controller
- *
- * Init HwAcpi Controller features (PEI phase).
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_HWACPI_HWACPIRESET_FILECODE
-
-extern ACPI_REG_WRITE FchInitResetAcpiMmioTable[];
-extern VOID ProgramFchHwAcpiResetP (IN VOID *FchDataPtr);
-
-/**
- * FchInitResetHwAcpiP - Config HwAcpi controller ( Preliminary
- * ) during Power-On
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitResetHwAcpiP (
- IN VOID *FchDataPtr
- )
-{
- FCH_RESET_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
-
- StdHeader = &((AMD_RESET_PARAMS *)FchDataPtr)->StdHeader;
-
- //
- // Enabled (Mmio_mem_enable)
- //
- RwPmio (FCH_PMIOA_REG24, AccessWidth8, 0xFF, BIT0, StdHeader);
-
- ProgramFchHwAcpiResetP (FchDataPtr);
-
- //
- // enable CF9
- //
- RwPmio (0xD2, AccessWidth8, ~BIT6, 0, StdHeader);
-}
-
-/**
- * FchInitResetHwAcpi - Config HwAcpi controller during Power-On
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitResetHwAcpi (
- IN VOID *FchDataPtr
- )
-{
- UINT16 SmbusBase;
- UINT8 Value;
- UINT16 AsfPort;
- FCH_RESET_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- //
- // Set Build option into SB
- //
- WritePci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG64, AccessWidth16, &(UserOptions.CfgSioPmeBaseAddress), StdHeader);
-
- //
- // Enabled SMBUS0/SMBUS1 (ASF) Base Address
- //
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG2C, AccessWidth16, 06, (UserOptions.CfgSmbus0BaseAddress) + BIT0); ///protect BIT[2:1]
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG28, AccessWidth16, 06, (UserOptions.CfgSmbus1BaseAddress) + BIT0);
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG60, AccessWidth16, 00, (UserOptions.CfgAcpiPm1EvtBlkAddr));
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG62, AccessWidth16, 00, (UserOptions.CfgAcpiPm1CntBlkAddr));
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG64, AccessWidth16, 00, (UserOptions.CfgAcpiPmTmrBlkAddr));
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG66, AccessWidth16, 00, (UserOptions.CfgCpuControlBlkAddr));
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG68, AccessWidth16, 00, (UserOptions.CfgAcpiGpe0BlkAddr));
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6A, AccessWidth16, 00, (UserOptions.CfgSmiCmdPortAddr));
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6C, AccessWidth16, 00, (UserOptions.CfgAcpiPmaCntBlkAddr));
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6E, AccessWidth16, 00, (UserOptions.CfgSmiCmdPortAddr) + 8);
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG48, AccessWidth32, 00, (UserOptions.CfgWatchDogTimerBase));
-
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG2E, AccessWidth8, ~(BIT1 + BIT2), 0); ///clear BIT[2:1]
- SmbusBase = (UINT16) (UserOptions.CfgSmbus0BaseAddress);
- Value = 0x00;
- LibAmdIoWrite (AccessWidth8, SmbusBase + 0x14, &Value, StdHeader);
-
- ProgramFchAcpiMmioTbl ((ACPI_REG_WRITE*) (&FchInitResetAcpiMmioTable[0]), StdHeader);
-
- //
- // Prevent RTC error
- //
- Value = 0x0A;
- LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG70, &Value, StdHeader);
- LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
- Value &= 0xEF;
- LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
-
- Value = 0x08;
- LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Value, StdHeader);
- LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader);
- if ( !LocalCfgPtr->EcKbd ) {
- //
- // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input
- //
- Value = Value | 0x0A;
- }
- LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader);
-
- Value = 0x09;
- LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Value, StdHeader);
- LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader);
- if ( !LocalCfgPtr->EcKbd ) {
- //
- // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input
- //
- Value = Value & 0xF9;
- }
-
- if ( LocalCfgPtr->LegacyFree ) {
- //
- // Disable IRQ1/IRQ12 filter enable for Legacy free with USB KBC emulation.
- //
- Value = Value & 0x9F;
- }
- //
- // Enabled IRQ input
- //
- Value = Value | BIT4;
- LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader);
-
- AsfPort = ((UINT16) UserOptions.CfgSmbus1BaseAddress & 0xFFF0);
- if ( AsfPort != 0 ) {
- UINT8 dbValue;
- dbValue = 0x70;
- LibAmdIoWrite (AccessWidth8, AsfPort + 0x0E, &dbValue, StdHeader);
- }
-}
-
-/**
- * FchInitRecoveryHwAcpi - Config HwAcpi controller during
- * Crisis Recovery
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitRecoveryHwAcpi (
- IN VOID *FchDataPtr
- )
-{
-}
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmEnvService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmEnvService.c
deleted file mode 100644
index a14be840f4..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmEnvService.c
+++ /dev/null
@@ -1,265 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config FCH Hwm controller
- *
- * Init Hwm Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_HWM_FAMILY_HUDSON2_HUDSON2HWMENVSERVICE_FILECODE
-
-FCH_HWM_TEMP_PAR TempParDefault[] = {
- { 5220, 27365 , 0 },
- { 5225, 27435 , 0 },
- { 5220, 27516 , BIT0 }, ///High Ratio
- { 5212, 27580 , BIT1 }, ///High Current
- { 5123, 27866 , 0 }
-};
-
-/**
- * HwmInitRegister - Init Hardware Monitor Register.
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-HwmInitRegister (
- IN VOID *FchDataPtr
- )
-{
- RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xB2, AccessWidth8, 0, 0x55);
- RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xB3, AccessWidth8, 0, 0x55);
- RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x91, AccessWidth8, 0, 0x55);
- RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x92, AccessWidth8, 0, 0x55);
-
- RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x00, AccessWidth8, 0, 0x06);
- RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x10, AccessWidth8, 0, 0x06);
- RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x20, AccessWidth8, 0, 0x06);
- RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x30, AccessWidth8, 0, 0x06);
- RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x40, AccessWidth8, 0, 0x06);
-
- RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x66, AccessWidth8, 0, 0x01);
- RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x6B, AccessWidth8, 0, 0x01);
- RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x70, AccessWidth8, 0, 0x01);
- RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x75, AccessWidth8, 0, 0x01);
- RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x7A, AccessWidth8, 0, 0x01);
-
- RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xE6, AccessWidth8, 0xff, 0x02);
- RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xF8, AccessWidth8, 0, 0x05);
- RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xF9, AccessWidth8, 0, 0x06);
- RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xFF, AccessWidth8, 0, 0x42);
- RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xE9, AccessWidth8, 0, 0xFF);
- RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xEB, AccessWidth8, 0, 0x1F);
- RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xEF, AccessWidth8, 0, 0x04);
- RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xFB, AccessWidth8, 0, 0x00);
- //2.9 Enhancement of FanOut0 Control
- RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG50, AccessWidth32, ~ (BIT11 + BIT20), (BIT11 + BIT20));
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGB6, AccessWidth8, 0x0F, 0x10);
-}
-
-/**
- * HwmProcessParameter - Hardware Monitor process Parameter
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-HwmProcessParameter (
- IN VOID *FchDataPtr
- )
-{
- UINT8 Index;
- UINT8 TempChannel;
- UINT8 ValueByte;
- UINT16 ValueWord;
- FCH_DATA_BLOCK *LocalCfgPtr;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
-
- HwmGetCalibrationFactor (LocalCfgPtr);
- //
- //temperatue parameter
- //
- for ( Index = 0; Index < 5 ; Index++ ) {
- if ( LocalCfgPtr->Hwm.HwmTempPar[Index].At == 0 ) {
- LocalCfgPtr->Hwm.HwmTempPar[Index] = TempParDefault[Index];
- }
- }
-
- for ( Index = 0; Index < 5 ; Index++ ) {
- if ( LocalCfgPtr->Hwm.HwmFanControl[Index].LowDutyReg03 == 100 ) {
- LocalCfgPtr->Hwm.HwmFanControl[Index].LowDutyReg03 = 255;
- } else {
- LocalCfgPtr->Hwm.HwmFanControl[Index].LowDutyReg03 = (LocalCfgPtr->Hwm.HwmFanControl[Index].LowDutyReg03 << 8) / 100;
- }
-
- if ( LocalCfgPtr->Hwm.HwmFanControl[Index].MedDutyReg04 == 100 ) {
- LocalCfgPtr->Hwm.HwmFanControl[Index].MedDutyReg04 = 255;
- } else {
- LocalCfgPtr->Hwm.HwmFanControl[Index].MedDutyReg04 = (LocalCfgPtr->Hwm.HwmFanControl[Index].MedDutyReg04 << 8) / 100;
- }
-
- ValueByte = (UINT8) ((256 - LocalCfgPtr->Hwm.HwmFanControl[Index].LowDutyReg03) / (LocalCfgPtr->Hwm.HwmFanControl[Index].HighTempReg0A - LocalCfgPtr->Hwm.HwmFanControl[Index].MedTempReg08));
- ValueWord = LocalCfgPtr->Hwm.HwmFanControl[Index].LowTempReg06;
-
- if (LocalCfgPtr->Hwm.HwmFanControl[Index].InputControlReg00 > 4) {
- TempChannel = 0;
- } else {
- TempChannel = LocalCfgPtr->Hwm.HwmFanControl[Index].InputControlReg00;
- }
-
- if ((LocalCfgPtr->Hwm.HwmFchtsiAutoPoll == 1) && (Index == 0)) {
- ValueWord = ValueWord << 8;
- } else {
- ValueByte = (UINT8) (ValueByte * 10000 / LocalCfgPtr->Hwm.HwmTempPar[TempChannel].At);
- ValueWord = ((ValueWord * 100 + LocalCfgPtr->Hwm.HwmTempPar[TempChannel].Ct ) * 100 * LocalCfgPtr->Hwm.HwmCalibrationFactor / LocalCfgPtr->Hwm.HwmTempPar[TempChannel].At) >> 3;
- }
- LocalCfgPtr->Hwm.HwmFanControl[Index].LowTempReg06 = ValueWord;
- LocalCfgPtr->Hwm.HwmFanControl[Index].MultiplierReg05 = ValueByte & 0x3f;
-
- ValueWord = LocalCfgPtr->Hwm.HwmFanControl[Index].MedTempReg08;
- if ((LocalCfgPtr->Hwm.HwmFchtsiAutoPoll == 1) && (Index == 0)) {
- ValueWord = ValueWord << 8;
- } else {
- ValueWord = ((ValueWord * 100 + LocalCfgPtr->Hwm.HwmTempPar[TempChannel].Ct ) * 100 * LocalCfgPtr->Hwm.HwmCalibrationFactor / LocalCfgPtr->Hwm.HwmTempPar[TempChannel].At) >> 3;
- }
- LocalCfgPtr->Hwm.HwmFanControl[Index].MedTempReg08 = ValueWord;
-
- ValueWord = LocalCfgPtr->Hwm.HwmFanControl[Index].HighTempReg0A;
- if ((LocalCfgPtr->Hwm.HwmFchtsiAutoPoll == 1) && (Index == 0)) {
- ValueWord = ValueWord << 8;
- } else {
- ValueWord = ((ValueWord * 100 + LocalCfgPtr->Hwm.HwmTempPar[TempChannel].Ct ) * 100 * LocalCfgPtr->Hwm.HwmCalibrationFactor / LocalCfgPtr->Hwm.HwmTempPar[TempChannel].At) >> 3;
- }
- LocalCfgPtr->Hwm.HwmFanControl[Index].HighTempReg0A = ValueWord;
- }
-}
-
-/**
- * hwmSetRegister - Hardware Monitor Set Parameter
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-HwmSetRegister (
- IN VOID *FchDataPtr
- )
-{
- UINT8 *DbValuePtr;
- UINT8 Index;
- UINT8 RegisterN;
- UINT8 RegisterPM2RegF8;
- UINT8 RegisterPM2RegF9;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- //
- //Configure Fans
- //
- for ( Index = 0; Index < 5 ; Index++ ) {
- DbValuePtr = &(LocalCfgPtr->Hwm.HwmFanControl[Index].InputControlReg00);
- for ( RegisterN = 0; RegisterN < 0x0E ; RegisterN++ ) {
- WritePmio2 (Index * 0x10 + RegisterN, AccessWidth8, DbValuePtr, StdHeader);
- DbValuePtr ++;
- }
- }
-
- //
- //Configure Sample Frequency Divider
- //
- WritePmio2 (FCH_PMIO2_REG63, AccessWidth8, &(LocalCfgPtr->Hwm.FanSampleFreqDiv), StdHeader);
-
- //
- //Configure Mode
- //
- ReadPmio2 (0xF8, AccessWidth8, &RegisterPM2RegF8, StdHeader);
- ReadPmio2 (0xF9, AccessWidth8, &RegisterPM2RegF9, StdHeader);
- for ( Index = 0; Index < 5 ; Index++ ) {
- if (LocalCfgPtr->Hwm.HwmTempPar[Index].Mode == BIT0) {
- RegisterPM2RegF8 |= 1 << (Index + 3);
- } else if (LocalCfgPtr->Hwm.HwmTempPar[Index].Mode == BIT1) {
- RegisterPM2RegF9 |= 1 << (Index + 3);
- }
- }
- WritePmio2 (0xF8, AccessWidth8, &RegisterPM2RegF8, StdHeader);
- WritePmio2 (0xF9, AccessWidth8, &RegisterPM2RegF9, StdHeader);
-}
-
-/**
- * hwmGetCalibrationFactor - Hardware Monitor Get Calibration
- * Factor
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-HwmGetCalibrationFactor (
- IN VOID *FchDataPtr
- )
-{
- UINT8 ValueByte;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- //
- //temperatue parameter
- //
- ReadPmio2 (FCH_PMIO2_REGEA, AccessWidth8, &ValueByte, StdHeader);
- if ( ValueByte & BIT7 ) {
- if ( ValueByte & BIT6 ) {
- LocalCfgPtr->Hwm.HwmCalibrationFactor = 0x100 + ValueByte;
- } else {
- LocalCfgPtr->Hwm.HwmCalibrationFactor = 0x200 + (ValueByte & 0x3f );
- }
- } else {
- LocalCfgPtr->Hwm.HwmCalibrationFactor = 0x200;
- }
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmLateService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmLateService.c
deleted file mode 100644
index 48a763691c..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmLateService.c
+++ /dev/null
@@ -1,170 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config FCH Hwm controller
- *
- * Init Hwm Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_HWM_FAMILY_HUDSON2_HUDSON2HWMLATESERVICE_FILECODE
-
-FCH_EC EcDefaultMassege = {
- 0x00, 0x00, 0x35, 0x0E, 0x00, 0x54, 0x9B, 0x02, 0x01, 0x00,
- 0x00, 0x01, 0x35, 0x0A, 0x00, 0x04, 0x00, 0x00, 0x01, 0x00,
- 0x00, 0x02, 0x05, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x03, 0x05, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x46, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x00,
- 0x00, 0x01, 0x5F, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x5F, 0x00,
- 0x00, 0x00, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x01, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x3E, 0x87, 0x00, 0x00, 0xA8, 0x11, 0x01, 0x00, 0x00,
- 0x00, 0x01, 0x86, 0x87, 0x00, 0x00, 0x14, 0x12, 0x01, 0x00, 0x01,
- 0x00, 0x02, 0x31, 0x86, 0x00, 0x00, 0x33, 0x15, 0x01, 0x00, 0x02,
- 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x04, 0x86, 0x87, 0x00, 0x00, 0xA6, 0x11, 0x01, 0x00, 0x00
-};
-
-/**
- * Table for Function Number
- *
- *
- *
- *
- */
-UINT8 FunctionNumber[] =
-{
- Fun_81,
- Fun_83,
- Fun_85,
- Fun_89,
-};
-
-/**
- * Table for Max Thermal Zone
- *
- *
- *
- *
- */
-UINT8 MaxZone[] =
-{
- 4,
- 2,
- 2,
- 5,
-};
-
-/**
- * Table for Max Register
- *
- *
- *
- *
- */
-UINT8 MaxRegister[] =
-{
- MSG_REG9,
- MSG_REGB,
- MSG_REG9,
- MSG_REGA,
-};
-
-/*-------------------------------------------------------------------------------
-;Procedure: FchECfancontrolservice
-;
-;Description: This routine service EC fan policy
-;
-;
-;Exit: None
-;
-;Modified: None
-;
-;-----------------------------------------------------------------------------
-*/
-VOID
-FchECfancontrolservice (
- IN VOID *FchDataPtr
- )
-{
- UINT8 ZoneNum;
- UINT8 FunNum;
- UINT8 RegNum;
- UINT8 *CurPoint;
- UINT8 FunIndex;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- if (!IsImcEnabled (StdHeader)) {
- return; //IMC is not enabled
- }
-
- CurPoint = &LocalCfgPtr->Imc.EcStruct.MsgFun81Zone0MsgReg0 + MaxZone[0] * (MaxRegister[0] - MSG_REG0 + 1);
-
- for ( FunIndex = 1; FunIndex <= 3; FunIndex++ ) {
- FunNum = FunctionNumber[FunIndex];
- for ( ZoneNum = 0; ZoneNum < MaxZone[FunIndex]; ZoneNum++ ) {
- for ( RegNum = MSG_REG0; RegNum <= MaxRegister[FunIndex]; RegNum++ ) {
- WriteECmsg (RegNum, AccessWidth8, CurPoint, StdHeader);
- CurPoint += 1;
- }
-
- WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &FunNum, StdHeader); // function number
- WaitForEcLDN9MailboxCmdAck (StdHeader);
- }
- }
-
- CurPoint = &LocalCfgPtr->Imc.EcStruct.MsgFun81Zone0MsgReg0;
- for ( FunIndex = 0; FunIndex <= 0; FunIndex++ ) {
- FunNum = FunctionNumber[FunIndex];
- for ( ZoneNum = 0; ZoneNum < MaxZone[FunIndex]; ZoneNum++ ) {
- for ( RegNum = MSG_REG0; RegNum <= MaxRegister[FunIndex]; RegNum++ ) {
- WriteECmsg (RegNum, AccessWidth8, CurPoint, StdHeader);
- CurPoint += 1;
- }
-
- WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &FunNum, StdHeader); // function number
- WaitForEcLDN9MailboxCmdAck (StdHeader);
- }
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmMidService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmMidService.c
deleted file mode 100644
index da471515fb..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmMidService.c
+++ /dev/null
@@ -1,248 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config FCH Hwm controller
- *
- * Init Hwm Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_HWM_FAMILY_HUDSON2_HUDSON2HWMMIDSERVICE_FILECODE
-
-/**
- * hwmFchtsiAutoPolling - Hardware Monitor Auto Poll SB-TSI.
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-HwmFchtsiAutoPolling (
- IN VOID *FchDataPtr
- )
-{
- UINT8 ValueByte;
- UINT16 SmbusBase;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- SmbusBase = (UINT16) (LocalCfgPtr->HwAcpi.Smbus0BaseAddress);
-
- if (LocalCfgPtr->Hwm.HwmFchtsiAutoPoll == 1) {
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG2E, AccessWidth8, ~(BIT1 + BIT2), BIT2);
- ValueByte = 0xff;
- LibAmdIoWrite (AccessWidth8, SmbusBase, &ValueByte, StdHeader);
- ValueByte = 0x08;
- LibAmdIoWrite (AccessWidth8, SmbusBase + 2, &ValueByte, StdHeader);
- ValueByte = 0x09;
- LibAmdIoWrite (AccessWidth8, SmbusBase + 3, &ValueByte, StdHeader);
- ValueByte = 0x98;
- LibAmdIoWrite (AccessWidth8, SmbusBase + 4, &ValueByte, StdHeader);
- ValueByte = 0x20;
- LibAmdIoWrite (AccessWidth8, SmbusBase + 5, &ValueByte, StdHeader);
- ValueByte = 0x48;
- LibAmdIoWrite (AccessWidth8, SmbusBase + 2, &ValueByte, StdHeader);
-
- LibAmdIoRead (AccessWidth8, SmbusBase + 0, &ValueByte, StdHeader);
- while ( ValueByte & BIT0 ) {
- LibAmdIoRead (AccessWidth8, SmbusBase + 0, &ValueByte, StdHeader);
- }
-
- ValueByte = 0x08;
- LibAmdIoWrite (AccessWidth8, SmbusBase + 2, &ValueByte, StdHeader);
- ValueByte = 0x10;
- LibAmdIoWrite (AccessWidth8, SmbusBase + 3, &ValueByte, StdHeader);
- ValueByte = 0x99;
- LibAmdIoWrite (AccessWidth8, SmbusBase + 4, &ValueByte, StdHeader);
-
- ValueByte = 0x80;
- LibAmdIoWrite (AccessWidth8, SmbusBase + 0x14, &ValueByte, StdHeader);
- ValueByte = 0x01;
- LibAmdIoWrite (AccessWidth8, SmbusBase + 0x17, &ValueByte, StdHeader);
- ValueByte = 0x81;
- LibAmdIoWrite (AccessWidth8, SmbusBase + 0x14, &ValueByte, StdHeader);
-
- //
- //map SB-TSI to tempin0
- //
- RwMem (ACPI_MMIO_BASE + PMIO2_BASE + FCH_PMIO2_REG92, AccessWidth8, ~BIT3, BIT3);
- } else {
- HwmFchtsiAutoPollingOff (LocalCfgPtr);
- }
-}
-
-/**
- * HwmFchtsiAutoPollingOff - Hardware Monitor Auto Poll SB-TSI
- * Off.
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-HwmFchtsiAutoPollingOff (
- IN VOID *FchDataPtr
- )
-{
- UINT8 ValueByte;
- UINT16 SmbusBase;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- if ( LocalCfgPtr->Hwm.HwMonitorEnable ) {
- SmbusBase = (UINT16) (LocalCfgPtr->HwAcpi.Smbus0BaseAddress);
- ValueByte = 0x00;
- LibAmdIoWrite (AccessWidth8, SmbusBase + 0x14, &ValueByte, StdHeader);
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG2E, AccessWidth8, ~(BIT1 + BIT2), 0);
- RwMem (ACPI_MMIO_BASE + PMIO2_BASE + FCH_PMIO2_REG92, AccessWidth8, ~BIT3, 0x00);
- }
-}
-
-/**
- * HwmGetRawData - Hardware Monitor Get Raw Data.
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-HwmGetRawData (
- IN VOID *FchDataPtr
- )
-{
- UINT8 Index;
- UINT16 ValueWord;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- //
- //fan speed
- //
- for ( Index = 0; Index < 5 ; Index++ ) {
- ReadPmio2 (FCH_PMIO2_REG69 + Index * 5, AccessWidth16, &ValueWord, StdHeader);
- if ( (ValueWord & 0xFFC0) != 0xFFC0 ) {
- LocalCfgPtr->Hwm.HwmCurrentRaw.FanSpeed[Index] = ValueWord;
- }
- }
- //
- //temperatue
- //
- for ( Index = 0; Index < 5 ; Index++ ) {
- ReadPmio2 (FCH_PMIO2_REG95 + Index * 4, AccessWidth16, &ValueWord, StdHeader);
- if ( ( Index == 1 ) || (ValueWord > 0x4000) ) {
- LocalCfgPtr->Hwm.HwmCurrentRaw.Temperature[Index] = ValueWord;
- }
- }
- //
- //voltage
- //
- for ( Index = 0; Index < 8 ; Index++ ) {
- ReadPmio2 (FCH_PMIO2_REGB8 + Index * 4, AccessWidth16, &ValueWord, StdHeader);
- if ( (ValueWord & 0xFFC0) != 0xFFC0 ) {
- LocalCfgPtr->Hwm.HwmCurrentRaw.Voltage[Index] = ValueWord;
- }
- }
-}
-
-/**
- * HwmCaculate - Hardware Monitor Caculate Raw Data to Display Data.
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-HwmCaculate (
- IN VOID *FchDataPtr
- )
-{
- UINT8 Index;
- UINT16 ValueWord;
- FCH_DATA_BLOCK *LocalCfgPtr;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
-
- //
- //fan speed
- //
- for ( Index = 0; Index < 5 ; Index++ ) {
- ValueWord = LocalCfgPtr->Hwm.HwmCurrentRaw.FanSpeed[Index];
- if ((ValueWord == 0xffff) || (ValueWord == 0x0000)) {
- LocalCfgPtr->Hwm.HwmCurrent.FanSpeed[Index] = 0;
- } else {
- LocalCfgPtr->Hwm.HwmCurrent.FanSpeed[Index] = ( 22720 >> LocalCfgPtr->Hwm.FanSampleFreqDiv ) * 60 / ValueWord / 2;
- }
- }
- //
- //temperatue
- //
- for ( Index = 0; Index < 5 ; Index++ ) {
- ValueWord = LocalCfgPtr->Hwm.HwmCurrentRaw.Temperature[Index];
- if ((LocalCfgPtr->Hwm.HwmFchtsiAutoPoll == 1) && (Index == 1)) {
- ValueWord = ((ValueWord & 0xff00) >> 8) * 10 + (((ValueWord & 0x00ff) * 10 ) >> 8);
- } else {
- ValueWord = ((ValueWord << 3) * LocalCfgPtr->Hwm.HwmTempPar[Index].At / LocalCfgPtr->Hwm.HwmCalibrationFactor / 100 - LocalCfgPtr->Hwm.HwmTempPar[Index].Ct) / 100 ;
- }
- if ( LocalCfgPtr->Hwm.HwmCurrent.Temperature[Index] == 0 ) {
- ValueWord = 0;
- }
- if ( ValueWord < 10000 ) {
- LocalCfgPtr->Hwm.HwmCurrent.Temperature[Index] = ValueWord;
- } else {
- LocalCfgPtr->Hwm.HwmCurrent.Temperature[Index] = 0;
- }
- }
- //
- //voltage
- //
- for ( Index = 0; Index < 8 ; Index++ ) {
- ValueWord = LocalCfgPtr->Hwm.HwmCurrentRaw.Voltage[Index];
- LocalCfgPtr->Hwm.HwmCurrent.Voltage[Index] = (ValueWord >> 6) * 512 / LocalCfgPtr->Hwm.HwmCalibrationFactor;
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/HwmEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/HwmEnv.c
deleted file mode 100644
index 88f1be7628..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/HwmEnv.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config FCH Hwm controller
- *
- * Init Hwm Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_HWM_HWMENV_FILECODE
-
-extern VOID HwmInitRegister (IN VOID* FchDataPtr);
-extern VOID HwmProcessParameter (IN VOID* FchDataPtr);
-extern VOID HwmSetRegister (IN VOID* FchDataPtr);
-
-/**
- * FchInitEnvHwm - Config Hwm controller before PCI emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitEnvHwm (
- IN VOID *FchDataPtr
- )
-{
- FCH_DATA_BLOCK *LocalCfgPtr;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
-
- if ( LocalCfgPtr->Hwm.HwMonitorEnable ) {
- HwmInitRegister (LocalCfgPtr);
- HwmProcessParameter (LocalCfgPtr);
- HwmSetRegister (LocalCfgPtr);
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/HwmLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/HwmLate.c
deleted file mode 100644
index 3dd309b64e..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/HwmLate.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config FCH Hwm controller
- *
- * Init Hwm Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_HWM_HWMLATE_FILECODE
-
-extern FCH_HWM_TEMP_PAR TempParDefault[];
-extern FCH_EC EcDefaultMassege;
-
-extern VOID FchECfancontrolservice (IN VOID* FchDataPtr);
-
-/**
- * FchInitLateHwm - Prepare Hwm controller to boot to OS.
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitLateHwm (
- IN VOID *FchDataPtr
- )
-{
- UINT8 RegisterPM2Reg01;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- ImcWakeup (LocalCfgPtr);
- if (( LocalCfgPtr->Hwm.HwmFchtsiAutoPoll == FALSE ) && ( LocalCfgPtr->Hwm.HwMonitorEnable )) {
- //
- // Overwrite Fan0Control to 0x04
- //
- RegisterPM2Reg01 = 0x04;
- WritePmio2 (FCH_PMIO2_REG01, AccessWidth8, &RegisterPM2Reg01, StdHeader);
-
- LocalCfgPtr->Imc.EcStruct = EcDefaultMassege;
- FchECfancontrolservice (LocalCfgPtr);
- }
-}
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/HwmMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/HwmMid.c
deleted file mode 100644
index f118aff48c..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/HwmMid.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config FCH Hwm controller
- *
- * Init Hwm Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_HWM_HWMMID_FILECODE
-
-extern VOID HwmFchtsiAutoPolling (IN VOID* FchDataPtr);
-extern VOID HwmGetRawData (IN VOID* FchDataPtr);
-extern VOID HwmCaculate (IN VOID* FchDataPtr);
-
-/**
- * FchInitMidHwm - Config Hwm controller after PCI emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitMidHwm (
- IN VOID *FchDataPtr
- )
-{
- FCH_DATA_BLOCK *LocalCfgPtr;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
-
- if ( LocalCfgPtr->Hwm.HwMonitorEnable ) {
- HwmFchtsiAutoPolling (LocalCfgPtr);
- HwmGetRawData (LocalCfgPtr);
- HwmCaculate (LocalCfgPtr);
- }
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/HwmReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/HwmReset.c
deleted file mode 100644
index 9d407db8ca..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/HwmReset.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config FCH Hwm controller
- *
- * Init Hwm Controller features (PEI phase).
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_HWM_HWMRESET_FILECODE
-
-/**
- * FchInitResetHwm - Config Hwm controller during Power-On
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitResetHwm (
- IN VOID *FchDataPtr
- )
-{
-}
-
-/**
- * FchInitRecoveryLpc - Config Hwm controller during Crisis
- * Recovery
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitRecoveryHwm (
- IN VOID *FchDataPtr
- )
-{
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Ide/IdeEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Ide/IdeEnv.c
deleted file mode 100644
index b219cff3db..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Ide/IdeEnv.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch IDE controller
- *
- * Init IDE Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#define FILECODE PROC_FCH_IDE_IDEENV_FILECODE
-
-/**
- * FchInitEnvIde - Config Ide controller before PCI emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitEnvIde (
- IN VOID *FchDataPtr
- )
-{
- UINT8 Channel;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- RwPci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG40), AccessWidth8, 0xff, BIT0, StdHeader);
-
- //
- // Enabling IDE Explicit Pre-Fetch IDE PCI Config 0x62[8]=0
- //
- RwPci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG62 + 1), AccessWidth8, ~BIT0, BIT5, StdHeader);
-
- //
- // Disable SATA MSI
- //
- RwPci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG34), AccessWidth8, 0x00, 0x00, StdHeader);
- RwPci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG06), AccessWidth8, 0xEF, 0x00, StdHeader);
-
- //
- // Set Ide Channel enable/disable by parameter
- //
- ReadPci (((IDE_BUS_DEV_FUN << 16) + FCH_SATA_REG40 + 11), AccessWidth8, &Channel, StdHeader);
- Channel &= 0xCF;
- if ( LocalCfgPtr->Sata.IdeDisUnusedIdePChannel ) {
- Channel |= 0x10;
- }
- if ( LocalCfgPtr->Sata.IdeDisUnusedIdeSChannel ) {
- Channel |= 0x20;
- }
- WritePci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG40 + 11), AccessWidth8, &Channel, StdHeader);
-
- //
- // IDE Controller Class ID & SSID
- // ** Get Sata Configuration ** for sync Sata & Ide with only one Legacy Ide device
- //
- if ( (LocalCfgPtr->Sata.SataIdeMode == 1) && (LocalCfgPtr->Sata.SataClass != SataLegacyIde) ) {
- //
- // Write the class code to IDE PCI register 08h-0Bh
- //
- RwPci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG08), AccessWidth32, 0, 0x01018F40, StdHeader);
- }
- if ( LocalCfgPtr->Sata.SataClass == SataLegacyIde ) {
- //
- //Set SATA controller to native mode
- //
- RwPci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG09), AccessWidth8, 0x00, 0x08F, StdHeader);
- }
- if (LocalCfgPtr->Ide.IdeSsid != NULL ) {
- RwPci ((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Ide.IdeSsid, StdHeader);
- }
-
- //
- // Disable write access to PCI header
- //
- RwPci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG40), AccessWidth8, ~BIT0, 0, StdHeader);
-}
-
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Ide/IdeLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Ide/IdeLate.c
deleted file mode 100644
index e25271b2b0..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Ide/IdeLate.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch IDE controller
- *
- * Init IDE Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#define FILECODE PROC_FCH_IDE_IDELATE_FILECODE
-/**
- * FchInitLateIde - Prepare IDE controller to boot to OS.
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitLateIde (
- IN VOID *FchDataPtr
- )
-{
-}
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Ide/IdeMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Ide/IdeMid.c
deleted file mode 100644
index 1f4c298fae..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Ide/IdeMid.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch IDE controller
- *
- * Init IDE Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#define FILECODE PROC_FCH_IDE_IDEMID_FILECODE
-
-/**
- * FchInitMidIde - Config IDE controller after PCI emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitMidIde (
- IN VOID *FchDataPtr
- )
-{
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/Family/Hudson2/Hudson2ImcService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/Family/Hudson2/Hudson2ImcService.c
deleted file mode 100644
index 826546a067..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/Family/Hudson2/Hudson2ImcService.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch Imc controller
- *
- * Init Imc Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 46088 $ @e \$Date: 2011-01-28 11:24:26 +0800 (Fri, 28 Jan 2011) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_IMC_FAMILY_HUDSON2_HUDSON2IMCSERVICE_FILECODE
-
-//
-// Declaration of local functions
-//
-
-
-/**
- * SoftwareToggleImcStrapping - Software Toggle IMC Firmware Strapping.
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-SoftwareToggleImcStrapping (
- IN VOID *FchDataPtr
- )
-{
- UINT8 ValueByte;
- UINT8 PortStatusByte;
- UINT32 AbValue;
- UINT32 ABStrapOverrideReg;
- AMD_CONFIG_PARAMS *StdHeader;
-
- StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader;
- GetChipSysMode (&PortStatusByte, StdHeader);
-
- ReadPmio (FCH_PMIOA_REGBF, AccessWidth8, &ValueByte, StdHeader);
-
- //
- //if ( (ValueByte & (BIT6 + BIT7)) != 0xC0 ) { // PwrGoodOut =1, PwrGoodEnB=1
- //The strapStatus register is not mapped into StrapOveride not in the same bit position. The following is difference.
- //
- //StrapStatus StrapOverride
- // bit4 bit17
- // bit6 bit12
- // bit12 bit15
- // bit15 bit16
- // bit16 bit18
- //
- ReadMem ((ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80), AccessWidth32, &AbValue);
- ABStrapOverrideReg = AbValue;
-
- if (AbValue & BIT4) {
- ABStrapOverrideReg = (ABStrapOverrideReg & ~BIT4) | BIT17;
- }
-
- if (AbValue & BIT6) {
- ABStrapOverrideReg = (ABStrapOverrideReg & ~BIT6) | BIT12;
- }
-
- if (AbValue & BIT12) {
- ABStrapOverrideReg = (ABStrapOverrideReg & ~BIT12) | BIT15;
- }
-
- if (AbValue & BIT15) {
- ABStrapOverrideReg = (ABStrapOverrideReg & ~BIT15) | BIT16;
- }
-
- if (AbValue & BIT16) {
- ABStrapOverrideReg = (ABStrapOverrideReg & ~BIT16) | BIT18;
- }
-
- ABStrapOverrideReg |= BIT31; /// Overwrite enable
-
- if ((PortStatusByte & ChipSysEcEnable) == 0) {
- ABStrapOverrideReg |= BIT2; /// bit2- EcEnableStrap
- } else {
- ABStrapOverrideReg &= ~BIT2; /// bit2=0 EcEnableStrap
- }
-
- WriteMem ((ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG84), AccessWidth32, &ABStrapOverrideReg);
- ValueByte |= (BIT6 + BIT7); /// PwrGoodOut =1, PwrGoodEnB=1
- WritePmio (FCH_PMIOA_REGBF, AccessWidth8, &ValueByte, StdHeader);
-
- ValueByte = 06;
- LibAmdIoWrite (AccessWidth8, 0xcf9, &ValueByte, StdHeader);
- FchStall (0xffffffff, StdHeader);
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/FchEcEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/FchEcEnv.c
deleted file mode 100644
index ae8aa362a7..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/FchEcEnv.c
+++ /dev/null
@@ -1,185 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * FCH Embedded Controller
- *
- * Init Ec Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_IMC_FCHECENV_FILECODE
-
-
-/**
- * FchInitEnvEc - Config Ec controller before PCI emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitEnvEc (
- IN VOID *FchDataPtr
- )
-{
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * EnterEcConfig - Force EC into Config mode
- *
- *
- *
- *
- */
-VOID
-EnterEcConfig (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT16 EcIndexPortDword;
- UINT8 FchEcData8;
-
- ReadPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGA4, AccessWidth16, &EcIndexPortDword, StdHeader);
- EcIndexPortDword &= ~(BIT0);
- FchEcData8 = 0x5A;
- LibAmdIoWrite (AccessWidth8, EcIndexPortDword, &FchEcData8, StdHeader);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * ExitEcConfig - Force EC exit Config mode
- *
- *
- *
- *
- */
-VOID
-ExitEcConfig (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT16 EcIndexPortDword;
- UINT8 FchEcData8;
-
- ReadPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGA4, AccessWidth16, &EcIndexPortDword, StdHeader);
- EcIndexPortDword &= ~(BIT0);
- FchEcData8 = 0xA5;
- LibAmdIoWrite (AccessWidth8, EcIndexPortDword, &FchEcData8, StdHeader);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * ReadEc8 - Read EC register data
- *
- *
- *
- * @param[in] Address - EC Register Offset Value
- * @param[in] Value - Read Data Buffer
- * @param[in] StdHeader
- *
- */
-VOID
-ReadEc8 (
- IN UINT8 Address,
- IN UINT8 *Value,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT16 EcIndexPortDword;
-
- ReadPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGA4, AccessWidth16, &EcIndexPortDword, StdHeader);
- EcIndexPortDword &= ~(BIT0);
- LibAmdIoWrite (AccessWidth8, EcIndexPortDword, &Address, StdHeader);
- LibAmdIoRead (AccessWidth8, EcIndexPortDword + 1, Value, StdHeader);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * RwEc8 - Read/Write EC register
- *
- *
- *
- * @param[in] Address - EC Register Offset Value
- * @param[in] AndMask - Data And Mask 8 bits
- * @param[in] OrMask - Data OR Mask 8 bits
- * @param[in] StdHeader
- *
- */
-VOID
-RwEc8 (
- IN UINT8 Address,
- IN UINT8 AndMask,
- IN UINT8 OrMask,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 Result;
-
- ReadEc8 (Address, &Result, StdHeader);
- Result = (Result & AndMask) | OrMask;
- WriteEc8 (Address, &Result, StdHeader);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * WriteEc8 - Write date into EC register
- *
- *
- *
- * @param[in] Address - EC Register Offset Value
- * @param[in] Value - Write Data Buffer
- * @param[in] StdHeader
- *
- */
-VOID
-WriteEc8 (
- IN UINT8 Address,
- IN UINT8 *Value,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT16 EcIndexPortDword;
-
- ReadPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGA4, AccessWidth16, &EcIndexPortDword, StdHeader);
- EcIndexPortDword &= ~(BIT0);
- LibAmdIoWrite (AccessWidth8, EcIndexPortDword, &Address, StdHeader);
- LibAmdIoWrite (AccessWidth8, EcIndexPortDword + 1, Value, StdHeader);
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/FchEcLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/FchEcLate.c
deleted file mode 100644
index 988d80bdec..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/FchEcLate.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * FCH Embedded Controller
- *
- * Init Ec Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_IMC_FCHECLATE_FILECODE
-
-/**
- * FchInitLateEc - Prepare Ec controller to boot to OS.
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitLateEc (
- IN VOID *FchDataPtr
- )
-{
-}
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/FchEcMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/FchEcMid.c
deleted file mode 100644
index 57df031aa5..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/FchEcMid.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * FCH Embedded Controller
- *
- * Init Ec Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_IMC_FCHECMID_FILECODE
-
-/**
- * FchInitMidIde - Config Ec controller after PCI emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitMidEc (
- IN VOID *FchDataPtr
- )
-{
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/FchEcReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/FchEcReset.c
deleted file mode 100644
index 2cbe428216..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/FchEcReset.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch Ec controller
- *
- * Init Ec Controller features (PEI phase).
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_IMC_FCHECRESET_FILECODE
-
-/**
- * FchInitResetEc - Config Ec controller during Power-On
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitResetEc (
- IN VOID *FchDataPtr
- )
-{
- FCH_RESET_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- //
- //Enable config mode
- //
- EnterEcConfig (StdHeader);
-
- //
- //Do settings for mailbox - logical device 0x09
- //
- RwEc8 (0x07, 0x00, 0x09, StdHeader); ///switch to device 9 (Mailbox)
- RwEc8 (0x60, 0x00, (MailBoxPort >> 8), StdHeader); ///set MSB of Mailbox port
- RwEc8 (0x61, 0x00, (MailBoxPort & 0xFF), StdHeader); ///set LSB of Mailbox port
- RwEc8 (0x30, 0x00, 0x01, StdHeader); ///;Enable Mailbox Registers Interface, bit0=1
-
- if ( LocalCfgPtr->EcKbd == ENABLED) {
- //
- //Enable KBRST#, IRQ1 & IRQ12, GateA20 Function signal from IMC
- //
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD6, AccessWidth8, ~BIT8, BIT0 + BIT1 + BIT2 + BIT3);
-
- //
- //Disable LPC Decoding of port 60/64
- //
- RwPci (((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG47), AccessWidth8, ~BIT5, 0, StdHeader);
-
- //
- //Enable logical device 0x07 (Keyboard controller)
- //
- RwEc8 (0x07, 0x00, 0x07, StdHeader);
- RwEc8 (0x30, 0x00, 0x01, StdHeader);
- }
-
- if (IsImcEnabled (StdHeader) && ( LocalCfgPtr->EcChannel0 == ENABLED)) {
- //
- //Logical device 0x03
- //
- RwEc8 (0x07, 0x00, 0x03, StdHeader);
- RwEc8 (0x60, 0x00, 0x00, StdHeader);
- RwEc8 (0x61, 0x00, 0x62, StdHeader);
- RwEc8 (0x30, 0x00, 0x01, StdHeader); ///;Enable Device 3
- }
-
- //
- //Enable EC (IMC) to generate SMI to BIOS
- //
- RwMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB3, AccessWidth8, ~BIT6, BIT6);
- ExitEcConfig (StdHeader);
-}
-
-/**
- * FchInitRecoveryLpc - Config Ec controller during Crisis
- * Recovery
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitRecoveryEc (
- IN VOID *FchDataPtr
- )
-{
-}
-
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcEnv.c
deleted file mode 100644
index c8b8e8d217..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcEnv.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch Imc controller
- *
- * Init Imc Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_IMC_IMCENV_FILECODE
-
-extern VOID SoftwareToggleImcStrapping (IN VOID *FchDataPtr);
-
-//
-// Declaration of local functions
-//
-
-
-/**
- * FchInitEnvImc - Config Imc controller before PCI emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitEnvImc (
- IN VOID *FchDataPtr
- )
-{
- UINT8 PortStatusByte;
- FCH_DATA_BLOCK *LocalCfgPtr;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
-
- GetChipSysMode (&PortStatusByte, LocalCfgPtr->StdHeader);
- ImcEnableSurebootTimer (LocalCfgPtr);
-
- //
- // Software IMC enable
- //
- if (((LocalCfgPtr->Imc.ImcEnableOverWrite == 1) && ((PortStatusByte & ChipSysEcEnable) == 0)) || ((LocalCfgPtr->Imc.ImcEnableOverWrite == 2) && ((PortStatusByte & ChipSysEcEnable) == ChipSysEcEnable))) {
- if (ValidateImcFirmware (LocalCfgPtr)) {
- SoftwareToggleImcStrapping (LocalCfgPtr);
- }
- }
-
- FchInitEnvEc (LocalCfgPtr);
-}
-
-/**
- * ValidateImcFirmware - Validate IMC Firmware.
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- * @retval TRUE Pass
- * @retval FALSE Failed
- */
-BOOLEAN
-ValidateImcFirmware (
- IN VOID *FchDataPtr
- )
-{
- UINT32 ImcSig;
- UINT32 ImcSigAddr;
- UINT32 ImcAddr;
- UINT32 CurAddr;
- UINT32 ImcBinSig0;
- UINT32 ImcBinSig1;
- UINT16 ImcBinSig2;
- UINT8 IMCChecksumeByte;
- UINT8 IMCByte;
-
- ImcAddr = 0;
-
- //
- // Software IMC enable
- //
- ImcSigAddr = 0x80000; /// start from 512k to 64M
- ImcSig = 0x0;
-
- while ( ( ImcSig != 0x55aa55aa ) && ( ImcSigAddr <= 0x4000000 ) ) {
- CurAddr = 0xffffffff - ImcSigAddr + 0x20001;
- ReadMem (CurAddr, AccessWidth32, &ImcSig);
- ReadMem ((CurAddr + 4), AccessWidth32, &ImcAddr);
- ImcSigAddr <<= 1;
- }
-
- IMCChecksumeByte = 0xff;
-
- if ( ImcSig == 0x55aa55aa ) {
- //
- // "_AMD_IMC_C" at offset 0x2000 of the binary
- //
- ReadMem ((ImcAddr + 0x2000), AccessWidth32, &ImcBinSig0);
- ReadMem ((ImcAddr + 0x2004), AccessWidth32, &ImcBinSig1);
- ReadMem ((ImcAddr + 0x2008), AccessWidth16, &ImcBinSig2);
-
- if ((ImcBinSig0 == 0x444D415F) && (ImcBinSig1 == 0x434D495F) && (ImcBinSig2 == 0x435F) ) {
- IMCChecksumeByte = 0;
-
- for ( CurAddr = ImcAddr; CurAddr < ImcAddr + 0x10000; CurAddr++ ) {
- ReadMem (CurAddr, AccessWidth8, &IMCByte);
- IMCChecksumeByte = IMCChecksumeByte + IMCByte;
- }
- }
- }
-
- if ( IMCChecksumeByte ) {
- return FALSE;
- } else {
- return TRUE;
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcLate.c
deleted file mode 100644
index 0ba9de5ea9..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcLate.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch Imc controller
- *
- * Init Imc Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_IMC_IMCLATE_FILECODE
-
-/**
- * FchInitLateImc - Prepare Imc controller to boot to OS.
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitLateImc (
- IN VOID *FchDataPtr
- )
-{
- ImcDisarmSurebootTimer (FchDataPtr);
- FchInitLateEc (FchDataPtr);
-}
-
-/**
- * ImcDisarmSurebootTimer - IMC Disarm Sureboot Timer.
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-ImcDisarmSurebootTimer (
- IN VOID *FchDataPtr
- )
-{
- FCH_DATA_BLOCK *LocalCfgPtr;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
-
- ImcDisableSurebootTimer (LocalCfgPtr);
- LocalCfgPtr->Imc.ImcSureBootTimer = 0;
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcLib.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcLib.c
deleted file mode 100644
index cd10599626..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcLib.c
+++ /dev/null
@@ -1,279 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * FCH IMC lib
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_IMC_IMCLIB_FILECODE
-
-VOID
-WriteECmsg (
- IN UINT8 Address,
- IN UINT8 OpFlag,
- IN VOID *Value,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 Index;
-
- ASSERT (OpFlag < AccessWidth64); /* TODO: Add the assertion to make it not crash for now. */
- OpFlag = (OpFlag & 0x7f) - 1;
- if (OpFlag == 0x02) OpFlag = 0x03;
-
- for (Index = 0; Index <= OpFlag; Index++) {
- /// EC_LDN9_MAILBOX_BASE_ADDRESS
- LibAmdIoWrite (AccessWidth8, 0x3E, &Address, StdHeader);
- Address++;
- /// EC_LDN9_MAILBOX_BASE_ADDRESS
- LibAmdIoWrite (AccessWidth8, 0x3F, (UINT8 *)Value + Index, StdHeader);
- }
-}
-
-VOID
-ReadECmsg (
- IN UINT8 Address,
- IN UINT8 OpFlag,
- OUT VOID *Value,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 Index;
-
- ASSERT (OpFlag < AccessWidth64); /* TODO: Add the assertion to make it not crash for now. */
- OpFlag = (OpFlag & 0x7f) - 1;
- if (OpFlag == 0x02) OpFlag = 0x03;
-
- for (Index = 0; Index <= OpFlag; Index++) {
- /// EC_LDN9_MAILBOX_BASE_ADDRESS
- LibAmdIoWrite (AccessWidth8, 0x3E, &Address, StdHeader);
- Address++;
- /// EC_LDN9_MAILBOX_BASE_ADDRESS
- LibAmdIoRead (AccessWidth8, 0x3F, (UINT8 *)Value + Index, StdHeader);
- }
-}
-
-VOID
-WaitForEcLDN9MailboxCmdAck (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 Msgdata;
- UINT16 Delaytime;
-
- Msgdata = 0;
-
- for (Delaytime = 0; Delaytime <= 500; Delaytime++) {
- ReadECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader);
- if ( Msgdata == 0xfa) {
- break;
- }
-
- FchStall (1000, StdHeader); /// Wait for 1ms
- }
-}
-
-/**
- * ImcSleep - IMC Sleep.
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-ImcSleep (
- IN VOID *FchDataPtr
- )
-{
- UINT8 Msgdata;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- if (!(IsImcEnabled (StdHeader)) ) {
- return; ///IMC is not enabled
- }
-
- Msgdata = 0x00;
- WriteECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader);
- Msgdata = 0xB4;
- WriteECmsg (MSG_REG1, AccessWidth8, &Msgdata, StdHeader);
- Msgdata = 0x00;
- WriteECmsg (MSG_REG2, AccessWidth8, &Msgdata, StdHeader);
- Msgdata = 0x96;
- WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &Msgdata, StdHeader);
- WaitForEcLDN9MailboxCmdAck (StdHeader);
-}
-
-
-/**
- * ImcEnableSurebootTimer - IMC Enable Sureboot Timer.
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-ImcEnableSurebootTimer (
- IN VOID *FchDataPtr
- )
-{
- UINT8 Msgdata;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- ImcDisableSurebootTimer (LocalCfgPtr);
-
- Msgdata = 0x00;
-
- if (!(IsImcEnabled (StdHeader)) || (LocalCfgPtr->Imc.ImcSureBootTimer == 0)) {
- return; ///IMC is not enabled
- }
-
- WriteECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader);
- Msgdata = 0x01;
- WriteECmsg (MSG_REG1, AccessWidth8, &Msgdata, StdHeader);
- Msgdata = ( (LocalCfgPtr->Imc.ImcSureBootTimer) << 6) -1;
- WriteECmsg (MSG_REG2, AccessWidth8, &Msgdata, StdHeader);
- Msgdata = 0x94;
- WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &Msgdata, StdHeader);
- WaitForEcLDN9MailboxCmdAck (StdHeader);
-}
-
-/**
- * ImcDisableSurebootTimer - IMC Disable Sureboot Timer.
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-ImcDisableSurebootTimer (
- IN VOID *FchDataPtr
- )
-{
- UINT8 Msgdata;
- AMD_CONFIG_PARAMS *StdHeader;
-
- StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader;
-
- if (!(IsImcEnabled (StdHeader)) ) {
- return; ///IMC is not enabled
- }
-
- Msgdata = 0x00;
- WriteECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader);
- Msgdata = 0x01;
- WriteECmsg (MSG_REG1, AccessWidth8, &Msgdata, StdHeader);
- Msgdata = 0x00;
- WriteECmsg (MSG_REG2, AccessWidth8, &Msgdata, StdHeader);
- Msgdata = 0x94;
- WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &Msgdata, StdHeader);
- WaitForEcLDN9MailboxCmdAck (StdHeader);
-}
-
-/**
- * ImcWakeup - IMC Wakeup.
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-ImcWakeup (
- IN VOID *FchDataPtr
- )
-{
- UINT8 Msgdata;
- AMD_CONFIG_PARAMS *StdHeader;
-
- StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader;
- if (!(IsImcEnabled (StdHeader)) ) {
- return; ///IMC is not enabled
- }
-
- Msgdata = 0x00;
- WriteECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader);
- Msgdata = 0xB5;
- WriteECmsg (MSG_REG1, AccessWidth8, &Msgdata, StdHeader);
- Msgdata = 0x00;
- WriteECmsg (MSG_REG2, AccessWidth8, &Msgdata, StdHeader);
- Msgdata = 0x96;
- WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &Msgdata, StdHeader);
- WaitForEcLDN9MailboxCmdAck (StdHeader);
-}
-
-/**
- * ImcIdle - IMC Idle.
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-ImcIdle (
- IN VOID *FchDataPtr
- )
-{
- UINT8 Msgdata;
- AMD_CONFIG_PARAMS *StdHeader;
-
- StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader;
-
- if (!(IsImcEnabled (StdHeader)) ) {
- return; ///IMC is not enabled
- }
-
- Msgdata = 0x00;
- WriteECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader);
- Msgdata = 0x01;
- WriteECmsg (MSG_REG1, AccessWidth8, &Msgdata, StdHeader);
- Msgdata = 0x00;
- WriteECmsg (MSG_REG2, AccessWidth8, &Msgdata, StdHeader);
- Msgdata = 0x98;
- WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &Msgdata, StdHeader);
- WaitForEcLDN9MailboxCmdAck (StdHeader);
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcMid.c
deleted file mode 100644
index 7b7330e856..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcMid.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch Imc controller
- *
- * Init Imc Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_IMC_IMCMID_FILECODE
-
-/**
- * FchInitMidImc - Config Imc controller after PCI emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitMidImc (
- IN VOID *FchDataPtr
- )
-{
- ImcEnableSurebootTimer (FchDataPtr);
- FchInitMidEc (FchDataPtr);
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcReset.c
deleted file mode 100644
index 36c7696428..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcReset.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch Imc controller
- *
- * Init Imc Controller features (PEI phase).
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#define FILECODE PROC_FCH_IMC_IMCRESET_FILECODE
-
-/**
- * FchInitResetImc - Config Imc controller during Power-On
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitResetImc (
- IN VOID *FchDataPtr
- )
-{
- UINT8 PortStatusByte;
- AMD_CONFIG_PARAMS *StdHeader;
-
- StdHeader = &((AMD_RESET_PARAMS *)FchDataPtr)->StdHeader;
- GetChipSysMode (&PortStatusByte, StdHeader);
-
- if ( ((PortStatusByte & ChipSysEcEnable) == 0x00) ) {
- //
- // EC is disabled by jumper setting or board config
- //
- RwPci (((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGA4), AccessWidth16, 0xFFFE, BIT0, StdHeader);
- } else {
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC4, AccessWidth8, 0xF7, 0x08);
- FchInitResetEc (FchDataPtr);
- // ecPowerOnInit ( FchDataPtr);
- ImcSleep (FchDataPtr);
- }
-}
-
-/**
- * FchInitRecoveryLpc - Config Imc controller during Crisis
- * Recovery
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitRecoveryImc (
- IN VOID *FchDataPtr
- )
-{
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/Family/Hudson2/EnvDefHudson2.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/Family/Hudson2/EnvDefHudson2.c
deleted file mode 100644
index f8de7ed5e5..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/Family/Hudson2/EnvDefHudson2.c
+++ /dev/null
@@ -1,355 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Graphics Controller family specific service procedure
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 49633 $ @e \$Date: 2011-03-26 06:52:29 +0800 (Sat, 26 Mar 2011) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "FchPlatform.h"
-#include "Filecode.h"
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-
-/*----------------------------------------------------------------
- * InitEnv Phase Data Block Default (Failsafe)
- *----------------------------------------------------------------
- */
-FCH_DATA_BLOCK InitEnvCfgDefault = {
- NULL, // StdHeader
-
- { // FCH_ACPI
- 0xB00, // Smbus0BaseAddress
- 0xB20, // Smbus1BaseAddress
- 0xE00, // SioPmeBaseAddress
- 0xFEC00000, // WatchDogTimerBase
- 0x400, // AcpiPm1EvtBlkAddr
- 0x404, // AcpiPm1CntBlkAddr
- 0x408, // AcpiPmTmrBlkAddr
- 0x410, // CpuControlBlkAddr
- 0x420, // AcpiGpe0BlkAddr
- 0x00B0, // SmiCmdPortAddr
- 0xFE00, // AcpiPmaCntBlkAddr
- TRUE, // AnyHt200MhzLink
- TRUE, // SpreadSpectrum
- UsePrevious, // PwrFailShadow
- 0, // StressResetMode
- FALSE, // MtC1eEnable
- NULL // OemProgrammingTablePtr
- },
-
- { // FCH_AB
- FALSE, // AbMsiEnable
- 0, // AlinkPhyPllPowerDown
- 0, // ALinkClkGateOff
- 0, // BLinkClkGateOff
- 0, // AbClockGating
- 0, // GppClockGating
- 0, // UmiL1TimerOverride
- 0, // UmiLinkWidth
- 0, // UmiDynamicSpeedChange
- 0, // PcieRefClockOverClocking
- 0, // UmiGppTxDriverStrength
- FALSE, // NbSbGen2
- 0, // FchPcieOrderRule
- 0, // SlowSpeedAbLinkClock
- 0 // ResetCpuOnSyncFlood
- },
-
- { // FCH_GPP
- { // Array of FCH_GPP_PORT_CONFIG PortCfg[4]
- {
- FALSE, // PortPresent
- FALSE, // PortDetected
- FALSE, // PortIsGen2
- FALSE, // PortHotPlug
- 0, // PortMisc
- },
- {
- FALSE, // PortPresent
- FALSE, // PortDetected
- FALSE, // PortIsGen2
- FALSE, // PortHotPlug
- 0, // PortMisc
- },
- {
- FALSE, // PortPresent
- FALSE, // PortDetected
- FALSE, // PortIsGen2
- FALSE, // PortHotPlug
- 0, // PortMisc
- },
- {
- FALSE, // PortPresent
- FALSE, // PortDetected
- FALSE, // PortIsGen2
- FALSE, // PortHotPlug
- 0, // PortMisc
- },
- },
- PortA4, // GppLinkConfig
- 0, // GppFoundGfxDev
- 0, // GppGen2
- 0, // GppGen2Strap
- 0, // GppMemWrImprove
- FALSE, // GppFunctionEnable
- 0, // GppUnhidePorts
- 0, // GppPortAspm
- 0, // GppLaneReversal
- 0, // GppPhyPllPowerDown
- 0, // GppDynamicPowerSaving
- 0, // PcieAer
- 0, // PcieRas
- 0, // PcieCompliance
- 0, // PcieSoftwareDownGrade
- 0, // GppHardwareDownGrade
- FALSE, // GppToggleReset
- },
-
- { // FCH_USB
- TRUE, // Ohci1Enable
- TRUE, // Ohci2Enable
- TRUE, // Ohci3Enable
- TRUE, // Ohci4Enable
- TRUE, // Ehci1Enable
- TRUE, // Ehci2Enable
- TRUE, // Ehci3Enable
- FALSE, // Xhci0Enable
- FALSE, // Xhci1Enable
- FALSE, // UsbMsiEnable
- 0, // OhciSsid
- 0, // Ohci4Ssid
- 0, // EhciSsid
- 0, // XhciSsid
- FALSE // UsbPhyPowerDown
- },
-
- { // FCH_SATA
- FALSE, // SataMsiEnable
- 0x00000000, // SataIdeSsid
- 0x00000000, // SataRaidSsid
- 0x00000000, // SataRaid5Ssid
- 0x00000000, // SataAhciSsid
- { // SATA_ST
- 0, // SataModeReg
- TRUE, // SataEnable
- 0, // Sata6AhciCap
- TRUE, // SataSetMaxGen2
- TRUE, // IdeEnable
- 0, // SataClkMode
- },
- 0, // SataClass
- 0, // SataIdeMode
- 0, // SataDisUnusedIdePChannel
- 0, // SataDisUnusedIdeSChannel
- 0, // IdeDisUnusedIdePChannel
- 0, // IdeDisUnusedIdeSChannel
- 0, // SataOptionReserved
- { // SATA_PORT_ST
- 0, // SataPortReg
- TRUE, // Port0
- TRUE, // Port1
- TRUE, // Port2
- TRUE, // Port3
- TRUE, // Port4
- TRUE, // Port5
- TRUE, // Port6
- TRUE, // Port7
- },
- { // SATA_PORT_ST
- 0, // SataPortReg
- FALSE, // Port0
- FALSE, // Port1
- FALSE, // Port2
- FALSE, // Port3
- FALSE, // Port4
- FALSE, // Port5
- FALSE, // Port6
- FALSE, // Port7
- },
- { // SATA_PORT_MD
- 0, // SataPortMode
- 0, // Port0
- 0, // Port1
- 0, // Port2
- 0, // Port3
- 0, // Port4
- 0, // Port5
- 0, // Port6
- 0, // Port7
- },
- 0, // SataAggrLinkPmCap
- 0, // SataPortMultCap
- 0, // SataClkAutoOff
- 0, // SataPscCap
- 0, // BiosOsHandOff
- 0, // SataFisBasedSwitching
- 0, // SataCccSupport
- 0, // SataSscCap
- 0, // SataMsiCapability
- 0, // SataForceRaid
- 0, // SataInternal100Spread
- 0, // SataDebugDummy
- 0, // SataTargetSupport8Device
- 0, // SataDisableGenericMode
- 0, // SataAhciEnclosureManagement:1
- 0, // SataSgpio0
- 0, // SataSgpio1
- 0, // SataPhyPllShutDown
- TRUE, // SataHotRemovalEnh
- { // SATA_PORT_ST
- 0, // SataPortReg
- FALSE, // Port0
- FALSE, // Port1
- FALSE, // Port2
- FALSE, // Port3
- FALSE, // Port4
- FALSE, // Port5
- FALSE, // Port6
- FALSE, // Port7
- },
- 0 // TempMmio
- },
-
- { // FCH_SMBUS
- 0x00000000 // SmbusSsid
- },
-
- { // FCH_IDE
- TRUE, // IdeEnable
- FALSE, // IdeMsiEnable
- 0x00000000 // IdeSsid
- },
-
- { // FCH_AZALIA
- AzDisable, // AzaliaEnable
- FALSE, // AzaliaMsiEnable
- 0x00000000, // AzaliaSsid
- 0, // AzaliaPinCfg
- 0, // AzaliaFrontPanel
- 0, // FrontPanelDetected
- 0, // AzaliaSnoop
- 0, // AzaliaDummy
- { // AZALIA_PIN
- 0, // AzaliaSdin0
- 0, // AzaliaSdin1
- 0, // AzaliaSdin2
- 0, // AzaliaSdin3
- },
- NULL, // *AzaliaOemCodecTablePtr
- NULL, // *AzaliaOemFpCodecTablePtr
- },
-
- { // FCH_SPI
- FALSE, // LpcMsiEnable
- 0x00000000, // LpcSsid
- 0, // RomBaseAddress
- 0, // Speed
- 0, // FastSpeed
- 0, // WriteSpeed
- 0, // Mode
- 0, // AutoMode
- 0, // BurstWrite
- },
-
- { // FCH_PCIB
- FALSE, // PcibMsiEnable
- 0x00000000, // PcibSsid
- 0x0F, // PciClks
- 0, // PcibClkStopOverride
- FALSE, // PcibClockRun
- },
-
- { // FCH_GEC
- FALSE, // GecEnable
- 0, // GecPhyStatus
- 0, // GecPowerPolicy
- 0, // GecDebugBus
- 0xFED61000, // GecShadowRomBase
- NULL, // *PtrDynamicGecRomAddress
- },
-
- { // FCH_SD
- SdDisable, // SdConfig
- 0, // Speed
- 0, // BitWidth
- },
-
- {0}, // FCH_HWM
- {0}, // FCH_IR
- { // FCH_HPET
- FALSE, // HpetEnable
- 0, // HpetTimer
- TRUE, // HpetMsiDis
- 0xFED00000 // HpetBase
- },
-
- { // FCH_GCPU
- 0, // AcDcMsg
- 0, // TimerTickTrack
- 0, // ClockInterruptTag
- 0, // OhciTrafficHanding
- 0, // EhciTrafficHanding
- 0, // GcpuMsgCMultiCore
- 0, // GcpuMsgCStage
- },
-
- {0}, // FCH_IMC
- {FALSE}, // FCH_SERIALDB
-
- { // FCH_MISC
- FALSE, // NativePcieSupport
- FALSE, // S3Resume
- FALSE, // RebootRequired
- 0, // FchVariant
- 0, // CG2PLL
- }
-};
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/Family/Hudson2/ResetDefHudson2.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/Family/Hudson2/ResetDefHudson2.c
deleted file mode 100644
index f2a7c41ee8..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/Family/Hudson2/ResetDefHudson2.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Graphics Controller family specific service procedure
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44909 $ @e \$Date: 2011-01-10 18:45:45 +0800 (Mon, 10 Jan 2011) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "FchPlatform.h"
-#include "Filecode.h"
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------
- * InitReset Phase Data Block Default (Failsafe)
- *----------------------------------------------------------------
- */
-FCH_RESET_DATA_BLOCK InitResetCfgDefault = {
- NULL, // StdHeader
- NULL, // FchReset
-
- FALSE, // NbSbGen2
- 0, // FastSpeed
- 0, // WriteSpeed
- 0, // Mode
- 0, // AutoMode
- 0, // BurstWrite
- FALSE, // SataIdeCombMdPriSecOpt
- 0, // Cg2Pll
- FALSE, // EcKbd
- FALSE, // LegacyFree
- FALSE, // SataSetMaxGen2
- 9, // SataClkMode
- 0, // SataModeReg
- FALSE, // SataInternal100Spread
- 2, // SpiSpeed
- TRUE, // EcChannel0
- FALSE, // SerialDebugBusEnable
- FALSE // GppToggleReset
-};
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitEnv.c
deleted file mode 100644
index 4fe936f552..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitEnv.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * FCH Initialization.
- *
- * Init IOAPIC/IOMMU/Misc NB features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 49837 $ @e \$Date: 2011-03-30 04:31:05 +0800 (Wed, 30 Mar 2011) $
- *
- */
-/*;********************************************************************************
-;
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*********************************************************************************/
-
-#include "FchPlatform.h"
-#include "FchTaskLauncher.h"
-#include "heapManager.h"
-#include "Ids.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_INTERFACE_FCHINITENV_FILECODE
-
-extern FCH_TASK_ENTRY *FchInitEnvTaskTable[];
-extern FCH_INTERFACE FchInterfaceDefault;
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * FchInitEnv - Config Fch before PCI emulation
- *
- *
- *
- * @param[in] EnvParams
- *
- */
-AGESA_STATUS
-FchInitEnv (
- IN AMD_ENV_PARAMS *EnvParams
- )
-{
- UINT8 i;
- UINT8 Data;
- FCH_DATA_BLOCK *FchParams;
- AGESA_STATUS Status;
-
- IDS_HDT_CONSOLE (FCH_TRACE, " FchInitEnv Enter... \n");
- FchParams = FchInitEnvCreatePrivateData (EnvParams);
-
- // Override internal data with IDS (Optional, internal build only)
- IDS_OPTION_CALLOUT (IDS_CALLOUT_FCH_INIT_ENV, FchParams, FchParams->StdHeader);
-
- //
- //to_do-Initialize PCI IRQ routing registers for INTA#-INTH#
- //
- for (i = 0; i < 8; i++) {
- Data = i | BIT7; // Select IRQ routing to APIC
- LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Data, &EnvParams->StdHeader);
- Data = i | BIT4;
- LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Data, &EnvParams->StdHeader);
- }
-
- AgesaFchOemCallout (FchParams);
- Status = FchTaskLauncher (&FchInitEnvTaskTable[0], FchParams);
- IDS_HDT_CONSOLE (FCH_TRACE, " FchInitEnv Exit... Status = [0x%x]\n", Status);
- return Status;
-}
-
-
-/**
- * A constructor for FCH build parameter structure at InitEnv stage
- *
- * Sets inputs to valid, basic level, defaults.
- *
- * @param[in,out] EnvParams InitEnv configuration data block
- *
- * @retval AGESA_SUCCESS Constructors are not allowed to fail
-*/
-AGESA_STATUS
-FchEnvConstructor (
- IN AMD_ENV_PARAMS *EnvParams
- )
-{
- EnvParams->FchInterface = FchInterfaceDefault;
- return AGESA_SUCCESS;
-}
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitLate.c
deleted file mode 100644
index 58e24f7d4f..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitLate.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * FCH Initialization.
- *
- * Init IOAPIC/IOMMU/Misc NB features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*;********************************************************************************
-;
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*********************************************************************************/
-
-#include "FchPlatform.h"
-#include "FchTaskLauncher.h"
-#include "heapManager.h"
-#include "Ids.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_INTERFACE_FCHINITLATE_FILECODE
-
-extern FCH_TASK_ENTRY *FchInitLateTaskTable[];
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * FchInitLate - Prepare Fch to boot to OS.
- *
- *
- *
- * @param[in] LateParams
- *
- */
-AGESA_STATUS
-FchInitLate (
- IN AMD_S3SAVE_PARAMS *LateParams
- )
-{
- FCH_DATA_BLOCK *FchParams;
- AGESA_STATUS Status;
-
- IDS_HDT_CONSOLE (FCH_TRACE, " FchInitLate Enter... \n");
- FchParams = FchInitLoadDataBlock (&LateParams->FchInterface, &LateParams->StdHeader);
- Status = FchTaskLauncher (&FchInitLateTaskTable[0], FchParams);
- IDS_HDT_CONSOLE (FCH_TRACE, " FchInitLate Exit... Status = [0x%x]\n", Status);
- return Status;
-}
-
-
-/**
- * A constructor for FCH build parameter structure at InitLate stage
- *
- * Sets inputs to valid, basic level, defaults.
- *
- * @param[in,out] LateParams
- *
- * @retval AGESA_SUCCESS Constructors are not allowed to fail
-*/
-AGESA_STATUS
-FchLateConstructor (
- IN AMD_LATE_PARAMS *LateParams
- )
-{
- return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitMid.c
deleted file mode 100644
index a259bde404..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitMid.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * FCH Initialization.
- *
- * Init IOAPIC/IOMMU/Misc NB features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*;********************************************************************************
-;
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*********************************************************************************/
-
-#include "FchPlatform.h"
-#include "FchTaskLauncher.h"
-#include "heapManager.h"
-#include "Ids.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_INTERFACE_FCHINITMID_FILECODE
-
-extern FCH_TASK_ENTRY *FchInitMidTaskTable[];
-
-/**
- * FchInitMid - Config Fch after PCI emulation
- *
- *
- *
- * @param[in] MidParams Fch configuration structure pointer.
- *
- */
-AGESA_STATUS
-FchInitMid (
- IN AMD_MID_PARAMS *MidParams
- )
-{
- FCH_DATA_BLOCK *FchParams;
- AGESA_STATUS Status;
-
- IDS_HDT_CONSOLE (FCH_TRACE, " FchInitMid Enter... \n");
- FchParams = FchInitLoadDataBlock (&MidParams->FchInterface, &MidParams->StdHeader);
- Status = FchTaskLauncher (&FchInitMidTaskTable[0], FchParams);
- IDS_HDT_CONSOLE (FCH_TRACE, " FchInitMid Exit... Status = [0x%x]\n", Status);
- return Status;
-}
-
-
-/**
- * A constructor for FCH build parameter structure at InitEnv stage
- *
- * Sets inputs to valid, basic level, defaults.
- *
- * @param[in] MidParams
- *
- * @retval AGESA_SUCCESS Constructors are not allowed to fail
-*/
-AGESA_STATUS
-FchMidConstructor (
- IN AMD_MID_PARAMS *MidParams
- )
-{
- return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitReset.c
deleted file mode 100644
index de64e18ebf..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitReset.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * FCH Init during Power-On Reset
- *
- * Prepare FCH environment during power on stage
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 49633 $ @e \$Date: 2011-03-26 06:52:29 +0800 (Sat, 26 Mar 2011) $
- *
- */
-/*;********************************************************************************
-;
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*********************************************************************************/
-
-#include "FchPlatform.h"
-#include "FchTaskLauncher.h"
-#include "heapManager.h"
-#include "Ids.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_INTERFACE_FCHINITRESET_FILECODE
-
-extern FCH_TASK_ENTRY *FchInitResetTaskTable[];
-extern FCH_RESET_INTERFACE FchResetInterfaceDefault;
-
-/**
- * FchInitReset - Config Fch during power on stage.
- *
- *
- *
- * @param[in] ResetParams
- *
- */
-AGESA_STATUS
-FchInitReset (
- IN AMD_RESET_PARAMS *ResetParams
- )
-{
- FCH_RESET_DATA_BLOCK FchParams;
-
- // Load private data block with default
- FchInitResetLoadPrivateDefault (&FchParams, &ResetParams->StdHeader);
-
- // Override external data with input parameters
- FchParams.StdHeader = &ResetParams->StdHeader;
- FchParams.FchReset = &ResetParams->FchInterface;
-
- // Override internal data with IDS (Optional, internal build only)
- IDS_OPTION_CALLOUT (IDS_CALLOUT_FCH_INIT_RESET, &FchParams, &ResetParams->StdHeader);
-
- AgesaFchOemCallout (&FchParams);
- return FchTaskLauncher (&FchInitResetTaskTable[0], &FchParams);
-}
-
-
-/**
- * A constructor for FCH build parameter structure at InitReset stage
- *
- * Sets inputs to valid, basic level, defaults.
- *
- * @param[in] ResetParams
- *
- * @retval AGESA_SUCCESS Constructors are not allowed to fail
-*/
-AGESA_STATUS
-FchResetConstructor (
- IN AMD_RESET_PARAMS *ResetParams
- )
-{
- ResetParams->FchInterface = FchResetInterfaceDefault;
- return AGESA_SUCCESS;
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitS3.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitS3.c
deleted file mode 100644
index 41fb5f8d6e..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitS3.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * FCH Initialization.
- *
- * Init IOAPIC/IOMMU/Misc NB features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*;********************************************************************************
-;
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*********************************************************************************/
-
-#include "FchPlatform.h"
-#include "FchTaskLauncher.h"
-#define FILECODE PROC_FCH_INTERFACE_FCHINITS3_FILECODE
-
-extern FCH_TASK_ENTRY *FchInitS3EarlyTaskTable[];
-extern FCH_TASK_ENTRY *FchInitS3LateTaskTable[];
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * FchInitS3EarlyRestore - Config Fch before ACPI S3 resume PCI config device restore
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-
-VOID
-FchInitS3EarlyRestore (
- IN FCH_DATA_BLOCK *FchDataPtr
- )
-{
- AGESA_STATUS AgesaStatus;
-
- FchDataPtr->Misc.S3Resume = 1;
- AgesaStatus = FchTaskLauncher (&FchInitS3EarlyTaskTable[0], FchDataPtr);
- FchDataPtr->Misc.S3Resume = 0;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * FchInitS3LateRestore - Config Fch after ACPI S3 resume PCI config device restore
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-
-VOID
-FchInitS3LateRestore (
- IN FCH_DATA_BLOCK *FchDataPtr
- )
-{
- AGESA_STATUS AgesaStatus;
-
- FchDataPtr->Misc.S3Resume = 1;
- AgesaStatus = FchTaskLauncher (&FchInitS3LateTaskTable[0], FchDataPtr);
- FchDataPtr->Misc.S3Resume = 0;
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchTaskLauncher.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchTaskLauncher.c
deleted file mode 100644
index f34f43b547..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchTaskLauncher.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * FCH task launcher
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#define FILECODE PROC_FCH_INTERFACE_FCHTASKLAUNCHER_FILECODE
-
-
-AGESA_STATUS
-FchTaskLauncher (
- IN FCH_TASK_ENTRY **TaskPtr,
- IN VOID *FchCfg
- )
-{
-// AGESA_STATUS AgesaStatus;
-
- while (*TaskPtr != NULL) {
- (*TaskPtr) (FchCfg);
- TaskPtr++;
- }
- return AGESA_SUCCESS;
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchTaskLauncher.h b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchTaskLauncher.h
deleted file mode 100644
index 3bca05cc8e..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchTaskLauncher.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * FCH task launcher
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#ifndef _FCH_TASK_LAUNCHER_H_
-#define _FCH_TASK_LAUNCHER_H_
-
-
-VOID
-FchInitResetLoadPrivateDefault (
- IN FCH_RESET_DATA_BLOCK *FchParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-FCH_DATA_BLOCK*
-FchInitEnvCreatePrivateData (
- IN AMD_ENV_PARAMS *EnvParams
- );
-
-FCH_DATA_BLOCK*
-FchInitLoadDataBlock (
- IN FCH_INTERFACE *FchInterface,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-FchTaskLauncher (
- IN FCH_TASK_ENTRY **TaskPtr,
- IN VOID *FchCfg
- );
-
-VOID
-FchInitS3EarlyRestore (
- IN FCH_DATA_BLOCK *FchDataPtr
- );
-
-VOID
-FchInitS3LateRestore (
- IN FCH_DATA_BLOCK *FchDataPtr
- );
-#endif
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/InitEnvDef.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/InitEnvDef.c
deleted file mode 100644
index 7566a4ba44..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/InitEnvDef.c
+++ /dev/null
@@ -1,170 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Fch Init during POWER-ON
- *
- * Prepare Fch environment during power on stage.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 49753 $ @e \$Date: 2011-03-29 04:51:46 +0800 (Tue, 29 Mar 2011) $
- *
- */
-/*;********************************************************************************
-;
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*********************************************************************************/
-
-#include "FchPlatform.h"
-#include "Ids.h"
-#include "heapManager.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_INTERFACE_INITENVDEF_FILECODE
-
-extern FCH_DATA_BLOCK InitEnvCfgDefault;
-
-FCH_DATA_BLOCK*
-FchInitLoadDataBlock (
- IN FCH_INTERFACE *FchInterface,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- FCH_DATA_BLOCK *FchParams;
- LOCATE_HEAP_PTR LocHeapPtr;
- AMD_CONFIG_PARAMS TempStdHeader;
- AGESA_STATUS AgesaStatus;
-
- TempStdHeader = *StdHeader;
- TempStdHeader.HeapStatus = HEAP_SYSTEM_MEM;
-
- // Locate the internal data block via heap manager
- LocHeapPtr.BufferHandle = AMD_FCH_DATA_BLOCK_HANDLE;
- AgesaStatus = HeapLocateBuffer (&LocHeapPtr, &TempStdHeader);
- ASSERT (!AgesaStatus);
-
- FchParams = (FCH_DATA_BLOCK *) LocHeapPtr.BufferPtr;
- ASSERT (FchParams != NULL);
- FchParams->StdHeader = StdHeader;
- return FchParams;
-}
-
-
-FCH_DATA_BLOCK*
-FchInitEnvCreatePrivateData (
- IN AMD_ENV_PARAMS *EnvParams
- )
-{
- FCH_DATA_BLOCK *FchParams;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
- AMD_CONFIG_PARAMS TempStdHeader;
- AGESA_STATUS AgesaStatus;
-
- TempStdHeader = EnvParams->StdHeader;
- TempStdHeader.HeapStatus = HEAP_SYSTEM_MEM;
-
- // First allocate internal data block via heap manager
- AllocHeapParams.RequestedBufferSize = sizeof (FCH_DATA_BLOCK);
- AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
- AllocHeapParams.BufferHandle = AMD_FCH_DATA_BLOCK_HANDLE;
- AgesaStatus = HeapAllocateBuffer (&AllocHeapParams, &TempStdHeader);
- ASSERT (!AgesaStatus);
-
- FchParams = (FCH_DATA_BLOCK *) AllocHeapParams.BufferPtr;
- ASSERT (FchParams != NULL);
- IDS_HDT_CONSOLE (FCH_TRACE, " FCH Data Block Allocation: [0x%x], Ptr = 0x%08x\n", AgesaStatus, FchParams);
-
- // Load private data block with default
- LibAmdMemCopy (
- (UINT8 *) FchParams,
- (UINT8 *) &InitEnvCfgDefault,
- sizeof (FCH_DATA_BLOCK),
- &EnvParams->StdHeader
- );
-
- // Update with external parameters
- FchParams->StdHeader = &EnvParams->StdHeader;
-
- FchParams->Sd.SdConfig = EnvParams->FchInterface.SdConfig;
- FchParams->Azalia.AzaliaEnable = EnvParams->FchInterface.AzaliaController;
- FchParams->Ir.IrConfig = EnvParams->FchInterface.IrConfig;
- FchParams->Ab.NbSbGen2 = EnvParams->FchInterface.UmiGen2;
- FchParams->Sata.SataClass = EnvParams->FchInterface.SataClass;
- FchParams->Sata.SataMode.SataEnable = EnvParams->FchInterface.SataEnable;
- FchParams->Sata.SataMode.IdeEnable = EnvParams->FchInterface.IdeEnable;
- FchParams->Sata.SataIdeMode = EnvParams->FchInterface.SataIdeMode;
- FchParams->Usb.Ohci1Enable = EnvParams->FchInterface.Ohci1Enable;
- FchParams->Usb.Ehci1Enable = EnvParams->FchInterface.Ohci1Enable;
- FchParams->Usb.Ohci2Enable = EnvParams->FchInterface.Ohci2Enable;
- FchParams->Usb.Ehci2Enable = EnvParams->FchInterface.Ohci2Enable;
- FchParams->Usb.Ohci3Enable = EnvParams->FchInterface.Ohci3Enable;
- FchParams->Usb.Ehci3Enable = EnvParams->FchInterface.Ohci3Enable;
- FchParams->Usb.Ohci4Enable = EnvParams->FchInterface.Ohci4Enable;
- FchParams->Usb.Xhci0Enable = EnvParams->FchInterface.XhciSwitch;
- FchParams->Usb.Xhci1Enable = EnvParams->FchInterface.XhciSwitch;
- FchParams->Gpp.GppFunctionEnable = EnvParams->FchInterface.GppEnable;
- FchParams->HwAcpi.PwrFailShadow = EnvParams->FchInterface.FchPowerFail;
-
- FchParams->HwAcpi.Smbus0BaseAddress = UserOptions.CfgSmbus0BaseAddress;
- FchParams->HwAcpi.Smbus1BaseAddress = UserOptions.CfgSmbus1BaseAddress;
- FchParams->HwAcpi.SioPmeBaseAddress = UserOptions.CfgSioPmeBaseAddress;
- FchParams->HwAcpi.AcpiPm1EvtBlkAddr = UserOptions.CfgAcpiPm1EvtBlkAddr;
- FchParams->HwAcpi.AcpiPm1CntBlkAddr = UserOptions.CfgAcpiPm1CntBlkAddr;
- FchParams->HwAcpi.AcpiPmTmrBlkAddr = UserOptions.CfgAcpiPmTmrBlkAddr;
- FchParams->HwAcpi.CpuControlBlkAddr = UserOptions.CfgCpuControlBlkAddr;
- FchParams->HwAcpi.AcpiGpe0BlkAddr = UserOptions.CfgAcpiGpe0BlkAddr;
- FchParams->HwAcpi.SmiCmdPortAddr = UserOptions.CfgSmiCmdPortAddr;
- FchParams->HwAcpi.AcpiPmaCntBlkAddr = UserOptions.CfgAcpiPmaCntBlkAddr;
- FchParams->HwAcpi.WatchDogTimerBase = UserOptions.CfgWatchDogTimerBase;
- FchParams->Sata.SataRaid5Ssid = UserOptions.CfgSataRaid5Ssid;
- FchParams->Sata.SataRaidSsid = UserOptions.CfgSataRaidSsid;
- FchParams->Sata.SataAhciSsid = UserOptions.CfgSataAhciSsid;
- FchParams->Sata.SataIdeSsid = UserOptions.CfgSataIdeSsid;
- FchParams->Gec.GecShadowRomBase = UserOptions.CfgGecShadowRomBase;
- FchParams->Spi.RomBaseAddress = UserOptions.CfgSpiRomBaseAddress;
- FchParams->Spi.LpcSsid = UserOptions.CfgLpcSsid;
- FchParams->Hpet.HpetBase = UserOptions.CfgHpetBaseAddress;
- FchParams->Azalia.AzaliaSsid = UserOptions.CfgAzaliaSsid;
- FchParams->Smbus.SmbusSsid = UserOptions.CfgSmbusSsid;
- FchParams->Ide.IdeSsid = UserOptions.CfgIdeSsid;
- FchParams->Usb.EhciSsid = UserOptions.CfgEhciSsid;
- FchParams->Usb.OhciSsid = UserOptions.CfgOhciSsid;
- FchParams->Gpp.GppLinkConfig = UserOptions.CfgFchGppLinkConfig;
- FchParams->Gpp.PortCfg[0].PortPresent = UserOptions.CfgFchGppPort0Present;
- FchParams->Gpp.PortCfg[1].PortPresent = UserOptions.CfgFchGppPort1Present;
- FchParams->Gpp.PortCfg[2].PortPresent = UserOptions.CfgFchGppPort2Present;
- FchParams->Gpp.PortCfg[3].PortPresent = UserOptions.CfgFchGppPort3Present;
- FchParams->Gpp.PortCfg[0].PortHotPlug = UserOptions.CfgFchGppPort0HotPlug;
- FchParams->Gpp.PortCfg[1].PortHotPlug = UserOptions.CfgFchGppPort1HotPlug;
- FchParams->Gpp.PortCfg[2].PortHotPlug = UserOptions.CfgFchGppPort2HotPlug;
- FchParams->Gpp.PortCfg[3].PortHotPlug = UserOptions.CfgFchGppPort3HotPlug;
-
-
- return FchParams;
-}
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/InitResetDef.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/InitResetDef.c
deleted file mode 100644
index a239aa4843..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/InitResetDef.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Fch Init during POWER-ON
- *
- * Prepare Fch environment during power on stage.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*;********************************************************************************
-;
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*********************************************************************************/
-
-#include "FchPlatform.h"
-#include "Ids.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_INTERFACE_INITRESETDEF_FILECODE
-
-extern FCH_RESET_DATA_BLOCK InitResetCfgDefault;
-
-VOID
-FchInitResetLoadPrivateDefault (
- IN FCH_RESET_DATA_BLOCK *FchParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- LibAmdMemCopy (
- (UINT8 *) FchParams,
- (UINT8 *) &InitResetCfgDefault,
- sizeof (FCH_RESET_DATA_BLOCK),
- StdHeader
- );
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Ir/IrEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Ir/IrEnv.c
deleted file mode 100644
index 5749f2a9c2..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Ir/IrEnv.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch Ir controller
- *
- * Init Ir Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 46088 $ @e \$Date: 2011-01-28 11:24:26 +0800 (Fri, 28 Jan 2011) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#define FILECODE PROC_FCH_IR_IRENV_FILECODE
-
-/**
- * FchInitEnvIr - Config Ir controller before PCI emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitEnvIr (
- IN VOID *FchDataPtr
- )
-{
- IR_CONFIG FchIrConfig;
- UINT8 Data;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
- FchIrConfig = LocalCfgPtr->Ir.IrConfig;
-
- //
- //IR init Logical device 0x05
- //
- if (FchIrConfig != IrDisable) {
- EnterEcConfig (StdHeader);
-
- RwEc8 (0x07, 0x00, 0x05, StdHeader); ///Select logical device 05, IR controller
- RwEc8 (0x60, 0x00, 0x05, StdHeader); ///Set Base Address to 550h
- RwEc8 (0x61, 0x00, 0x50, StdHeader);
- RwEc8 (0x70, 0xF0, 0x05, StdHeader); ///Set IRQ to 05h
- RwEc8 (0x30, 0x00, 0x01, StdHeader); ///Enable logical device 5, IR controller
-
- Data = 0xAB;
- LibAmdIoWrite (AccessWidth8, 0x550, &Data, StdHeader);
- LibAmdIoRead (AccessWidth8, 0x551, &Data, StdHeader);
- Data = (((Data & 0xFC ) | 0x20) | (UINT8) FchIrConfig);
- LibAmdIoWrite (AccessWidth8, 0x551, &Data, StdHeader);
-
- ExitEcConfig (StdHeader);
-
- Data = 0xA0; /// EC APIC index
- LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Data, StdHeader);
- Data = 0x05; /// IRQ5
- LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Data, StdHeader);
- } else {
- EnterEcConfig (StdHeader);
-
- RwEc8 (0x07, 0x00, 0x05, StdHeader); ///Select logical device 05, IR controller
- RwEc8 (0x30, 0x00, 0x00, StdHeader); ///Disable logical device 5, IR controller
-
- ExitEcConfig (StdHeader);
- }
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Ir/IrLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Ir/IrLate.c
deleted file mode 100644
index dfd4a3aa9a..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Ir/IrLate.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch Ir controller
- *
- * Init Ir Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#define FILECODE PROC_FCH_IR_IRLATE_FILECODE
-
-/**
- * FchInitLateIr - Prepare Ir controller to boot to OS.
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitLateIr (
- IN VOID *FchDataPtr
- )
-{
-}
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Ir/IrMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Ir/IrMid.c
deleted file mode 100644
index 2f7fbeb73e..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Ir/IrMid.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch Ir controller
- *
- * Init Ir Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#define FILECODE PROC_FCH_IR_IRMID_FILECODE
-
-/**
- * FchInitMidIr - Config Ir controller after PCI emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitMidIr (
- IN VOID *FchDataPtr
- )
-{
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Oem.h b/src/vendorcode/amd/agesa/f12/Proc/Fch/Oem.h
deleted file mode 100644
index 5e2fad9279..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Oem.h
+++ /dev/null
@@ -1,141 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * FCH oem definition
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44854 $ @e \$Date: 2011-01-07 16:48:51 +0800 (Fri, 07 Jan 2011) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#define ACPI_SLEEP_TRAP 0x01
-
-/**
- * Module Specific Defines for platform BIOS
- *
- */
-
-/**
- * PCIEX_BASE_ADDRESS - Define PCIE base address
- *
- * Option MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000
- */
-#ifdef MOVE_PCIEBAR_TO_F0000000
- #define PCIEX_BASE_ADDRESS 0xF7000000
-#else
- #define PCIEX_BASE_ADDRESS 0xE0000000
-#endif
-
-#define SATA_IDE_MODE_SSID 0x78001022
-/**
- * SATA_RAID_MODE_SSID - Sata controller RAID mode SSID.
- * Define value for SSID while SATA controller set to RAID mode.
- */
-#define SATA_RAID_MODE_SSID 0x78021022
-
-/**
- * SATA_RAID5_MODE_SSID - Sata controller RAID5 mode SSID.
- * Define value for SSID while SATA controller set to RAID5 mode.
- */
-#define SATA_RAID5_MODE_SSID 0x78031022
-
-/**
- * SATA_AHCI_MODE_SSID - Sata controller AHCI mode SSID.
- * Define value for SSID while SATA controller set to AHCI mode.
- */
-#define SATA_AHCI_SSID 0x78011022
-
-/**
- * OHCI_SSID - All FCH OHCI controllers SSID value.
- *
- */
-#define OHCI_SSID 0x78071022
-
-/**
- * EHCI_SSID - All FCH EHCI controllers SSID value.
- *
- */
-#define EHCI_SSID 0x78081022
-
-/**
- * OHCI4_SSID - OHCI (USB 1.1 mode *HW force) controllers SSID value.
- *
- */
-#define OHCI4_SSID 0x78091022
-
-/**
- * SMBUS_SSID - Smbus controller (South Bridge device 0x14 function 0) SSID value.
- *
- */
-#define SMBUS_SSID 0x780B1022
-
-/**
- * IDE_SSID - SATA IDE controller (South Bridge device 0x14 function 1) SSID value.
- *
- */
-#define IDE_SSID 0x780C1022
-
-/**
- * AZALIA_SSID - AZALIA controller (South Bridge device 0x14 function 2) SSID value.
- *
- */
-#define AZALIA_SSID 0x780D1022
-
-/**
- * LPC_SSID - LPC controller (South Bridge device 0x14 function 3) SSID value.
- *
- */
-#define LPC_SSID 0x780E1022
-
-/**
- * PCIB_SSID - PCIB controller (South Bridge device 0x14 function 4) SSID value.
- *
- */
-#define PCIB_SSID 0x780F1022
-
-
-#ifndef XHCI_SUPPORT
- #define FCH_NO_XHCI_SUPPORT TRUE
-#endif
-
-#ifdef NO_EC_SUPPORT
- #define FCH_NO_IMC_SUPPORT TRUE
-#endif
-
-#ifdef NO_EC_SUPPORT
- #define FCH_NO_HWM_SUPPORT TRUE
-#endif
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcib/PcibEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcib/PcibEnv.c
deleted file mode 100644
index e8036d6a46..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcib/PcibEnv.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch Pcib controller
- *
- * Init Pcib Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#define FILECODE PROC_FCH_PCIB_PCIBENV_FILECODE
-
-/**
- * FchInitEnvPcibPciTable - PCI device registers initial during
- * early POST.
- *
- */
-REG8_MASK FchInitEnvPcibPciTable[] =
-{
- //
- // PCIB Bridge (Bus 0, Dev 20, Func 4)
- //
- {0x00, PCIB_BUS_DEV_FUN, 0},
- {FCH_PCIB_REG40, 0xFF, BIT5}, /// PCI-bridge Subtractive Decode
- {FCH_PCIB_REG4B, 0xFF, BIT7}, ///
- {FCH_PCIB_REG66, 0xFF, BIT4}, /// Enabling One-Prefetch-Channel Mode, PCIB_PCI_config 0x64 [20]
- {FCH_PCIB_REG65, 0xFF, BIT7}, /// proper operation of CLKRUN#.
- {FCH_PCIB_REG0D, 0x00, 0x40}, /// Setting Latency Timers to 0x40, Enables the PCIB to retain ownership
- {FCH_PCIB_REG1B, 0x00, 0x40}, /// of the bus on the Primary side and on the Secondary side when GNT# is deasserted.
- {FCH_PCIB_REG66 + 1, 0xFF, BIT1}, /// Enable PCI bus GNT3#..
- {0xFF, 0xFF, 0xFF},
-};
-
-/**
- * FchInitEnvPcib - Config Pcib controller before PCI emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitEnvPcib (
- IN VOID *FchDataPtr
- )
-{
- UINT8 VerbPciClks;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- //
- //Early post initialization of pci config space
- //
- ProgramPciByteTable ((REG8_MASK*) (&FchInitEnvPcibPciTable[0]), sizeof (FchInitEnvPcibPciTable) / sizeof (REG8_MASK), StdHeader);
-
- //
- //Disable or Enable PCI Clks based on input
- //
- VerbPciClks = ((LocalCfgPtr->Pcib.PciClks & 0x0F) << 2);
-
- RwPci ((PCIB_BUS_DEV_FUN << 16) + FCH_PCIB_REG42, AccessWidth8, ~(BIT5 + BIT4 + BIT3 + BIT2), VerbPciClks, StdHeader);
-
- //
- // PCIB MSI
- //
- if (LocalCfgPtr->Pcib.PcibMsiEnable) {
- RwPci ((PCIB_BUS_DEV_FUN << 16) + FCH_PCIB_REG40, AccessWidth8, ~BIT3, BIT3, StdHeader);
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcib/PcibLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcib/PcibLate.c
deleted file mode 100644
index 0ae3d3a880..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcib/PcibLate.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch Pcib controller
- *
- * Init Pcib Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#define FILECODE PROC_FCH_PCIB_PCIBLATE_FILECODE
-
-/**
- * FchInitLatePcib - Prepare Pcib controller to boot to OS.
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitLatePcib (
- IN VOID *FchDataPtr
- )
-{
- UINT8 Value;
- UINT8 NStBit;
- UINT8 NSBit;
- UINT32 VarDd;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- //
- // We need to do the following setting in late post also because some bios core pci enumeration changes these values
- // programmed during early post.
- // Master Latency Timer
- //
- Value = 0x40;
- WritePci ((PCIB_BUS_DEV_FUN << 16) + FCH_PCIB_REG0D, AccessWidth8, &Value, StdHeader);
- WritePci ((PCIB_BUS_DEV_FUN << 16) + FCH_PCIB_REG1B, AccessWidth8, &Value, StdHeader);
-
- //
- // CLKRUN#
- // FCH P2P AutoClock control settings.
- // VarDd = (FchDataPtr->PcibAutoClkCtrlLow) | (FchDataPtr->PcibAutoClkCtrlLow);
- //
- if ( LocalCfgPtr->Pcib.PcibClockRun ) {
- ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG54, AccessWidth8, &Value);
- NStBit = Value & 0x03;
- NSBit = (Value & 0x3F ) >> 2;
- VarDd = (4 + (NStBit * 2) + (( 17 + NSBit) * 3) + 4) | 0x01;
-
- VarDd = 9; // for A12
- WritePci ((PCIB_BUS_DEV_FUN << 16) + FCH_PCIB_REG4C, AccessWidth32, &VarDd, StdHeader);
- }
-
- VarDd = (LocalCfgPtr->Pcib.PcibClkStopOverride);
- RwPci ((PCIB_BUS_DEV_FUN << 16) + FCH_PCIB_REG50, AccessWidth16, 0x3F, (UINT16) (VarDd << 6), StdHeader);
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcib/PcibMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcib/PcibMid.c
deleted file mode 100644
index 297db243ff..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcib/PcibMid.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch Pcib controller
- *
- * Init Pcib Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#define FILECODE PROC_FCH_PCIB_PCIBMID_FILECODE
-
-/**
- * FchInitMidPcib - Config Pcib controller after PCI emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitMidPcib (
- IN VOID *FchDataPtr
- )
-{
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcib/PcibReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcib/PcibReset.c
deleted file mode 100644
index 20c1a552a2..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcib/PcibReset.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch Pcib controller
- *
- * Init Pcib Controller features (PEI phase).
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 48244 $ @e \$Date: 2011-03-05 12:39:46 +0800 (Sat, 05 Mar 2011) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#define FILECODE PROC_FCH_PCIB_PCIBRESET_FILECODE
-/**
- * FchInitResetPcibPciTable - Pcib device registers initial
- * during the power on stage.
- *
- *
- *
- *
- */
-REG8_MASK FchInitResetPcibPciTable[] =
-{
- //
- // P2P Bridge (Bus 0, Dev 20, Func 4)
- //
- {0x00, PCIB_BUS_DEV_FUN, 0},
- {FCH_PCIB_REG4B, 0xFF, BIT6 + BIT7 + BIT4},
- // ENH230012: Disable P2P bridge decoder for IO address 0x1000-0x1FFF in Reset
- // ENH261115: Add PCI port 80 support in Hudson-2/3. Platform bios define SB_PCIB_PORT_80_SUPPORT to support it
-#ifdef SB_PCIB_PORT_80_SUPPORT
- {FCH_PCIB_REG1C, 0x00, 0xF0},
- {FCH_PCIB_REG1D, 0x00, 0x00},
- {FCH_PCIB_REG04, 0x00, 0x21},
-#endif
- {FCH_PCIB_REG40, 0xDF, 0x20},
- {FCH_PCIB_REG50, 0x02, 0x01},
- {0xFF, 0xFF, 0xFF},
-};
-
-/**
- * FchInitResetPcib - Config Pcib controller during Power-On
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitResetPcib (
- IN VOID *FchDataPtr
- )
-{
- AMD_CONFIG_PARAMS *StdHeader;
-
- StdHeader = &((AMD_RESET_PARAMS *)FchDataPtr)->StdHeader;
-
- ProgramPciByteTable (
- (REG8_MASK*) (&FchInitResetPcibPciTable[0]),
- sizeof (FchInitResetPcibPciTable) / sizeof (REG8_MASK),
- StdHeader
- );
-}
-
-/**
- * FchInitRecoveryPcib - Config Pcib controller during Crisis
- * Recovery
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitRecoveryPcib (
- IN VOID *FchDataPtr
- )
-{
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbEnv.c
deleted file mode 100644
index 98b87e5291..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbEnv.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch Ab Bridge
- *
- * Init Ab Bridge features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_PCIE_ABENV_FILECODE
-
-/**
- * FchInitEnvAb - Config Ab Bridge before PCI emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitEnvAb (
- IN VOID *FchDataPtr
- )
-{
- FchInitEnvAbLinkInit (FchDataPtr);
-}
-
-/**
- * FchInitEnvAbSpecial - Config Ab Bridge special timing
- *
- * This routine must separate with FchInitEnvAb and give Ab
- * bridge little time to get ready
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitEnvAbSpecial (
- IN VOID *FchDataPtr
- )
-{
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbLate.c
deleted file mode 100644
index 1c59cd8e1c..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbLate.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch Ab Bridge
- *
- * Init Ab Bridge features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_PCIE_ABLATE_FILECODE
-
-/**
- * FchInitLateAb - Prepare Ab Bridge to boot to OS.
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitLateAb (
- IN VOID *FchDataPtr
- )
-{
- UINT32 AbValue;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- AbValue = ReadAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), StdHeader);
- AbValue &= 0xf0;
-
- if ( LocalCfgPtr->Ab.PcieOrderRule && AbValue ) {
- AbValue = ReadAlink (FCH_RCINDXC_REG02 | (UINT32) (RCINDXC << 29), StdHeader);
- AbValue = AbValue | BIT9;
- WriteAlink (FCH_RCINDXC_REG02 | (UINT32) (RCINDXC << 29), AbValue, StdHeader);
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbMid.c
deleted file mode 100644
index 718fd03beb..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbMid.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch Ab Bridge
- *
- * Init Ab Bridge features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_PCIE_ABMID_FILECODE
-
-/**
- * FchInitMidAb - Config Ab Bridge after PCI emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitMidAb (
- IN VOID *FchDataPtr
- )
-{
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbReset.c
deleted file mode 100644
index 5165b33d54..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbReset.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch Ab Bridge
- *
- * Init Ab Bridge features (PEI phase).
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 45603 $ @e \$Date: 2011-01-19 14:29:05 +0800 (Wed, 19 Jan 2011) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#include "FchDef.h"
-#define FILECODE PROC_FCH_PCIE_ABRESET_FILECODE
-
-/**
- * FchInitResetAb - Config Ab Bridge during Power-On
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitResetAb (
- IN VOID *FchDataPtr
- )
-{
- FchProgramAbPowerOnReset (FchDataPtr);
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbEnvService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbEnvService.c
deleted file mode 100644
index 034ab05dfe..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbEnvService.c
+++ /dev/null
@@ -1,360 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Hudson2 AB
- *
- * Init AB bridge.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 48048 $ @e \$Date: 2011-03-03 10:13:06 +0800 (Thu, 03 Mar 2011) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABENVSERVICE_FILECODE
-
-//
-// Declaration of local functions
-//
-VOID AbCfgTbl (IN AB_TBL_ENTRY *ABTbl, IN AMD_CONFIG_PARAMS *StdHeader);
-
-/**
- * Hudson2PcieOrderRule - AB-Link Configuration Table for ablink
- * Post Pass Np Downstream/Upstream Feature
- *
- */
-AB_TBL_ENTRY Hudson2PcieOrderRule[] =
-{
- //
- // abPostPassNpDownStreamTbl
- //
- {ABCFG, FCH_ABCFG_REG10060, BIT31, BIT31},
- {ABCFG, FCH_ABCFG_REG1009C, BIT4 + BIT5, BIT4 + BIT5},
- {ABCFG, FCH_ABCFG_REG9C, BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7, BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7},
- {ABCFG, FCH_ABCFG_REG90, BIT21 + BIT22 + BIT23, BIT21 + BIT22 + BIT23},
- {ABCFG, FCH_ABCFG_REGF0, BIT6 + BIT5, BIT6 + BIT5},
- {AXINDC, FCH_AX_INDXC_REG02, BIT9, BIT9},
- {ABCFG, FCH_ABCFG_REG10090, BIT9 + BIT10 + BIT11 + BIT12, BIT9 + BIT10 + BIT11 + BIT12},
-
- //
- // abPostPassNpUpStreamTbl
- //
- {ABCFG, FCH_ABCFG_REG58, BIT10, BIT10},
- {ABCFG, FCH_ABCFG_REGF0, BIT3 + BIT4, BIT3 + BIT4},
- {ABCFG, FCH_ABCFG_REG54, BIT1, BIT1},
- { (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF},
-};
-
-/**
- * Hudson2InitEnvAbTable - AB-Link Configuration Table for Hudson2
- *
- */
-AB_TBL_ENTRY Hudson2InitEnvAbTable[] =
-{
- //
- // Enable downstream posted transactions to pass non-posted transactions.
- //
- {ABCFG, FCH_ABCFG_REG10090, BIT8 + BIT16, BIT8 + BIT16},
-
- //
- // Enable Hudson-2 to issue memory read/write requests in the upstream direction.
- //
- {AXCFG, FCH_AB_REG04, BIT2, BIT2},
-
- //
- // Enabling IDE/PCIB Prefetch for Performance Enhancement
- // PCIB prefetch ABCFG 0x10060 [20] = 1 ABCFG 0x10064 [20] = 1
- //
- {ABCFG, FCH_ABCFG_REG10060, BIT20, BIT20}, /// PCIB prefetch enable
- {ABCFG, FCH_ABCFG_REG10064, BIT20, BIT20}, /// PCIB prefetch enable
-
- //
- // Controls the USB OHCI controller prefetch used for enhancing performance of ISO out devices.
- // Setting B-Link Prefetch Mode (ABCFG 0x80 [18:17] = 11)
- //
- {ABCFG, FCH_ABCFG_REG80, BIT0 + BIT17 + BIT18, BIT0 + BIT17 + BIT18},
-
- //
- // Enabled SMI ordering enhancement. ABCFG 0x90[21]
- // USB Delay A-Link Express L1 State. ABCFG 0x90[17]
- //
- {ABCFG, FCH_ABCFG_REG90, BIT21 + BIT17, BIT21 + BIT17},
-
- //
- // Disable the credit variable in the downstream arbitration equation
- // Register bit to qualify additional address bits into downstream register programming. (A12 BIT1 default is set)
- //
- {ABCFG, FCH_ABCFG_REG9C, BIT0, BIT0},
-
- //
- // Enabling Detection of Upstream Interrupts ABCFG 0x94 [20] = 1
- // ABCFG 0x94 [19:0] = cpu interrupt delivery address [39:20]
- //
- {ABCFG, FCH_ABCFG_REG94, BIT20, BIT20 + 0x00FEE},
-
- //
- // Programming cycle delay for AB and BIF clock gating
- // Enable the AB and BIF clock-gating logic.
- // Enable the A-Link int_arbiter enhancement to allow the A-Link bandwidth to be used more efficiently
- // Enable the requester ID for upstream traffic. [16]: SB/NB link [17]: GPP
- //
- {ABCFG, FCH_ABCFG_REG10054, 0x00FFFFFF, 0x010407FF},
- {ABCFG, FCH_ABCFG_REG98, 0xFFFC00FF, 0x00034700},
- {ABCFG, FCH_ABCFG_REG54, 0x00FF0000, 0x00040000},
-
- //
- // Non-Posted Memory Write Support
- //
- {AXINDC, FCH_AX_INDXC_REG10, BIT9, BIT9},
-
- //
- // UMI L1 Configuration
- //Step 1: AXINDC_Reg 0x02[0] = 0x1 Set REGS_DLP_IGNORE_IN_L1_EN to ignore DLLPs during L1 so that txclk can be turned off.
- //Step 2: AXINDP_Reg 0x02[15] = 0x1 Sets REGS_LC_ALLOW_TX_L1_CONTROL to allow TX to prevent LC from going to L1 when there are outstanding completions.
- //
- {AXINDC, FCH_AX_INDXC_REG02, BIT0, BIT0},
- {AXINDP, FCH_AX_INDXP_REG02, BIT15, BIT15},
- {ABCFG, 0, 0, (UINT8) 0xFF}, /// This dummy entry is to clear ab index
- { (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF},
-};
-
-/**
- * FchInitEnvAbLinkInit - Set ABCFG registers before PCI
- * emulation.
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitEnvAbLinkInit (
- IN VOID *FchDataPtr
- )
-{
- UINT32 AbValue;
- UINT16 AbTempVar;
- UINT8 AbValue8;
- UINT8 FchALinkClkGateOff;
- UINT8 FchBLinkClkGateOff;
- UINT32 FchResetCpuOnSyncFlood;
- AB_TBL_ENTRY *AbTblPtr;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- FchALinkClkGateOff = (UINT8) LocalCfgPtr->Ab.ALinkClkGateOff;
- FchBLinkClkGateOff = (UINT8) LocalCfgPtr->Ab.BLinkClkGateOff;
- //
- // AB CFG programming
- //
- if ( LocalCfgPtr->Ab.SlowSpeedAbLinkClock ) {
- RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40, AccessWidth8, ~BIT1, BIT1);
- } else {
- RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40, AccessWidth8, ~BIT1, 0);
- }
-
- //
- // Read Arbiter address, Arbiter address is in PMIO 6Ch
- //
- ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6C, AccessWidth16, &AbTempVar);
- /// Write 0 to enable the arbiter
- AbValue8 = 0;
- LibAmdIoWrite (AccessWidth8, AbTempVar, &AbValue8, StdHeader);
-
-
- FchResetCpuOnSyncFlood = LocalCfgPtr->Ab.ResetCpuOnSyncFlood;
-
- if ( LocalCfgPtr->Ab.PcieOrderRule == 1 ) {
- AbTblPtr = (AB_TBL_ENTRY *) (&Hudson2PcieOrderRule[0]);
- AbCfgTbl (AbTblPtr, StdHeader);
- }
-
- if ( LocalCfgPtr->Ab.PcieOrderRule == 2 ) {
- RwAlink (FCH_ABCFG_REG10090 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x7 << 10), (UINT32) (0x7 << 10), StdHeader);
- RwAlink (FCH_ABCFG_REG58 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1F << 11), (UINT32) (0x1C << 11), StdHeader);
- RwAlink (FCH_ABCFG_REGB4 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x3 << 0), (UINT32) (0x3 << 0), StdHeader);
- }
-
- AbTblPtr = (AB_TBL_ENTRY *) (&Hudson2InitEnvAbTable[0]);
- AbCfgTbl (AbTblPtr, StdHeader);
-
- if ( FchResetCpuOnSyncFlood ) {
- RwAlink (FCH_ABCFG_REG10050 | (UINT32) (ABCFG << 29), ~BIT2, BIT2, StdHeader);
- }
-
- if ( LocalCfgPtr->Ab.AbClockGating ) {
- RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16), StdHeader);
- RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16), StdHeader);
- RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x1 << 24), StdHeader);
- RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x1 << 24), StdHeader);
- } else {
- RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x0 << 24), StdHeader);
- RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x0 << 24), StdHeader);
- }
-
-
- if ( LocalCfgPtr->Ab.GppClockGating ) {
- RwAlink (FCH_ABCFG_REG98 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xF << 12), (UINT32) (0x4 << 12), StdHeader);
- RwAlink (FCH_ABCFG_REG98 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xF << 8), (UINT32) (0x7 << 8), StdHeader);
- RwAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 0), (UINT32) (0x1 << 0), StdHeader);
- } else {
- RwAlink (FCH_ABCFG_REG98 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xF << 8), (UINT32) (0x0 << 8), StdHeader);
- RwAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 0), (UINT32) (0x0 << 0), StdHeader);
- }
-
- if ( LocalCfgPtr->Ab.UmiL1TimerOverride ) {
- RwAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x7 << 12), (UINT32) (LocalCfgPtr->Ab.UmiL1TimerOverride << 12), StdHeader);
- RwAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 15), (UINT32) (0x1 << 15), StdHeader);
- }
-
- if ( LocalCfgPtr->Ab.UmiLinkWidth ) {
-// RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16));
- }
-
- if ( LocalCfgPtr->Ab.UmiDynamicSpeedChange ) {
- RwAlink ((UINT32) FCH_AX_INDXP_REGA4, ~ (UINT32) (0x1 << 0), (UINT32) (0x1 << 0), StdHeader);
- RwAlink ((UINT32) FCH_AX_CFG_REG88, ~ (UINT32) (0xF << 0), (UINT32) (0x2 << 0), StdHeader);
- RwAlink ((UINT32) FCH_AX_INDXP_REGA4, ~ (UINT32) (0x1 << 18), (UINT32) (0x1 << 18), StdHeader);
- }
-
- if ( LocalCfgPtr->Ab.PcieRefClockOverClocking ) {
-// RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16));
- }
-
- if ( LocalCfgPtr->Ab.UmiGppTxDriverStrength ) {
- RwAlink (FCH_ABCFG_REGA8 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x3 << 18), (UINT32) ((LocalCfgPtr->Ab.UmiGppTxDriverStrength - 1) << 18), StdHeader);
- RwAlink (FCH_ABCFG_REGA0 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 8), (UINT32) (0x1 << 8), StdHeader);
- }
-
- if ( LocalCfgPtr->Gpp.PcieAer ) {
-// RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16));
- }
-
- if ( LocalCfgPtr->Gpp.PcieRas ) {
-// RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16));
- }
-
- //
- // Ab Bridge MSI
- //
- if ( LocalCfgPtr->Ab.AbMsiEnable) {
- AbValue = ReadAlink (FCH_ABCFG_REG94 | (UINT32) (ABCFG << 29), StdHeader);
- AbValue = AbValue | BIT20;
- WriteAlink (FCH_ABCFG_REG94 | (UINT32) (ABCFG << 29), AbValue, StdHeader);
- }
-
- //
- // A/B Clock Gate-OFF
- //
- if ( FchALinkClkGateOff ) {
- RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x2E, AccessWidth8, 0xFE, BIT0);
- } else {
- RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x2E, AccessWidth8, 0xFE, 0x00);
- }
-
- if ( FchBLinkClkGateOff ) {
- //RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x2D, AccessWidth8, 0xEF, 0x10); /// A11 Only
- RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x2E, AccessWidth8, 0xFD, BIT1);
- } else {
- RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x2E, AccessWidth8, 0xFD, 0x00);
- }
-}
-
-/**
- * AbCfgTbl - Program ABCFG by input table.
- *
- *
- * @param[in] ABTbl ABCFG config table.
- * @param[in] StdHeader
- *
- */
-VOID
-AbCfgTbl (
- IN AB_TBL_ENTRY *ABTbl,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 AbValue;
-
- while ( (ABTbl->RegType) != 0xFF ) {
- if ( ABTbl->RegType == AXINDC ) {
- AbValue = 0x30 | (ABTbl->RegType << 29);
- WriteAlink (AbValue, (ABTbl->RegIndex & 0x00FFFFFF), StdHeader);
- AbValue = 0x34 | (ABTbl->RegType << 29);
- WriteAlink (AbValue, ((ReadAlink (AbValue, StdHeader)) & (0xFFFFFFFF^ (ABTbl->RegMask))) | ABTbl->RegData, StdHeader);
- } else if ( ABTbl->RegType == AXINDP ) {
- AbValue = 0x38 | (ABTbl->RegType << 29);
- WriteAlink (AbValue, (ABTbl->RegIndex & 0x00FFFFFF), StdHeader);
- AbValue = 0x3C | (ABTbl->RegType << 29);
- WriteAlink (AbValue, ((ReadAlink (AbValue, StdHeader)) & (0xFFFFFFFF^ (ABTbl->RegMask))) | ABTbl->RegData, StdHeader);
- } else {
- AbValue = ABTbl->RegIndex | (ABTbl->RegType << 29);
- WriteAlink (AbValue, ((ReadAlink (AbValue, StdHeader)) & (0xFFFFFFFF^ (ABTbl->RegMask))) | ABTbl->RegData, StdHeader);
- }
-
- ++ABTbl;
- }
-
- //
- //Clear ALink Access Index
- //
- AbValue = 0;
- LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &AbValue, StdHeader);
-}
-
-/**
- * Is UMI One Lane GEN1 Mode?
- *
- *
- * @retval TRUE or FALSE
- *
- */
-BOOLEAN
-IsUmiOneLaneGen1Mode (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 AbValue;
-
- AbValue = ReadAlink ((UINT32) (FCH_AX_CFG_REG68), StdHeader);
- AbValue >>= 16;
- if (((AbValue & 0x0f) == 1) && ((AbValue & 0x03f0) == 0x0010)) {
- return (TRUE);
- } else {
- return (FALSE);
- }
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbResetService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbResetService.c
deleted file mode 100644
index 366adfd160..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbResetService.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Hudson2 AB
- *
- * Init AB bridge.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 47163 $ @e \$Date: 2011-02-16 07:23:13 +0800 (Wed, 16 Feb 2011) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABRESETSERVICE_FILECODE
-
-
-/**
- * FchProgramAbPowerOnReset - Config Ab Bridge during Power-On
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchProgramAbPowerOnReset (
- IN VOID *FchDataPtr
- )
-{
- UINT32 AbValue;
- FCH_RESET_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
- UINT8 EfuseValue;
-
- LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- //
- // Set A-Link bridge access address.
- // This is an I/O address. The I/O address must be on 16-byte boundary.
- //
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGE0, AccessWidth32, 00, ALINK_ACCESS_INDEX);
-
- //
- // Enable Hudson-2 to issue memory read/write requests in the upstream direction
- //
- WriteAlink (0x80000004, 0x04, StdHeader);
-
- //
- // Disable the credit variable in the downstream arbitration equation
- //
- AbValue = ReadAlink (FCH_ABCFG_REG9C | (UINT32) (ABCFG << 29), StdHeader);
- AbValue = AbValue | BIT0;
- WriteAlink (FCH_ABCFG_REG9C | (UINT32) (ABCFG << 29), AbValue, StdHeader);
-
- //
- // AXINDC 0x10[9]=1, Enabling Non-Posted memory write for K8 platform.
- //
- WriteAlink (0x30, 0x10, StdHeader);
- WriteAlink (0x34, ReadAlink (0x34, StdHeader) | BIT9, StdHeader);
-
- RwAlink (FCH_ABCFG_REG10050 | (UINT32) (ABCFG << 29), ~BIT2, 0x00, StdHeader);
-
- //
- // Configure UMI target link speed
- //
- EfuseValue = PCIE_FORCE_GEN1_EFUSE_LOCATION;
- GetEfuseStatus (&EfuseValue, StdHeader);
- if ( EfuseValue & BIT0 ) {
- LocalCfgPtr->NbSbGen2 = 0;
- }
-
- EfuseValue = FCH_Variant_EFUSE_LOCATION;
- GetEfuseStatus (&EfuseValue, StdHeader);
- if ((EfuseValue == 0x07) || (EfuseValue == 0x08)) {
- LocalCfgPtr->NbSbGen2 = 0;
- }
-
- if (LocalCfgPtr->NbSbGen2) {
- AbValue = 2;
- } else {
- AbValue = 1;
- }
- RwAlink ((UINT32)FCH_AX_CFG_REG88, 0xFFFFFFF0, AbValue, StdHeader);
-
- if (LocalCfgPtr->NbSbGen2) {
- AbValue = BIT0;
- } else {
- AbValue = 0;
- }
- RwAlink (FCH_AX_INDXP_REGA4, 0xFFFFFFFE, AbValue, StdHeader);
-
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbService.c
deleted file mode 100644
index f5e9c94437..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbService.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Hudson2 AB
- *
- * Init AB bridge.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABSERVICE_FILECODE
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppResetService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppResetService.c
deleted file mode 100644
index 16fcde15b5..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppResetService.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Hudson2 Pcie controller
- *
- * Init GPP (pcie Controller) features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44855 $ @e \$Date: 2011-01-07 16:51:55 +0800 (Fri, 07 Jan 2011) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2GPPRESETSERVICE_FILECODE
-
-
-/**
- * ProgramFchGppInitReset - Config Gpp at PowerOnReset
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-ProgramFchGppInitReset (
- IN VOID *FchDataPtr
- )
-{
- FCH_RESET_DATA_BLOCK *LocalCfgPtr;
- LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
-
- //
- // Toggle GEVENT4 to reset all GPP devices
- //
- ProgramGppTogglePcieReset (LocalCfgPtr->GppToggleReset, LocalCfgPtr->StdHeader);
- if (LocalCfgPtr->SerialDebugBusEnable) {
- RwAlink (FCH_ABCFG_REGC0, (UINT32) (ABCFG << 29), ~BIT12, 0x00);
- }
-}
-
-/**
- * FchResetPcie - Toggle GEVENT4 to assert/deassert GPP device
- * reset
- *
- *
- * @param[in] ResetBlock - PCIE reset for FCH GPP or NB PCIE
- * @param[in] ResetOp - Assert or deassert PCIE reset
- * @param[in] StdHeader
- *
- */
-VOID
-FchResetPcie (
- IN RESET_BLOCK ResetBlock,
- IN RESET_OP ResetOp,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 Or8;
- UINT8 Mask8;
-
- if (ResetBlock == NbBlock) {
- if (ResetOp == AssertReset) {
- Or8 = BIT4;
- Mask8 = 0;
- LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC4), &Or8, &Mask8, StdHeader);
- } else if (ResetOp == DeassertReset) {
- Or8 = 0;
- Mask8 = BIT4;
- LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC4), &Or8, &Mask8, StdHeader);
- }
- } else if (ResetBlock == FchBlock) {
- Or8 = BIT1;
- Mask8 = BIT1 + BIT0;
- LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GEVENT_REG04), &Or8, &Mask8, StdHeader);
- if (ResetOp == AssertReset) {
- Or8 = 0;
- Mask8 = BIT5;
- LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + GPIO_BASE + FCH_GEVENT_REG04), &Or8, &Mask8, StdHeader);
- Or8 = BIT4;
- Mask8 = 0;
- LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBF), &Or8, &Mask8, StdHeader);
- } else if (ResetOp == DeassertReset) {
- Or8 = 0;
- Mask8 = BIT4;
- LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBF), &Or8, &Mask8, StdHeader);
- Or8 = BIT5;
- Mask8 = 0;
- LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + GPIO_BASE + FCH_GEVENT_REG04), &Or8, &Mask8, StdHeader);
- }
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppService.c
deleted file mode 100644
index fc26d97151..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppService.c
+++ /dev/null
@@ -1,207 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Hudson2 Pcie controller
- *
- * Init GPP (pcie Controller) features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 49633 $ @e \$Date: 2011-03-26 06:52:29 +0800 (Sat, 26 Mar 2011) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Ids.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2GPPSERVICE_FILECODE
-
-/**
- * ProgramGppTogglePcieReset - Toggle PCIE_RST2#
- *
- *
- * @param[in] DoToggling
- * @param[in] StdHeader
- *
- */
-VOID
-ProgramGppTogglePcieReset (
- IN BOOLEAN DoToggling,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- if (DoToggling) {
- FchResetPcie (FchBlock, AssertReset, StdHeader);
- FchStall (500, StdHeader);
- FchResetPcie (FchBlock, DeassertReset, StdHeader);
- } else {
- RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GEVENT_REG04, AccessWidth8, ~(BIT1 + BIT0), 0x02);
- }
-}
-
-/**
- * FchGppDynamicPowerSaving - GPP Dynamic Power Saving
- *
- *
- * @param[in] FchDataPtr
- *
- */
-VOID
-FchGppDynamicPowerSaving (
- IN VOID *FchDataPtr
- )
-{
- FCH_GPP_PORT_CONFIG *PortCfg;
- UINT8 FchGppLaneReversal;
- UINT8 FchAlinkPhyPllPowerDown;
- UINT8 FchGppPhyPllPowerDown;
- UINT32 GppData32;
- UINT32 HoldGppData32;
- UINT32 AbValue;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- if (!LocalCfgPtr->Gpp.GppDynamicPowerSaving || LocalCfgPtr->SerialDb.SerialDebugBusEnable) {
- return;
- }
-
- FchAlinkPhyPllPowerDown = (UINT8) LocalCfgPtr->Ab.UmiPhyPllPowerDown;
- FchGppLaneReversal = (UINT8) LocalCfgPtr->Gpp.GppLaneReversal;
- FchGppPhyPllPowerDown = (UINT8) LocalCfgPtr->Gpp.GppPhyPllPowerDown;
-
- if (LocalCfgPtr->Gpp.GppHardwareDownGrade) {
- PortCfg = &LocalCfgPtr->Gpp.PortCfg[LocalCfgPtr->Gpp.GppHardwareDownGrade - 1];
- PortCfg->PortDetected = TRUE;
- }
-
- GppData32 = 0;
- HoldGppData32 = 0;
-
- switch ( LocalCfgPtr->Gpp.GppLinkConfig ) {
- case PortA4:
- PortCfg = &LocalCfgPtr->Gpp.PortCfg[0];
- if ( PortCfg->PortDetected == FALSE ) {
- GppData32 |= 0x0f0f;
- HoldGppData32 |= 0x1000;
- }
- break;
-
- case PortA2B2:
- PortCfg = &LocalCfgPtr->Gpp.PortCfg[0];
- if ( PortCfg->PortDetected == FALSE ) {
- GppData32 |= ( FchGppLaneReversal )? 0x0c0c:0x0303;
- HoldGppData32 |= 0x1000;
- }
-
- PortCfg = &LocalCfgPtr->Gpp.PortCfg[1];
- if ( PortCfg->PortDetected == FALSE ) {
- GppData32 |= ( FchGppLaneReversal )? 0x0303:0x0c0c;
- HoldGppData32 |= 0x2000;
- }
- break;
-
- case PortA2B1C1:
- PortCfg = &LocalCfgPtr->Gpp.PortCfg[0];
- if ( PortCfg->PortDetected == FALSE ) {
- GppData32 |= ( FchGppLaneReversal )? 0x0c0c:0x0303;
- HoldGppData32 |= 0x1000;
- }
-
- PortCfg = &LocalCfgPtr->Gpp.PortCfg[1];
- if ( PortCfg->PortDetected == FALSE ) {
- GppData32 |= ( FchGppLaneReversal )? 0x0202:0x0404;
- HoldGppData32 |= 0x2000;
- }
-
- PortCfg = &LocalCfgPtr->Gpp.PortCfg[2];
- if ( PortCfg->PortDetected == FALSE ) {
- GppData32 |= ( FchGppLaneReversal )? 0x0101:0x0808;
- HoldGppData32 |= 0x4000;
- }
- break;
-
- case PortA1B1C1D1:
- PortCfg = &LocalCfgPtr->Gpp.PortCfg[0];
- if ( PortCfg->PortDetected == FALSE ) {
- GppData32 |= ( FchGppLaneReversal )? 0x0808:0x0101;
- HoldGppData32 |= 0x1000;
- }
-
- PortCfg = &LocalCfgPtr->Gpp.PortCfg[1];
- if ( PortCfg->PortDetected == FALSE ) {
- GppData32 |= ( FchGppLaneReversal )? 0x0404:0x0202;
- HoldGppData32 |= 0x2000;
- }
-
- PortCfg = &LocalCfgPtr->Gpp.PortCfg[2];
- if ( PortCfg->PortDetected == FALSE ) {
- GppData32 |= ( FchGppLaneReversal )? 0x0202:0x0404;
- HoldGppData32 |= 0x4000;
- }
-
- PortCfg = &LocalCfgPtr->Gpp.PortCfg[3];
- if ( PortCfg->PortDetected == FALSE ) {
- GppData32 |= ( FchGppLaneReversal )? 0x0101:0x0808;
- HoldGppData32 |= 0x8000;
- }
- break;
-
- default:
- ASSERT (FALSE);
- break;
- }
-
- //
- // Power Saving With GPP Disable
- // ABCFG 0xC0[8] = 0x0
- // ABCFG 0xC0[15:12] = 0xF
- // Enable "Power Saving Feature for A-Link Express Lanes"
- // Enable "Power Saving Feature for GPP Lanes"
- // ABCFG 0x90[19] = 1
- // ABCFG 0x90[6] = 1
- // RCINDC_Reg 0x65 [27:0] = 0xFFFFFFF
- // ABCFG 0xC0[7:4] = 0x0
- //
- if ( FchAlinkPhyPllPowerDown && FchGppPhyPllPowerDown ) {
- AbValue = ReadAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), StdHeader);
- WriteAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), (( AbValue | HoldGppData32 ) & (~ BIT8 )), StdHeader);
- RwAlink (FCH_AX_INDXC_REG40, ~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12), StdHeader);
- RwAlink ((FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29)), 0xFFFFFFFF, (BIT6 + BIT19), StdHeader);
- RwAlink (RC_INDXC_REG65, 0xFFFFFFFF, ((GppData32 & 0x0F) == 0x0F) ? GppData32 | 0x0CFF0000 : GppData32, StdHeader);
- RwAlink (RC_INDXC_REG40, ~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12), StdHeader);
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieEnvService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieEnvService.c
deleted file mode 100644
index ab789a2a6f..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieEnvService.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Hudson2 Pcie controller
- *
- * Init Pcie Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 46088 $ @e \$Date: 2011-01-28 11:24:26 +0800 (Fri, 28 Jan 2011) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2PCIEENVSERVICE_FILECODE
-
-
-/**
- * ProgramPcieNativeMode - Config Pcie Native Mode
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-ProgramPcieNativeMode (
- IN VOID *FchDataPtr
- )
-{
- UINT8 FchNativepciesupport;
- FCH_DATA_BLOCK *LocalCfgPtr;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- FchNativepciesupport = (UINT8) LocalCfgPtr->Misc.NativePcieSupport;
-
- //
- // PCIE Native setting
- //
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBA + 1, AccessWidth8, ~BIT14, 0);
- if ( FchNativepciesupport == 1) {
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG74 + 3, AccessWidth8, ~(BIT3 + BIT1 + BIT0), BIT3 + BIT2 + BIT0);
- } else {
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG74 + 3, AccessWidth8, ~(BIT3 + BIT1 + BIT0), BIT3 + BIT2);
- }
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieService.c
deleted file mode 100644
index 5483ee7cb3..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieService.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Hudson2 Pcie controller
- *
- * Init Pcie Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2PCIESERVICE_FILECODE
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppEnv.c
deleted file mode 100644
index d9bd43564b..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppEnv.c
+++ /dev/null
@@ -1,562 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch Gpp controller
- *
- * Init Gpp Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 49753 $ @e \$Date: 2011-03-29 04:51:46 +0800 (Tue, 29 Mar 2011) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Ids.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_PCIE_GPPENV_FILECODE
-//
-// Declaration of local functions
-//
-VOID FchGppRasInitialization (IN FCH_DATA_BLOCK* FchDataPtr);
-VOID FchGppAerInitialization (IN FCH_DATA_BLOCK* FchDataPtr);
-VOID PreInitGppLink (IN FCH_DATA_BLOCK* FchDataPtr);
-UINT8 CheckGppLinkStatus (IN FCH_DATA_BLOCK* FchDataPtr);
-VOID AfterGppLinkInit (IN FCH_DATA_BLOCK* FchDataPtr);
-
-//
-//-----------------------------------------------------------------------------------
-// Early GPP initialization sequence:
-//
-// 1) Set port enable bit fields by current GPP link configuration mode
-// 2) Deassert GPP reset and pull EP out of reset - Clear GPP_RESET (abcfg:0xC0[8] = 0)
-// 3) Loop polling for the link status of all ports
-// 4) Misc operations after link training:
-// - (optional) Detect GFX device
-// - Hide empty GPP configuration spaces (Disable empty GPP ports)
-// - (optional) Power down unused GPP ports
-// - (optional) Configure PCIE_P2P_Int_Map (abcfg:0xC4[7:0])
-// 5) GPP init completed
-//
-//
-// *) Gen2 vs Gen1
-// Gen2 mode Gen1 mode
-// ---------------------------------------------------------------
-// STRAP_PHY_PLL_CLKF[6:0] 7'h32 7'h19
-// STRAP_BIF_GEN2_EN 1 0
-//
-// PCIE_PHY_PLL clock locks @ 5GHz
-//
-//
-
-/**
- * FchInitEnvGpp - Config Gpp controller before PCI emulation
- *
- * - GppEarlyInit
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitEnvGpp (
- IN VOID *FchDataPtr
- )
-{
- //
- // GppEarlyInit
- //
- UINT8 FchGppMemWrImprove;
- UINT8 FchGppLaneReversal;
- UINT8 FchAlinkPhyPllPowerDown;
- UINT32 AbValue;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- FchGppMemWrImprove = LocalCfgPtr->Gpp.GppMemWrImprove;
- FchGppLaneReversal = (UINT8) LocalCfgPtr->Gpp.GppLaneReversal;
- FchAlinkPhyPllPowerDown = (UINT8) LocalCfgPtr->Ab.UmiPhyPllPowerDown;
-
- OutPort80 (0x90, StdHeader);
-
- //
- // Configure NB-FCH link PCIE PHY PLL power down for L1
- //
- if ( FchAlinkPhyPllPowerDown == TRUE ) {
- //
- // Set PCIE_P_CNTL in Alink PCIEIND space
- //
- WriteAlink (FCH_AX_INDXC_REG30 | (UINT32) (AXINDC << 29), 0x40, StdHeader);
- AbValue = ReadAlink (FCH_AX_DATAC_REG34 | (UINT32) (AXINDC << 29), StdHeader);
- AbValue |= BIT12 + BIT3 + BIT0;
- AbValue &= ~(BIT9 + BIT4);
- WriteAlink (FCH_AX_DATAC_REG34 | (UINT32) (AXINDC << 29), AbValue, StdHeader);
- RwAlink (FCH_AX_INDXC_REG02 | (UINT32) (AXINDC << 29), ~(BIT8), (BIT8), StdHeader);
- RwAlink (FCH_AX_INDXC_REG02 | (UINT32) (AXINDC << 29), ~(BIT3), (BIT3), StdHeader);
- }
-
- //
- // AXINDC_Reg 0xA4[18] = 0x1
- //
- WriteAlink (FCH_AX_INDXP_REG38 | (UINT32) (AXINDP << 29), 0xA4, StdHeader);
- AbValue = ReadAlink (FCH_AX_DATAP_REG3C | (UINT32) (AXINDP << 29), StdHeader);
- AbValue |= BIT18;
- WriteAlink (FCH_AX_DATAP_REG3C | (UINT32) (AXINDP << 29), AbValue, StdHeader);
-
- //
- // Set ABCFG 0x031C[0] = 1 to enable lane reversal
- //
- AbValue = ReadAlink (FCH_ABCFG_REG31C | (UINT32) (ABCFG << 29), StdHeader);
- if ( FchGppLaneReversal ) {
- WriteAlink (FCH_ABCFG_REG31C | (UINT32) (ABCFG << 29), AbValue | BIT0, StdHeader);
- } else {
- WriteAlink (FCH_ABCFG_REG31C | (UINT32) (ABCFG << 29), AbValue | 0x00, StdHeader);
- }
-
- //
- // Set abcfg:0x90[20] = 1 to enable GPP bridge multi-function
- //
- AbValue = ReadAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), StdHeader);
- WriteAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), AbValue | BIT20, StdHeader);
-
- //
- // Initialize and configure GPP
- //
- if (LocalCfgPtr->Gpp.GppFunctionEnable) {
- ProgramGppTogglePcieReset (LocalCfgPtr->Gpp.GppToggleReset, StdHeader);
- FchGppAerInitialization (LocalCfgPtr);
- FchGppRasInitialization (LocalCfgPtr);
-
- //
- // PreInit - Enable GPP link training
- //
- PreInitGppLink (LocalCfgPtr);
-
- //
- // GPP Upstream Memory Write Arbitration Enhancement ABCFG 0x54[26] = 1
- // GPP Memory Write Max Payload Improvement RCINDC_Reg 0x10[12:10] = 0x4
- //
- if ( FchGppMemWrImprove == TRUE ) {
- RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~BIT26, (BIT26), StdHeader);
- RwAlink (FCH_RCINDXC_REG10 | (UINT32) (RCINDXC << 29), ~(BIT12 + BIT11 + BIT10), (BIT12), StdHeader);
- }
-
- if (CheckGppLinkStatus (LocalCfgPtr) && !LocalCfgPtr->Misc.S3Resume) {
- //
- // Toggle GPP reset (Note this affects all Hudson-2 GPP ports)
- //
- ProgramGppTogglePcieReset (LocalCfgPtr->Gpp.GppToggleReset, StdHeader);
- }
-
- //
- // Misc operations after link training
- //
- AfterGppLinkInit (LocalCfgPtr);
- }
- FchGppDynamicPowerSaving (LocalCfgPtr);
-
- OutPort80 (0x9F, StdHeader);
-}
-
-/**
- * FchGppAerInitialization - Initializing AER
- *
- *
- * @param[in] FchDataPtr
- *
- */
-VOID
-FchGppAerInitialization (
- IN FCH_DATA_BLOCK *FchDataPtr
- )
-{
- AMD_CONFIG_PARAMS *StdHeader;
-
- StdHeader = FchDataPtr->StdHeader;
-
- if (FchDataPtr->Gpp.PcieAer) {
- //
- // GPP strap configuration
- //
- RwAlink (FCH_ABCFG_REG310 | (UINT32) (ABCFG << 29), ~(BIT7 + BIT4), BIT28 + BIT27 + BIT26 + BIT1, StdHeader);
- RwAlink (FCH_ABCFG_REG314 | (UINT32) (ABCFG << 29), ~(UINT32) (0xfff << 15), 0, StdHeader);
-
- //
- // AB strap configuration
- //
- RwAlink (FCH_ABCFG_REGF0 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT15 + BIT14, StdHeader);
- RwAlink (FCH_ABCFG_REGF4 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT3, StdHeader);
- } else {
- //
- // Hard System Hang running MeatGrinder Test on multiple blocks
- // GPP Error Reporting Configuration
- RwAlink (FCH_ABCFG_REGF0 | (UINT32) (ABCFG << 29), ~(BIT1), 0, StdHeader);
- }
-
-}
-
-/**
- * FchGppRasInitialization - Initializing RAS
- *
- *
- * @param[in] FchDataPtr
- *
- */
-VOID
-FchGppRasInitialization (
- IN FCH_DATA_BLOCK *FchDataPtr
- )
-{
- if (FchDataPtr->Gpp.PcieRas) {
- RwAlink (FCH_ABCFG_REGF4 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT0, FchDataPtr->StdHeader);
- }
-}
-
-/**
- * PreInitGppLink - Enable GPP link training.
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-PreInitGppLink (
- IN FCH_DATA_BLOCK *FchDataPtr
- )
-{
- GPP_LINKMODE CfgMode;
- UINT8 PortId;
- UINT32 GppPortCfg;
- UINT16 Tmp16Value;
- FCH_GPP_PORT_CONFIG *PortCfg;
- AMD_CONFIG_PARAMS *StdHeader;
-
- UINT8 PortMask[5] = {
- 0x01,
- 0x00,
- 0x03,
- 0x07,
- 0x0F
- };
-
- //
- // PCIE_GPP_ENABLE (abcfg:0xC0):
- //
- // GPP_LINK_CONFIG ([3:0]) PortA PortB PortC PortD Description
- // ----------------------------------------------------------------------------------
- // 0000 0-3 x4 Config
- // 0001 N/A
- // 0010 0-1 2-3 0 2:2 Config
- // 0011 0-1 2 3 2:1:1 Config
- // 0100 0 1 2 3 1:1:1:1 Config
- //
- // For A12 and above:
- // ABCFG:0xC0[12] - Port A hold training (default 1)
- // ABCFG:0xC0[13] - Port B hold training (default 1)
- // ABCFG:0xC0[14] - Port C hold training (default 1)
- // ABCFG:0xC0[15] - Port D hold training (default 1)
- //
- //
- //
- // Set port enable bit fields based on current GPP link configuration mode
- //
- CfgMode = FchDataPtr->Gpp.GppLinkConfig;
- StdHeader = FchDataPtr->StdHeader;
-
- ASSERT (CfgMode == PortA4 || CfgMode == PortA2B2 || CfgMode == PortA2B1C1 || CfgMode == PortA1B1C1D1);
-
- GppPortCfg = (UINT32) PortMask[CfgMode];
-
- //
- // Mask out non-applicable ports according to the target link configuration mode
- //
- for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) {
- FchDataPtr->Gpp.PortCfg[PortId].PortPresent &= (UINT8 ) (GppPortCfg >> PortId) & BIT0;
- }
-
- //
- // Deassert GPP reset and pull EP out of reset - Clear GPP_RESET (abcfg:0xC0[8] = 0)
- //
- Tmp16Value = (UINT16) (~GppPortCfg << 12);
- GppPortCfg = (UINT32) (Tmp16Value + (GppPortCfg << 4) + CfgMode);
- WriteAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), GppPortCfg, StdHeader);
-
- GppPortCfg = ReadAlink (0xC0 | (UINT32) (RCINDXC << 29), StdHeader);
- WriteAlink (0xC0 | (UINT32) (RCINDXC << 29), GppPortCfg | 0x400, StdHeader); /// Set STRAP_F0_MSI_EN
-
- //
- // A-Link L1 Entry Delay Shortening
- // AXINDP_Reg 0xA0[7:4] = 0x3
- // KR Does not need this portion of code.
- RwAlink (FCH_AX_INDXP_REGA0, 0xFFFFFF0F, 0x30, StdHeader);
- RwAlink (FCH_AX_INDXP_REGB1, 0xFFFFFFFF, BIT19, StdHeader);
- RwAlink (FCH_AX_INDXP_REGB1, 0xFFFFFFFF, BIT28, StdHeader);
-
- //
- // GPP L1 Entry Delay Shortening
- // RCINDP_Reg 0xA0[7:4] = 0x1 Enter L1 sooner after ACK'ing PM request.
- // This is done to reduce number of NAK received with L1 enabled.
- //
- for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) {
- RwAlink (FCH_RCINDXP_REGA0 | PortId << 24, 0xFFFFFF0F, 0x10, StdHeader);
- // Hard System Hang running MeatGrinder Test on multiple blocks
- // GPP Error Reporting Configuration
- RwAlink (FCH_RCINDXP_REG6A | PortId << 24, ~(BIT1), 0, StdHeader);
- }
-
- if (FchDataPtr->Misc.S3Resume) {
- for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) {
- PortCfg = &FchDataPtr->Gpp.PortCfg[PortId];
- if (PortCfg->PortHotPlug == TRUE) {
- PortCfg->PortDetected = FALSE;
- } else {
- if (PortCfg->PortIsGen2 == 1) {
- FchGppForceGen1 (FchDataPtr, (UINT8) (1 << PortId));
- } else {
- FchGppForceGen2 (FchDataPtr, (UINT8) (1 << PortId));
- }
- }
- }
- }
-
- //
- // Obtain original Gen2 strap value (LC_GEN2_EN_STRAP)
- //
- FchDataPtr->Gpp.GppGen2Strap = (UINT8) (ReadAlink (FCH_RCINDXP_REGA4 | 0 << 24, StdHeader) & BIT0);
-}
-
-/**
- * CheckGppLinkStatus - loop polling the link status for each GPP port
- *
- *
- * Return: ToggleStatus[3:0] = Port bitmap for those need to clear De-emphasis
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-UINT8
-CheckGppLinkStatus (
- IN FCH_DATA_BLOCK *FchDataPtr
- )
-{
- UINT32 PortId;
- UINT8 PortScanMap;
- UINT8 GppHwDowngrade;
- FCH_GPP_PORT_CONFIG *PortCfg;
- UINT8 FailedPorts;
-
-
- PortScanMap = 0;
- FailedPorts = 0;
-
- //
- // Obtain a list of ports to be checked
- //
- for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) {
- PortCfg = &FchDataPtr->Gpp.PortCfg[PortId];
- if ( PortCfg->PortPresent == TRUE && PortCfg->PortDetected == FALSE ) {
- PortScanMap |= 1 << PortId;
- }
- }
-
- GppHwDowngrade = (UINT8)FchDataPtr->Gpp.GppHardwareDownGrade;
- if (GppHwDowngrade != 0) {
- //
- // Skip polling and always assume this port to be present
- //
- PortScanMap &= ~(1 << (GppHwDowngrade - 1));
- }
-
- //
- //GPP Gen2 Speed Change
- // if ((GPP Gen2 == enabled) and (RCINDP_Reg 0xA4[0] == 0x1)) {
- // PCIe_Cfg 0x88[3:0] = 0x2
- // RCINDP_Reg 0xA2[13] = 0x0
- // RCINDP_Reg 0xC0[15] = 0x0
- // RCINDP_Reg 0xA4[29] = 0x1
- // } else {
- // PCIe_Cfg 0x88[3:0] = 0x1
- // RCINDP_Reg 0xA4[0] = 0x0
- // RCINDP_Reg 0xA2[13] = 0x1
- // RCINDP_Reg 0xC0[15] = 0x0
- // RCINDP_Reg 0xA4[29] = 0x1
- // }
- //
- FchStall (5000, FchDataPtr->StdHeader);
- if (FchDataPtr->Gpp.GppGen2 && FchDataPtr->Gpp.GppGen2Strap) {
- FchGppForceGen2 (FchDataPtr, PortScanMap);
- FailedPorts = GppPortPollingLtssm (FchDataPtr, PortScanMap, TRUE);
-
- if (FailedPorts) {
- FchGppForceGen1 (FchDataPtr, FailedPorts);
- FailedPorts = GppPortPollingLtssm (FchDataPtr, FailedPorts, FALSE);
- }
- } else {
- FchGppForceGen1 (FchDataPtr, PortScanMap);
- FailedPorts = GppPortPollingLtssm (FchDataPtr, PortScanMap, FALSE);
- }
- return FailedPorts;
-}
-
-/**
- * AfterGppLinkInit
- * - Search for display device behind each GPP port
- * - If the port is empty AND not hotplug-capable:
- * * Turn off link training
- * * (optional) Power down the port
- * * Hide the configuration space (Turn off the port)
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-AfterGppLinkInit (
- IN FCH_DATA_BLOCK *FchDataPtr
- )
-{
- UINT32 PortId;
- FCH_GPP_PORT_CONFIG *PortCfg;
- UINT32 RegBusNumber;
- UINT32 AbValue;
- UINT32 AbIndex;
- UINT8 Value;
- UINT8 FchGppGen2;
- AMD_CONFIG_PARAMS *StdHeader;
-
- StdHeader = FchDataPtr->StdHeader;
- FchGppGen2 = FchDataPtr->Gpp.GppGen2;
-
- FchDataPtr->Gpp.GppFoundGfxDev = 0;
- AbValue = ReadAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), StdHeader);
- //
- // Link Bandwidth Notification Capability Enable
- //RCINDC:0xC1[0] = 1
- //
- RwAlink (FCH_RCINDXC_REGC1, 0xFFFFFFFF, BIT0, StdHeader);
-
- for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) {
- //
- // Program requester ID for every port
- //
- AbIndex = FCH_RCINDXP_REG21 | (UINT32) (RCINDXP << 29) | (PortId << 24);
- WriteAlink (AbIndex, (FCH_GPP_DEV << 3) + PortId, StdHeader);
- //
- // Link Bandwidth Notification Capability Enable
- //PCIe Cfg 0x68[10] = 0
- //PCIe Cfg 0x68[11] = 0
- //
- RwPci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x68), AccessWidth16, ~(BIT10 + BIT11), 0, StdHeader);
-
- PortCfg = &FchDataPtr->Gpp.PortCfg[PortId];
- //
- // Check if there is GFX device behind each GPP port
- //
- if ( PortCfg->PortDetected == TRUE ) {
- RegBusNumber = (SBTEMP_BUS << 16) + (SBTEMP_BUS << 8);
- WritePci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x18), AccessWidth32, &RegBusNumber, StdHeader);
- ReadPci (PCI_ADDRESS (SBTEMP_BUS, 0, 0, 0x0B), AccessWidth8, &Value, StdHeader);
- if ( Value == 3 ) {
- FchDataPtr->Gpp.GppFoundGfxDev |= (1 << PortId);
- }
-
- RegBusNumber = 0;
- WritePci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x18), AccessWidth32, &RegBusNumber, StdHeader);
- } else if ( PortCfg->PortPresent == FALSE || PortCfg->PortHotPlug == FALSE ) {
- //
- // Mask off non-applicable ports
- //
- AbValue &= ~(1 << (PortId + 4));
- }
-
- if ( PortCfg->PortHotPlug == TRUE ) {
- //
- // Hot Plug: PCIe Native Support
- // RCINDP_Reg 0x10[3] = 0x1
- // PCIe_Cfg 0x5A[8] = 0x1
- // PCIe_Cfg 0x6C[6] = 0x1
- // RCINDP_Reg 0x20[19] = 0x0
- //
- RwAlink ((FCH_RCINDXP_REG10 | (UINT32) (RCINDXP << 29) | (PortId << 24)), 0xFFFFFFFF, BIT3, StdHeader);
- RwPci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x5b), AccessWidth8, 0xff, BIT0, StdHeader);
- RwPci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x6c), AccessWidth8, 0xff, BIT6, StdHeader);
- RwAlink ((FCH_RCINDXP_REG20 | (UINT32) (RCINDXP << 29) | (PortId << 24)), ~BIT19, 0, StdHeader);
- }
- }
-
- if ( FchDataPtr->Gpp.GppUnhidePorts == FALSE ) {
- if ((AbValue & 0xF0) == 0) {
- AbValue = BIT8; /// if all ports are empty set GPP_RESET
- } else if ((AbValue & 0xE0) != 0 && (AbValue & 0x10) == 0) {
- AbValue |= BIT4; /// PortA should always be visible whenever other ports are exist
- }
-
- //
- // Update GPP_Portx_Enable (abcfg:0xC0[7:5])
- //
- WriteAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), AbValue, StdHeader);
- }
-
- //
- // Common initialization for open GPP ports
- //
- for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) {
- ReadPci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x80), AccessWidth8, &Value, StdHeader);
- if (Value != 0xff) {
- //
- // Set pciCfg:PCIE_DEVICE_CNTL2[3:0] = 4'h6 (0x80[3:0])
- //
- Value &= 0xf0;
- Value |= 0x06;
- WritePci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x80), AccessWidth8, &Value, StdHeader);
-
- //
- // Set PCIEIND_P:PCIE_RX_CNTL[RX_RCB_CPL_TIMEOUT_MODE] (0x70:[19]) = 1
- //
- AbIndex = FCH_RCINDXP_REG70 | (UINT32) (RCINDXP << 29) | (PortId << 24);
- AbValue = ReadAlink (AbIndex, StdHeader) | BIT19;
- WriteAlink (AbIndex, AbValue, StdHeader);
-
- //
- // Set PCIEIND_P:PCIE_TX_CNTL[TX_FLUSH_TLP_DIS] (0x20:[19]) = 0
- //
- AbIndex = FCH_RCINDXP_REG20 | (UINT32) (RCINDXP << 29) | (PortId << 24);
- AbValue = ReadAlink (AbIndex, StdHeader) & ~BIT19;
- WriteAlink (AbIndex, AbValue, StdHeader);
-
- }
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppHp.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppHp.c
deleted file mode 100644
index 97d18c349e..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppHp.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch GPP controller
- *
- * Init GPP features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 49456 $ @e \$Date: 2011-03-24 04:13:38 +0800 (Thu, 24 Mar 2011) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_PCIE_GPPHP_FILECODE
-/**
- * GPP hot plug handler
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- * @param[in] HpPort The hot plug port number.
- *
- */
-VOID
-FchGppHotPlugSmiProcess (
- IN AMD_FCH_CFG *FchDataPtr,
- IN UINT32 HpPort
- )
-{
- UINT8 FailedPort;
-
- //
- // First restore GPP pads if needed
- //
- if (FchDataPtr->Gpp->GppDynamicPowerSaving && FchDataPtr->Ab->AlinkPhyPllPowerDown && FchDataPtr->Gpp->GppPhyPllPowerDown) {
- RwAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), ~(UINT32) (1 << (12 + HpPort)), 0, StdHeader);
- RwAlink (RC_INDXC_REG65, ~(UINT32) (0x101 << HpPort), 0, StdHeader);
- FchStall (1000);
- }
-
- FailedPort = (UINT8) (1 << HpPort);
- if (FchDataPtr->Gpp->GppGen2 && FchDataPtr->Gpp->GppGen2Strap) {
- if (GppPortPollingLtssm (FchDataPtr, FailedPort, TRUE)) {
- FchGppForceGen1 (FchDataPtr, FailedPort);
- FailedPort = GppPortPollingLtssm (FchDataPtr, FailedPort, FALSE);
- }
- } else {
- FchGppForceGen1 (FchDataPtr, FailedPort);
- FailedPort = GppPortPollingLtssm (FchDataPtr, FailedPort, FALSE);
- }
-}
-
-
-/**
- * GPP hot-unplug handler
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- * @param[in] HpPort The hot plug port number.
- *
- */
-VOID
-FchGppHotUnplugSmiProcess (
- IN AMD_FCH_CFG *FchDataPtr,
- IN UINT32 HpPort
- )
-{
- FchDataPtr->Gpp->PortCfg[HpPort].PortDetected = FALSE;
-
- if (FchDataPtr->Gpp->GppGen2 && FchDataPtr->Gpp->GppGen2Strap) {
- FchGppForceGen2 (FchDataPtr, (UINT8) (1 << HpPort));
- }
-
- if (FchDataPtr->Gpp->GppDynamicPowerSaving && FchDataPtr->Ab->AlinkPhyPllPowerDown && FchDataPtr->Gpp->GppPhyPllPowerDown) {
- RwAlink (FCH_RCINDXP_REGA2 | HpPort << 24, ~(UINT32) (BIT17), BIT17, StdHeader);
- RwAlink (FCH_RCINDXP_REGA2 | HpPort << 24, ~(UINT32) (BIT8), BIT8, StdHeader);
- RwAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), ~(UINT32) (1 << (12 + HpPort)), (1 << (12 + HpPort)), StdHeader);
- RwAlink (FCH_RCINDXP_REGA2 | HpPort << 24, ~(UINT32) (BIT17), 0, StdHeader);
- }
-
- //
- // Finally re-configure GPP pads if needed
- //
- FchGppDynamicPowerSaving (FchDataPtr);
-}
-
-
-/**
- * SMI handler for GPP hot-plug
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- * @param[in] IsPlugged Is a card currently plugged in the GPP port?
- *
- */
-VOID
-FchGppHotplugSmiCallback (
- IN AMD_FCH_CFG *FchDataPtr,
- IN BOOLEAN IsPlugged
- )
-{
- UINT32 PortNum;
- UINT32 HpPort;
-
- if (!FchDataPtr->Gpp->GppFunctionEnable) {
- return;
- }
-
- HpPort = 0xff;
- for (PortNum = 0; PortNum < MAX_GPP_PORTS; PortNum++) {
- if (FchDataPtr->Gpp->PortCfg[PortNum].PortHotPlug == TRUE) {
- HpPort = PortNum;
- break;
- }
- }
-
- if (HpPort == 0xff) {
- return;
- }
-
- if (IsPlugged) {
- OutPort80 (0x9C);
- FchGppHotPlugSmiProcess (FchDataPtr, HpPort);
- } else {
- OutPort80 (0x9D);
- FchGppHotUnplugSmiProcess (FchDataPtr, HpPort);
- }
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppLate.c
deleted file mode 100644
index 38f6868585..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppLate.c
+++ /dev/null
@@ -1,351 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch Gpp controller
- *
- * Init Gpp Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 49456 $ @e \$Date: 2011-03-24 04:13:38 +0800 (Thu, 24 Mar 2011) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_PCIE_GPPLATE_FILECODE
-//
-// Declaration of local functions
-//
-VOID FchGppSetAspm (IN UINT32 PciAddress, IN UINT8 LxState, IN AMD_CONFIG_PARAMS *StdHeader);
-VOID FchGppSetEpAspm (IN UINT32 PciAddress, IN UINT8 LxState, IN AMD_CONFIG_PARAMS *StdHeader);
-VOID FchGppValidateAspm (IN UINT32 PciAddress, IN UINT8 *LxState, IN AMD_CONFIG_PARAMS *StdHeader);
-UINT8 FchFindPciCap (IN UINT32 PciAddress, IN UINT8 TargetCapId, IN AMD_CONFIG_PARAMS *StdHeader);
-
-//
-//-----------------------------------------------------------------------------------
-// GPP initialization sequence:
-//
-// 1) Set port enable bit fields by current GPP link configuration mode
-// 2) Deassert GPP reset and pull EP out of reset - Clear GPP_RESET (abcfg:0xC0[8] = 0)
-// 3) Loop polling for the link status of all ports
-// 4) Misc operations after link training:
-// - (optional) Detect GFX device
-// - Hide empty GPP configuration spaces (Disable empty GPP ports)
-// - (optional) Power down unused GPP ports
-// - (optional) Configure PCIE_P2P_Int_Map (abcfg:0xC4[7:0])
-// 5) GPP init completed
-//
-//
-// *) Gen2 vs Gen1
-// Gen2 mode Gen1 mode
-// ---------------------------------------------------------------
-// STRAP_PHY_PLL_CLKF[6:0] 7'h32 7'h19
-// STRAP_BIF_GEN2_EN 1 0
-//
-// PCIE_PHY_PLL clock locks @ 5GHz
-//
-//
-
-
-/**
- * FchInitLateGpp - Prepare Gpp controller to boot to OS.
- *
- * PcieGppLateInit
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitLateGpp (
- IN VOID *FchDataPtr
- )
-{
- UINT8 PortId;
- UINT8 BusNum;
- UINT8 AspmValue;
- UINT8 PortAspmValue;
- UINT8 AllowStrapControlByAB;
- UINT8 FchGppPhyPllPowerDown;
- FCH_GPP_PORT_CONFIG *PortCfg;
- UINT32 PciAspmValue;
- UINT32 AbValue;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- //
- // Disable hidden register decode and serial number capability
- //
- AbValue = ReadAlink (FCH_ABCFG_REG330 | (UINT32) (ABCFG << 29), StdHeader);
- WriteAlink (FCH_ABCFG_REG330 | (UINT32) (ABCFG << 29), AbValue & ~(BIT26 + BIT10), StdHeader);
-
- if (ReadAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), StdHeader) & BIT8) {
- return;
- }
-
- //
- // Configure ASPM
- //
- AspmValue = (UINT8)LocalCfgPtr->Gpp.GppPortAspm;
- FchGppPhyPllPowerDown = (UINT8) LocalCfgPtr->Gpp.GppPhyPllPowerDown;
-
- AllowStrapControlByAB = 0x01;
-
- for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) {
- //
- // write pci_reg3d with 0x01 to fix yellow mark for GPP bridge under some OS
- // when native PCIE is enabled but MSI is not available
- // BIF/GPP allowing strap STRAP_BIF_INTERRUPT_PIN_SB controlled by AB reg
- //
- PortCfg = &LocalCfgPtr->Gpp.PortCfg[PortId];
- if (PortCfg->PortHotPlug) {
- RwPci (PCI_ADDRESS (0, 21, PortId, 0x04), AccessWidth8, 0xFE, 0x00, StdHeader); ///clear IO enable to fix possible hotplug hang
- }
-
- WritePci (PCI_ADDRESS (0, 21, PortId, 0x3d), AccessWidth8, &AllowStrapControlByAB, StdHeader);
- ReadPci (PCI_ADDRESS (0, 21, PortId, 0x19), AccessWidth8, &BusNum, StdHeader);
-
- if (BusNum != 0xFF) {
- ReadPci (PCI_ADDRESS (BusNum, 0, 0, 0x00), AccessWidth32, &PciAspmValue, StdHeader);
- if (PciAspmValue != 0xffffffff) {
- PortAspmValue = AspmValue;
- //
- // Validate ASPM support on EP side
- //
- FchGppValidateAspm (PCI_ADDRESS (BusNum, 0, 0, 0), &PortAspmValue, StdHeader);
- //
- // Set ASPM on EP side
- //
- FchGppSetEpAspm (PCI_ADDRESS (BusNum, 0, 0, 0), PortAspmValue, StdHeader);
- //
- // Set ASPM on port side
- //
- FchGppSetAspm (PCI_ADDRESS (0, 21, PortId, 0), PortAspmValue, StdHeader);
- }
- }
- RwAlink ((FCH_RCINDXP_REG02 | (UINT32) (RCINDXP << 29) | (PortId << 24) ), ~(BIT15), (BIT15), StdHeader);
- }
- RwAlink ((FCH_RCINDXC_REG02 | (UINT32) (RCINDXC << 29)), ~(BIT0), (BIT0), StdHeader);
-
- //
- // Configure Lock HWInit registers
- //
- AbValue = ReadAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), StdHeader);
- if (AbValue & 0xF0) {
- AbValue = ReadAlink (FCH_RCINDXC_REG10 | (UINT32) (RCINDXC << 29), StdHeader);
- WriteAlink (FCH_RCINDXC_REG10 | (UINT32) (RCINDXC << 29), AbValue | BIT0, StdHeader); /// Set HWINIT_WR_LOCK
-
- if ( FchGppPhyPllPowerDown == TRUE ) {
- //
- // Power Saving Feature for GPP Lanes
- //
- // Set PCIE_P_CNTL in Alink PCIEIND space
- //
- AbValue = ReadAlink (RC_INDXC_REG40 | (UINT32) (RCINDXC << 29), StdHeader);
- AbValue |= BIT12 + BIT3 + BIT0;
- AbValue &= ~(BIT9 + BIT4);
- WriteAlink (RC_INDXC_REG40 | (UINT32) (RCINDXC << 29), AbValue, StdHeader);
- RwAlink (FCH_RCINDXC_REG02, ~(BIT8), (BIT8), StdHeader);
- RwAlink (FCH_RCINDXC_REG02, ~(BIT3), (BIT3), StdHeader);
- }
- }
-
- //
- // Restore strap0 via override
- //
- if (LocalCfgPtr->Gpp.PcieAer) {
- RwAlink (FCH_ABCFG_REG310 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT7, StdHeader);
- RwAlink (RC_INDXC_REGC0, 0xFFFFFFFF, BIT9, StdHeader);
- }
-}
-
-/**
- * FchGppSetAspm - Set GPP ASPM
- *
- *
- * @param[in] PciAddress PCI Address.
- * @param[in] LxState Lane State.
- * @param[in] StdHeader
- *
- */
-VOID
-FchGppSetAspm (
- IN UINT32 PciAddress,
- IN UINT8 LxState,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 PcieCapOffset;
- UINT8 DeviceType;
-
- PcieCapOffset = FchFindPciCap (PciAddress, PCIE_CAP_ID, StdHeader);
-
- if (PcieCapOffset) {
- //
- // Read link capabilities register (0x0C[11:10] - ASPM support)
- //
- ReadPci (PciAddress + PcieCapOffset + 0x0D, AccessWidth8, &DeviceType, StdHeader);
- if (DeviceType & BIT2) {
- DeviceType = (DeviceType >> 2) & (BIT1 + BIT0);
- //
- // Set ASPM state in link control register
- //
- RwPci (PciAddress + PcieCapOffset + 0x10, AccessWidth8, 0xffffffff, LxState & DeviceType, StdHeader);
- }
- }
-}
-
-/**
- * FchGppSetEpAspm - Set EP ASPM
- *
- *
- * @param[in] PciAddress PCI Address.
- * @param[in] LxState Lane State.
- * @param[in] StdHeader
- *
- */
-VOID
-FchGppSetEpAspm (
- IN UINT32 PciAddress,
- IN UINT8 LxState,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 DeviceType;
- UINT8 MaxFuncs;
- UINT32 DevBDF;
-
- MaxFuncs = 1;
- ReadPci (PciAddress + 0x0E, AccessWidth8, &DeviceType, StdHeader);
-
- if (DeviceType & BIT7) {
- MaxFuncs = 8; /// multi-function device
- }
-
- while (MaxFuncs != 0) {
- DevBDF = PciAddress + (UINT32) ((MaxFuncs - 1) << 16);
- FchGppSetAspm (DevBDF, LxState, StdHeader);
- MaxFuncs--;
- }
-}
-
-/**
- * FchGppValidateAspm - Validate EndPoint support for GPP ASPM
- *
- *
- * @param[in] PciAddress PCI Address.
- * @param[in] LxState Lane State.
- * @param[in] StdHeader
- *
- */
-VOID
-FchGppValidateAspm (
- IN UINT32 PciAddress,
- IN UINT8 *LxState,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 PcieCapOffset;
- UINT8 DeviceType;
- UINT8 MaxFuncs;
- UINT32 DevBDF;
-
- MaxFuncs = 1;
- ReadPci (PciAddress + 0x0E, AccessWidth8, &DeviceType, StdHeader);
-
- if (DeviceType & BIT7) {
- MaxFuncs = 8; /// multi-function device
- }
-
- while (MaxFuncs != 0) {
- DevBDF = PciAddress + (UINT32) ((MaxFuncs - 1) << 16);
- PcieCapOffset = FchFindPciCap (DevBDF, PCIE_CAP_ID, StdHeader);
-
- if (PcieCapOffset) {
- //
- // Read link capabilities register (0x0C[11:10] - ASPM support)
- //
- ReadPci (DevBDF + PcieCapOffset + 0x0D, AccessWidth8, &DeviceType, StdHeader);
- if (DeviceType & BIT2) {
- DeviceType = (DeviceType >> 2) & (BIT1 + BIT0);
- //
- // Update ASPM state as what endpoint support
- //
- *LxState &= DeviceType;
- }
- }
- MaxFuncs--;
- }
-}
-
-/**
- * FchFindPciCap - Find PCI Cap
- *
- *
- * @param[in] PciAddress PCI Address.
- * @param[in] TargetCapId Target Cap ID.
- * @param[in] StdHeader
- *
- */
-UINT8
-FchFindPciCap (
- IN UINT32 PciAddress,
- IN UINT8 TargetCapId,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 NextCapPtr;
- UINT8 CapId;
-
- NextCapPtr = 0x34;
- while (NextCapPtr != 0) {
- ReadPci (PciAddress + NextCapPtr, AccessWidth8, &NextCapPtr, StdHeader);
-
- if (NextCapPtr == 0xff) {
- return 0;
- }
-
- if (NextCapPtr != 0) {
- ReadPci (PciAddress + NextCapPtr, AccessWidth8, &CapId, StdHeader);
- if (CapId == TargetCapId) {
- break;
- } else {
- NextCapPtr++;
- }
- }
- }
- return NextCapPtr;
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppLib.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppLib.c
deleted file mode 100644
index 4c12177b23..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppLib.c
+++ /dev/null
@@ -1,193 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Fch Gpp Library
- *
- * Gpp Library
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44909 $ @e \$Date: 2011-01-10 18:45:45 +0800 (Mon, 10 Jan 2011) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#include "FchDef.h"
-#define FILECODE PROC_FCH_PCIE_GPPLIB_FILECODE
-
-/**
- * FchGppForceGen2 - Set GPP to Gen2
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- * @param[in] ActivePorts Activate Ports.
- *
- */
-VOID
-FchGppForceGen2 (
- IN VOID *FchDataPtr,
- IN CONST UINT8 ActivePorts
- )
-{
- UINT32 PortId;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) {
- if (ActivePorts & (1 << PortId)) {
- RwAlink (FCH_RCINDXP_REGA4 | PortId << 24, 0xFFFFFFFF, BIT29 + BIT0, StdHeader);
- RwAlink ((FCH_ABCFG_REG340 + PortId * 4) | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT21, StdHeader);
- RwAlink (FCH_RCINDXP_REGA2 | PortId << 24, ~BIT13, 0, StdHeader);
- RwAlink (FCH_RCINDXP_REGC0 | PortId << 24, ~BIT15, 0, StdHeader);
- RwPci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x88), AccessWidth8, 0xf0, 0x02, StdHeader);
-
- (&LocalCfgPtr->Gpp.PortCfg[PortId])->PortIsGen2 = 2;
- }
- }
-}
-
-/**
- * FchGppForceGen1 - Set GPP to Gen1
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- * @param[in] ActivePorts Activate Ports.
- *
- */
-VOID
-FchGppForceGen1 (
- IN VOID *FchDataPtr,
- IN CONST UINT8 ActivePorts
- )
-{
- UINT32 PortId;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) {
- if (ActivePorts & (1 << PortId) && LocalCfgPtr->Gpp.GppHardwareDownGrade != PortId + 1) {
- RwAlink ((FCH_ABCFG_REG340 + PortId * 4) | (UINT32) (ABCFG << 29), ~BIT21, 0, StdHeader);
- RwAlink (FCH_RCINDXP_REGA4 | PortId << 24, ~BIT0, BIT29, StdHeader);
- RwAlink (FCH_RCINDXP_REGA2 | PortId << 24, 0xFFFFFFFF, BIT13, StdHeader);
- RwAlink (FCH_RCINDXP_REGC0 | PortId << 24, ~BIT15, 0, StdHeader);
- RwPci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x88), AccessWidth8, 0xf0, 0x01, StdHeader);
-
- (&LocalCfgPtr->Gpp.PortCfg[PortId])->PortIsGen2 = 1;
- }
- }
-}
-
-/**
- * GppPortPollingLtssm - Loop polling the LTSSM for each GPP port marked in PortMap
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- * @param[in] ActivePorts A bitmap of ports which should be polled
- * @param[in] IsGen2 TRUE if the polling is in Gen2 mode
- *
- * @retval FailedPorts A bitmap of ports which failed to train
- *
- */
-UINT8
-GppPortPollingLtssm (
- IN VOID *FchDataPtr,
- IN UINT8 ActivePorts,
- IN BOOLEAN IsGen2
- )
-{
- UINT32 RetryCounter;
- UINT8 PortId;
- UINT8 FailedPorts;
- FCH_GPP_PORT_CONFIG *PortCfg;
- UINT32 AbIndex;
- UINT32 GppData32;
- UINT8 EmptyPorts;
- UINT8 Index;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- FailedPorts = 0;
- RetryCounter = MAX_LT_POLLINGS;
- EmptyPorts = ActivePorts;
-
- while (RetryCounter-- && ActivePorts) {
- for (PortId = 0; PortId < MAX_GPP_PORTS; PortId++) {
- if (ActivePorts & (1 << PortId)) {
- PortCfg = &LocalCfgPtr->Gpp.PortCfg[PortId];
- AbIndex = FCH_RCINDXP_REGA5 | (UINT32) (RCINDXP << 29) | (PortId << 24);
- GppData32 = ReadAlink (AbIndex, StdHeader) & 0x3F3F3F3F;
-
- if ((UINT8) (GppData32) > 0x04) {
- EmptyPorts &= ~(1 << PortId);
- }
-
- if ((UINT8) (GppData32) == 0x10) {
- ActivePorts &= ~(1 << PortId);
- PortCfg->PortDetected = TRUE;
- break;
- }
-
- if (IsGen2) {
- for (Index = 0; Index < 4; Index++) {
- if ((UINT8) (GppData32) == 0x29 || (UINT8) (GppData32) == 0x2A ) {
- ActivePorts &= ~(1 << PortId);
- FailedPorts |= (1 << PortId);
- break;
- }
- GppData32 >>= 8;
- }
- }
- }
- }
-
- if (EmptyPorts && RetryCounter < (MAX_LT_POLLINGS - 200)) {
- ActivePorts &= ~EmptyPorts;
- }
-
- FchStall (1000, StdHeader);
- }
-
- FailedPorts |= ActivePorts;
- return FailedPorts;
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppMid.c
deleted file mode 100644
index 34c842bf51..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppMid.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch Gpp controller
- *
- * Init Gpp Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_PCIE_GPPMID_FILECODE
-//
-// Declaration of local functions
-//
-
-/**
- * FchInitMidGpp - Config Gpp controller after PCI emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitMidGpp (
- IN VOID *FchDataPtr
- )
-{
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppReset.c
deleted file mode 100644
index 92ffde6663..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppReset.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch Gpp controller
- *
- * Init Gpp features (PEI phase).
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#include "FchDef.h"
-#define FILECODE PROC_FCH_PCIE_GPPRESET_FILECODE
-
-/**
- * FchInitResetGpp - Config Gpp during Power-On
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitResetGpp (
- IN VOID *FchDataPtr
- )
-{
- ProgramFchGppInitReset (FchDataPtr);
-}
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieEnv.c
deleted file mode 100644
index 570609b013..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieEnv.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch Pcie controller
- *
- * Init Pcie Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 45603 $ @e \$Date: 2011-01-19 14:29:05 +0800 (Wed, 19 Jan 2011) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#include "FchDef.h"
-#define FILECODE PROC_FCH_PCIE_PCIEENV_FILECODE
-
-/**
- * FchInitEnvPcie - Config Pcie before PCI emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitEnvPcie (
- IN VOID *FchDataPtr
- )
-{
- //
- // PCIE Native setting
- //
- ProgramPcieNativeMode (FchDataPtr);
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieLate.c
deleted file mode 100644
index e8f0e45774..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieLate.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch Pcie controller
- *
- * Init Pcie Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_PCIE_PCIELATE_FILECODE
-
-/**
- * FchInitLatePcie - Prepare Pcie to boot to OS.
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitLatePcie (
- IN VOID *FchDataPtr
- )
-{
-}
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieMid.c
deleted file mode 100644
index 227b61873b..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieMid.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch Pcie controller
- *
- * Init Pcie Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_PCIE_PCIEMID_FILECODE
-
-/**
- * FchInitMidPcie - Config Pcie after PCI emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitMidPcie (
- IN VOID *FchDataPtr
- )
-{
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieReset.c
deleted file mode 100644
index b4d7618759..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieReset.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch Pcie Component
- *
- * Init Pcie features (PEI phase).
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 45603 $ @e \$Date: 2011-01-19 14:29:05 +0800 (Wed, 19 Jan 2011) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_PCIE_PCIERESET_FILECODE
-
-/**
- * FchInitResetPcie - Config Pcie controller during Power-On
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitResetPcie (
- IN VOID *FchDataPtr
- )
-{
-}
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/AhciEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/AhciEnv.c
deleted file mode 100644
index cee7dd3a19..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/AhciEnv.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch SATA controller (AHCI mode)
- *
- * Init SATA AHCI features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_SATA_AHCIENV_FILECODE
-
-/**
- * FchInitEnvSataAhci - Config SATA Ahci controller before PCI
- * emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitEnvSataAhci (
- IN VOID *FchDataPtr
- )
-{
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- //
- // Class code
- //
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG08), AccessWidth32, 0, 0x01060140, StdHeader);
- //
- // Device ID
- //
- if ( LocalCfgPtr->Sata.SataClass == SataAhci7804 ) {
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG02), AccessWidth16, 0, FCH_SATA_AMDAHCI_DID, StdHeader);
- } else {
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG02), AccessWidth16, 0, FCH_SATA_AHCI_DID, StdHeader);
- }
- //
- // SSID
- //
- if (LocalCfgPtr->Sata.SataAhciSsid != NULL ) {
- RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Sata.SataAhciSsid, StdHeader);
- }
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/AhciLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/AhciLate.c
deleted file mode 100644
index 022835baea..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/AhciLate.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch SATA controller (AHCI mode)
- *
- * Init SATA AHCI features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_SATA_AHCILATE_FILECODE
-
-/**
- * FchInitLateSataAhci - Prepare SATA AHCI controller to boot to
- * OS.
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitLateSataAhci (
- IN VOID *FchDataPtr
- )
-{
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/AhciLib.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/AhciLib.c
deleted file mode 100644
index be2f3ec702..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/AhciLib.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Fch SATA AHCI controller Library
- *
- * SATA AHCI Library
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_SATA_AHCILIB_FILECODE
-
-/**
- * sataAhciSetDeviceNumMsi - Program AHCI controller support
- * device number cap & MSI cap
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-SataAhciSetDeviceNumMsi (
- IN VOID *FchDataPtr
- )
-{
-
- FCH_INTERFACE *LocalCfgPtr;
-
- LocalCfgPtr = (FCH_INTERFACE *)FchDataPtr;
-
- SataSetDeviceNumMsi (LocalCfgPtr);
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/AhciMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/AhciMid.c
deleted file mode 100644
index 6312a83294..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/AhciMid.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch SATA controller (AHCI mode)
- *
- * Init SATA AHCI features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_SATA_AHCIMID_FILECODE
-
-/**
- * FchInitMidSataAhci - Config SATA Ahci controller after PCI
- * emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitMidSataAhci (
- IN VOID *FchDataPtr
- )
-{
- UINT32 Bar5;
- FCH_DATA_BLOCK *LocalCfgPtr;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- SataAhciSetDeviceNumMsi (LocalCfgPtr);
- SataBar5setting (LocalCfgPtr, &Bar5);
- ShutdownUnconnectedSataPortClock (LocalCfgPtr, Bar5);
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Family/Hudson2/Hudson2SataEnvService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Family/Hudson2/Hudson2SataEnvService.c
deleted file mode 100644
index 627b54deff..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Family/Hudson2/Hudson2SataEnvService.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Graphics Controller family specific service procedure
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 49766 $ @e \$Date: 2011-03-29 06:18:48 +0800 (Tue, 29 Mar 2011) $
- *
- */
-
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*/
-
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATAENVSERVICE_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-//
-// Local Routine
-//
-VOID FchSataCombineControlDataByte (IN UINT8 *ControlReg);
-VOID FchSataCombineControlDataWord (IN UINT16 *ControlReg);
-
-SATA_PHY_SETTING SataPhyTable[] =
-{
- //Gen3
- 0x0030, 0x0057A607,
- 0x0031, 0x0057A607,
- 0x0032, 0x0057A407,
- 0x0033, 0x0057A407,
- 0x0034, 0x0057A607,
- 0x0035, 0x0057A607,
- 0x0036, 0x0057A403,
- 0x0037, 0x0057A403,
-
- //Gen2
- 0x0120, 0x00071302,
-
- //Gen1
- 0x0110, 0x00174101
-};
-
-/**
- * FchInitEnvProgramSataPciRegs - Sata Pci Configuration Space
- * register setting
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitEnvProgramSataPciRegs (
- IN VOID *FchDataPtr
- )
-{
- UINT8 *PortRegByte;
- UINT16 *PortRegWord;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
- //
- // Caculate SataPortReg for SATA_ESP_PORT
- //
- PortRegByte = &(LocalCfgPtr->Sata.SataEspPort.SataPortReg);
- FchSataCombineControlDataByte (PortRegByte);
- PortRegByte = &(LocalCfgPtr->Sata.SataPortPower.SataPortReg);
- FchSataCombineControlDataByte (PortRegByte);
- PortRegWord = &(LocalCfgPtr->Sata.SataPortMd.SataPortMode);
- FchSataCombineControlDataWord (PortRegWord);
- PortRegByte = &(LocalCfgPtr->Sata.SataHotRemovalEnhPort.SataPortReg);
- FchSataCombineControlDataByte (PortRegByte);
-
- //
- // Set Sata PCI Configuration Space Write enable
- //
- SataEnableWriteAccess (StdHeader);
-
- //
- // Enables the SATA watchdog timer register prior to the SATA BIOS post
- //
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG44), AccessWidth8, 0xff, BIT0, StdHeader);
-
- //
- // SATA PCI Watchdog timer setting
- // Set timer out to 0x20 to fix IDE to SATA Bridge dropping drive issue.
- //
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG44 + 2), AccessWidth8, 0, 0x20, StdHeader);
-
- //
- // BIT4:disable fast boot
- //
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG40), AccessWidth8, 0xff, BIT4, StdHeader);
-
- //
- // Enable IDE DMA read enhancement
- //
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG48 + 3), AccessWidth8, 0xff, BIT7, StdHeader);
-
- //
- // Unused SATA Ports Disabled
- //
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG40 + 2), AccessWidth8, 0, LocalCfgPtr->Sata.SataPortPower.SataPortReg, StdHeader);
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG4C), AccessWidth32, (UINT32) (~ (0x3f << 26)), (UINT32) (0x3f << 26), StdHeader);
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG48), AccessWidth32, (UINT32) (~ (0x01 << 11)), (UINT32) (0x01 << 11), StdHeader);
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG84), AccessWidth32, (UINT32) (~ (0x01 << 31)), (UINT32) (0x00 << 31), StdHeader);
-}
-
-/**
- * FchSataCombineControlDataByte - Combine port control options
- * to one control byte.
- *
- *
- * @param[in] *ControlReg - Data pointer for control byte.
- *
- */
-VOID
-FchSataCombineControlDataByte (
- IN UINT8 *ControlReg
- )
-{
- UINT8 Index;
- UINT8 PortControl;
-
- *ControlReg = 0;
- for ( Index = 0; Index < 8; Index++ ) {
- PortControl = *( ControlReg + 1 + Index );
- *ControlReg |= PortControl << Index;
- }
-}
-/**
- * FchSataCombineControlDataWord - Combine port control options
- * to one control Word.
- *
- *
- * @param[in] *ControlReg - Data pointer for control byte.
- *
- */
-VOID
-FchSataCombineControlDataWord (
- IN UINT16 *ControlReg
- )
-{
- UINT8 Index;
- UINT8 PortControl;
-
- *ControlReg = 0;
- for ( Index = 0; Index < 8; Index++ ) {
- PortControl = *( (UINT8 *)ControlReg + 2 + Index );
- *ControlReg |= PortControl << (Index * 2);
- }
-}
-
-
-VOID
-FchProgramSataPhy (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- SATA_PHY_SETTING *PhyTablePtr;
- UINT16 Index;
-
- PhyTablePtr = &SataPhyTable[0];
-
- for (Index = 0; Index < (sizeof (SataPhyTable) / sizeof (SATA_PHY_SETTING)); Index++) {
- RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG80, AccessWidth16, 0x00, PhyTablePtr->PhyCoreControlWord, StdHeader);
- RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG98, AccessWidth32, 0x00, PhyTablePtr->PhyFineTuneDword, StdHeader);
- ++PhyTablePtr;
- }
-
-
- RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG80, AccessWidth16, 0x00, 0x110, StdHeader);
- RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG9C, AccessWidth32, (UINT32) (~(0x7 << 4)), (UINT32) (0x2 << 4), StdHeader);
- RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG80, AccessWidth16, 0x00, 0x10, StdHeader);
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Family/Hudson2/Hudson2SataResetService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Family/Hudson2/Hudson2SataResetService.c
deleted file mode 100644
index ce795b63d8..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Family/Hudson2/Hudson2SataResetService.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch Sata controller
- *
- * Init Sata Controller features (PEI phase).
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATARESETSERVICE_FILECODE
-
-/**
- * FchInitResetSataProgram - Config Sata controller during
- * Power-On
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitResetSataProgram (
- IN VOID *FchDataPtr
- )
-{
- UINT8 SataPortNum;
- UINT8 PortStatusByte;
- UINT8 EfuseByte;
- UINT8 FchSataMode;
- UINT8 FchSataInternal100Spread;
- FCH_RESET_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- //
- //FchSataMode = LocalCfgPtr->Sata.SATA_MODE.SataMode.SataModeReg;
- //New structure need calculate Sata Register value
- //
- FchSataMode = 0;
- if ( LocalCfgPtr->FchReset->SataEnable ) FchSataMode |= 0x01;
- if ( LocalCfgPtr->Sata6AhciCap ) FchSataMode |= 0x02;
- if ( LocalCfgPtr->SataSetMaxGen2 ) FchSataMode |= 0x04;
- if ( LocalCfgPtr->FchReset->IdeEnable ) FchSataMode |= 0x08;
-
- FchSataMode |= (( LocalCfgPtr->SataClkMode ) << 4 ) ;
- LocalCfgPtr->SataModeReg = FchSataMode; ///Save Back to Structure
-
- FchSataInternal100Spread = ( UINT8 ) LocalCfgPtr->SataInternal100Spread;
- SataPortNum = 0;
-
- //
- // Sata Workaround
- //
- for ( SataPortNum = 0; SataPortNum < 0x08; SataPortNum++ ) {
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG40 + 2), AccessWidth8, 0xFF, 1 << SataPortNum, StdHeader);
- FchStall (2, StdHeader);
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG40 + 2), AccessWidth8, (0xFF ^ (1 << SataPortNum)) , 0x00, StdHeader);
- FchStall (2, StdHeader);
- }
-
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG84 + 3), AccessWidth8, ~BIT2, 0, StdHeader);
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REGA0), AccessWidth8, ~(BIT2 + BIT3 + BIT4 + BIT5 + BIT6), BIT2 + BIT3 + BIT4 + BIT5, StdHeader);
-
- //
- // Sata Setting for clock mode only
- //
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGDA, AccessWidth8, 0, FchSataMode);
-
- if ( FchSataInternal100Spread ) {
- RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x1E, AccessWidth8, 0xFF, BIT4);
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG84), AccessWidth32, 0xFFFFFFFB, 0x00, StdHeader);
- } else {
- RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x1E, AccessWidth8, ~BIT4, 0x00);
- }
-
- EfuseByte = SATA_FIS_BASE_EFUSE_LOC;
- GetEfuseStatus (&EfuseByte, StdHeader);
-
- if (EfuseByte & BIT0) {
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGDA, AccessWidth8, 0xFB, 0x04);
- }
-
- ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGDA, AccessWidth8, &PortStatusByte);
- if ( ((PortStatusByte & 0xF0) == 0x10) ) {
- RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_PMIOA_REG08, AccessWidth8, 0, BIT5);
- }
-
- if ( FchSataInternal100Spread ) {
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG84), AccessWidth32, 0xFFFFFFFF, 0x04, StdHeader);
- }
-}
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Family/Hudson2/Hudson2SataService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Family/Hudson2/Hudson2SataService.c
deleted file mode 100644
index ef57858495..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Family/Hudson2/Hudson2SataService.c
+++ /dev/null
@@ -1,681 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Graphics Controller family specific service procedure
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 48230 $ @e \$Date: 2011-03-05 06:55:12 +0800 (Sat, 05 Mar 2011) $
- *
- */
-
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*/
-
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATASERVICE_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-UINT8 NumOfSataPorts = 8;
-
-/**
- * FchSataGpioInitial - Sata GPIO function Procedure
- *
- * - Private function
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchSataGpioInitial (
- IN VOID *FchDataPtr
- )
-{
- UINT32 Bar5;
- UINT32 FchSataBarRegDword;
- UINT32 EMb;
- UINT32 SataGpioVariableDword;
- UINT8 FchSataSgpio0;
- FCH_DATA_BLOCK *LocalCfgPtr;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
-
- Bar5 = 0;
- EMb = 0;
- FchSataSgpio0 = (UINT8) LocalCfgPtr->Sata.SataSgpio0;
-
- SataBar5setting (LocalCfgPtr, &Bar5);
- ReadMem (Bar5 + FCH_SATA_BAR5_REG1C , AccessWidth32, &FchSataBarRegDword);
- EMb = (Bar5 + (( FchSataBarRegDword & 0xFFFF0000) >> 14));
-
- if ( EMb ) {
- SataGpioVariableDword = 0x03040C00;
- WriteMem ( Bar5 + EMb, AccessWidth32, &SataGpioVariableDword);
- SataGpioVariableDword = 0x00C08240;
- WriteMem ( Bar5 + EMb + 4, AccessWidth32, &SataGpioVariableDword);
- SataGpioVariableDword = 0x00000001;
- WriteMem ( Bar5 + EMb + 8, AccessWidth32, &SataGpioVariableDword);
-
- if ( FchSataSgpio0 ) {
- SataGpioVariableDword = 0x00000060;
- } else {
- SataGpioVariableDword = 0x00000061;
- }
-
- WriteMem ( Bar5 + EMb + 0x0C, AccessWidth32, &SataGpioVariableDword);
- RwMem ((Bar5 + FCH_SATA_BAR5_REG20), AccessWidth16, ~(BIT8), BIT8);
-
- do {
- ReadMem (Bar5 + FCH_SATA_BAR5_REG20 , AccessWidth32, &FchSataBarRegDword);
- FchSataBarRegDword = FchSataBarRegDword & BIT8;
- } while ( FchSataBarRegDword != 0 );
-
- SataGpioVariableDword = 0x03040F00;
- WriteMem ( Bar5 + EMb, AccessWidth32, &SataGpioVariableDword);
- SataGpioVariableDword = 0x00008240;
- WriteMem ( Bar5 + EMb + 4, AccessWidth32, &SataGpioVariableDword);
- SataGpioVariableDword = 0x00000002;
- WriteMem ( Bar5 + EMb + 8, AccessWidth32, &SataGpioVariableDword);
- SataGpioVariableDword = 0x00800000;
- WriteMem ( Bar5 + EMb + 0x0C, AccessWidth32, &SataGpioVariableDword);
- SataGpioVariableDword = 0x0F003700;
- WriteMem ( Bar5 + EMb + 0x0C, AccessWidth32, &SataGpioVariableDword);
- RwMem ((Bar5 + FCH_SATA_BAR5_REG20), AccessWidth16, ~(BIT8), BIT8);
-
- do {
- ReadMem (Bar5 + FCH_SATA_BAR5_REG20 , AccessWidth32, &FchSataBarRegDword);
- FchSataBarRegDword = FchSataBarRegDword & BIT8;
- } while ( FchSataBarRegDword != 0 );
- }
-}
-
-/**
- * FchInitMidProgramSataRegs - Sata Pci Configuration Space
- * register setting
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitMidProgramSataRegs (
- IN VOID *FchDataPtr
- )
-{
- UINT8 FchSataMsiCapability;
- UINT8 FchSataTargetSupport8Device;
- UINT8 FchSataDisableGenericMode;
- UINT8 FchSataSgpio0;
- UINT8 FchSataSgpio1;
- UINT8 FchSataPhyPllShutDown;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- FchSataMsiCapability = (UINT8) LocalCfgPtr->Sata.SataMsiCapability;
- FchSataTargetSupport8Device = (UINT8) LocalCfgPtr->Sata.SataTargetSupport8Device;
- FchSataDisableGenericMode = (UINT8) LocalCfgPtr->Sata.SataDisableGenericMode;
- FchSataSgpio0 = (UINT8) LocalCfgPtr->Sata.SataSgpio0;
- FchSataSgpio1 = (UINT8) LocalCfgPtr->Sata.SataSgpio1;
- FchSataPhyPllShutDown = (UINT8) LocalCfgPtr->Sata.SataPhyPllShutDown;
-
- //
- // Enabled SATA MSI capability
- // SATA MSI and D3 Power State Capability
- //
- if ( FchSataMsiCapability ) {
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG34), AccessWidth8, 0, 0x50, StdHeader);
- } else {
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG34), AccessWidth8, 0, 0x70, StdHeader);
- }
-
- //
- // Disable SATA FLR Capability
- //
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG70), AccessWidth16, 0x00FF, 0x00, StdHeader);
-
- //
- // Sata Target Support 8 devices function
- //
- if ( FchSataTargetSupport8Device ) {
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGDA, AccessWidth16, ~BIT12, BIT12);
- } else {
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGDA, AccessWidth16, ~BIT12, 0x00);
- }
-
- //
- // Sata Generic Mode setting
- //
- if ( FchSataDisableGenericMode ) {
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGDA, AccessWidth16, ~BIT13, BIT13);
- } else {
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGDA, AccessWidth16, ~BIT13, 0x00);
- }
-
- //
- // Sata GPIO Initial
- //
- if ( FchSataSgpio0 ) {
- FchSataGpioInitial ( LocalCfgPtr );
- }
-
- if ( FchSataSgpio1 ) {
- FchSataGpioInitial ( LocalCfgPtr );
- }
-
- //
- // Sata Phy Pll Shutdown setting
- //
- if ( FchSataPhyPllShutDown ) {
- RwPci (((SATA_BUS_DEV_FUN << 16) + 0x87), AccessWidth8, ~(BIT6), BIT6, StdHeader);
- } else {
- RwPci (((SATA_BUS_DEV_FUN << 16) + 0x87), AccessWidth8, ~(BIT6), 0x00, StdHeader);
- }
-
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG4C), AccessWidth32, (UINT32) (~ (0x3f << 26)), (UINT32) (0x3f << 26), StdHeader);
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG48), AccessWidth32, (UINT32) (~ (0x01 << 11)), (UINT32) (0x01 << 11), StdHeader);
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG84), AccessWidth32, (UINT32) (~ (0x01 << 31)), (UINT32) (0x00 << 31), StdHeader);
-}
-
-
-/**
- * FchInitLateProgramSataRegs - Sata Pci Configuration Space
- * register setting
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitLateProgramSataRegs (
- IN VOID *FchDataPtr
- )
-{
- UINT8 PortNumByte;
- UINT32 Bar5;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- SataBar5setting (LocalCfgPtr, &Bar5);
- //
- //Clear error status
- //
- RwMem ((Bar5 + FCH_SATA_BAR5_REG130), AccessWidth32, 0xFFFFFFFF, 0xFFFFFFFF);
- RwMem ((Bar5 + FCH_SATA_BAR5_REG1B0), AccessWidth32, 0xFFFFFFFF, 0xFFFFFFFF);
- RwMem ((Bar5 + FCH_SATA_BAR5_REG230), AccessWidth32, 0xFFFFFFFF, 0xFFFFFFFF);
- RwMem ((Bar5 + FCH_SATA_BAR5_REG2B0), AccessWidth32, 0xFFFFFFFF, 0xFFFFFFFF);
- RwMem ((Bar5 + FCH_SATA_BAR5_REG330), AccessWidth32, 0xFFFFFFFF, 0xFFFFFFFF);
- RwMem ((Bar5 + FCH_SATA_BAR5_REG3B0), AccessWidth32, 0xFFFFFFFF, 0xFFFFFFFF);
- RwMem ((Bar5 + FCH_SATA_BAR5_REG430), AccessWidth32, 0xFFFFFFFF, 0xFFFFFFFF);
- RwMem ((Bar5 + FCH_SATA_BAR5_REG4B0), AccessWidth32, 0xFFFFFFFF, 0xFFFFFFFF);
-
- for ( PortNumByte = 0; PortNumByte < MAX_SATA_PORTS; PortNumByte++ ) {
- RwMem ((Bar5 + 0x110 + (PortNumByte * 0x80)), AccessWidth32, 0xFFFFFFFF, 0x00);
- }
-}
-
-/**
- * sataBar5RegSet - Sata Bar5 register setting
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-SataBar5RegSet (
- IN VOID *FchDataPtr
- )
-{
- UINT32 AndMaskDword;
- UINT32 OrMaskDword;
- UINT32 Bar5;
- UINT8 EfuseByte;
- UINT8 FchSataAggrLinkPmCap;
- UINT8 FchSataPortMultCap;
- UINT8 FchSataPscCap;
- UINT8 FchSataSscCap;
- UINT8 FchSataFisBasedSwitching;
- UINT8 FchSataCccSupport;
- UINT8 FchSataAhciEnclosureManagement;
- FCH_DATA_BLOCK *LocalCfgPtr;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
-
- FchSataAggrLinkPmCap = (UINT8) LocalCfgPtr->Sata.SataAggrLinkPmCap;
- FchSataPortMultCap = (UINT8) LocalCfgPtr->Sata.SataPortMultCap;
- FchSataPscCap = (UINT8) LocalCfgPtr->Sata.SataPscCap;
- FchSataSscCap = (UINT8) LocalCfgPtr->Sata.SataSscCap;
- FchSataFisBasedSwitching = (UINT8) LocalCfgPtr->Sata.SataFisBasedSwitching;
- FchSataCccSupport = (UINT8) LocalCfgPtr->Sata.SataCccSupport;
- FchSataAhciEnclosureManagement = (UINT8) LocalCfgPtr->Sata.SataAhciEnclosureManagement;
-
- AndMaskDword = 0;
- OrMaskDword = 0;
- Bar5 = 0;
-
- SataBar5setting (LocalCfgPtr, &Bar5);
- EfuseByte = SATA_FIS_BASE_EFUSE_LOC;
- GetEfuseStatus (&EfuseByte, LocalCfgPtr->StdHeader);
-
- if ( !FchSataPortMultCap ) {
- AndMaskDword |= BIT12;
- }
-
- if ( FchSataAggrLinkPmCap ) {
- OrMaskDword |= BIT11;
- } else {
- AndMaskDword |= BIT11;
- }
-
- if ( FchSataPscCap ) {
- OrMaskDword |= BIT1;
- } else {
- AndMaskDword |= BIT1;
- }
-
- if ( FchSataSscCap ) {
- OrMaskDword |= BIT26;
- } else {
- AndMaskDword |= BIT26;
- }
-
- if ( FchSataFisBasedSwitching ) {
- if (EfuseByte & BIT1) {
- AndMaskDword |= BIT10;
- } else {
- OrMaskDword |= BIT10;
- }
- } else {
- AndMaskDword |= BIT10;
- }
-
- //
- // Disabling CCC (Command Completion Coalescing) support.
- //
- if ( FchSataCccSupport ) {
- OrMaskDword |= BIT19;
- } else {
- AndMaskDword |= BIT19;
- }
-
- if ( FchSataAhciEnclosureManagement ) {
- OrMaskDword |= BIT27;
- } else {
- AndMaskDword |= BIT27;
- }
-
- RwMem ((Bar5 + FCH_SATA_BAR5_REGFC), AccessWidth32, ~AndMaskDword, OrMaskDword);
-
- //
- // SATA ESP port setting
- // These config bits are set for SATA driver to identify which ports are external SATA ports and need to
- // support hotplug. If a port is set as an external SATA port and need to support hotplug, then driver will
- // not enable power management (HIPM & DIPM) for these ports.
- //
- if ( LocalCfgPtr->Sata.SataEspPort.SataPortReg != 0 ) {
- RwMem ((Bar5 + FCH_SATA_BAR5_REGF8), AccessWidth32, ~(LocalCfgPtr->Sata.SataEspPort.SataPortReg), 0);
- RwMem ((Bar5 + FCH_SATA_BAR5_REGF8), AccessWidth32, 0xFF00FF00, (LocalCfgPtr->Sata.SataEspPort.SataPortReg << 16));
- //
- // External SATA Port Indication Registers
- // If any of the ports was programmed as an external port, HCAP.SXS should also be set
- //
- RwMem ((Bar5 + FCH_SATA_BAR5_REGFC), AccessWidth32, ~(BIT20), BIT20);
- } else {
- //
- // External SATA Port Indication Registers
- // If any of the ports was programmed as an external port, HCAP.SXS should also be set (Clear for no ESP port)
- //
- RwMem ((Bar5 + FCH_SATA_BAR5_REGF8), AccessWidth32, 0xFF00FF00, 0x00);
- RwMem ((Bar5 + FCH_SATA_BAR5_REGFC), AccessWidth32, ~(BIT20), 0x00);
- }
-
- if ( FchSataFisBasedSwitching ) {
- if (EfuseByte & BIT1) {
- RwMem ((Bar5 + FCH_SATA_BAR5_REGF8), AccessWidth32, 0x00FFFFFF, 0x00);
- } else {
- RwMem ((Bar5 + FCH_SATA_BAR5_REGF8), AccessWidth32, 0x00FFFFFF, 0xFF000000);
- }
- } else {
- RwMem ((Bar5 + FCH_SATA_BAR5_REGF8), AccessWidth32, 0x00FFFFFF, 0x00);
- }
-
- if ( LocalCfgPtr->Sata.BiosOsHandOff == 1 ) {
- RwMem ((Bar5 + FCH_SATA_BAR5_REG24), AccessWidth8, ~BIT0, BIT0);
- } else {
- RwMem ((Bar5 + FCH_SATA_BAR5_REG24), AccessWidth8, ~BIT0, 0x00);
- }
-}
-
-/**
- * FchSataSetDeviceNumMsi - Program Sata controller support
- * device number cap & MSI cap
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchSataSetDeviceNumMsi (
- IN VOID *FchDataPtr
- )
-{
- UINT32 Bar5;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- Bar5 = 0;
- SataBar5setting (LocalCfgPtr, &Bar5);
- //
- // RAID or AHCI
- //
- if (LocalCfgPtr->Sata.SataMode.IdeEnable == DISABLED) {
- //
- // IDE2 Controller is enabled
- //
- if (LocalCfgPtr->Sata.SataMode.Sata6AhciCap == ENABLED) {
- //
- // 6 AHCI mode
- //
- RwMem ((Bar5 + FCH_SATA_BAR5_REG0C), AccessWidth8, 0x00, 0x3F);
- RwMem ((Bar5 + FCH_SATA_BAR5_REG00), AccessWidth8, ~(BIT2 + BIT1 + BIT0), BIT2 + BIT0);
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG50 + 2), AccessWidth8, ~(BIT3 + BIT2 + BIT1), BIT2 + BIT1, StdHeader);
- RwMem ((Bar5 + FCH_SATA_BAR5_REGFC), AccessWidth8, 0x07, 0x30);
- } else {
- RwMem ((Bar5 + FCH_SATA_BAR5_REG0C), AccessWidth8, 0x00, 0x0F);
- if ( LocalCfgPtr->Sata.SataCccSupport ) {
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG50 + 2), AccessWidth8, ~(BIT3 + BIT2 + BIT1), BIT2 + BIT1, StdHeader);
- RwMem ((Bar5 + FCH_SATA_BAR5_REGFC), AccessWidth8, 0x07, 0x20);
- } else {
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG50 + 2), AccessWidth8, ~(BIT3 + BIT2 + BIT1), BIT2, StdHeader);
- }
- }
- } else {
- //
- // IDE2 Controller is disabled
- //
- RwMem ((Bar5 + FCH_SATA_BAR5_REG00), AccessWidth8, ~(BIT2 + BIT1 + BIT0), BIT2 + BIT1 + BIT0);
- RwMem ((Bar5 + FCH_SATA_BAR5_REG0C), AccessWidth8, 0x00, 0xFF);
- if ( LocalCfgPtr->Sata.SataCccSupport ) {
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG50 + 2), AccessWidth8, ~(BIT3 + BIT2 + BIT1), BIT3, StdHeader);
- RwMem ((Bar5 + FCH_SATA_BAR5_REGFC), AccessWidth8, 0x07, 0x40);
- } else {
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG50 + 2), AccessWidth8, ~(BIT3 + BIT2 + BIT1), BIT2 + BIT1, StdHeader);
- }
- }
-}
-
-
-/**
- * FchSataDriveDetection - Sata drive detection
- *
- * - Sata Ide & Sata Ide to Ahci only
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- * @param[in] *Bar5Ptr Sata BAR5 base address.
- *
- */
-VOID
-FchSataDriveDetection (
- IN VOID *FchDataPtr,
- IN UINT32 *Bar5Ptr
- )
-{
- UINT32 SataBarInfo;
- UINT8 PortNumByte;
- UINT8 SataPortType;
- UINT16 IoBaseWord;
- UINT16 SataLoopVarWord;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- for ( PortNumByte = 0; PortNumByte < 4; PortNumByte++ ) {
-
- ReadMem (*Bar5Ptr + FCH_SATA_BAR5_REG128 + PortNumByte * 0x80, AccessWidth32, &SataBarInfo);
-
- if ( ( SataBarInfo & 0x0F ) == 0x03 ) {
- if ( PortNumByte & BIT0 ) {
- //
- //this port belongs to secondary channel
- //
- ReadPci (((UINT32) (SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG18), AccessWidth16, &IoBaseWord, StdHeader);
- } else {
- //
- //this port belongs to primary channel
- //
- ReadPci (((UINT32) (SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG10), AccessWidth16, &IoBaseWord, StdHeader);
- }
-
- //
- //if legacy ide mode, then the bar registers don't contain the correct values. So we need to hardcode them
- //
- if ( LocalCfgPtr->Sata.SataClass == SataLegacyIde ) {
- IoBaseWord = ( (0x170) | ((UINT16) ( (~((UINT8) (PortNumByte & BIT0) << 7)) & 0x80 )) );
- }
-
- if ( PortNumByte & BIT1 ) {
- //
- //this port is slave
- //
- SataPortType = 0xB0;
- } else {
- //
- //this port is master
- //
- SataPortType = 0xA0;
- }
-
- IoBaseWord &= 0xFFF8;
- LibAmdIoWrite (AccessWidth8, IoBaseWord + 6, &SataPortType, StdHeader);
-
- //
- //Wait in loop for 30s for the drive to become ready
- //
- for ( SataLoopVarWord = 0; SataLoopVarWord < 300000; SataLoopVarWord++ ) {
- LibAmdIoRead (AccessWidth8, IoBaseWord + 7, &SataPortType, StdHeader);
- if ( (SataPortType & 0x88) == 0 ) {
- break;
- }
- FchStall (100, StdHeader);
- }
- }
- }
-}
-
-/**
- * FchShutdownUnconnectedSataPortClock - Shutdown unconnected
- * Sata port clock
- *
- * - Sata Ide & Sata Ide to Ahci only
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- * @param[in] Bar5 Sata BAR5 base address.
- *
- */
-VOID
-FchShutdownUnconnectedSataPortClock (
- IN VOID *FchDataPtr,
- IN UINT32 Bar5
- )
-{
- UINT8 PortNumByte;
- UINT8 PortSataStatusByte;
- UINT8 NumOfPorts;
- UINT8 FchSataClkAutoOff;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
- FchSataClkAutoOff = (UINT8) LocalCfgPtr->Sata.SataClkAutoOff;
-
- NumOfPorts = 0;
- //
- // Enable SATA auto clock control by default
- //
- for ( PortNumByte = 0; PortNumByte < MAX_SATA_PORTS; PortNumByte++ ) {
- ReadMem (Bar5 + FCH_SATA_BAR5_REG128 + (PortNumByte * 0x80), AccessWidth8, &PortSataStatusByte);
- //
- // Shutdown the clock for the port and do the necessary port reporting changes.
- // Error port status should be 1 not 3
- //
- if ( ((PortSataStatusByte & 0x0F) != 0x03) && (! ((LocalCfgPtr->Sata.SataEspPort.SataPortReg) & (1 << PortNumByte))) ) {
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG40 + 2), AccessWidth8, 0xFF, (1 << PortNumByte), StdHeader);
- RwMem (Bar5 + FCH_SATA_BAR5_REG0C, AccessWidth8, ~(1 << PortNumByte), 00);
- }
- } ///end of for (PortNumByte=0;PortNumByte<6;PortNumByte++)
-
- ReadMem (Bar5 + FCH_SATA_BAR5_REG0C, AccessWidth8, &PortSataStatusByte);
-
- //
- //if all ports are in disabled state, report at least one port
- //
- if ( (PortSataStatusByte & 0xFF) == 0) {
- RwMem (Bar5 + FCH_SATA_BAR5_REG0C, AccessWidth8, (UINT32) ~(0xFF), 01);
- }
-
- ReadMem (Bar5 + FCH_SATA_BAR5_REG0C, AccessWidth8, &PortSataStatusByte);
-
- for (PortNumByte = 0; PortNumByte < MAX_SATA_PORTS; PortNumByte ++) {
- if (PortSataStatusByte & (1 << PortNumByte)) {
- NumOfPorts++;
- }
- }
-
- if ( NumOfPorts == 0) {
- NumOfPorts = 0x01;
- }
-
- RwMem (Bar5 + FCH_SATA_BAR5_REG00, AccessWidth8, 0xE0, NumOfPorts - 1);
-}
-
-/**
- * FchSataSetPortGenMode - Set Sata port mode (each) for
- * Gen1/Gen2/Gen3
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchSataSetPortGenMode (
- IN VOID *FchDataPtr
- )
-{
- UINT32 Bar5;
- UINT8 PortNumByte;
- UINT8 PortModeByte;
- UINT16 SataPortMode;
- BOOLEAN FchSataHotRemovalEnh;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- FchSataHotRemovalEnh = LocalCfgPtr->Sata.SataHotRemovalEnh;
-
- SataBar5setting (LocalCfgPtr, &Bar5);
- SataPortMode = (UINT16)LocalCfgPtr->Sata.SataPortMd.SataPortMode;
- PortNumByte = 0;
-
- while ( PortNumByte < 8 ) {
- PortModeByte = (UINT8) (SataPortMode & 3);
- if ( (PortModeByte == BIT0) || (PortModeByte == BIT1) ) {
- if ( PortModeByte == BIT0 ) {
- //
- // set GEN 1
- //
- RwMem (Bar5 + FCH_SATA_BAR5_REG12C + PortNumByte * 0x80, AccessWidth8, 0x0F, 0x10);
- }
-
- if ( PortModeByte == BIT1 ) {
- //
- // set GEN2 (default is GEN3)
- //
- RwMem (Bar5 + FCH_SATA_BAR5_REG12C + PortNumByte * 0x80, AccessWidth8, 0x0F, 0x20);
- }
-
- RwMem (Bar5 + FCH_SATA_BAR5_REG12C + PortNumByte * 0x80, AccessWidth8, 0xFF, 0x01);
- }
-
- SataPortMode >>= 2;
- PortNumByte ++;
- }
-
- FchStall (1000, StdHeader);
- SataPortMode = (UINT16)LocalCfgPtr->Sata.SataPortMd.SataPortMode;
- PortNumByte = 0;
-
- while ( PortNumByte < 8 ) {
- PortModeByte = (UINT8) (SataPortMode & 3);
-
- if ( (PortModeByte == BIT0) || (PortModeByte == BIT1) ) {
- RwMem (Bar5 + FCH_SATA_BAR5_REG12C + PortNumByte * 0x80, AccessWidth8, 0xFE, 0x00);
- }
-
- PortNumByte ++;
- SataPortMode >>= 2;
- }
-
- //
- // Sata Hot Removal Enhance setting
- //
- if ( FchSataHotRemovalEnh ) {
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG80), AccessWidth16, ~BIT8, BIT8, StdHeader);
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REGA8), AccessWidth16, ~BIT0, BIT0, StdHeader);
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG80), AccessWidth16, ~BIT8, 0, StdHeader);
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Ide2AhciEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Ide2AhciEnv.c
deleted file mode 100644
index 89add10c67..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Ide2AhciEnv.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch SATA controller (Ide2Ahci mode)
- *
- * Init SATA Ide2Ahci features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_SATA_IDE2AHCIENV_FILECODE
-
-/**
- * FchInitEnvSataIde2Ahci - Config SATA Ide2Ahci controller
- * before PCI emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitEnvSataIde2Ahci (
- IN VOID *FchDataPtr
- )
-{
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- //
- // Class code
- //
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG08), AccessWidth32, 0, 0x01018F40, StdHeader);
- //
- // Device ID
- //
- if ( LocalCfgPtr->Sata.SataClass == SataIde2Ahci7804 ) {
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG02), AccessWidth16, 0, FCH_SATA_AMDAHCI_DID, StdHeader);
- } else {
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG02), AccessWidth16, 0, FCH_SATA_AHCI_DID, StdHeader);
- }
- //
- // SSID
- //
- if (LocalCfgPtr->Sata.SataAhciSsid != NULL ) {
- RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Sata.SataAhciSsid, StdHeader);
- }
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Ide2AhciLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Ide2AhciLate.c
deleted file mode 100644
index 449da54c3b..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Ide2AhciLate.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch SATA controller (Ide2Ahci mode)
- *
- * Init SATA Ide2Ahci features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_SATA_IDE2AHCILATE_FILECODE
-
-/**
- * FchInitLateSataIde2Ahci - Prepare SATA Ide2Ahci controller to
- * boot to OS.
- *
- * - Set class ID to Ide2Ahci (if set to Ide2Ahci * Mode)
- * - Enable Ide2Ahci interrupt
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitLateSataIde2Ahci (
- IN VOID *FchDataPtr
- )
-{
- UINT32 Bar5;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- //
- //program the AHCI class code
- //
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG08), AccessWidth32, 0, 0x01060100, StdHeader);
-
- SataBar5setting (LocalCfgPtr, &Bar5);
-
- //
- //Set interrupt enable bit
- //
- RwMem ((Bar5 + 0x04), AccessWidth8, (UINT32)~0, BIT1);
- ShutdownUnconnectedSataPortClock (LocalCfgPtr, Bar5);
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Ide2AhciLib.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Ide2AhciLib.c
deleted file mode 100644
index f52f9e67ce..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Ide2AhciLib.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Fch SATA Ide2Ahci controller Library
- *
- * SATA Ide2Ahci Library
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_SATA_IDE2AHCILIB_FILECODE
-
-/**
- * sataIde2AhciSetDeviceNumMsi - Program Ide2Ahci controller support
- * device number cap & MSI cap
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-SataIde2AhciSetDeviceNumMsi (
- IN VOID *FchDataPtr
- )
-{
- FCH_INTERFACE *LocalCfgPtr;
-
- LocalCfgPtr = (FCH_INTERFACE *)FchDataPtr;
-
- SataSetDeviceNumMsi (LocalCfgPtr);
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Ide2AhciMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Ide2AhciMid.c
deleted file mode 100644
index 4cf3b8100e..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Ide2AhciMid.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch SATA controller (Ide2Ahci mode)
- *
- * Init SATA Ide2Ahci features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_SATA_IDE2AHCIMID_FILECODE
-
-/**
- * FchInitMidSataIde2Ahci - Config SATA Ide2Ahci controller
- * after PCI emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitMidSataIde2Ahci (
- IN VOID *FchDataPtr
- )
-{
- UINT32 Bar5;
- FCH_DATA_BLOCK *LocalCfgPtr;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
-
- SataIde2AhciSetDeviceNumMsi (LocalCfgPtr);
-
- SataBar5setting (LocalCfgPtr, &Bar5);
- //
- //If this is not S3 resume and also if SATA set to one of IDE mode, then implement drive detection workaround.
- //
- if ( ! (LocalCfgPtr->Misc.S3Resume) ) {
- SataDriveDetection (LocalCfgPtr, &Bar5);
- }
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/RaidEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/RaidEnv.c
deleted file mode 100644
index 3e455bfe4c..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/RaidEnv.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch SATA controller (Raid mode)
- *
- * Init SATA Raid features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_SATA_RAIDENV_FILECODE
-//
-// Declaration of local functions
-//
-
-/**
- * FchInitEnvSataRaid - Config SATA Raid controller before PCI
- * emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitEnvSataRaid (
- IN VOID *FchDataPtr
- )
-{
- UINT32 SataSSIDValue;
- UINT32 DeviceId;
- UINT8 EfuseValue;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- //
- // Class code
- //
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG08), AccessWidth32, 0, 0x01040040, StdHeader);
- //
- // Device ID
- //
- SataSSIDValue = NULL;
- if (LocalCfgPtr->Sata.SataRaid5Ssid != NULL ) {
- SataSSIDValue = LocalCfgPtr->Sata.SataRaid5Ssid;
- }
-
- DeviceId = FCH_SATA_RAID5_DID;
- EfuseValue = SATA_EFUSE_LOCATION;
- GetEfuseStatus (&EfuseValue, StdHeader);
-
- if (( EfuseValue & SATA_EFUSE_BIT ) || ( LocalCfgPtr->Sata.SataForceRaid == 1 )) {
- DeviceId = FCH_SATA_RAID_DID;
- if (LocalCfgPtr->Sata.SataRaidSsid != NULL ) {
- SataSSIDValue = LocalCfgPtr->Sata.SataRaidSsid;
- }
- }
-
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG02), AccessWidth16, 0, DeviceId, StdHeader);
- //
- // SSID
- //
- if (SataSSIDValue != NULL ) {
- RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG2C, AccessWidth32, 0, SataSSIDValue, StdHeader);
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/RaidLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/RaidLate.c
deleted file mode 100644
index f77d206df9..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/RaidLate.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch SATA controller (Raid mode)
- *
- * Init SATA Raid features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_SATA_RAIDLATE_FILECODE
-//
-// Declaration of local functions
-//
-
-/**
- * FchInitLateSataRaid - Prepare SATA Raid controller to boot to
- * OS.
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitLateSataRaid (
- IN VOID *FchDataPtr
- )
-{
-}
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/RaidLib.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/RaidLib.c
deleted file mode 100644
index b7e0d5bd05..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/RaidLib.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Fch SATA AHCI/RAID controller Library
- *
- * SATA AHCI/RAID Library
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_SATA_RAIDLIB_FILECODE
-
-/**
- * sataRaidSetDeviceNumMsi - Program RAID controller support
- * device number cap & MSI cap
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-SataRaidSetDeviceNumMsi (
- IN VOID *FchDataPtr
- )
-{
- FCH_INTERFACE *LocalCfgPtr;
-
- LocalCfgPtr = (FCH_INTERFACE *)FchDataPtr;
-
- SataSetDeviceNumMsi (LocalCfgPtr);
-}
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/RaidMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/RaidMid.c
deleted file mode 100644
index 7763e369bd..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/RaidMid.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch SATA controller (Raid mode)
- *
- * Init SATA Raid features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_SATA_RAIDMID_FILECODE
-//
-// Declaration of local functions
-//
-
-/**
- * FchInitMidSataRaid - Config SATA Raid controller after PCI
- * emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitMidSataRaid (
- IN VOID *FchDataPtr
- )
-{
- UINT32 Bar5;
- FCH_DATA_BLOCK *LocalCfgPtr;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
-
- SataRaidSetDeviceNumMsi (LocalCfgPtr);
- SataBar5setting (LocalCfgPtr, &Bar5);
- ShutdownUnconnectedSataPortClock (LocalCfgPtr, Bar5);
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataEnv.c
deleted file mode 100644
index e5a84a9571..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataEnv.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch SATA controller
- *
- * Init SATA features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_SATA_SATAENV_FILECODE
-
-extern VOID FchInitEnvProgramSataPciRegs (IN VOID *FchDataPtr);
-
-/**
- * FchInitEnvSata - Config SATA controller before PCI emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitEnvSata (
- IN VOID *FchDataPtr
- )
-{
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- if ( LocalCfgPtr->Sata.SataMode.SataEnable == 0 ) {
- return; //return if SATA controller is disabled.
- }
-
- FchInitEnvProgramSataPciRegs (FchDataPtr);
- //
- // Call Sub-function for each Sata mode
- //
- if (( LocalCfgPtr->Sata.SataClass == SataAhci7804) || (LocalCfgPtr->Sata.SataClass == SataAhci )) {
- FchInitEnvSataAhci ( LocalCfgPtr );
- }
-
- if (( LocalCfgPtr->Sata.SataClass == SataIde2Ahci) || (LocalCfgPtr->Sata.SataClass == SataIde2Ahci7804 )) {
- FchInitEnvSataIde2Ahci ( LocalCfgPtr );
- }
-
- if (( LocalCfgPtr->Sata.SataClass == SataNativeIde) || (LocalCfgPtr->Sata.SataClass == SataLegacyIde )) {
- FchInitEnvSataIde ( LocalCfgPtr );
- }
-
- if ( LocalCfgPtr->Sata.SataClass == SataRaid) {
- FchInitEnvSataRaid ( LocalCfgPtr );
- }
-
- //
- // SATA IRQ Resource
- //
- SataSetIrqIntResource (LocalCfgPtr, StdHeader);
-
- //
- // SATA PHY Programming Sequence
- //
- FchProgramSataPhy (StdHeader);
-
- SataDisableWriteAccess (StdHeader);
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataEnvLib.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataEnvLib.c
deleted file mode 100644
index d4d85b5075..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataEnvLib.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Fch SATA controller Library
- *
- * SATA Library
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_SATA_SATAENVLIB_FILECODE
-
-/**
- * sataSetIrqIntResource - Config SATA IRQ/INT# resource
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- * @param[in] StdHeader
- *
- */
-VOID
-SataSetIrqIntResource (
- IN VOID *FchDataPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 ValueByte;
- FCH_DATA_BLOCK *LocalCfgPtr;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- //
- // IRQ14/IRQ15 come from IDE or SATA
- //
- ValueByte = 0x08;
- LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &ValueByte, StdHeader);
- LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, &ValueByte, StdHeader);
- ValueByte = ValueByte & 0x0F;
-
- if (LocalCfgPtr->Sata.SataClass == SataLegacyIde) {
- ValueByte = ValueByte | 0x50;
- } else {
- if (LocalCfgPtr->Sata.SataIdeMode == 1) {
- //
- // Both IDE & SATA set to Native mode
- //
- ValueByte = ValueByte | 0xF0;
- }
- }
-
- LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &ValueByte, StdHeader);
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataIdeEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataIdeEnv.c
deleted file mode 100644
index 5b19e7930f..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataIdeEnv.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch SATA (IDE mode) controller
- *
- * Init SATA IDE (Native IDE) mode features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_SATA_SATAIDEENV_FILECODE
-
-/**
- * FchInitEnvSataIde - Config SATA IDE controller before PCI
- * emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitEnvSataIde (
- IN VOID *FchDataPtr
- )
-{
- UINT8 ChannelByte;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- //
- // Class code
- //
- if ( LocalCfgPtr->Sata.SataClass == SataLegacyIde ) {
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG08), AccessWidth32, 0, 0x01018A40, StdHeader);
- } else {
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG08), AccessWidth32, 0, 0x01018F40, StdHeader);
- }
- //
- // Device ID
- //
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG02), AccessWidth16, 0, FCH_SATA_DID, StdHeader);
- //
- // SSID
- //
- if (LocalCfgPtr->Sata.SataIdeSsid != NULL ) {
- RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Sata.SataIdeSsid, StdHeader);
- }
- //
- // Sata IDE Channel configuration
- //
- ChannelByte = 0x00;
- ReadPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG48 + 3), AccessWidth8, &ChannelByte, StdHeader);
- ChannelByte &= 0xCF;
-
- if ( LocalCfgPtr->Sata.SataDisUnusedIdePChannel ) {
- ChannelByte |= 0x10;
- }
-
- if ( LocalCfgPtr->Sata.SataDisUnusedIdeSChannel ) {
- ChannelByte |= 0x20;
- }
-
- WritePci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG48 + 3), AccessWidth8, &ChannelByte, StdHeader);
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataIdeLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataIdeLate.c
deleted file mode 100644
index 98e12cf13c..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataIdeLate.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch SATA (IDE mode) controller
- *
- * Init SATA IDE (Native IDE) mode features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_SATA_SATAIDELATE_FILECODE
-
-/**
- * FchInitLateSataIde - Prepare SATA controller to boot to OS.
- *
- * - Set class ID to AHCI (if set to AHCI * Mode)
- * - Enable AHCI interrupt
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitLateSataIde (
- IN VOID *FchDataPtr
- )
-{
- UINT32 Bar5;
- FCH_DATA_BLOCK *LocalCfgPtr;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
-
- SataBar5setting (LocalCfgPtr, &Bar5);
- ShutdownUnconnectedSataPortClock (LocalCfgPtr, Bar5);
-}
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataIdeLib.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataIdeLib.c
deleted file mode 100644
index 2607b6c8c7..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataIdeLib.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Fch SATA Ide controller Library
- *
- * SATA Ide2Ahci Library
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_SATA_SATAIDELIB_FILECODE
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataIdeMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataIdeMid.c
deleted file mode 100644
index 2aca675167..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataIdeMid.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch SATA (IDE mode) controller
- *
- * Init SATA IDE (Native IDE) mode features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_SATA_SATAIDEMID_FILECODE
-
-/**
- * FchInitMidSataIde - Config SATA controller after PCI
- * emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitMidSataIde (
- IN VOID *FchDataPtr
- )
-{
- UINT32 Bar5;
- FCH_DATA_BLOCK *LocalCfgPtr;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
-
- Bar5 = 0;
- SataBar5setting (LocalCfgPtr, &Bar5);
- //
- //If this is not S3 resume and also if SATA set to one of IDE mode, then implement drive detection workaround.
- //
- if ( ! (LocalCfgPtr->Misc.S3Resume) ) {
- SataDriveDetection (LocalCfgPtr, &Bar5);
- }
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataLate.c
deleted file mode 100644
index 4973ac5d6d..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataLate.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch SATA controller
- *
- * Init SATA features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 46088 $ @e \$Date: 2011-01-28 11:24:26 +0800 (Fri, 28 Jan 2011) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_SATA_SATALATE_FILECODE
-
-extern VOID FchInitLateProgramSataRegs (IN VOID *FchDataPtr);
-
-/**
- * FchInitLateSata - Prepare SATA controller to boot to OS.
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitLateSata (
- IN VOID *FchDataPtr
- )
-{
- UINT8 SataPciCommandByte;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- //
- //Return immediately is sata controller is not enabled
- //
- if ( LocalCfgPtr->Sata.SataMode.SataEnable == 0 ) {
- return;
- }
-
- //
- // Set Sata PCI Configuration Space Write enable
- //
- SataEnableWriteAccess (StdHeader);
-
- //
- // Set Sata Controller Memory & IO access enable
- //
- ReadPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG04), AccessWidth8, &SataPciCommandByte, StdHeader);
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG04), AccessWidth8, 0xFF, 0x03, StdHeader);
-
- //
- // Call Sub-function for each Sata mode
- //
- if (( LocalCfgPtr->Sata.SataClass == SataAhci7804) || (LocalCfgPtr->Sata.SataClass == SataAhci )) {
- FchInitLateSataAhci ( LocalCfgPtr );
- }
-
- if (( LocalCfgPtr->Sata.SataClass == SataIde2Ahci) || (LocalCfgPtr->Sata.SataClass == SataIde2Ahci7804 )) {
- FchInitLateSataIde2Ahci ( LocalCfgPtr );
- }
-
- if (( LocalCfgPtr->Sata.SataClass == SataNativeIde) || (LocalCfgPtr->Sata.SataClass == SataLegacyIde )) {
- FchInitLateSataIde ( LocalCfgPtr );
- }
-
- if ( LocalCfgPtr->Sata.SataClass == SataRaid) {
- FchInitLateSataRaid ( LocalCfgPtr );
- }
-
- FchInitLateProgramSataRegs ( LocalCfgPtr );
-
- //
- // Restore Sata Controller Memory & IO access status
- //
- WritePci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG04), AccessWidth8, &SataPciCommandByte, StdHeader);
-
- //
- // Set Sata PCI Configuration Space Write disable
- //
- SataDisableWriteAccess (StdHeader);
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataLib.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataLib.c
deleted file mode 100644
index e88d51ef04..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataLib.c
+++ /dev/null
@@ -1,260 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Fch SATA controller Library
- *
- * SATA Library
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 46088 $ @e \$Date: 2011-01-28 11:24:26 +0800 (Fri, 28 Jan 2011) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_SATA_SATALIB_FILECODE
-
-extern VOID FchSataSetDeviceNumMsi (IN VOID *FchDataPtr);
-
-/**
- * sataBar5setting - Config SATA BAR5
- *
- *
- * @param[in] FchDataPtr - Fch configuration structure pointer.
- * @param[in] *Bar5Ptr - SATA BAR5 buffer.
- *
- */
-VOID
-SataBar5setting (
- IN VOID *FchDataPtr,
- IN UINT32 *Bar5Ptr
- )
-{
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- //
- //Get BAR5 value
- //
- ReadPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG24), AccessWidth32, Bar5Ptr, StdHeader);
-
- //
- //Assign temporary BAR if is not already assigned
- //
- if ( (*Bar5Ptr == 0) || (*Bar5Ptr == - 1) ) {
- //
- //assign temporary BAR5
- //
- if ( (LocalCfgPtr->Sata.TempMmio == 0) || (LocalCfgPtr->Sata.TempMmio == - 1) ) {
- *Bar5Ptr = 0xFEC01000;
- } else {
- *Bar5Ptr = LocalCfgPtr->Sata.TempMmio;
- }
- WritePci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG24), AccessWidth32, Bar5Ptr, StdHeader);
- }
-
- //
- //Clear Bits 9:0
- //
- *Bar5Ptr = *Bar5Ptr & 0xFFFFFC00;
-}
-
-/**
- * sataEnableWriteAccess - Enable Sata PCI configuration space
- *
- * @param[in] StdHeader
- *
- */
-VOID
-SataEnableWriteAccess (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- //
- // BIT0 Enable write access to PCI header
- //
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG40), AccessWidth8, 0xff, BIT0, StdHeader);
-}
-
-/**
- * sataDisableWriteAccess - Disable Sata PCI configuration space
- *
- * @param[in] StdHeader
- *
- */
-VOID
-SataDisableWriteAccess (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- //
- // Disable write access to PCI header
- //
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG40), AccessWidth8, ~BIT0, 0, StdHeader);
-}
-
-
-
-#ifdef SATA_BUS_DEV_FUN_FPGA
-
-/**
- * FchSataBar5settingFpga
- *
- * @param[in] LocalCfgPtr
- * @param[in] Bar5
- *
- */
-VOID
-FchSataBar5settingFpga (
- IN FCH_DATA_BLOCK *LocalCfgPtr,
- IN UINT32 *Bar5
- )
-{
- UINT8 Value;
-
- //Get BAR5 value
- ReadPci (((SATA_BUS_DEV_FUN_FPGA << 16) + FCH_SATA_REG24), AccWidthUint32, Bar5);
-
- //Assign temporary BAR if is not already assigned
- if ( (*Bar5 == 0) || (*Bar5 == - 1) ) {
- //assign temporary BAR5
- if ( (LocalCfgPtr->Sata.TempMMIO == 0) || (LocalCfgPtr->Sata.TempMMIO == - 1) ) {
- *Bar5 = 0xFEC01000;
- } else {
- *Bar5 = LocalCfgPtr->Sata.TempMMIO;
- }
- WritePci (((SATA_BUS_DEV_FUN_FPGA << 16) + FCH_SATA_REG24), AccWidthUint32, Bar5);
- }
-
- //Clear Bits 9:0
- *Bar5 = *Bar5 & 0xFFFFFC00;
- Value = 0x07;
- WritePci (((SATA_BUS_DEV_FUN_FPGA << 16) + 0x04), AccWidthUint8, &Value);
- WritePci (((PCIB_BUS_DEV_FUN << 16) + 0x04), AccWidthUint8, &Value);
-}
-
-/**
- * FchSataDriveDetectionFpga
- *
- * @param[in] LocalCfgPtr
- * @param[in] Bar5
- *
- */
-VOID
-FchSataDriveDetectionFpga (
- IN FCH_DATA_BLOCK *LocalCfgPtr,
- IN UINT32 *Bar5
- )
-{
- UINT32 SataBarFpgaInfo;
- UINT8 PortNum;
- UINT8 SataFpaPortType;
- UINT16 IoBase;
- UINT16 SataFpgaLoopVarWord;
- AMD_CONFIG_PARAMS *StdHeader;
-
- StdHeader = LocalCfgPtr->StdHeader;
-
- TRACE ((DMSG_FCH_TRACE, "FCH - Entering sata drive detection procedure\n\n"));
- TRACE ((DMSG_FCH_TRACE, "SATA BAR5 is %X \n", *pBar5));
-
- for ( PortNum = 0; PortNum < 4; PortNum++ ) {
- ReadMem (*Bar5 + FCH_SATA_BAR5_REG128 + PortNum * 0x80, AccWidthUint32, &SataBarFpgaInfo);
- if ( ( SataBarFpgaInfo & 0x0F ) == 0x03 ) {
- if ( PortNum & BIT0 ) {
- //this port belongs to secondary channel
- ReadPci (((UINT32) (SATA_BUS_DEV_FUN_FPGA << 16) + FCH_SATA_REG18), AccWidthUint16, &IoBase);
- } else {
- //this port belongs to primary channel
- ReadPci (((UINT32) (SATA_BUS_DEV_FUN_FPGA << 16) + FCH_SATA_REG10), AccWidthUint16, &IoBase);
- }
-
- //if legacy ide mode, then the bar registers don't contain the correct values. So we need to hardcode them
- if ( LocalCfgPtr->Sata.SataClass == SataLegacyIde ) {
- IoBase = ( (0x170) | ((UINT16) ( (~((UINT8) (PortNum & BIT0) << 7)) & 0x80 )) );
- }
-
- if ( PortNum & BIT1 ) {
- //this port is slave
- SataFpaPortType = 0xB0;
- } else {
- //this port is master
- SataFpaPortType = 0xA0;
- }
-
- IoBase &= 0xFFF8;
- LibAmdIoWrite (AccessWidth8, IoBase + 6, &SataFpaPortType, StdHeader);
-
- //Wait in loop for 30s for the drive to become ready
- for ( SataFpgaLoopVarWord = 0; SataFpgaLoopVarWord < 300000; SataFpgaLoopVarWord++ ) {
- LibAmdIoRead (AccessWidth8, IoBase + 7, &SataFpaPortType, StdHeader);
- if ( (SataFpaPortType & 0x88) == 0 ) {
- break;
- }
- FchStall (100, StdHeader);
- }
- }
- }
-}
-
-/**
- * FchSataDriveFpga -
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchSataDriveFpga (
- IN VOID *FchDataPtr
- )
-{
- UINT32 Bar5;
- FCH_DATA_BLOCK *LocalCfgPtr;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
-
- Bar5 = 0;
- SataBar5setting (LocalCfgPtr, &Bar5);
-
- FchSataBar5settingFpga (LocalCfgPtr, &Bar5);
- FchSataDriveDetectionFpga (LocalCfgPtr, &Bar5);
-}
-
-#endif
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataMid.c
deleted file mode 100644
index d9497ea2a7..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataMid.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch SATA controller
- *
- * Init SATA features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_SATA_SATAMID_FILECODE
-
-extern VOID FchInitMidProgramSataRegs (IN VOID *FchDataPtr);
-
-/**
- * FchInitMidSata - Config SATA controller after PCI emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitMidSata (
- IN VOID *FchDataPtr
- )
-{
- UINT8 SataPciCommandByte;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- if ( LocalCfgPtr->Sata.SataMode.SataEnable == 0 ) {
- return; ///return if SATA controller is disabled.
- }
-
- //
- // Set Sata PCI Configuration Space Write enable
- //
- SataEnableWriteAccess (StdHeader);
-
- //
- // Set Sata Controller Memory & IO access enable
- //
- ReadPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG04), AccessWidth8, &SataPciCommandByte, StdHeader);
- RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG04), AccessWidth8, 0xFF, 0x03, StdHeader);
-
- //
- // Sata Bar5 register setting for Index 0xFC
- //
- SataBar5RegSet ( LocalCfgPtr );
-
- FchInitMidProgramSataRegs ( LocalCfgPtr );
-
- //
- // Set Sata port mode (each) for Gen1/Gen2/Gen3
- //
- SataSetPortGenMode ( LocalCfgPtr );
-
- //
- // Call Sub-function for each Sata mode
- //
- if (( LocalCfgPtr->Sata.SataClass == SataAhci7804) || (LocalCfgPtr->Sata.SataClass == SataAhci )) {
- FchInitMidSataAhci ( LocalCfgPtr );
- }
-
- if (( LocalCfgPtr->Sata.SataClass == SataIde2Ahci) || (LocalCfgPtr->Sata.SataClass == SataIde2Ahci7804 )) {
- FchInitMidSataIde2Ahci ( LocalCfgPtr );
- }
-
- if (( LocalCfgPtr->Sata.SataClass == SataNativeIde) || (LocalCfgPtr->Sata.SataClass == SataLegacyIde )) {
- FchInitMidSataIde ( LocalCfgPtr );
- }
-
- if ( LocalCfgPtr->Sata.SataClass == SataRaid) {
- FchInitMidSataRaid ( LocalCfgPtr );
- }
-
-#ifdef SATA_BUS_DEV_FUN_FPGA
- FchSataDriveFpga ( LocalCfgPtr );
-#endif
-
- //
- // Restore Sata Controller Memory & IO access status
- //
- WritePci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG04), AccessWidth8, &SataPciCommandByte, StdHeader);
-
- //
- // Set Sata PCI Configuration Space Write disable
- //
- SataDisableWriteAccess (StdHeader);
-}
-
-/**
- * SataSetDeviceNumMsi - Program Sata controller support device
- * number cap & MSI cap
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-SataSetDeviceNumMsi (
- IN VOID *FchDataPtr
- )
-{
- FchSataSetDeviceNumMsi ( FchDataPtr );
-}
-
-/**
- * SataDriveDetection - Sata drive detection
- *
- * - Sata Ide & Sata Ide to Ahci only
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- * @param[in] *Bar5Ptr Sata BAR5 base address.
- *
- */
-VOID
-SataDriveDetection (
- IN VOID *FchDataPtr,
- IN UINT32 *Bar5Ptr
- )
-{
- FchSataDriveDetection ( FchDataPtr, Bar5Ptr );
-}
-
-/**
- * shutdownUnconnectedSataPortClock - Shutdown unconnected Sata port clock
- *
- * - Sata Ide & Sata Ide to Ahci only
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- * @param[in] Bar5 Sata BAR5 base address.
- *
- */
-VOID
-ShutdownUnconnectedSataPortClock (
- IN VOID *FchDataPtr,
- IN UINT32 Bar5
- )
-{
- FchShutdownUnconnectedSataPortClock ( FchDataPtr, Bar5);
-}
-
-/**
- * SataSetPortGenMode - Set Sata port mode (each) for
- * Gen1/Gen2/Gen3
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-SataSetPortGenMode (
- IN VOID *FchDataPtr
- )
-{
- FchSataSetPortGenMode ( FchDataPtr );
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataReset.c
deleted file mode 100644
index b6d92ded89..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/SataReset.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch Sata controller
- *
- * Init Sata Controller features (PEI phase).
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 45603 $ @e \$Date: 2011-01-19 14:29:05 +0800 (Wed, 19 Jan 2011) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_SATA_SATARESET_FILECODE
-
-extern VOID FchInitResetSataProgram (IN VOID *FchDataPtr);
-
-/**
- * FchInitResetSata - Config Sata controller during Power-On
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitResetSata (
- IN VOID *FchDataPtr
- )
-{
- FchInitResetSataProgram ( FchDataPtr );
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sd/SdEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sd/SdEnv.c
deleted file mode 100644
index 29040a7de8..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sd/SdEnv.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch SD controller
- *
- * Init SD Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#define FILECODE PROC_FCH_SD_SDENV_FILECODE
-
-/**
- * FchInitEnvSd - Config SD controller before PCI emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitEnvSd (
- IN VOID *FchDataPtr
- )
-{
- UINT8 SdData;
- UINT32 SdData32;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- //
- // SD Configuration
- //
- if ( LocalCfgPtr->Sd.SdConfig != SdDisable) {
- RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG41, AccessWidth8, 0xF1, 0x48);
- RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG42, AccessWidth8, 0xFE, 0x00);
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGE7, AccessWidth8, 0x00, 0x12);
- //
- // INT#A SD resource
- //
- SdData = 0x97; /// Azalia APIC index
- LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &SdData, StdHeader);
- SdData = 0x10; /// IRQ16 (INTA#)
- LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &SdData, StdHeader);
-
- ReadPci ((SD_BUS_DEV_FUN << 16) + SD_PCI_REGA4, AccessWidth32, &SdData32, StdHeader);
- SdData32 |= BIT31 + BIT24 + BIT18 + BIT16; ///ADMA
-
- if ( LocalCfgPtr->Sd.SdConfig == SdDma) {
- SdData32 &= ~(BIT16 + BIT24); ///DMA
- } else if ( LocalCfgPtr->Sd.SdConfig == SdPio) {
- SdData32 &= ~(BIT16 + BIT18 + BIT24); ///PIO
- }
-
- SdData32 &= ~(BIT17 + BIT23); ///clear bitwidth
- SdData32 |= (LocalCfgPtr->Sd.SdSpeed << 17) + (LocalCfgPtr->Sd.SdBitWidth << 23);
- RwPci ((SD_BUS_DEV_FUN << 16) + SD_PCI_REGA4, AccessWidth32, 0, SdData32, StdHeader);
-
- // SD: Some SD cards cannot be detected in HIGH speed mode
- RwPci ((SD_BUS_DEV_FUN << 16) + SD_PCI_REGB0, AccessWidth32, (UINT32) (~ (0x03 << 10)), (UINT32) (0x03 << 10), StdHeader);
- } else {
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD3, AccessWidth8, 0xBF, 0x00);
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sd/SdLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sd/SdLate.c
deleted file mode 100644
index ad66637f1e..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sd/SdLate.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch SD controller
- *
- * Init SD Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#define FILECODE PROC_FCH_SD_SDLATE_FILECODE
-
-/**
- * FchInitLateSd - Prepare SD controller to boot to OS.
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitLateSd (
- IN VOID *FchDataPtr
- )
-{
-}
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sd/SdMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Sd/SdMid.c
deleted file mode 100644
index 8b6a5509da..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Sd/SdMid.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch SD controller
- *
- * Init SD Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#define FILECODE PROC_FCH_SD_SDMID_FILECODE
-
-/**
- * FchInitMidSd - Config SD controller after PCI emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitMidSd (
- IN VOID *FchDataPtr
- )
-{
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/LpcEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/LpcEnv.c
deleted file mode 100644
index d2738975e4..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/LpcEnv.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch LPC controller
- *
- * Init LPC Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#define FILECODE PROC_FCH_SPI_LPCENV_FILECODE
-/**
- * FchInitEnvLpcPciTable - PCI device registers initial during
- * early POST.
- *
- */
-REG8_MASK FchInitEnvLpcPciTable[] =
-{
- //
- // LPC Device (Bus 0, Dev 20, Func 3)
- //
- {0x00, LPC_BUS_DEV_FUN, 0},
- {FCH_LPC_REG40, ~BIT2, BIT2}, /// Enabling LPC DMA Function 0x40[2]=1b 0x78[0]=0b
- {FCH_LPC_REG48, 0x00, BIT0 + BIT1 + BIT2},
- {FCH_LPC_REG78, 0xFC, 00}, /// Enabling LPC DMA Function 0x40[2]=1b 0x78[0]=0b / Disables MSI capability
- {FCH_LPC_REGBB, ~BIT0, BIT0 + BIT3 + BIT4 + BIT5}, /// Enabled SPI Prefetch from HOST.
- {0xFF, 0xFF, 0xFF},
-};
-
-/**
- * FchInitEnvLpc - Config LPC controller before PCI emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitEnvLpc (
- IN VOID *FchDataPtr
- )
-{
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- //
- // LPC CFG programming
- //
- //
- // Turn on and configure LPC clock (48MHz)
- //
- RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x28, AccessWidth32, ~(BIT21 + BIT20 + BIT19), 2 << 19);
- RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40, AccessWidth8, ~BIT7, 0);
-
- //
- // Initialization of pci config space
- //
- ProgramPciByteTable ((REG8_MASK*) (&FchInitEnvLpcPciTable[0]), sizeof (FchInitEnvLpcPciTable) / sizeof (REG8_MASK), StdHeader);
-
- //
- // SSID for LPC Controller
- //
- if (LocalCfgPtr->Spi.LpcSsid != NULL ) {
- RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Spi.LpcSsid, StdHeader);
- }
- //
- // LPC MSI
- //
- if ( LocalCfgPtr->Spi.LpcMsiEnable ) {
- RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG78, AccessWidth32, ~BIT1, BIT1, StdHeader);
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/LpcLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/LpcLate.c
deleted file mode 100644
index 2246c950d4..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/LpcLate.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch LPC controller
- *
- * Init LPC Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#define FILECODE PROC_FCH_SPI_LPCLATE_FILECODE
-
-/**
- * FchInitLateLpc - Prepare Ir controller to boot to OS.
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitLateLpc (
- IN VOID *FchDataPtr
- )
-{
- RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGBB, AccessWidth8, 0xBF, BIT3 + BIT4 + BIT5, ((FCH_DATA_BLOCK *)FchDataPtr)->StdHeader);
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/LpcMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/LpcMid.c
deleted file mode 100644
index 92e77bc202..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/LpcMid.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch LPC controller
- *
- * Init LPC Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#define FILECODE PROC_FCH_SPI_LPCMID_FILECODE
-
-/**
- * FchInitMidLpc - Config Lpc controller after PCI emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitMidLpc (
- IN VOID *FchDataPtr
- )
-{
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/LpcReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/LpcReset.c
deleted file mode 100644
index 45e842ac49..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/LpcReset.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch LPC controller
- *
- * Init LPC Controller features (PEI phase).
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#define FILECODE PROC_FCH_SPI_LPCRESET_FILECODE
-/**
- * FchInitResetLpcPciTable - Lpc (Spi) device registers initial
- * during the power on stage.
- *
- *
- *
- *
- */
-REG8_MASK FchInitResetLpcPciTable[] =
-{
- //
- // LPC Device (Bus 0, Dev 20, Func 3)
- //
- {0x00, LPC_BUS_DEV_FUN, 0},
-
- {FCH_LPC_REG48, 0x00, BIT0 + BIT1 + BIT2},
- {FCH_LPC_REG7C, 0x00, BIT0 + BIT2},
- {FCH_LPC_REG78, 0xF0, BIT2 + BIT3}, /// Enable LDRQ pin
- {FCH_LPC_REGBB, 0xFF, BIT3 + BIT4 + BIT5},
- //
- // Set 0xBB [5:3] = 111 to improve SPI timing margin.
- // Set 0xBA [6:5] = 11 improve SPI timing margin. (SPI Prefetch enhancement)
- //
- {FCH_LPC_REGBB, 0xBE, BIT0 + BIT3 + BIT4 + BIT5},
- {FCH_LPC_REGBA, 0x9F, BIT5 + BIT6},
- // Force EC_PortActive to 1 to fix possible IR non function issue when NO_EC_SUPPORT is defined
- {FCH_LPC_REGA4, ~ BIT0, BIT0},
- {0xFF, 0xFF, 0xFF},
-};
-
-
-/**
- * FchInitResetLpc - Config Lpc controller during Power-On
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitResetLpc (
- IN VOID *FchDataPtr
- )
-{
- FCH_RESET_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- //
- // enable prefetch on Host, set LPC cfg 0xBB bit 0 to 1
- //
- RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGBA, AccessWidth16, 0xFFFF, BIT8, StdHeader);
-
- ProgramPciByteTable ( (REG8_MASK*) (&FchInitResetLpcPciTable[0]), sizeof (FchInitResetLpcPciTable) / sizeof (REG8_MASK), StdHeader);
-
- if ( LocalCfgPtr->LegacyFree ) {
- RwPci (((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG44), AccessWidth32, 00, 0x0003C000, StdHeader);
- } else {
- RwPci (((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG44), AccessWidth32, 00, 0xFF03FFD5, StdHeader);
- }
-
- // Enabling SPI ROM Prefetch
- // Set LPC cfg 0xBA bit 8
- RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGBA, AccessWidth16, 0xFFFF, BIT8, StdHeader);
-
- // Enable SPI Prefetch for USB, set LPC cfg 0xBA bit 7 to 1.
- RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGBA, AccessWidth16, 0xFFFF, BIT7, StdHeader);
-}
-
-/**
- * FchInitRecoveryLpc - Config Lpc controller during Crisis
- * Recovery
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitRecoveryLpc (
- IN VOID *FchDataPtr
- )
-{
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/SpiEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/SpiEnv.c
deleted file mode 100644
index 5be4752390..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/SpiEnv.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch Spi (Lpc) controller
- *
- * Init Spi (Lpc) Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#define FILECODE PROC_FCH_SPI_SPIENV_FILECODE
-
-/**
- * FchInitEnvSpi - Config Spi controller before PCI emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitEnvSpi (
- IN VOID *FchDataPtr
- )
-{
- FchInitEnvLpc (FchDataPtr);
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/SpiLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/SpiLate.c
deleted file mode 100644
index bc6387e242..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/SpiLate.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch Spi (Lpc) controller
- *
- * Init Spi (Lpc) Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#define FILECODE PROC_FCH_SPI_SPILATE_FILECODE
-
-/**
- * FchInitLateSpi - Prepare Spi controller to boot to OS.
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitLateSpi (
- IN VOID *FchDataPtr
- )
-{
- FchInitLateLpc (FchDataPtr);
-}
-
-/**
- * FchSpiUnlock - Fch SPI Unlock
- *
- *
- * @param[in] FchDataPtr
- *
- */
-VOID
-FchSpiUnlock (
- IN VOID *FchDataPtr
- )
-{
- UINT32 SpiRomBase;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
- SpiRomBase = UserOptions.CfgSpiRomBaseAddress;
-
- RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG50, AccessWidth32, ~(BIT0 + BIT1), 0, StdHeader);
- RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG54, AccessWidth32, ~(BIT0 + BIT1), 0, StdHeader);
- RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG58, AccessWidth32, ~(BIT0 + BIT1), 0, StdHeader);
- RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG5C, AccessWidth32, ~(BIT0 + BIT1), 0, StdHeader);
- RwMem (SpiRomBase + FCH_SPI_MMIO_REG00, AccessWidth32, ~(BIT22 + BIT23), (BIT22 + BIT23));
-}
-
-/**
- * FchSpiLock - Fch SPI lock
- *
- *
- * @param[in] FchDataPtr
- *
- */
-VOID
-FchSpiLock (
- IN VOID *FchDataPtr
- )
-{
- UINT32 SpiRomBase;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
- SpiRomBase = UserOptions.CfgSpiRomBaseAddress;
-
- RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG50, AccessWidth32, ~(BIT0 + BIT1), (BIT0 + BIT1), StdHeader);
- RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG54, AccessWidth32, ~(BIT0 + BIT1), (BIT0 + BIT1), StdHeader);
- RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG58, AccessWidth32, ~(BIT0 + BIT1), (BIT0 + BIT1), StdHeader);
- RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG5C, AccessWidth32, ~(BIT0 + BIT1), (BIT0 + BIT1), StdHeader);
- RwMem (SpiRomBase + FCH_SPI_MMIO_REG00, AccessWidth32, ~(BIT22 + BIT23), 0);
-} \ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/SpiMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/SpiMid.c
deleted file mode 100644
index 6ba636a983..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/SpiMid.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch Spi (Lpc) controller
- *
- * Init Spi (Lpc) Controller features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#define FILECODE PROC_FCH_SPI_SPIMID_FILECODE
-
-/**
- * FchInitMidSpi - Config Spi controller after PCI emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitMidSpi (
- IN VOID *FchDataPtr
- )
-{
- FchInitMidLpc (FchDataPtr);
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/SpiReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/SpiReset.c
deleted file mode 100644
index d288cce5d4..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/SpiReset.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch Spi controller
- *
- * Init Spi Controller features (PEI phase).
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#define FILECODE PROC_FCH_SPI_SPIRESET_FILECODE
-
-/**
- * FchInitResetSpi - Config Spi controller during Power-On
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitResetSpi (
- IN VOID *FchDataPtr
- )
-{
- UINT32 SpiModeByte;
- UINT32 SpiRomBase;
- FCH_RESET_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
- SpiRomBase = UserOptions.CfgSpiRomBaseAddress;
-
- //
- // Set Spi ROM Base Address
- //
- RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGA0, AccessWidth32, 0x001F, SpiRomBase, StdHeader);
-
- //
- // Spi Mode Initial
- //
- RwMem (SpiRomBase + FCH_SPI_MMIO_REG00, AccessWidth32, 0xFFFFFFFF, (BIT19 + BIT24 + BIT25 + BIT26));
- RwMem (SpiRomBase + FCH_SPI_MMIO_REG0C, AccessWidth32, 0xFFC0FFFF, 0 );
-
- if (LocalCfgPtr->SpiSpeed) {
- RwMem (SpiRomBase + FCH_SPI_MMIO_REG0C, AccessWidth32, ~(BIT13 + BIT12), ((LocalCfgPtr->SpiSpeed - 1 ) << 12));
- }
-
- if (LocalCfgPtr->FastSpeed) {
- RwMem (SpiRomBase + FCH_SPI_MMIO_REG0C, AccessWidth32, ~(BIT15 + BIT14), ((LocalCfgPtr->FastSpeed - 1 ) << 14));
- }
-
- RwMem (SpiRomBase + FCH_SPI_MMIO_REG1C, AccessWidth32, ~(BIT10), ((LocalCfgPtr->BurstWrite) << 10));
-
- SpiModeByte = LocalCfgPtr->Mode;
- if (LocalCfgPtr->Mode) {
- if ((SpiModeByte == FCH_SPI_MODE_QUAL_114) || (SpiModeByte == FCH_SPI_MODE_QUAL_112) || (SpiModeByte == FCH_SPI_MODE_QUAL_144) || (SpiModeByte == FCH_SPI_MODE_QUAL_122)) {
- }
- RwMem (SpiRomBase + FCH_SPI_MMIO_REG00, AccessWidth32, ~( BIT18 + BIT29 + BIT30), ((LocalCfgPtr->Mode & 1) << 18) + ((LocalCfgPtr->Mode & 6) << 28));
- }
-}
-
-/**
- * FchInitRecoverySpi - Config Spi controller during Crisis
- * Recovery
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitRecoverySpi (
- IN VOID *FchDataPtr
- )
-{
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/EhciEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/EhciEnv.c
deleted file mode 100644
index 72d2fe4b08..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/EhciEnv.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch USB EHCI controller
- *
- * Init USB EHCI features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*;********************************************************************************
-;
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*********************************************************************************/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_USB_EHCIENV_FILECODE
-
-/**
- * FchInitEnvUsbEhci - Config USB EHCI controller before PCI
- * emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitEnvUsbEhci (
- IN VOID *FchDataPtr
- )
-{
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/EhciLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/EhciLate.c
deleted file mode 100644
index 98daf4a788..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/EhciLate.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch USB EHCI controller
- *
- * Init USB EHCI features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*;********************************************************************************
-;
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*********************************************************************************/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_USB_EHCILATE_FILECODE
-
-/**
- * FchInitLateUsbEhci - Config USB EHCI controller before OS
- * boot
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitLateUsbEhci (
- IN VOID *FchDataPtr
- )
-{
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/EhciMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/EhciMid.c
deleted file mode 100644
index b651022af3..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/EhciMid.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch USB EHCI controller
- *
- * Init USB EHCI features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*;********************************************************************************
-;
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*********************************************************************************/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_USB_EHCIMID_FILECODE
-
-extern VOID FchEhciInitAfterPciInit (IN UINT32 Value, IN FCH_DATA_BLOCK* FchDataPtr);
-//
-// Declaration of local functions
-//
-/**
- * EhciInitAfterPciInit - Config USB controller after PCI emulation
- *
- * @param[in] Value Controller PCI config address (bus# + device# + function#)
- * @param[in] FchDataPtr Fch configuration structure pointer.
- */
-VOID EhciInitAfterPciInit (IN UINT32 Value, IN FCH_DATA_BLOCK* FchDataPtr);
-
-/**
- * FchInitMidUsbEhci - Config USB EHCI controller after PCI
- * emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitMidUsbEhci (
- IN VOID *FchDataPtr
- )
-{
- FCH_DATA_BLOCK *LocalCfgPtr;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
-
- FchInitMidUsbEhci1 (LocalCfgPtr);
- FchInitMidUsbEhci2 (LocalCfgPtr);
- FchInitMidUsbEhci3 (LocalCfgPtr);
-}
-
-/**
- * FchInitMidUsbEhci1 - Config USB1 EHCI controller after PCI emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitMidUsbEhci1 (
- IN FCH_DATA_BLOCK *FchDataPtr
- )
-{
- UINT32 DeviceId;
-
- DeviceId = (USB1_EHCI_BUS_DEV_FUN << 16);
- EhciInitAfterPciInit (DeviceId, FchDataPtr);
-
-}
-
-/**
- * FchInitMidUsbEhci2 - Config USB2 EHCI controller after PCI emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitMidUsbEhci2 (
- IN FCH_DATA_BLOCK *FchDataPtr
- )
-{
- UINT32 DeviceId;
-
- DeviceId = (USB2_EHCI_BUS_DEV_FUN << 16);
- EhciInitAfterPciInit (DeviceId, FchDataPtr);
-
-}
-
-/**
- * FchInitMidUsbEhci3 - Config USB3 EHCI controller after PCI emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-
-VOID
-FchInitMidUsbEhci3 (
- IN FCH_DATA_BLOCK *FchDataPtr
- )
-{
- UINT32 DeviceId;
-
- DeviceId = (USB3_EHCI_BUS_DEV_FUN << 16);
- EhciInitAfterPciInit (DeviceId, FchDataPtr);
-
-}
-
-/**
- * EhciInitAfterPciInit - Config EHCI controller after PCI
- * emulation
- *
- *
- * @param[in] Value EHCI Controler info.
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-EhciInitAfterPciInit (
- IN UINT32 Value,
- IN FCH_DATA_BLOCK *FchDataPtr
- )
-{
- FchEhciInitAfterPciInit ( Value, FchDataPtr);
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/EhciReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/EhciReset.c
deleted file mode 100644
index 5b93b11600..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/EhciReset.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch Ehci controller
- *
- * Init Ehci Controller features (PEI phase).
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_USB_EHCIRESET_FILECODE
-
-/**
- * FchInitResetEhci - Config Ehci controller during Power-On
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitResetEhci (
- IN VOID *FchDataPtr
- )
-{
-}
-
-/**
- * FchInitRecoveryLpc - Config Ehci controller during Crisis
- * Recovery
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitRecoveryEhci (
- IN VOID *FchDataPtr
- )
-{
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciEnvService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciEnvService.c
deleted file mode 100644
index 7e061c806b..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciEnvService.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch USB EHCI controller
- *
- * Init USB EHCI features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*;********************************************************************************
-;
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*********************************************************************************/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2EHCIENVSERVICE_FILECODE
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciLateService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciLateService.c
deleted file mode 100644
index 9f59a8b62b..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciLateService.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch USB EHCI controller
- *
- * Init USB EHCI features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*;********************************************************************************
-;
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*********************************************************************************/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2EHCILATESERVICE_FILECODE
-//
-// Declaration of local functions
-//
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciMidService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciMidService.c
deleted file mode 100644
index c79064e9d5..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciMidService.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch USB EHCI controller
- *
- * Init USB EHCI features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 47163 $ @e \$Date: 2011-02-16 07:23:13 +0800 (Wed, 16 Feb 2011) $
- *
- */
-/*;********************************************************************************
-;
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*********************************************************************************/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2EHCIMIDSERVICE_FILECODE
-//
-// Declaration of local functions
-//
-
-/**
- * FchEhciInitAfterPciInit - Config USB controller after PCI emulation
- *
- * @param[in] Value Controller PCI config address (bus# + device# + function#)
- * @param[in] FchDataPtr Fch configuration structure pointer.
- */
-VOID
-FchEhciInitAfterPciInit (
- IN UINT32 Value,
- IN FCH_DATA_BLOCK *FchDataPtr
- )
-{
- UINT32 BarAddress;
- UINT32 Var;
-
- //
- //Get BAR address
- //
- ReadPci ((UINT32) Value + FCH_EHCI_REG10, AccessWidth32, &BarAddress, FchDataPtr->StdHeader);
- if ( (BarAddress != - 1) && (BarAddress != 0) ) {
- //
- //Enable Memory access
- //
- RwPci ((UINT32) Value + FCH_EHCI_REG04, AccessWidth8, 0, BIT1, FchDataPtr->StdHeader);
- if (FchDataPtr->Usb.EhciSsid != NULL ) {
- RwPci ((UINT32) Value + FCH_EHCI_REG2C, AccessWidth32, 0x00, FchDataPtr->Usb.EhciSsid, FchDataPtr->StdHeader);
- }
- //
- //USB Common PHY CAL & Control Register setting
- //
- Var = 0x00020F00;
- WriteMem (BarAddress + FCH_EHCI_BAR_REGC0, AccessWidth32, &Var);
- //
- // IN AND OUT DATA PACKET FIFO THRESHOLD
- // EHCI BAR 0xA4 //IN threshold bits[7:0]=0x40 //OUT threshold bits[23:16]=0x40
- //
- RwMem (BarAddress + FCH_EHCI_BAR_REGA4, AccessWidth32, 0xFF00FF00, 0x00400040);
- //
- // EHCI Dynamic Clock Gating Feature
- // Enable Global Clock Gating (BIT14)
- //
- RwMem (BarAddress + FCH_EHCI_BAR_REGBC, AccessWidth32, ~( BIT12 + BIT14), BIT12 + BIT14);
- RwMem (BarAddress + FCH_EHCI_BAR_REGB0, AccessWidth32, ~BIT5, BIT5);
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth16, ~BIT12, BIT12);
- //
- // Enable adding extra flops to PHY rsync path
- // Step 1:
- // EHCI_BAR 0xB4 [6] = 1
- // EHCI_BAR 0xB4 [7] = 0
- // EHCI_BAR 0xB4 [12] = 0 ("VLoad")
- // All other bit field untouched
- // Step 2:
- // EHCI_BAR 0xB4[12] = 1
- //
- // USB 2.0 Ports Driving Strength
- // Step1 is done by default
- // Step2
- RwMem (BarAddress + FCH_EHCI_BAR_REGB4, AccessWidth32, ~BIT12, BIT12);
- // Step3
- RwMem (BarAddress + FCH_EHCI_BAR_REGC4, AccessWidth32, (UINT32) (~ 0x00000f00), 0x00000200);
- RwMem (BarAddress + FCH_EHCI_BAR_REGC0, AccessWidth32, (UINT32) (~ 0x0000ff00), 0x00000f00);
-
- //Set EHCI_pci_configx50[6]='1' to disable EHCI MSI support
- RwPci ((UINT32) Value + FCH_EHCI_REG50, AccessWidth32, ~ ((UINT32) (0x01 << 6)), (UINT32) (0x01 << 6), FchDataPtr->StdHeader);
- // EHCI Async Park Mode
- //Set EHCI_pci_configx50[11:8]=0x1
- //Set EHCI_pci_configx50[15:12]=0x1
- //Set EHCI_pci_configx50[17]=0x1
- RwPci ((UINT32) Value + FCH_EHCI_REG50, AccessWidth32, ~ ((UINT32) (0x0F << 8)), (UINT32) (0x01 << 8), FchDataPtr->StdHeader);
- RwPci ((UINT32) Value + FCH_EHCI_REG50, AccessWidth32, ~ ((UINT32) (0x0F << 12)), (UINT32) (0x01 << 12), FchDataPtr->StdHeader);
- RwPci ((UINT32) Value + FCH_EHCI_REG50, AccessWidth32, ~ ((UINT32) (0x01 << 17)), (UINT32) (0x01 << 17), FchDataPtr->StdHeader);
-
- // Enabling EHCI Async Stop Enhancement
- //Set EHCI_pci_configx50[29]='1' to disableEnabling EHCI Async Stop Enhancement
- //
- RwPci ((UINT32) Value + FCH_EHCI_REG50, AccessWidth32, ~ ((UINT32) (0x01 << 29)), (UINT32) (0x01 << 29), FchDataPtr->StdHeader);
- //
- // recommended setting "EHCI Advance PHY Power Savings"
- // Set EHCI_pci_configx50[31]='1'
- // Fix for EHCI controller driver yellow sign issue under device manager
- // when used in conjunction with HSET tool driver. EHCI PCI config 0x50[20]=1
- // Disable USB data cache to resolve USB controller hang issue with Lan adaptor.
- // EHCI PCI config register 50h bit 26 to `1'.
- //
- RwPci ((UINT32) Value + FCH_EHCI_REG50 + 2, AccessWidth16, (UINT16)0xFFFF, BIT16 + BIT10, FchDataPtr->StdHeader);
- //
- // USB Delay A-Link Express L1 State
- // PING Response Fix Enable EHCI_PCI_Config x54[1] = 1
- // Enable empty list mode. x54[3]
- // Enable "L1 Early Exit" functionality. 0x54 [6:5] = 0x3 0x54 [9:7] = 0x4
- // EHCI PING Response Fix Enable 0x54 [1] = 0x1
- //
- RwPci ((UINT32) Value + FCH_EHCI_REG54, AccessWidth32, ~BIT0, 0x0000026b, FchDataPtr->StdHeader);
- if ( FchDataPtr->Usb.UsbMsiEnable) {
- RwPci ((UINT32) Value + FCH_EHCI_REG50, AccessWidth32, ~BIT6, 0x00, FchDataPtr->StdHeader);
- }
- // Long Delay on Framelist Read Causing EHCI DMA to Address 0 - Fix
- // RWPCI ((UINT32) Value + FCH_EHCI_REG54, AccWidthUint32 | S3_SAVE, ~BIT13, BIT13);
- // LS connection can't wake up system from S3/S4/S5 when EHCI owns the port - Fix
- RwPci ((UINT32) Value + FCH_EHCI_REG54, AccessWidth32, ~BIT4, BIT4, FchDataPtr->StdHeader);
- // EHCI lMU Hangs when Run/Stop is Set First and PDC is Enabled Near End uFrame 7 - Fix Enable
- RwPci ((UINT32) Value + FCH_EHCI_REG54, AccessWidth32, ~BIT11, BIT11, FchDataPtr->StdHeader);
- // RPR 7.25 SB02674
- RwPci ((UINT32) Value + FCH_EHCI_REG54, AccessWidth16, (UINT16)0x5FFF, BIT13 + BIT15, FchDataPtr->StdHeader);
- // RPR 7.26 SB02684
- RwPci ((UINT32) Value + FCH_EHCI_REG50 + 2, AccessWidth16, ~BIT3, BIT3, FchDataPtr->StdHeader);
- // RPR 7.26 SB02687
- RwPci ((UINT32) Value + FCH_EHCI_REG54 + 2, AccessWidth16, (UINT16)0xFFFC, BIT0 + BIT1, FchDataPtr->StdHeader);
- // RPR 7.28 SB02700
- RwPci ((UINT32) Value + FCH_EHCI_REG54 + 2, AccessWidth16, (UINT16)0xFFFB, BIT2, FchDataPtr->StdHeader);
- // RPR 7.29 SB02703
- RwPci ((UINT32) Value + FCH_EHCI_REG54 + 2, AccessWidth16, (UINT16)0xFFF7, BIT3, FchDataPtr->StdHeader);
- } else {
- //
- // Fake Bar
- //
- BarAddress = FCH_FAKE_USB_BAR_ADDRESS;
- WritePci ((UINT32) Value + FCH_EHCI_REG10, AccessWidth32, &BarAddress, FchDataPtr->StdHeader);
- //
- //Enable Memory access
- //
- RwPci ((UINT32) Value + FCH_EHCI_REG04, AccessWidth8, 0, BIT1, FchDataPtr->StdHeader);
- //
- // Enable Global Clock Gating (BIT14)
- //
- RwMem (BarAddress + FCH_EHCI_BAR_REGBC, AccessWidth32, ~( BIT12 + BIT14), BIT12 + BIT14);
- RwMem (BarAddress + FCH_EHCI_BAR_REGB0, AccessWidth32, ~BIT5, BIT5);
- RwPci ((UINT32) Value + FCH_EHCI_REG04, AccessWidth8, 0, 0, FchDataPtr->StdHeader);
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciEnvService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciEnvService.c
deleted file mode 100644
index 73547cb810..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciEnvService.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config FCH USB OHCI controller
- *
- * Init USB OHCI features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*;********************************************************************************
-;
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*********************************************************************************/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2OHCIENVSERVICE_FILECODE
-//
-// Declaration of local functions
-//
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciLateService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciLateService.c
deleted file mode 100644
index f316234e91..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciLateService.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config FCH USB OHCI controller
- *
- * Init USB OHCI features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*;********************************************************************************
-;
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*********************************************************************************/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2OHCILATESERVICE_FILECODE
-//
-// Declaration of local functions
-//
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciMidService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciMidService.c
deleted file mode 100644
index cb4cdd2b65..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciMidService.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config FCH USB OHCI controller
- *
- * Init USB OHCI features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 47163 $ @e \$Date: 2011-02-16 07:23:13 +0800 (Wed, 16 Feb 2011) $
- *
- */
-/*;********************************************************************************
-;
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*********************************************************************************/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2OHCIMIDSERVICE_FILECODE
-//
-// Declaration of local functions
-//
-
-/**
- * FchOhciInitAfterPciInit - Config USB OHCI controller after
- * PCI emulation
- *
- * @param[in] Value Controller PCI config address (bus# + device# + function#)
- * @param[in] FchDataPtr Fch configuration structure pointer.
- */
-VOID
-FchOhciInitAfterPciInit (
- IN UINT32 Value,
- IN FCH_DATA_BLOCK *FchDataPtr
- )
-{
- //
- // Disable the MSI capability of USB host controllers
- //
- RwPci ((UINT32) Value + FCH_OHCI_REG40 + 1, AccessWidth8, 0xFF, BIT0, FchDataPtr->StdHeader);
- RwPci ((UINT32) Value + FCH_OHCI_REG50, AccessWidth8, ~(BIT0 + BIT5 + BIT12), BIT0, FchDataPtr->StdHeader);
- //
- // USB SMI Handshake
- //
- RwPci ((UINT32) Value + FCH_OHCI_REG50 + 1, AccessWidth8, ~BIT4, 0x00, FchDataPtr->StdHeader);
-
- if (Value != (USB4_OHCI_BUS_DEV_FUN << 16)) {
- if ( FchDataPtr->Usb.OhciSsid != NULL ) {
- RwPci ((UINT32) Value + FCH_OHCI_REG2C, AccessWidth32, 0x00, FchDataPtr->Usb.OhciSsid, FchDataPtr->StdHeader);
- }
- }
- //
- // recommended setting to, enable fix to cover the corner case S3 wake up issue from some USB 1.1 devices
- //OHCI 0_PCI_Config 0x50[30] = 1
- //
- RwPci ((UINT32) Value + FCH_OHCI_REG50 + 3, AccessWidth8, ~BIT6, BIT6, FchDataPtr->StdHeader);
- //
- // L1 Early Exit
- // Set OHCI Arbiter Mode.
- // Set Enable Global Clock Gating.
- //
- RwPci ((UINT32) Value + FCH_OHCI_REG80, AccessWidth8, ~(BIT0 + BIT4 + BIT5 + BIT6 + BIT7), BIT0 + BIT4 + BIT7, FchDataPtr->StdHeader);
- //
- // Enable OHCI SOF Synchronization.
- // Enable OHCI Periodic List Advance.
- //
- RwPci ((UINT32) Value + FCH_OHCI_REG50 + 2, AccessWidth8, ~(BIT3 + BIT4), BIT3 + BIT4, FchDataPtr->StdHeader);
- if ( FchDataPtr->Usb.UsbMsiEnable) {
- RwPci ((UINT32) Value + FCH_OHCI_REG40 + 1, AccessWidth8, ~BIT0, 0x00, FchDataPtr->StdHeader);
- RwPci ((UINT32) Value + FCH_OHCI_REG50, AccessWidth8, ~BIT5, BIT5, FchDataPtr->StdHeader);
- }
- // full-speed false crc errors detected. Issue - fix enable
- RwPci ((UINT32) Value + FCH_OHCI_REG80, AccessWidth32, (UINT32) (~(0x01 << 10)), (UINT32) (0x01 << 10), FchDataPtr->StdHeader);
- // SB02643
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGB4, AccessWidth8, ~BIT7, BIT7);
- // RPR 7.27 SB02686
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGED, AccessWidth8, ~BIT2, BIT2);
- // SB02698
- RwPci ((UINT32) Value + FCH_OHCI_REG50, AccessWidth8, ~BIT0, BIT0, FchDataPtr->StdHeader);
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciEnvService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciEnvService.c
deleted file mode 100644
index cdcc556318..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciEnvService.c
+++ /dev/null
@@ -1,325 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config FCH USB3 controller
- *
- * Init USB3 features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 48230 $ @e \$Date: 2011-03-05 06:55:12 +0800 (Sat, 05 Mar 2011) $
- *
- */
-/*;********************************************************************************
-;
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*********************************************************************************/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCIENVSERVICE_FILECODE
-
-//
-// Declaration of local functions
-//
-
-/**
- * FchXhciInitIndirectReg - Config XHCI Indirect Registers
- *
- *
- *
- * @param[in] StdHeader AMD Standard Header
- *
- */
-VOID
-FchXhciInitIndirectReg (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- //
- // SuperSpeed PHY Configuration (adaptation mode setting)
- //
- RwXhciIndReg ( FCH_XHCI_IND_REG94, 0xFFFFFC00, 0x00000021, StdHeader);
- RwXhciIndReg ( FCH_XHCI_IND_REGD4, 0xFFFFFC00, 0x00000021, StdHeader);
- //
- // SuperSpeed PHY Configuration (CR phase and frequency filter settings)
- //
- RwXhciIndReg ( FCH_XHCI_IND_REG98, 0xFFFFFFC0, 0x0000000A, StdHeader);
- RwXhciIndReg ( FCH_XHCI_IND_REGD8, 0xFFFFFFC0, 0x0000000A, StdHeader);
- //
- // BLM Meaasge
- //
- RwXhciIndReg ( FCH_XHCI_IND_REG00, 0xF8FFFFFF, 0x07000000, StdHeader);
- //
- // xHCI USB 2.0 PHY Settings
- // Step 1 is done by hardware default
- // Step 2
- RwXhciIndReg ( FCH_XHCI_IND60_REG00, ~ BIT12, BIT12, StdHeader);
- // Step 3
- RwXhciIndReg ( FCH_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x02 << 8)), StdHeader);
- RwXhciIndReg ( FCH_XHCI_IND60_REG08, ~ ((UINT32) (0xff << 8)), ((UINT32) (0x0f << 8)), StdHeader);
-}
-
-/**
- * XhciA12Fix - Config XHCI A12 Fix
- *
- *
- */
-VOID
-XhciA12Fix (
- )
-{
- //
- // PLUG/UNPLUG of USB 2.0 devices make the XHCI USB 2.0 ports unfunctional - fix enable
- // ACPI_USB3.0_REG 0x20[12:11] = 2'b11
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~((UINT32) (0x3 << 11)), (UINT32) (0x3 << 11));
- //
- // XHC 2 USB2 ports interactional issue - fix enable
- // ACPI_USB3.0_REG 0x20[16] = 1'b1
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~((UINT32) (0x1 << 16)), (UINT32) (0x1 << 16));
- //
- // XHC USB2.0 Ports suspend Enhancement
- // ACPI_USB3.0_REG 0x20[15] = 1'b1
- //
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~((UINT32) (0x1 << 15)), (UINT32) (0x1 << 15));
- //
- // XHC HS/FS IN Data Buffer Underflow issue - fix enable
- // ACPI_USB3.0_REG 0x20[20:18] = 0x7
- //
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~((UINT32) (0x7 << 18)), (UINT32) (0x7 << 18));
- //
- // XHC stuck in U3 after system resuming from S3 -fix enable
- // ACPI_USB3.0_REG 0x98[19] = 1'b1
- //
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG98, AccessWidth32, ~((UINT32) (0x1 << 19)), (UINT32) (0x1 << 19));
- //
- // Change XHC1 ( Dev 16 function 1) Interrupt Pin register to INTB# - Fix enable
- // ACPI_PMIO_F0[18] =1
- //
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth32, ~((UINT32) (0x1 << 18)), (UINT32) (0x1 << 18));
- //
- // EHCI3/OHCI3 blocks Blink Global Clock Gating when EHCI/OHCI Dev 22 fn 0/2 are disabled
- // ACPI_PMIO_F0[13] =1
- //
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth32, ~((UINT32) (0x1 << 13)), (UINT32) (0x1 << 13));
- //
- // Access register through JTAG fail when switch from XHCI to EHCI/OHCI - Fix enable
- // ACPI_PMIO_F0[17] =1
- //
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth32, ~((UINT32) (0x1 << 17)), (UINT32) (0x1 << 17));
- //
- // USB leakage current on differential lines when ports are switched to XHCI - Fix enable
- // ACPI_PMIO_F0[14] =1
- //
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth32, ~((UINT32) (0x1 << 14)), (UINT32) (0x1 << 14));
- //
- // Fix for Incorrect Gated Signals in xhc_to_s5
- // ACPI_PMIO_F0[16] =1
- //
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth32, ~((UINT32) (0x1 << 16)), (UINT32) (0x1 << 16));
-}
-
-/**
- * IsLpcRom - Is LPC Rom?
- *
- *
- * @retval TRUE or FALSE
- *
- */
-BOOLEAN
-IsLpcRom (
- OUT VOID
- )
-{
- return ( (BOOLEAN) ((ACPIMMIO32 (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80) & BIT1) == 0) );
-}
-
-/**
- * FchXhciInitBeforePciInit - Config XHCI controller before PCI
- * emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchXhciInitBeforePciInit (
- IN FCH_DATA_BLOCK *FchDataPtr
- )
-{
- UINT16 BcdAddress;
- UINT16 BcdSize;
- UINT16 AcdAddress;
- UINT16 AcdSize;
- UINT16 FwAddress;
- UINT16 FwSize;
- UINTN XhciFwStarting;
- UINT32 SpiValidBase;
- UINT32 RegData;
- UINT16 Index;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
-
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0x00000000, 0x00400700);
- FchStall (20, StdHeader);
-
- //
- // Get ROM SIG starting address for USB firmware starting address (offset 0x0C to SIG address)
- //
- GetRomSigPtr (&XhciFwStarting, StdHeader);
-
- if (XhciFwStarting == 0) {
- return;
- }
- XhciFwStarting = ACPIMMIO32 (XhciFwStarting + FW_TO_SIGADDR_OFFSET);
- if (IsLpcRom ()) {
- //
- //XHCI firmware re-load
- //
- RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGCC, AccessWidth32, ~BIT2, (BIT2 + BIT1 + BIT0), StdHeader);
- RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGCC, AccessWidth32, 0x00000FFF, (UINT32) (XhciFwStarting), StdHeader);
- }
- //
- // Enable SuperSpeed receive special error case logic. 0x20 bit8
- // Enable USB2.0 RX_Valid Synchronization. 0x20 bit9
- // Enable USB2.0 DIN/SE0 Synchronization. 0x20 bit10
- //
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, 0xFFFFF8FF, 0x00000700);
- //
- // SuperSpeed PHY Configuration (adaptation timer setting)
- //
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90, AccessWidth32, 0xFFF00000, 0x000AAAAA);
- //RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90 + 0x40, AccessWidth32, 0xFFF00000, 0x000AAAAA);
-
- //
- // Step 1. to enable Xhci IO and Firmware load mode
- //
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0xF0FFFFFC, 0x00000003);
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0xEFFFFFFF, 0x10000000);
-
- //
- // Step 2. to read a portion of the USB3_APPLICATION_CODE from BIOS ROM area and program certain registers.
- //
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA0, AccessWidth32, 0x00000000, (SPI_HEAD_LENGTH << 16));
-
- BcdAddress = ACPIMMIO16 (XhciFwStarting + BCD_ADDR_OFFSET);
- BcdSize = ACPIMMIO16 (XhciFwStarting + BCD_SIZE_OFFSET);
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4, AccessWidth16, 0x0000, BcdAddress);
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4 + 2, AccessWidth16, 0x0000, BcdSize);
-
- AcdAddress = ACPIMMIO16 (XhciFwStarting + ACD_ADDR_OFFSET);
- AcdSize = ACPIMMIO16 (XhciFwStarting + ACD_SIZE_OFFSET);
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8, AccessWidth16, 0x0000, AcdAddress);
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8 + 2, AccessWidth16, 0x0000, AcdSize);
-
- SpiValidBase = SPI_BASE2 (XhciFwStarting + 4) | SPI_BAR0_VLD | SPI_BASE0 | SPI_BAR1_VLD | SPI_BASE1 | SPI_BAR2_VLD;
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB0, AccessWidth32, 0x00000000, SpiValidBase);
- //
- // Copy Type0/1/2 data block from ROM image to MMIO starting from 0xC0
- //
- for (Index = 0; Index < SPI_HEAD_LENGTH; Index++) {
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + Index, AccessWidth8, 0, ACPIMMIO8 (XhciFwStarting + Index));
- }
-
- for (Index = 0; Index < BcdSize; Index++) {
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + Index, AccessWidth8, 0, ACPIMMIO8 (XhciFwStarting + BcdAddress + Index));
- }
-
- for (Index = 0; Index < AcdSize; Index++) {
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + BcdSize + Index, AccessWidth8, 0, ACPIMMIO8 (XhciFwStarting + AcdAddress + Index));
- }
-
- //
- // Step 3. to enable the instruction RAM preload functionality.
- //
- FwAddress = ACPIMMIO16 (XhciFwStarting + FW_ADDR_OFFSET);
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth16, 0x0000, ACPIMMIO16 (XhciFwStarting + FwAddress));
- FwAddress += 2;
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04, AccessWidth16, 0x0000, FwAddress);
-
- FwSize = ACPIMMIO16 (XhciFwStarting + FW_SIZE_OFFSET);
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04 + 2, AccessWidth16, 0x0000, FwSize);
- //
- // Set the starting address offset for Instruction RAM preload.
- //
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG08, AccessWidth16, 0x0000, 0);
-
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~BIT29, BIT29);
-
- for (;;) {
- ReadMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccessWidth32, &RegData);
- if (RegData & BIT30) break;
- }
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~BIT29, 0);
-
- //
- // Step 4. to release resets in XHCI_ACPI_MMIO_AMD_REG00. wait for USPLL to lock by polling USPLL lock.
- //
-
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~U3PLL_RESET, 0); ///Release U3PLLreset
- for (;;) {
- ReadMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccessWidth32, &RegData);
- if (RegData & U3PLL_LOCK) break;
- }
-
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~U3PHY_RESET, 0); ///Release U3PHY
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~U3CORE_RESET, 0); ///Release core reset
-
- //
- // SuperSpeed PHY Configuration
- //
- //RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90, AccessWidth32, 0xFFF00000, 0x000AAAAA);
- //RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGD0, AccessWidth32, 0xFFF00000, 0x000AAAAA);
-
- FchXhciInitIndirectReg (StdHeader);
-
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF, AccessWidth8, ~(BIT4 + BIT5), 0); /// Disable Device 22
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF, AccessWidth8, ~(BIT7), BIT7); /// Enable 2.0 devices
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~(BIT21), BIT21);
- //
- // Step 5.
- //
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~(BIT17 + BIT18 + BIT19), BIT17 + BIT18);
-
- XhciA12Fix ();
-
- //
- // UMI Lane Configuration Information for XHCI Firmware to Calculate the Bandwidth for USB 3.0 ISOC Devices
- //
- if (!(IsUmiOneLaneGen1Mode (StdHeader))) {
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~(BIT25 + BIT24), BIT24);
- }
- // RPR 8.23 FS/LS devices not functional after resume from S4 fix enable (SB02699)
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~(BIT22), BIT22);
- // RPR 8.24 XHC USB2.0 Hub disable issue fix enable (SB02702)
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth32, ~(BIT20), BIT20);
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciLateService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciLateService.c
deleted file mode 100644
index 56561e8b6d..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciLateService.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config FCH USB3 controller
- *
- * Init USB3 features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*;********************************************************************************
-;
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*********************************************************************************/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCILATESERVICE_FILECODE
-
-//
-// Declaration of local functions
-//
-
-/**
- * FchInitLateUsbXhciProgram - Config USB3 controller before OS
- * Boot
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitLateUsbXhciProgram (
- IN VOID *FchDataPtr
- )
-{
- UINT8 IndexValue;
- UINT8 Value;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- if ( LocalCfgPtr->Usb.Xhci1Enable == TRUE ) {
- ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x10, AccessWidth8, &Value, StdHeader);
- IndexValue = XHCI_REGISTER_BAR00;
- WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
-
- ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x11, AccessWidth8, &Value, StdHeader);
- IndexValue = XHCI_REGISTER_BAR01;
- WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
-
- ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x12, AccessWidth8, &Value, StdHeader);
- IndexValue = XHCI_REGISTER_BAR02;
- WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
-
- ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x13, AccessWidth8, &Value, StdHeader);
- IndexValue = XHCI_REGISTER_BAR03;
- WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
-
- ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x04, AccessWidth8, &Value, StdHeader);
- IndexValue = XHCI_REGISTER_04H;
- WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
-
- ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x0C, AccessWidth8, &Value, StdHeader);
- IndexValue = XHCI_REGISTER_0CH;
- WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
-
- ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x3C, AccessWidth8, &Value, StdHeader);
- IndexValue = XHCI_REGISTER_3CH;
- WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
-
- ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x10, AccessWidth8, &Value, StdHeader);
- IndexValue = XHCI1_REGISTER_BAR00;
- WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
-
- ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x11, AccessWidth8, &Value, StdHeader);
- IndexValue = XHCI1_REGISTER_BAR01;
- WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
-
- ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x12, AccessWidth8, &Value, StdHeader);
- IndexValue = XHCI1_REGISTER_BAR02;
- WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
-
- ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x13, AccessWidth8, &Value, StdHeader);
- IndexValue = XHCI1_REGISTER_BAR03;
- WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
-
- ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x04, AccessWidth8, &Value, StdHeader);
- IndexValue = XHCI1_REGISTER_04H;
- WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
-
- ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x0C, AccessWidth8, &Value, StdHeader);
- IndexValue = XHCI1_REGISTER_0CH;
- WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
-
- ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x3C, AccessWidth8, &Value, StdHeader);
- IndexValue = XHCI1_REGISTER_3CH;
- WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
- }
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciMidService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciMidService.c
deleted file mode 100644
index d601ceecfd..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciMidService.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config FCH USB3 controller
- *
- * Init USB3 features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*;********************************************************************************
-;
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*********************************************************************************/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCIMIDSERVICE_FILECODE
-
-//
-// Declaration of local functions
-//
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciResetService.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciResetService.c
deleted file mode 100644
index 6173ffa144..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciResetService.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config FCH Xhci controller
- *
- * Init Xhci Controller features (PEI phase).
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCIRESETSERVICE_FILECODE
-
-/**
- * FchInitResetXhciProgram - Config Xhci controller during
- * Power-On
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitResetXhciProgram (
- IN VOID *FchDataPtr
- )
-{
- UINT8 IndexValue;
- UINT32 ValueDword;
- UINT8 ValueByte;
- FCH_RESET_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccessWidth32, &ValueDword, StdHeader);
- ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccessWidth32, &ValueDword, StdHeader);
- if ( ValueDword == (FCH_USB_XHCI_DID << 16) + FCH_USB_XHCI_VID) {
- //
- // First Xhci controller.
- //
- ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccessWidth32, &ValueDword, StdHeader);
- ValueDword = 0;
-
- IndexValue = XHCI_REGISTER_BAR00;
- ReadBiosram (IndexValue, AccessWidth32, &ValueDword, StdHeader);
- WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x10, AccessWidth32, &ValueDword, StdHeader);
-
- IndexValue = XHCI_REGISTER_04H;
- ReadBiosram (IndexValue, AccessWidth8, &ValueByte, StdHeader);
- WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x04, AccessWidth8, &ValueByte, StdHeader);
-
- IndexValue = XHCI_REGISTER_0CH;
- ReadBiosram (IndexValue, AccessWidth8, &ValueByte, StdHeader);
- WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x0C, AccessWidth8, &ValueByte, StdHeader);
-
- IndexValue = XHCI_REGISTER_3CH;
- ReadBiosram (IndexValue, AccessWidth8, &ValueByte, StdHeader);
- WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x3C, AccessWidth8, &ValueByte, StdHeader);
- //
- // Second Xhci controller.
- //
- ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x00, AccessWidth32, &ValueDword, StdHeader);
- ValueDword = 0;
-
- IndexValue = XHCI1_REGISTER_BAR00;
- ReadBiosram (IndexValue, AccessWidth32, &ValueDword, StdHeader);
- WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x10, AccessWidth32, &ValueDword, StdHeader);
-
- IndexValue = XHCI1_REGISTER_04H;
- ReadBiosram (IndexValue, AccessWidth8, &ValueByte, StdHeader);
- WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x04, AccessWidth8, &ValueByte, StdHeader);
-
- IndexValue = XHCI1_REGISTER_0CH;
- ReadBiosram (IndexValue, AccessWidth8, &ValueByte, StdHeader);
- WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x0C, AccessWidth8, &ValueByte, StdHeader);
-
- IndexValue = XHCI1_REGISTER_3CH;
- ReadBiosram (IndexValue, AccessWidth8, &ValueByte, StdHeader);
- WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x3C, AccessWidth8, &ValueByte, StdHeader);
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/OhciEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/OhciEnv.c
deleted file mode 100644
index 2b9c55bac5..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/OhciEnv.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch USB OHCI controller
- *
- * Init USB OHCI features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*;********************************************************************************
-;
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*********************************************************************************/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_USB_OHCIENV_FILECODE
-
-/**
- * FchInitEnvUsbOhci - Config USB OHCI controller before PCI
- * emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitEnvUsbOhci (
- IN VOID *FchDataPtr
- )
-{
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/OhciLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/OhciLate.c
deleted file mode 100644
index e40f77c64a..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/OhciLate.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch USB OHCI controller
- *
- * Init USB OHCI features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*;********************************************************************************
-;
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*********************************************************************************/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_USB_OHCILATE_FILECODE
-
-/**
- * FchInitLateUsbOhci - Config USB OHCI controller before OS
- * Boot
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitLateUsbOhci (
- IN VOID *FchDataPtr
- )
-{
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/OhciMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/OhciMid.c
deleted file mode 100644
index e9fc31ca53..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/OhciMid.c
+++ /dev/null
@@ -1,214 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch USB OHCI controller
- *
- * Init USB OHCI features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*;********************************************************************************
-;
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*********************************************************************************/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_USB_OHCIMID_FILECODE
-//
-// Declaration of local functions
-//
-
-extern VOID FchOhciInitAfterPciInit (IN UINT32 Value, IN FCH_DATA_BLOCK* FchDataPtr);
-/**
- * OhciInitAfterPciInit - Config USB OHCI controller after PCI emulation
- *
- * @param[in] Value Controller PCI config address (bus# + device# + function#)
- * @param[in] FchDataPtr Fch configuration structure pointer.
- */
-VOID OhciInitAfterPciInit (IN UINT32 Value, IN FCH_DATA_BLOCK* FchDataPtr);
-
-/**
- * FchInitMidUsbOhci - Config USB OHCI controller after PCI
- * emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitMidUsbOhci (
- IN VOID *FchDataPtr
- )
-{
- FCH_INTERFACE *LocalCfgPtr;
-
- LocalCfgPtr = (FCH_INTERFACE *)FchDataPtr;
-
- FchInitMidUsbOhci1 (LocalCfgPtr);
- FchInitMidUsbOhci2 (LocalCfgPtr);
- FchInitMidUsbOhci3 (LocalCfgPtr);
- FchInitMidUsbOhci4 (LocalCfgPtr);
-}
-
-/**
- * FchInitMidUsbOhci1 - Config USB1 OHCI controller after PCI
- * emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitMidUsbOhci1 (
- IN VOID *FchDataPtr
- )
-{
- UINT32 DeviceId;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- DeviceId = (USB1_OHCI_BUS_DEV_FUN << 16);
- OhciInitAfterPciInit (DeviceId, LocalCfgPtr);
-
- if (LocalCfgPtr->Usb.OhciSsid != NULL ) {
- RwPci ((USB1_OHCI_BUS_DEV_FUN << 16) + FCH_OHCI_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Usb.OhciSsid, StdHeader);
- }
-}
-
-/**
- * FchInitMidUsbOhci2 - Config USB2 OHCI controller after PCI
- * emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitMidUsbOhci2 (
- IN VOID *FchDataPtr
- )
-{
- UINT32 DeviceId;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- DeviceId = (USB2_OHCI_BUS_DEV_FUN << 16);
- OhciInitAfterPciInit (DeviceId, LocalCfgPtr);
-
- if (LocalCfgPtr->Usb.OhciSsid != NULL ) {
- RwPci ((USB2_OHCI_BUS_DEV_FUN << 16) + FCH_OHCI_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Usb.OhciSsid, StdHeader);
- }
-}
-
-/**
- * FchInitMidUsbOhci3 - Config USB3 OHCI controller after PCI
- * emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitMidUsbOhci3 (
- IN VOID *FchDataPtr
- )
-{
- UINT32 DeviceId;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- DeviceId = (USB3_OHCI_BUS_DEV_FUN << 16);
- OhciInitAfterPciInit (DeviceId, LocalCfgPtr);
-
- if (LocalCfgPtr->Usb.OhciSsid != NULL ) {
- RwPci ((USB3_OHCI_BUS_DEV_FUN << 16) + FCH_OHCI_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Usb.OhciSsid, StdHeader);
- }
-}
-
-/**
- * FchInitMidUsbOhci4 - Config USB4 OHCI controller after PCI
- * emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitMidUsbOhci4 (
- IN VOID *FchDataPtr
- )
-{
- UINT32 DeviceId;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- DeviceId = (USB4_OHCI_BUS_DEV_FUN << 16);
- OhciInitAfterPciInit (DeviceId, LocalCfgPtr);
-
- if (LocalCfgPtr->Usb.Ohci4Ssid != NULL ) {
- RwPci ((USB4_OHCI_BUS_DEV_FUN << 16) + FCH_OHCI_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Usb.Ohci4Ssid, StdHeader);
- }
-}
-
-/**
- * OhciInitAfterPciInit - Config OHCI controller after PCI
- * emulation
- *
- *
- * @param[in] Value OHCI Controler info.
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-OhciInitAfterPciInit (
- IN UINT32 Value,
- IN FCH_DATA_BLOCK *FchDataPtr
- )
-{
- FchOhciInitAfterPciInit ( Value, FchDataPtr);
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/OhciReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/OhciReset.c
deleted file mode 100644
index 7d4ec9f24d..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/OhciReset.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch Ohci controller
- *
- * Init Ohci Controller features (PEI phase).
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_USB_OHCIRESET_FILECODE
-
-/**
- * FchInitResetOhci - Config Ohci controller during Power-On
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitResetOhci (
- IN VOID *FchDataPtr
- )
-{
-}
-
-/**
- * FchInitRecoveryLpc - Config Ohci controller during Crisis
- * Recovery
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitRecoveryOhci (
- IN VOID *FchDataPtr
- )
-{
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/UsbEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/UsbEnv.c
deleted file mode 100644
index 60f50a5e8c..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/UsbEnv.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch USB controller
- *
- * Init USB features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*;********************************************************************************
-;
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*********************************************************************************/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_USB_USBENV_FILECODE
-/**
- * FchInitEnvUsb - Config USB controller before PCI emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitEnvUsb (
- IN VOID *FchDataPtr
- )
-{
- //
- // Disabled All USB controller *** Move to each controller ***
- //
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF, AccessWidth8, BIT7, 0);
- //
- // Clear PM_IO 0x65[4] UsbResetByPciRstEnable, Set this bit so that usb gets reset whenever there is PCIRST.
- // Enable UsbResumeEnable (USB PME) * Default value
- // USB SleepCtrl set as BIT9+BIT8 (6 uframes)
- //
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth16, ~BIT2, BIT2 + BIT7 + BIT8 + BIT9);
-
- SetUsbEnableReg (FchDataPtr);
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEE, AccessWidth8, ~(BIT2), 0 );
-}
-
-
-/**
- * SetUsbEnableReg
- * emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-SetUsbEnableReg (
- IN FCH_DATA_BLOCK *FchDataPtr
- )
-{
- UINT8 UsbModeReg;
-
- UsbModeReg = 0;
-
- // Overwrite EHCI3/OHCI3 by Xhci1Enable
- if (FchDataPtr->Usb.Xhci1Enable) {
- FchDataPtr->Usb.Ohci3Enable = FALSE;
- FchDataPtr->Usb.Ehci3Enable = FALSE;
- }
-
- if ( FchDataPtr->Usb.Ohci1Enable ) UsbModeReg |= 0x01;
- if ( FchDataPtr->Usb.Ehci1Enable ) UsbModeReg |= 0x02;
- if ( FchDataPtr->Usb.Ohci2Enable ) UsbModeReg |= 0x04;
- if ( FchDataPtr->Usb.Ehci2Enable ) UsbModeReg |= 0x08;
- if ( FchDataPtr->Usb.Ohci3Enable ) UsbModeReg |= 0x10;
- if ( FchDataPtr->Usb.Ehci3Enable ) UsbModeReg |= 0x20;
- if ( FchDataPtr->Usb.Ohci4Enable ) UsbModeReg |= 0x40;
-
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF, AccessWidth8, BIT7, UsbModeReg);
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/UsbLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/UsbLate.c
deleted file mode 100644
index 038ed24451..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/UsbLate.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch USB controller
- *
- * Init USB features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*;********************************************************************************
-;
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*********************************************************************************/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_USB_USBLATE_FILECODE
-
-/**
- * FchInitLateUsb - Config USB controller before OS Boot
- * emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitLateUsb (
- IN VOID *FchDataPtr
- )
-{
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/UsbMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/UsbMid.c
deleted file mode 100644
index f6ab38d54a..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/UsbMid.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch USB controller
- *
- * Init USB features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*;********************************************************************************
-;
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*********************************************************************************/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_USB_USBMID_FILECODE
-
-/**
- * FchInitMidUsb - Config USB controller after PCI emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitMidUsb (
- IN VOID *FchDataPtr
- )
-{
- FCH_DATA_BLOCK *LocalCfgPtr;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
- if ( LocalCfgPtr->Usb.UsbPhyPowerDown ) {
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth8, ~BIT0, BIT0);
- } else {
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth8, ~BIT0, 0);
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/UsbReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/UsbReset.c
deleted file mode 100644
index e51332e845..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/UsbReset.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch Usb controller
- *
- * Init Usb Controller features (PEI phase).
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_USB_USBRESET_FILECODE
-
-/**
- * FchInitResetUsb - Config Usb controller during Power-On
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitResetUsb (
- IN VOID *FchDataPtr
- )
-{
-}
-
-/**
- * FchInitRecoveryLpc - Config Usb controller during Crisis
- * Recovery
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitRecoveryUsb (
- IN VOID *FchDataPtr
- )
-{
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/XhciEnv.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/XhciEnv.c
deleted file mode 100644
index a3d82b954d..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/XhciEnv.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch USB3 controller
- *
- * Init USB3 features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 47163 $ @e \$Date: 2011-02-16 07:23:13 +0800 (Wed, 16 Feb 2011) $
- *
- */
-/*;********************************************************************************
-;
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*********************************************************************************/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_USB_XHCIENV_FILECODE
-
-extern VOID FchXhciInitBeforePciInit (IN FCH_DATA_BLOCK* FchDataPtr);
-extern VOID FchXhciInitIndirectReg (IN AMD_CONFIG_PARAMS *StdHeader);
-
-//
-// Declaration of local functions
-//
-VOID XhciInitBeforePciInit (IN FCH_DATA_BLOCK* FchDataPtr);
-VOID XhciInitIndirectReg (IN AMD_CONFIG_PARAMS *StdHeader);
-
-/**
- * FchInitEnvUsbXhci - Config XHCI controller before PCI
- * emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitEnvUsbXhci (
- IN VOID *FchDataPtr
- )
-{
- UINT8 XhciEfuse;
- FCH_DATA_BLOCK *LocalCfgPtr;
- AMD_CONFIG_PARAMS *StdHeader;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr;
- StdHeader = LocalCfgPtr->StdHeader;
-
- if ( LocalCfgPtr->Usb.Xhci1Enable == TRUE ) {
- if ( LocalCfgPtr->Misc.S3Resume == 0 ) {
- XhciInitBeforePciInit (LocalCfgPtr);
- } else {
- XhciInitIndirectReg (StdHeader);
- }
- } else {
- //
- // for power saving.
- //
- // add Efuse checking for Xhci enable/disable
- XhciEfuse = XHCI_EFUSE_LOCATION;
- GetEfuseStatus (&XhciEfuse, StdHeader);
- if ((XhciEfuse & (BIT0 + BIT1)) != (BIT0 + BIT1)) {
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0xF0FFFBFF, 0x0);
- }
- }
-}
-
-/**
- * XhciInitIndirectReg - Config XHCI Indirect Registers
- *
- *
- *
- * @param[in] StdHeader AMD Standard Header
- *
- */
-VOID
-XhciInitIndirectReg (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- FchXhciInitIndirectReg (StdHeader);
-}
-
-/**
- * XhciInitBeforePciInit - Config XHCI controller before PCI
- * emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-XhciInitBeforePciInit (
- IN FCH_DATA_BLOCK *FchDataPtr
- )
-{
- FchXhciInitBeforePciInit ( FchDataPtr );
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/XhciLate.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/XhciLate.c
deleted file mode 100644
index 4c35ff3a2e..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/XhciLate.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch USB3 controller
- *
- * Init USB3 features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*;********************************************************************************
-;
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*********************************************************************************/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_USB_XHCILATE_FILECODE
-
-extern VOID FchInitLateUsbXhciProgram (IN VOID *FchDataPtr);
-
-/**
- * FchInitLateUsbXhci - Config USB3 controller before OS Boot
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitLateUsbXhci (
- IN VOID *FchDataPtr
- )
-{
- FchInitLateUsbXhciProgram ( FchDataPtr );
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/XhciMid.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/XhciMid.c
deleted file mode 100644
index 3f61626a58..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/XhciMid.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch USB3 controller
- *
- * Init USB3 features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*;********************************************************************************
-;
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*********************************************************************************/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_USB_XHCIMID_FILECODE
-
-/**
- * FchInitMidUsbXhci - Config USB3 controller after PCI
- * emulation
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitMidUsbXhci (
- IN VOID *FchDataPtr
- )
-{
- FCH_DATA_BLOCK *LocalCfgPtr;
-
- LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr;
-
- if ( LocalCfgPtr->Usb.Xhci1Enable == TRUE ) {
- //
- // Block Write to DID & SID to pass DTM
- //
- RwXhciIndReg (FCH_XHCI_IND_REG04, ~BIT8, BIT8, ((FCH_DATA_BLOCK *)FchDataPtr)->StdHeader);
- }
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/XhciRecovery.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/XhciRecovery.c
deleted file mode 100644
index 6bb82ccc94..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/XhciRecovery.c
+++ /dev/null
@@ -1,332 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch Xhci controller
- *
- * Init Xhci Controller features (PEI phase).
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 01:16:51 -0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_USB_XHCIRECOVERY_FILECODE
-
-/**
- * XhciIndirectRegInit - Config XHCI Indirect Registers
- *
- *
- *
- * @param[in] StdHeader AMD Standard Header
- *
- */
-VOID
-XhciIndirectRegInit (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- //
- // SuperSpeed PHY Configuration (adaptation mode setting)
- //
- RwXhciIndReg ( FCH_XHCI_IND_REG94, 0xFFFFFC00, 0x00000021, StdHeader);
- RwXhciIndReg ( FCH_XHCI_IND_REGD4, 0xFFFFFC00, 0x00000021, StdHeader);
- //
- // SuperSpeed PHY Configuration (CR phase and frequency filter settings)
- //
- RwXhciIndReg ( FCH_XHCI_IND_REG98, 0xFFFFFFC0, 0x0000000A, StdHeader);
- RwXhciIndReg ( FCH_XHCI_IND_REGD8, 0xFFFFFFC0, 0x0000000A, StdHeader);
- //
- // BLM Meaasge
- //
- RwXhciIndReg ( FCH_XHCI_IND_REG00, 0xF8FFFFFF, 0x07000000, StdHeader);
- //
- // xHCI USB 2.0 PHY Settings
- // Step 1 is done by hardware default
- // Step 2
- RwXhciIndReg ( FCH_XHCI_IND60_REG00, ~ BIT12, BIT12, StdHeader);
- // Step 3
- RwXhciIndReg ( FCH_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x02 << 8)), StdHeader);
- RwXhciIndReg ( FCH_XHCI_IND60_REG08, ~ ((UINT32) (0xff << 8)), ((UINT32) (0x0f << 8)), StdHeader);
-}
-
-/**
- * XhciA12Patch - Config XHCI A12 Fix
- *
- *
- */
-VOID
-XhciA12Patch (
- )
-{
- //
- // PLUG/UNPLUG of USB 2.0 devices make the XHCI USB 2.0 ports unfunctional - fix enable
- // ACPI_USB3.0_REG 0x20[12:11] = 2'b11
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~((UINT32) (0x3 << 11)), (UINT32) (0x3 << 11));
- //
- // XHC 2 USB2 ports interactional issue - fix enable
- // ACPI_USB3.0_REG 0x20[16] = 1'b1
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~((UINT32) (0x1 << 16)), (UINT32) (0x1 << 16));
- //
- // XHC USB2.0 Ports suspend Enhancement
- // ACPI_USB3.0_REG 0x20[15] = 1'b1
- //
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~((UINT32) (0x1 << 15)), (UINT32) (0x1 << 15));
- //
- // XHC HS/FS IN Data Buffer Underflow issue - fix enable
- // ACPI_USB3.0_REG 0x20[19:18] = 2'b11
- //
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~((UINT32) (0x3 << 18)), (UINT32) (0x3 << 18));
- //
- // XHC stuck in U3 after system resuming from S3 -fix enable
- // ACPI_USB3.0_REG 0x98[19] = 1'b1
- //
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG98, AccessWidth32, ~((UINT32) (0x1 << 19)), (UINT32) (0x1 << 19));
- //
- // Change XHC1 ( Dev 16 function 1) Interrupt Pin register to INTB# - Fix enable
- // ACPI_PMIO_F0[18] =1
- //
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth32, ~((UINT32) (0x1 << 18)), (UINT32) (0x1 << 18));
- //
- // EHCI3/OHCI3 blocks Blink Global Clock Gating when EHCI/OHCI Dev 22 fn 0/2 are disabled
- // ACPI_PMIO_F0[13] =1
- //
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth32, ~((UINT32) (0x1 << 13)), (UINT32) (0x1 << 13));
- //
- // Access register through JTAG fail when switch from XHCI to EHCI/OHCI - Fix enable
- // ACPI_PMIO_F0[17] =1
- //
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth32, ~((UINT32) (0x1 << 17)), (UINT32) (0x1 << 17));
- //
- // USB leakage current on differential lines when ports are switched to XHCI - Fix enable
- // ACPI_PMIO_F0[14] =1
- //
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth32, ~((UINT32) (0x1 << 14)), (UINT32) (0x1 << 14));
-}
-
-/**
- * IsItLpcRom - Is LPC Rom?
- *
- *
- * @retval TRUE or FALSE
- *
- */
-BOOLEAN
-IsItLpcRom (
- OUT VOID
- )
-{
- return ( (BOOLEAN) ((ACPIMMIO32 (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80) & BIT1) == 0) );
-}
-
-/**
- * Is UMI in x1-Lane and GEN1 Mode?
- *
- *
- * @retval TRUE or FALSE
- *
- */
-BOOLEAN
-IsUmiX1LaneGen1Mode (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 AbValue;
-
- AbValue = ReadAlink ((UINT32) (FCH_AX_CFG_REG68), StdHeader);
- AbValue >>= 16;
- if (((AbValue & 0x0f) == 1) && ((AbValue & 0x03f0) == 0x0010)) {
- return (TRUE);
- } else {
- return (FALSE);
- }
-}
-
-/**
- * FchXhciEarlyInit - Config XHCI controller in recovery mode
- *
- *
- */
-VOID
-FchXhciEarlyInit (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT16 BcdAddress;
- UINT16 BcdSize;
- UINT16 AcdAddress;
- UINT16 AcdSize;
- UINT16 FwAddress;
- UINT16 FwSize;
- UINTN XhciFwStarting;
- UINT32 SpiValidBase;
- UINT32 RegData;
- UINT16 Index;
-
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0x00000000, 0x00400700);
- FchStall (20, StdHeader);
-
- //
- // Get ROM SIG starting address for USB firmware starting address (offset 0x0C to SIG address)
- //
- GetRomSigPtr (&XhciFwStarting, StdHeader);
-
- if (XhciFwStarting == 0) {
- return;
- }
- XhciFwStarting = ACPIMMIO32 (XhciFwStarting + FW_TO_SIGADDR_OFFSET);
- if (IsItLpcRom ()) {
- //
- //XHCI firmware re-load
- //
- RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGCC, AccessWidth32, ~BIT2, (BIT2 + BIT1 + BIT0), StdHeader);
- RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGCC, AccessWidth32, 0x00000FFF, (UINT32) (XhciFwStarting), StdHeader);
- }
- //
- // Enable SuperSpeed receive special error case logic. 0x20 bit8
- // Enable USB2.0 RX_Valid Synchronization. 0x20 bit9
- // Enable USB2.0 DIN/SE0 Synchronization. 0x20 bit10
- //
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, 0xFFFFF8FF, 0x00000700);
- //
- // SuperSpeed PHY Configuration (adaptation timer setting)
- //
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90, AccessWidth32, 0xFFF00000, 0x000AAAAA);
- //RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90 + 0x40, AccessWidth32, 0xFFF00000, 0x000AAAAA);
-
- //
- // Step 1. to enable Xhci IO and Firmware load mode
- //
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0xF0FFFFFC, 0x00000003);
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0xEFFFFFFF, 0x10000000);
-
- //
- // Step 2. to read a portion of the USB3_APPLICATION_CODE from BIOS ROM area and program certain registers.
- //
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA0, AccessWidth32, 0x00000000, (SPI_HEAD_LENGTH << 16));
-
- BcdAddress = ACPIMMIO16 (XhciFwStarting + BCD_ADDR_OFFSET);
- BcdSize = ACPIMMIO16 (XhciFwStarting + BCD_SIZE_OFFSET);
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4, AccessWidth16, 0x0000, BcdAddress);
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4 + 2, AccessWidth16, 0x0000, BcdSize);
-
- AcdAddress = ACPIMMIO16 (XhciFwStarting + ACD_ADDR_OFFSET);
- AcdSize = ACPIMMIO16 (XhciFwStarting + ACD_SIZE_OFFSET);
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8, AccessWidth16, 0x0000, AcdAddress);
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8 + 2, AccessWidth16, 0x0000, AcdSize);
-
- SpiValidBase = SPI_BASE2 (XhciFwStarting + 4) | SPI_BAR0_VLD | SPI_BASE0 | SPI_BAR1_VLD | SPI_BASE1 | SPI_BAR2_VLD;
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB0, AccessWidth32, 0x00000000, SpiValidBase);
- //
- // Copy Type0/1/2 data block from ROM image to MMIO starting from 0xC0
- //
- for (Index = 0; Index < SPI_HEAD_LENGTH; Index++) {
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + Index, AccessWidth8, 0, ACPIMMIO8 (XhciFwStarting + Index));
- }
-
- for (Index = 0; Index < BcdSize; Index++) {
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + Index, AccessWidth8, 0, ACPIMMIO8 (XhciFwStarting + BcdAddress + Index));
- }
-
- for (Index = 0; Index < AcdSize; Index++) {
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + BcdSize + Index, AccessWidth8, 0, ACPIMMIO8 (XhciFwStarting + AcdAddress + Index));
- }
-
- //
- // Step 3. to enable the instruction RAM preload functionality.
- //
- FwAddress = ACPIMMIO16 (XhciFwStarting + FW_ADDR_OFFSET);
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth16, 0x0000, ACPIMMIO16 (XhciFwStarting + FwAddress));
- FwAddress += 2;
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04, AccessWidth16, 0x0000, FwAddress);
-
- FwSize = ACPIMMIO16 (XhciFwStarting + FW_SIZE_OFFSET);
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04 + 2, AccessWidth16, 0x0000, FwSize);
- //
- // Set the starting address offset for Instruction RAM preload.
- //
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG08, AccessWidth16, 0x0000, 0);
-
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~BIT29, BIT29);
-
- for (;;) {
- ReadMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccessWidth32, &RegData);
- if (RegData & BIT30) break;
- }
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~BIT29, 0);
-
- //
- // Step 4. to release resets in XHCI_ACPI_MMIO_AMD_REG00. wait for USPLL to lock by polling USPLL lock.
- //
-
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~U3PLL_RESET, 0); ///Release U3PLLreset
- for (;;) {
- ReadMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccessWidth32, &RegData);
- if (RegData & U3PLL_LOCK) break;
- }
-
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~U3PHY_RESET, 0); ///Release U3PHY
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~U3CORE_RESET, 0); ///Release core reset
-
- //
- // SuperSpeed PHY Configuration
- //
- //RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90, AccessWidth32, 0xFFF00000, 0x000AAAAA);
- //RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGD0, AccessWidth32, 0xFFF00000, 0x000AAAAA);
-
- XhciIndirectRegInit (StdHeader);
-
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF, AccessWidth8, ~(BIT4 + BIT5), 0); /// Disable Device 22
- RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF, AccessWidth8, ~(BIT7), BIT7); /// Enable 2.0 devices
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~(BIT21), BIT21);
- //
- // Step 5.
- //
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~(BIT17 + BIT18 + BIT19), BIT17 + BIT18);
-
- XhciA12Patch ();
-
- //
- // UMI Lane Configuration Information for XHCI Firmware to Calculate the Bandwidth for USB 3.0 ISOC Devices
- //
- if (!(IsUmiX1LaneGen1Mode (StdHeader))) {
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~(BIT25 + BIT24), BIT24);
- }
- // RPR 8.23 FS/LS devices not functional after resume from S4 fix enable (SB02699)
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~(BIT22), BIT22);
- // RPR 8.24 XHC USB2.0 Hub disable issue fix enable (SB02702)
- RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth32, ~(BIT20), BIT20);
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/XhciReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/XhciReset.c
deleted file mode 100644
index d1606afa55..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Usb/XhciReset.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Config Fch Xhci controller
- *
- * Init Xhci Controller features (PEI phase).
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-****************************************************************************
-*/
-#include "FchPlatform.h"
-#include "Filecode.h"
-#define FILECODE PROC_FCH_USB_XHCIRESET_FILECODE
-
-extern VOID FchInitResetXhciProgram (IN VOID *FchDataPtr);
-
-/**
- * FchInitResetXhci - Config Xhci controller during Power-On
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitResetXhci (
- IN VOID *FchDataPtr
- )
-{
- FchInitResetXhciProgram ( FchDataPtr );
-}
-
-/**
- * FchInitRecoveryLpc - Config Xhci controller during Crisis
- * Recovery
- *
- *
- *
- * @param[in] FchDataPtr Fch configuration structure pointer.
- *
- */
-VOID
-FchInitRecoveryXhci (
- IN VOID *FchDataPtr
- )
-{
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c
deleted file mode 100644
index 5f267c6f6f..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c
+++ /dev/null
@@ -1,486 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Family specific function translation
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39255 $ @e \$Date: 2010-10-08 11:27:41 -0700 (Fri, 08 Oct 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "amdlib.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include "GnbPcieFamServices.h"
-#include "GnbCommonLib.h"
-#include "GnbPcieConfig.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBPCIETRANSLATION_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------------------*/
-/**
- * Configure engine list to support lane allocation according to configuration ID.
- *
- *
- *
- * @param[in] Wrapper Pointer to wrapper config descriptor
- * @param[in] EngineType Engine Type
- * @param[in] ConfigurationId Configuration ID
- * @retval AGESA_SUCCESS Configuration successfully applied
- * @retval AGESA_UNSUPPORTED No more configuration available for given engine type
- * @retval AGESA_ERROR Requested configuration not supported
- */
-AGESA_STATUS
-PcieFmConfigureEnginesLaneAllocation (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIE_ENGINE_TYPE EngineType,
- IN UINT8 ConfigurationId
- )
-{
- AGESA_STATUS Status;
- PCIe_COMPLEX_CONFIG *Complex;
- PCIe_PLATFORM_CONFIG *Pcie;
- PCIe_FAM_CONFIG_SERVICES *PcieConfigService;
-
- Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header);
- Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Wrapper->Header);
- Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, &PcieConfigService, GnbLibGetHeader (Pcie));
- ASSERT (Status == AGESA_SUCCESS);
- if (Status == AGESA_SUCCESS) {
- return PcieConfigService->PcieFmConfigureEnginesLaneAllocation (Wrapper, EngineType, ConfigurationId);
- }
- return AGESA_ERROR;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get core configuration value
- *
- *
- *
- * @param[in] Wrapper Pointer to internal configuration data area
- * @param[in] CoreId Core ID
- * @param[in] ConfigurationSignature Configuration signature
- * @param[out] ConfigurationValue Configuration value (for core configuration)
- * @retval AGESA_SUCCESS Configuration successfully applied
- * @retval AGESA_ERROR Core configuration value can not be determined
- */
-AGESA_STATUS
-PcieFmGetCoreConfigurationValue (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN UINT8 CoreId,
- IN UINT64 ConfigurationSignature,
- IN UINT8 *ConfigurationValue
- )
-{
- AGESA_STATUS Status;
- PCIe_COMPLEX_CONFIG *Complex;
- PCIe_PLATFORM_CONFIG *Pcie;
- PCIe_FAM_INIT_SERVICES *PcieInitService;
-
- Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header);
- Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Wrapper->Header);
- Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, &PcieInitService, GnbLibGetHeader (Pcie));
- ASSERT (Status == AGESA_SUCCESS);
- if (Status == AGESA_SUCCESS) {
- return PcieInitService->PcieFmGetCoreConfigurationValue (Wrapper, CoreId, ConfigurationSignature, ConfigurationValue);
- }
- return AGESA_ERROR;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Check if engine can be remapped to Device/function number requested by user
- * defined engine descriptor
- *
- * Function only called if requested device/function does not much native device/function
- *
- * @param[in] PortDescriptor Pointer to user defined engine descriptor
- * @param[in] Engine Pointer engine configuration
- * @retval TRUE Descriptor can be mapped to engine
- * @retval FALSE Descriptor can NOT be mapped to engine
- */
-
-BOOLEAN
-PcieFmCheckPortPciDeviceMapping (
- IN PCIe_PORT_DESCRIPTOR *PortDescriptor,
- IN PCIe_ENGINE_CONFIG *Engine
- )
-{
- AGESA_STATUS Status;
- PCIe_COMPLEX_CONFIG *Complex;
- PCIe_PLATFORM_CONFIG *Pcie;
- PCIe_FAM_CONFIG_SERVICES *PcieConfigService;
-
- Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header);
- Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header);
- Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, &PcieConfigService, GnbLibGetHeader (Pcie));
- ASSERT (Status == AGESA_SUCCESS);
- if (Status == AGESA_SUCCESS) {
- return PcieConfigService->PcieFmCheckPortPciDeviceMapping (PortDescriptor, Engine);
- }
- return FALSE;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get core configuration string
- *
- * Debug function for logging configuration
- *
- * @param[in] Wrapper Pointer to internal configuration data area
- * @param[in] ConfigurationValue Configuration value
- * @retval Configuration string
- */
-
-CONST CHAR8*
-PcieFmDebugGetCoreConfigurationString (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN UINT8 ConfigurationValue
- )
-{
- AGESA_STATUS Status;
- PCIe_COMPLEX_CONFIG *Complex;
- PCIe_PLATFORM_CONFIG *Pcie;
- PCIe_FAM_DEBUG_SERVICES *PcieDebugService;
-
- Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header);
- Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header);
- Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId, &PcieDebugService, GnbLibGetHeader (Pcie));
- ASSERT (Status == AGESA_SUCCESS);
- if (Status == AGESA_SUCCESS) {
- return PcieDebugService->PcieFmDebugGetCoreConfigurationString (Wrapper, ConfigurationValue);
- }
- return " !!! Something Wrong !!!";
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get wrapper name
- *
- * Debug function for logging wrapper name
- *
- * @param[in] Wrapper Pointer to internal configuration data area
- * @retval Wrapper Name string
- */
-
-CONST CHAR8*
-PcieFmDebugGetWrapperNameString (
- IN PCIe_WRAPPER_CONFIG *Wrapper
- )
-{
- AGESA_STATUS Status;
- PCIe_COMPLEX_CONFIG *Complex;
- PCIe_PLATFORM_CONFIG *Pcie;
- PCIe_FAM_DEBUG_SERVICES *PcieDebugService;
-
- Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header);
- Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header);
- Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId, &PcieDebugService, GnbLibGetHeader (Pcie));
- ASSERT (Status == AGESA_SUCCESS);
- if (Status == AGESA_SUCCESS) {
- return PcieDebugService->PcieFmDebugGetWrapperNameString (Wrapper);
- }
- return " !!! Something Wrong !!!";
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get register address name
- *
- * Debug function for logging register trace
- *
- * @param[in] Silicon Silicon config descriptor
- * @param[in] AddressFrame Address Frame
- * @retval Register address name
- */
-CONST CHAR8*
-PcieFmDebugGetHostRegAddressSpaceString (
- IN PCIe_SILICON_CONFIG *Silicon,
- IN UINT16 AddressFrame
- )
-{
- AGESA_STATUS Status;
- PCIe_COMPLEX_CONFIG *Complex;
- PCIe_PLATFORM_CONFIG *Pcie;
- PCIe_FAM_DEBUG_SERVICES *PcieDebugService;
-
- Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Silicon->Header);
- Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header);
- Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId, &PcieDebugService, GnbLibGetHeader (Pcie));
- ASSERT (Status == AGESA_SUCCESS);
- if (Status == AGESA_SUCCESS) {
- return PcieDebugService->PcieFmDebugGetHostRegAddressSpaceString (Silicon, AddressFrame);
- }
- return " !!! Something Wrong !!!";
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Check if the lane can be muxed by link width requested by user
- * defined engine descriptor
- *
- * Check Engine StartCoreLane could be aligned by user requested link width(x1, x2, x4, x8, x16).
- * Check Engine StartCoreLane could be aligned by user requested link width x2.
- *
- * @param[in] PortDescriptor Pointer to user defined engine descriptor
- * @param[in] Engine Pointer engine configuration
- * @retval TRUE Lane can be muxed
- * @retval FALSE Lane can NOT be muxed
- */
-
-BOOLEAN
-PcieFmCheckPortPcieLaneCanBeMuxed (
- IN PCIe_PORT_DESCRIPTOR *PortDescriptor,
- IN PCIe_ENGINE_CONFIG *Engine
- )
-{
- AGESA_STATUS Status;
- PCIe_COMPLEX_CONFIG *Complex;
- PCIe_PLATFORM_CONFIG *Pcie;
- PCIe_FAM_CONFIG_SERVICES *PcieConfigService;
-
- Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header);
- Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header);
- Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, &PcieConfigService, GnbLibGetHeader (Pcie));
- ASSERT (Status == AGESA_SUCCESS);
- if (Status == AGESA_SUCCESS) {
- return PcieConfigService->PcieFmCheckPortPcieLaneCanBeMuxed (PortDescriptor, Engine);
- }
- return FALSE;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Map engine to specific PCI device address
- *
- *
- *
- * @param[in] Engine Pointer to engine configuration
- * @retval AGESA_ERROR Fail to map PCI device address
- * @retval AGESA_SUCCESS Successfully allocate PCI address
- */
-
-AGESA_STATUS
-PcieFmMapPortPciAddress (
- IN PCIe_ENGINE_CONFIG *Engine
- )
-{
- AGESA_STATUS Status;
- PCIe_COMPLEX_CONFIG *Complex;
- PCIe_PLATFORM_CONFIG *Pcie;
- PCIe_FAM_CONFIG_SERVICES *PcieConfigService;
-
- Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header);
- Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header);
- Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, &PcieConfigService, GnbLibGetHeader (Pcie));
- ASSERT (Status == AGESA_SUCCESS);
- if (Status == AGESA_SUCCESS) {
- return PcieConfigService->PcieFmMapPortPciAddress (Engine);
- }
- return AGESA_ERROR;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get total number of silicons/wrappers/engines for this complex
- *
- *
- *
- * @param[in] SocketId Socket ID.
- * @param[out] Length Length of configuration info block
- * @param[out] StdHeader Standard Configuration Header
- * @retval AGESA_SUCCESS Configuration data length is correct
- */
-AGESA_STATUS
-PcieFmGetComplexDataLength (
- IN UINT8 SocketId,
- OUT UINTN *Length,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS Status;
- PCIe_FAM_CONFIG_SERVICES *PcieConfigService;
- Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId, &PcieConfigService, StdHeader);
- ASSERT (Status == AGESA_SUCCESS);
- if (Status == AGESA_SUCCESS) {
- return PcieConfigService->PcieFmGetComplexDataLength (SocketId, Length, StdHeader);
- }
- return Status;
-}
-
-
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Build configuration
- *
- *
- * @param[in] SocketId Socket ID.
- * @param[out] Buffer Pointer to buffer to build internal complex data structure
- * @param[out] StdHeader Standard configuration header.
- * @retval AGESA_SUCCESS Configuration data build successfully
- */
-AGESA_STATUS
-PcieFmBuildComplexConfiguration (
- IN UINT8 SocketId,
- OUT VOID *Buffer,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS Status;
- PCIe_FAM_CONFIG_SERVICES *PcieConfigService;
- Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId, &PcieConfigService, StdHeader);
- ASSERT (Status == AGESA_SUCCESS);
- if (Status == AGESA_SUCCESS) {
- return PcieConfigService->PcieFmBuildComplexConfiguration (SocketId, Buffer, StdHeader);
- }
- return Status;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get max link speed capability supported by this port
- *
- *
- *
- * @param[in] Flags See Flags PCIE_PORT_GEN_CAP_BOOT / PCIE_PORT_GEN_CAP_MAX
- * @param[in] Engine Pointer to engine config descriptor
- * @retval PcieGen1/PcieGen2 Max supported link gen capability
- */
-PCIE_LINK_SPEED_CAP
-PcieFmGetLinkSpeedCap (
- IN UINT32 Flags,
- IN PCIe_ENGINE_CONFIG *Engine
- )
-{
- AGESA_STATUS Status;
- PCIe_COMPLEX_CONFIG *Complex;
- PCIe_PLATFORM_CONFIG *Pcie;
- PCIe_FAM_INIT_SERVICES *PcieInitService;
-
- Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header);
- Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header);
- Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, &PcieInitService, GnbLibGetHeader (Pcie));
- ASSERT (Status == AGESA_SUCCESS);
- if (Status == AGESA_SUCCESS) {
- return PcieInitService->PcieFmGetLinkSpeedCap (Flags, Engine);
- }
- return PcieGen1;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get native PHY lane bitmap
- *
- *
- * @param[in] PhyLaneBitmap Package PHY lane bitmap
- * @param[in] Engine Standard configuration header.
- * @retval Native PHY lane bitmap
- */
-UINT32
-PcieFmGetNativePhyLaneBitmap (
- IN UINT32 PhyLaneBitmap,
- IN PCIe_ENGINE_CONFIG *Engine
- )
-{
- AGESA_STATUS Status;
- PCIe_COMPLEX_CONFIG *Complex;
- PCIe_PLATFORM_CONFIG *Pcie;
- PCIe_FAM_INIT_SERVICES *PcieInitService;
-
- Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header);
- Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header);
- Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, &PcieInitService, GnbLibGetHeader (Pcie));
- ASSERT (Status == AGESA_SUCCESS);
- if (Status == AGESA_SUCCESS) {
- return PcieInitService->PcieFmGetNativePhyLaneBitmap (PhyLaneBitmap, Engine);
- }
- return 0x0;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get SB port info
- *
- *
- * @param[out] SocketId Socket ID
- * @param[out] SbPort Pointer to SB configuration descriptor
- * @param[in] StdHeader Standard configuration header.
- * @retval AGESA_SUCCESS SB configuration determined successfully
- */
-AGESA_STATUS
-PcieFmGetSbConfigInfo (
- IN UINT8 SocketId,
- OUT PCIe_PORT_DESCRIPTOR *SbPort,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS Status;
- PCIe_FAM_CONFIG_SERVICES *PcieConfigService;
- Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId, &PcieConfigService, StdHeader);
- ASSERT (Status == AGESA_SUCCESS);
- if (Status == AGESA_SUCCESS) {
- return PcieConfigService->PcieFmGetSbConfigInfo (SocketId, SbPort, StdHeader);
- }
- return Status;
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c
deleted file mode 100644
index 90e9ca52a1..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c
+++ /dev/null
@@ -1,242 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe ALIB
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39433 $ @e \$Date: 2010-10-11 14:15:36 -0700 (Mon, 11 Oct 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "amdlib.h"
-#include "heapManager.h"
-#include "cpuLateInit.h"
-#include "Gnb.h"
-#include "GnbFamServices.h"
-#include "GnbCommonLib.h"
-#include "OptionGnb.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBIOMMUIVRS_GNBIOMMUIVRS_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-extern GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions;
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-#define IVRS_TABLE_LENGTH 8 * 1024
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-VOID
-GnbIommuIvrsTableDump (
- IN VOID *Ivrs,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-
-IOMMU_IVRS_HEADER IvrsHeader = {
- {'I', 'V', 'R', 'S'},
- sizeof (IOMMU_IVRS_HEADER),
- 2,
- 0,
- {'A', 'M', 'D', ' ', ' ', 0},
- {'A', 'M', 'D', 'I', 'O', 'M', 'M', 'U'},
- 1,
- {'A','M','D',' '},
- 0,
- 0,
- 0
-};
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Build IVRS table
- *
- *
- *
- * @param[in] StdHeader Standard Configuration Header
- * @retval AGESA_SUCCESS
- * @retval AGESA_ERROR
- */
-
-AGESA_STATUS
-GnbIommuIvrsTable (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS Status;
- AMD_LATE_PARAMS *LateParamsPtr;
- VOID *Ivrs;
- BOOLEAN IvrsSupport;
- UINT32 SocketId;
- UINT32 SiliconId;
- UINT32 NumberOfSockets;
- UINT32 NumberOfSilicons;
-
- Status = AGESA_SUCCESS;
- LateParamsPtr = (AMD_LATE_PARAMS*) StdHeader;
- IvrsSupport = FALSE;
- Ivrs = LateParamsPtr->AcpiIvrs;
- if (Ivrs == NULL) {
- Ivrs = GnbAllocateHeapBuffer (
- AMD_ACPI_IVRS_BUFFER_HANDLE,
- IVRS_TABLE_LENGTH,
- StdHeader
- );
- ASSERT (Ivrs != NULL);
- if (Ivrs == NULL) {
- return AGESA_ERROR;
- }
- LateParamsPtr->AcpiIvrs = Ivrs;
- }
- LibAmdMemFill (Ivrs, 0x0, IVRS_TABLE_LENGTH, StdHeader);
- LibAmdMemCopy (Ivrs, &IvrsHeader, sizeof (IvrsHeader), StdHeader);
- NumberOfSockets = GnbGetNumberOfSockets (StdHeader);
- for (SocketId = 0; SocketId < NumberOfSockets; SocketId++) {
- if (GnbIsDevicePresentInSocket (SocketId, StdHeader)) {
- NumberOfSilicons = GnbGetNumberOfSiliconsOnSocket (SocketId, StdHeader);
- for (SiliconId = 0; SiliconId < NumberOfSilicons; SiliconId++) {
- if (GnbFmCheckIommuPresent (SocketId, SiliconId, StdHeader)) {
- IDS_HDT_CONSOLE (GNB_TRACE, "Build IVRS for Socket %d Silicon %d\n", SocketId, SiliconId);
- IvrsSupport = TRUE;
- GnbFmCreateIvrsEntry (SocketId, SiliconId, IvrsIvhdBlock, Ivrs, StdHeader);
- if (GnbBuildOptions.IvrsRelativeAddrNamesSupport) {
- GnbFmCreateIvrsEntry (SocketId, SiliconId, IvrsIvhdrBlock, Ivrs, StdHeader);
- }
- }
- }
- }
- }
- if (IvrsSupport == TRUE) {
- ChecksumAcpiTable ((ACPI_TABLE_HEADER*) Ivrs, StdHeader);
- GNB_DEBUG_CODE (GnbIommuIvrsTableDump (Ivrs, StdHeader));
- } else {
- IDS_HDT_CONSOLE (GNB_TRACE, " IVRS table not generated\n");
- LateParamsPtr->AcpiIvrs = NULL;
- }
- return Status;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Dump IVRS table
- *
- *
- * @param[in] Ivrs Pointer to IVRS table
- * @param[in] StdHeader Standard Configuration Header
- */
-
-VOID
-GnbIommuIvrsTableDump (
- IN VOID *Ivrs,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 *Block;
- UINT8 *Entry;
- Block = (UINT8 *) Ivrs + sizeof (IOMMU_IVRS_HEADER);
- IDS_HDT_CONSOLE (GNB_TRACE, "<---------- IVRS Table Start -----------> \n");
- IDS_HDT_CONSOLE (GNB_TRACE, " IVInfo = 0x%08x\n", ((IOMMU_IVRS_HEADER *) Ivrs)-> IvInfo);
- while (Block < ((UINT8 *) Ivrs + ((IOMMU_IVRS_HEADER *) Ivrs)->TableLength)) {
- if (*Block == IvrsIvhdBlock) {
- IDS_HDT_CONSOLE (GNB_TRACE, " <-------------IVHD Block Start -------->\n");
- IDS_HDT_CONSOLE (GNB_TRACE, " Flags = 0x%02x\n", ((IVRS_IVHD_ENTRY *) Block)->Flags);
- IDS_HDT_CONSOLE (GNB_TRACE, " DeviceId = 0x%04x\n", ((IVRS_IVHD_ENTRY *) Block)->DeviceId);
- IDS_HDT_CONSOLE (GNB_TRACE, " CapabilityOffset = 0x%02x\n", ((IVRS_IVHD_ENTRY *) Block)->CapabilityOffset);
- IDS_HDT_CONSOLE (GNB_TRACE, " BaseAddress = 0x%08x%08x\n", (UINT32) (((IVRS_IVHD_ENTRY *) Block)->BaseAddress >> 32), (UINT32) ((IVRS_IVHD_ENTRY *) Block)->BaseAddress);
- IDS_HDT_CONSOLE (GNB_TRACE, " PCI Segment = 0x%04x\n", ((IVRS_IVHD_ENTRY *) Block)->PciSegment);
- IDS_HDT_CONSOLE (GNB_TRACE, " IommuInfo = 0x%04x\n", ((IVRS_IVHD_ENTRY *) Block)->IommuInfo);
- IDS_HDT_CONSOLE (GNB_TRACE, " IommuEfr = 0x%08x\n", ((IVRS_IVHD_ENTRY *) Block)->IommuEfr);
- Entry = Block + sizeof (IVRS_IVHD_ENTRY);
- IDS_HDT_CONSOLE (GNB_TRACE, " <-------------IVHD Block Device Entries Start -------->\n");
- while (Entry < (Block + ((IVRS_IVHD_ENTRY *) Block)->Length)) {
- IDS_HDT_CONSOLE (GNB_TRACE, " ");
- switch (*Entry) {
- case IvhdEntrySelect:
- case IvhdEntryEndRange:
- GnbLibDebugDumpBuffer (Entry, 4, 1, 4);
- Entry = Entry + 4;
- break;
- case IvhdEntryStartRange:
- GnbLibDebugDumpBuffer (Entry, 8, 1, 8);
- Entry = Entry + 8;
- break;
- case IvhdEntryAliasStartRange:
- GnbLibDebugDumpBuffer (Entry, 12, 1, 12);
- Entry = Entry + 12;
- break;
- case IvhdEntryAliasSelect:
- case IvhdEntryExtendedSelect:
- case IvhdEntrySpecialDevice:
- GnbLibDebugDumpBuffer (Entry, 8, 1, 8);
- Entry = Entry + 8;
- break;
- case IvhdEntryPadding:
- Entry = Entry + 4;
- break;
- default:
- IDS_HDT_CONSOLE (GNB_TRACE, " Unsupported entry type [%d]\n");
- ASSERT (FALSE);
- }
- }
- IDS_HDT_CONSOLE (GNB_TRACE, " <-------------IVHD Block Device Entries End -------->\n");
- IDS_HDT_CONSOLE (GNB_TRACE, " <-------------IVHD Block End ---------->\n");
- Block = Block + ((IVRS_IVHD_ENTRY *) Block)->Length;
- }
- }
- IDS_HDT_CONSOLE (GNB_TRACE, "<---------- IVRS Table Raw Data --------> \n");
- GnbLibDebugDumpBuffer (Ivrs, ((IOMMU_IVRS_HEADER *) Ivrs)->TableLength, 1, 16);
- IDS_HDT_CONSOLE (GNB_TRACE, "\n");
- IDS_HDT_CONSOLE (GNB_TRACE, "<---------- IVRS Table End -------------> \n");
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.h
deleted file mode 100644
index c9ccb07c34..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe ALIB
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39433 $ @e \$Date: 2010-10-11 14:15:36 -0700 (Mon, 11 Oct 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-#ifndef _GNBIOMMUIVRS_H_
-#define _GNBIOMMUIVRS_H_
-
-AGESA_STATUS
-GnbIommuIvrsTable (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c
deleted file mode 100644
index ff4d979702..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe ALIB
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39433 $ @e \$Date: 2010-10-11 14:15:36 -0700 (Mon, 11 Oct 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "amdlib.h"
-#include "heapManager.h"
-#include "cpuLateInit.h"
-#include "Gnb.h"
-#include "GnbFamServices.h"
-#include "GnbCommonLib.h"
-#include "GnbIommuIvrs.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBIVRSLIB_GNBIVRSLIB_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Create IVHDR entry for device range
- *
- *
- * @param[in] StartRange Address of start range
- * @param[in] EndRange Address of end range
- * @param[in] DataSetting Data setting
- * @param[in] Ivhd Pointer to IVHD entry
- * @param[in] StdHeader Standard configuration header
- *
- */
-VOID
-GnbIvhdAddDeviceRangeEntry (
- IN PCI_ADDR StartRange,
- IN PCI_ADDR EndRange,
- IN UINT8 DataSetting,
- IN IVRS_IVHD_ENTRY *Ivhd,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- IVHD_GENERIC_ENTRY *Entry;
- Entry = (IVHD_GENERIC_ENTRY *) ((UINT8 *) Ivhd + Ivhd->Length);
- Entry->Type = IvhdEntryStartRange;
- Entry->DeviceId = DEVICE_ID (StartRange);
- Entry->DataSetting = DataSetting;
- Ivhd->Length += sizeof (IVHD_GENERIC_ENTRY);
- Entry = (IVHD_GENERIC_ENTRY *) ((UINT8 *) Ivhd + Ivhd->Length);
- Entry->Type = IvhdEntryEndRange;
- Entry->DeviceId = DEVICE_ID (EndRange);
- Ivhd->Length += sizeof (IVHD_GENERIC_ENTRY);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Create IVHDR entry for aliased range
- *
- *
- * @param[in] StartRange Address of start range
- * @param[in] EndRange Address of end range
- * @param[in] Alias Address of alias requestor ID for range
- * @param[in] DataSetting Data setting
- * @param[in] Ivhd Pointer to IVHD entry
- * @param[in] StdHeader Standard configuration header
- *
- */
-VOID
-GnbIvhdAddDeviceAliasRangeEntry (
- IN PCI_ADDR StartRange,
- IN PCI_ADDR EndRange,
- IN PCI_ADDR Alias,
- IN UINT8 DataSetting,
- IN IVRS_IVHD_ENTRY *Ivhd,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- IVHD_ALIAS_ENTRY *RangeEntry;
- IVHD_GENERIC_ENTRY *Entry;
- UINT8 Padding;
- Padding = (UINT8) ((Ivhd->Length + 0x7) & (~ 0x7));
- RangeEntry = (IVHD_ALIAS_ENTRY *) ((UINT8 *) Ivhd + Padding);
- RangeEntry->Type = IvhdEntryAliasStartRange;
- RangeEntry->DeviceId = DEVICE_ID (StartRange);
- RangeEntry->AliasDeviceId = DEVICE_ID (Alias);
- RangeEntry->DataSetting = DataSetting;
- Ivhd->Length += sizeof (IVHD_ALIAS_ENTRY);
- Entry = (IVHD_GENERIC_ENTRY *) ((UINT8 *) Ivhd + Ivhd->Length);
- Entry->Type = IvhdEntryEndRange;
- Entry->DeviceId = DEVICE_ID (EndRange);
- Ivhd->Length += (sizeof (IVHD_GENERIC_ENTRY) + Padding);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Create IVHDR entry for special device
- *
- *
- * @param[in] SpecialDevice Special device Type
- * @param[in] Device Address of requestor ID for special device
- * @param[in] Id Apic ID/ Hpet ID
- * @param[in] DataSetting Data setting
- * @param[in] Ivhd Pointer to IVHD entry
- * @param[in] StdHeader Standard configuration header
- *
- */
-VOID
-GnbIvhdAddSpecialDeviceEntry (
- IN IVHD_SPECIAL_DEVICE SpecialDevice,
- IN PCI_ADDR Device,
- IN UINT8 Id,
- IN UINT8 DataSetting,
- IN IVRS_IVHD_ENTRY *Ivhd,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- IVHD_SPECIAL_ENTRY *SpecialEntry;
- UINT8 Padding;
- Padding = (UINT8) ((Ivhd->Length + 0x7) & (~ 0x7));
- SpecialEntry = (IVHD_SPECIAL_ENTRY *) ((UINT8 *) Ivhd + Padding);
- SpecialEntry->Type = IvhdEntrySpecialDevice;
- SpecialEntry->AliasDeviceId = DEVICE_ID (Device);
- SpecialEntry->Variety = (UINT8) SpecialDevice;
- Ivhd->Length += (sizeof (IVHD_SPECIAL_ENTRY) + Padding);
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.h
deleted file mode 100644
index 55459c9fa2..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe ALIB
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39433 $ @e \$Date: 2010-10-11 14:15:36 -0700 (Mon, 11 Oct 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-#ifndef _GNBIVRSLIB_H_
-#define _GNBIVRSLIB_H_
-
-
-VOID
-GnbIvhdAddDeviceRangeEntry (
- IN PCI_ADDR StartRange,
- IN PCI_ADDR EndRange,
- IN UINT8 DataSetting,
- IN IVRS_IVHD_ENTRY *Ivhd,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-GnbIvhdAddDeviceAliasRangeEntry (
- IN PCI_ADDR StartRange,
- IN PCI_ADDR EndRange,
- IN PCI_ADDR Alias,
- IN UINT8 DataSetting,
- IN IVRS_IVHD_ENTRY *Ivhd,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-GnbIvhdAddSpecialDeviceEntry (
- IN IVHD_SPECIAL_DEVICE SpecialDevice,
- IN PCI_ADDR Device,
- IN UINT8 Id,
- IN UINT8 DataSetting,
- IN IVRS_IVHD_ENTRY *Ivhd,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-
-#endif
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.c
deleted file mode 100644
index c6dfcb32fa..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * SB services
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39931 $ @e \$Date: 2010-10-16 18:19:16 -0700 (Sat, 16 Oct 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "amdlib.h"
-#include "Gnb.h"
-#include "GnbCommonLib.h"
-#include "GnbIvrsLib.h"
-#include "GnbSbLib.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBSBIOMMULIB_GNBSBIOMMULIB_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Create IVHD entry
- *
- *
- * @param[in] Ivhd IVHD header pointer
- * @param[in] StdHeader Standard configuration header
- *
- */
-VOID
-SbCreateIvhdEntries (
- OUT IVRS_IVHD_ENTRY *Ivhd,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- PCI_ADDR Start;
- PCI_ADDR End;
- PCI_ADDR PciAddress;
- UINT32 Value;
- IDS_HDT_CONSOLE (GNB_TRACE, "SbCreateIvhdEntries Entry\n");
- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 4, 0);
-// P2P alias entry
- GnbLibPciRead (PciAddress.AddressValue | 0x18, AccessWidth32, &Value, StdHeader);
- Start.AddressValue = MAKE_SBDFO (0, (Value >> 8) & 0xff, 0, 0, 0);
- End.AddressValue = MAKE_SBDFO (0, (Value >> 16) & 0xff, 0x1f, 0x7, 0);
- GnbIvhdAddDeviceAliasRangeEntry (Start, End, PciAddress, 0, Ivhd, StdHeader);
- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0, 0);
-// HPET
- GnbIvhdAddSpecialDeviceEntry (IvhdSpecialDeviceHpet, PciAddress, 0, 0, Ivhd, StdHeader);
-// APIC
- GnbIvhdAddSpecialDeviceEntry (
- IvhdSpecialDeviceIoapic,
- PciAddress,
- GnbLiGetIoapicId (SbGetSbIoApicBaseAddress (StdHeader), StdHeader),
- 0xD7,
- Ivhd,
- StdHeader
- );
- IDS_HDT_CONSOLE (GNB_TRACE, "SbCreateIvhdEntries Exit\n");
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.h b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.h
deleted file mode 100644
index 4b9c26e676..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * SB services
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39931 $ @e \$Date: 2010-10-16 18:19:16 -0700 (Sat, 16 Oct 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-#ifndef _GNBSBIOMMULIB_H_
-#define _GNBSBIOMMULIB_H_
-
-
-VOID
-SbCreateIvhdEntries (
- OUT IVRS_IVHD_ENTRY *Ivhd,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbCoherentFam10.c b/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbCoherentFam10.c
deleted file mode 100644
index 9c08032677..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbCoherentFam10.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Coherent Family 10h Routines.
- *
- * Coherent feature Northbridge implementation specific to Family 10h processors.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "htNb.h"
-#include "htNbCommonHardware.h"
-#include "htNbCoherentFam10.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_FAM10_HTNBCOHERENTFAM10_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Return whether the current configuration exceeds the capability.
- *
- * @HtNbMethod{::F_IS_EXCEEDED_CAPABLE}.
- *
- * Get Node capability and update the minimum supported system capability.
- *
- * @param[in] Node the Node
- * @param[in] State sysMpCap (updated) and NodesDiscovered
- * @param[in] Nb this northbridge
- *
- * @retval TRUE system is not capable of current config.
- * @retval FALSE system is capable of current config.
- */
-BOOLEAN
-Fam10IsExceededCapable (
- IN UINT8 Node,
- IN STATE_DATA *State,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT32 Temp;
- UINT8 MaxNodes;
- PCI_ADDR Reg;
-
- ASSERT (Node < MAX_NODES);
-
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_NB_FUNC_03,
- REG_NB_CAPABILITY_3XE8);
-
- LibAmdPciReadBits (Reg, 18, 16, &Temp, Nb->ConfigHandle);
-
- if (Temp != 0) {
- MaxNodes = (UINT8) (1 << (~Temp & 0x3)); // That is, 1, 2, 4, or 8
- } else {
- MaxNodes = 8;
- }
- if (State->SysMpCap > MaxNodes) {
- State->SysMpCap = MaxNodes;
- }
- // Note since sysMpCap is one based and NodesDiscovered is zero based, equal returns true
- //
- return ((BOOLEAN) (State->SysMpCap <= State->NodesDiscovered));
-}
-
-/**
- * Stop a link, so that it is isolated from a connected device.
- *
- * @HtNbMethod{::F_STOP_LINK}.
- *
- * Use is for fatal incompatible configurations, or for user interface
- * request to power off a link (IgnoreLink, SkipRegang).
- * Set ConnDly to make the power effective at the warm reset.
- * Set XMT and RCV off.
- *
- * @param[in] Node the node to stop a link on.
- * @param[in] Link the link to stop.
- * @param[in] State access to special routine for writing link control register
- * @param[in] Nb this northbridge.
- */
-VOID
-Fam10StopLink (
- IN UINT8 Node,
- IN UINT8 Link,
- IN STATE_DATA *State,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT32 Temp;
- PCI_ADDR Reg;
-
- // Set ConnDly
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_LINK_GLOBAL_EXT_CONTROL_0x16C);
- Temp = 1;
- LibAmdPciWriteBits (Reg, 8, 8, &Temp, Nb->ConfigHandle);
- // Set TransOff and EndOfChain
- Reg = Nb->MakeLinkBase (Node, Link, Nb);
- Reg.Address.Register += HTHOST_LINK_CONTROL_REG;
- Temp = 3;
- State->HtFeatures->SetHtControlRegisterBits (Reg, 7, 6, &Temp, State);
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbCoherentFam10.h b/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbCoherentFam10.h
deleted file mode 100644
index 49d428f92b..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbCoherentFam10.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Coherent Family 10h specific Routines.
- *
- * Coherent feature Northbridge implementation specific to Family 10h processors.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/**
- * Return whether the current configuration exceeds the capability.
- *
- */
-BOOLEAN
-Fam10IsExceededCapable (
- IN UINT8 Node,
- IN STATE_DATA *State,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Stop a link, so that it is isolated from a connected device.
- */
-VOID
-Fam10StopLink (
- IN UINT8 Node,
- IN UINT8 Link,
- IN STATE_DATA *State,
- IN NORTHBRIDGE *Nb
- );
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbFam10.c b/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbFam10.c
deleted file mode 100644
index cf404526d3..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbFam10.c
+++ /dev/null
@@ -1,365 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Initializers for Family 10h northbridge support.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44846 $ @e \$Date: 2011-01-07 13:21:05 +0800 (Fri, 07 Jan 2011) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "OptionsHt.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "htNb.h"
-#include "CommonReturns.h"
-#include "htNbCoherent.h"
-#include "htNbCoherentFam10.h"
-#include "htNbNonCoherent.h"
-#include "htNbNonCoherentFam10.h"
-#include "htNbOptimization.h"
-#include "htNbOptimizationFam10.h"
-#include "htNbSystemFam10.h"
-#include "htNbUtilities.h"
-#include "htNbUtilitiesFam10.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_FAM10_HTNBFAM10_FILECODE
-
-extern OPTION_HT_CONFIGURATION OptionHtConfiguration;
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/***************************************************************************
- *** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS ***
- ***************************************************************************/
-
-/**
- * Map Northbridge links to package links for Family 10h, Rev D, multi-module.
- *
- * Unfortunately, there is no way to do this except to type the BKDG text into this data structure.
- * Note that there is one entry per package external sublink and each connected internal link.
- */
-CONST PACKAGE_HTLINK_MAP_ITEM ROMDATA HtFam10RevDPackageLinkMap[] =
-{
- {0, 0, 0}, ///< Module zero, link 0: package link 0
- {4, 0, 4}, ///< Module zero, link 4: package link 4
- {0, 1, 1}, ///< Module one, link 0: package link 1
- {4, 1, 5}, ///< Module one, link 4: package link 5
- {3, 0, 2}, ///< Module zero, link 3: package link 2
- {7, 0, 6}, ///< Module zero, link 7: package link 6
- {2, 0, 3}, ///< Module zero, link 2: package link 3
- {1, 1, 7}, ///< Module one, link 1: package link 7
- {1, 0, HT_LIST_MATCH_INTERNAL_LINK_0}, ///< Internal Link
- {5, 0, HT_LIST_MATCH_INTERNAL_LINK_1}, ///< Internal Link
- {6, 0, HT_LIST_MATCH_INTERNAL_LINK_2}, ///< Internal Link
- {2, 1, HT_LIST_MATCH_INTERNAL_LINK_0}, ///< Internal Link
- {6, 1, HT_LIST_MATCH_INTERNAL_LINK_1}, ///< Internal Link
- {5, 1, HT_LIST_MATCH_INTERNAL_LINK_2}, ///< Internal Link
- {HT_LIST_TERMINAL, HT_LIST_TERMINAL, HT_LIST_TERMINAL}, ///< End
-};
-
-/**
- * A default Ignore Link list for rev D to power off the 3rd internal sublink.
- */
-STATIC CONST IGNORE_LINK ROMDATA Fam10RevDIgnoreLinkList[] = {
- HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK_2, POWERED_OFF,
- HT_LIST_TERMINAL
-};
-
-/**
- * Initial construction data for Family 10h North Bridge, default, full features.
- */
-CONST NORTHBRIDGE ROMDATA HtFam10NbDefault =
-{
- 8,
- WriteRoutingTable,
- WriteNodeID,
- ReadDefaultLink,
- EnableRoutingTables,
- DisableRoutingTables,
- VerifyLinkIsCoherent,
- ReadToken,
- WriteToken,
- WriteFullRoutingTable,
- IsIllegalTypeMix,
- Fam10IsExceededCapable,
- Fam10StopLink,
- (PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse,
- HandleSpecialNodeCase,
- ReadSouthbridgeLink,
- VerifyLinkIsNonCoherent,
- Fam10SetConfigAddrMap,
- Fam10NorthBridgeFreqMask,
- GatherLinkFeatures,
- SetLinkRegang,
- SetLinkFrequency,
- SetLinkUnitIdClumping,
- Fam10WriteTrafficDistribution,
- Fam10WriteLinkPairDistribution,
- (PF_WRITE_VICTIM_DISTRIBUTION)CommonVoid,
- Fam10BufferOptimizations,
- Fam10GetNumCoresOnNode,
- SetTotalNodesAndCores,
- GetNodeCount,
- LimitNodes,
- ReadTrueLinkFailStatus,
- Fam10GetNextLink,
- GetPackageLink,
- MakeLinkBase,
- Fam10GetModuleInfo,
- Fam10PostMailbox,
- Fam10RetrieveMailbox,
- Fam10GetSocket,
- (PF_GET_ENABLED_COMPUTE_UNITS)CommonReturnZero8,
- (PF_GET_DUALCORE_COMPUTE_UNITS)CommonReturnZero8,
- 0x00000001,
- 0x00000200,
- 18,
- TRUE,
- TRUE,
- ((AMD_FAMILY_10) & ~(AMD_FAMILY_10_HY | AMD_FAMILY_10_PH)),
- NULL,
- 0,
- NULL,
- MakeKey,
- NULL
-};
-
-/**
- * Initial construction data for Family 10h North Bridge, default, full features.
- */
-CONST NORTHBRIDGE ROMDATA HtFam10RevDNbDefault =
-{
- 8,
- WriteRoutingTable,
- WriteNodeID,
- ReadDefaultLink,
- EnableRoutingTables,
- DisableRoutingTables,
- VerifyLinkIsCoherent,
- ReadToken,
- WriteToken,
- WriteFullRoutingTable,
- IsIllegalTypeMix,
- Fam10IsExceededCapable,
- Fam10StopLink,
- (PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse,
- HandleSpecialNodeCase,
- ReadSouthbridgeLink,
- VerifyLinkIsNonCoherent,
- Fam10SetConfigAddrMap,
- Fam10RevDNorthBridgeFreqMask,
- GatherLinkFeatures,
- SetLinkRegang,
- SetLinkFrequency,
- SetLinkUnitIdClumping,
- Fam10WriteTrafficDistribution,
- Fam10WriteLinkPairDistribution,
- (PF_WRITE_VICTIM_DISTRIBUTION)CommonVoid,
- Fam10RevDBufferOptimizations,
- Fam10RevDGetNumCoresOnNode,
- SetTotalNodesAndCores,
- GetNodeCount,
- LimitNodes,
- ReadTrueLinkFailStatus,
- Fam10GetNextLink,
- GetPackageLink,
- MakeLinkBase,
- Fam10GetModuleInfo,
- Fam10PostMailbox,
- Fam10RetrieveMailbox,
- Fam10RevDGetSocket,
- (PF_GET_ENABLED_COMPUTE_UNITS)CommonReturnZero8,
- (PF_GET_DUALCORE_COMPUTE_UNITS)CommonReturnZero8,
- 0x00000001,
- 0x00000200,
- 18,
- TRUE,
- TRUE,
- (AMD_FAMILY_10_HY | AMD_FAMILY_10_PH),
- (PACKAGE_HTLINK_MAP) &HtFam10RevDPackageLinkMap,
- 0,
- (IGNORE_LINK *)&Fam10RevDIgnoreLinkList,
- MakeKey,
- NULL
-};
-
-/**
- * Initial construction data for Family 10h North Bridge, for non-coherent only builds.
- */
-CONST NORTHBRIDGE ROMDATA HtFam10NbNonCoherentOnly =
-{
- 8,
- (PF_WRITE_ROUTING_TABLE)CommonVoid,
- (PF_WRITE_NODEID)CommonVoid,
- (PF_READ_DEFAULT_LINK)CommonReturnZero8,
- (PF_ENABLE_ROUTING_TABLES)CommonVoid,
- (PF_DISABLE_ROUTING_TABLES)CommonVoid,
- (PF_VERIFY_LINK_IS_COHERENT)CommonReturnFalse,
- (PF_READ_TOKEN)CommonReturnZero8,
- (PF_WRITE_TOKEN)CommonVoid,
- (PF_WRITE_FULL_ROUTING_TABLE)CommonVoid,
- (PF_IS_ILLEGAL_TYPE_MIX)CommonReturnFalse,
- (PF_IS_EXCEEDED_CAPABLE)CommonReturnFalse,
- (PF_STOP_LINK)CommonVoid,
- (PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse,
- (PF_HANDLE_SPECIAL_NODE_CASE)CommonReturnFalse,
- ReadSouthbridgeLink,
- VerifyLinkIsNonCoherent,
- Fam10SetConfigAddrMap,
- Fam10NorthBridgeFreqMask,
- GatherLinkFeatures,
- SetLinkRegang,
- SetLinkFrequency,
- SetLinkUnitIdClumping,
- (PF_WRITE_TRAFFIC_DISTRIBUTION)CommonVoid,
- (PF_WRITE_LINK_PAIR_DISTRIBUTION)CommonVoid,
- (PF_WRITE_VICTIM_DISTRIBUTION)CommonVoid,
- Fam10BufferOptimizations,
- Fam10GetNumCoresOnNode,
- SetTotalNodesAndCores,
- GetNodeCount,
- LimitNodes,
- ReadTrueLinkFailStatus,
- Fam10GetNextLink,
- GetPackageLink,
- MakeLinkBase,
- Fam10GetModuleInfo,
- Fam10PostMailbox,
- Fam10RetrieveMailbox,
- Fam10GetSocket,
- (PF_GET_ENABLED_COMPUTE_UNITS)CommonReturnZero8,
- (PF_GET_DUALCORE_COMPUTE_UNITS)CommonReturnZero8,
- 0x00000001,
- 0x00000200,
- 18,
- TRUE,
- TRUE,
- ((AMD_FAMILY_10) & ~(AMD_FAMILY_10_HY | AMD_FAMILY_10_PH)),
- NULL,
- 0,
- NULL,
- MakeKey,
- NULL
-};
-
-/**
- * Initial construction data for Family 10h North Bridge, for RevD compatible non-coherent only builds.
- */
-CONST NORTHBRIDGE ROMDATA HtFam10RevDNbNonCoherentOnly =
-{
- 8,
- (PF_WRITE_ROUTING_TABLE)CommonVoid,
- (PF_WRITE_NODEID)CommonVoid,
- (PF_READ_DEFAULT_LINK)CommonReturnZero8,
- (PF_ENABLE_ROUTING_TABLES)CommonVoid,
- (PF_DISABLE_ROUTING_TABLES)CommonVoid,
- (PF_VERIFY_LINK_IS_COHERENT)CommonReturnFalse,
- (PF_READ_TOKEN)CommonReturnZero8,
- (PF_WRITE_TOKEN)CommonVoid,
- (PF_WRITE_FULL_ROUTING_TABLE)CommonVoid,
- (PF_IS_ILLEGAL_TYPE_MIX)CommonReturnFalse,
- (PF_IS_EXCEEDED_CAPABLE)CommonReturnFalse,
- (PF_STOP_LINK)CommonVoid,
- (PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse,
- (PF_HANDLE_SPECIAL_NODE_CASE)CommonReturnFalse,
- ReadSouthbridgeLink,
- VerifyLinkIsNonCoherent,
- Fam10SetConfigAddrMap,
- Fam10RevDNorthBridgeFreqMask,
- GatherLinkFeatures,
- SetLinkRegang,
- SetLinkFrequency,
- SetLinkUnitIdClumping,
- (PF_WRITE_TRAFFIC_DISTRIBUTION)CommonVoid,
- (PF_WRITE_LINK_PAIR_DISTRIBUTION)CommonVoid,
- (PF_WRITE_VICTIM_DISTRIBUTION)CommonVoid,
- Fam10BufferOptimizations,
- Fam10RevDGetNumCoresOnNode,
- SetTotalNodesAndCores,
- GetNodeCount,
- LimitNodes,
- ReadTrueLinkFailStatus,
- Fam10GetNextLink,
- GetPackageLink,
- MakeLinkBase,
- Fam10GetModuleInfo,
- Fam10PostMailbox,
- Fam10RetrieveMailbox,
- Fam10GetSocket,
- (PF_GET_ENABLED_COMPUTE_UNITS)CommonReturnZero8,
- (PF_GET_DUALCORE_COMPUTE_UNITS)CommonReturnZero8,
- 0x00000001,
- 0x00000200,
- 18,
- TRUE,
- TRUE,
- (AMD_FAMILY_10_HY | AMD_FAMILY_10_PH),
- NULL,
- 0,
- NULL,
- MakeKey,
- NULL
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbNonCoherentFam10.c b/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbNonCoherentFam10.c
deleted file mode 100644
index 2cac1d4f25..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbNonCoherentFam10.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Northbridge non-coherent support for Family 10h processors.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "htNb.h"
-#include "htNbCommonHardware.h"
-#include "htNbNonCoherentFam10.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_FAM10_HTNBNONCOHERENTFAM10_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Enable config access to a non-coherent chain for the given bus range.
- *
- * @HtNbMethod{::F_SET_CONFIG_ADDR_MAP}
- *
- * @param[in] ConfigMapIndex the map entry to set
- * @param[in] SecBus The secondary bus number to use
- * @param[in] SubBus The subordinate bus number to use
- * @param[in] TargetNode The Node that shall be the recipient of the traffic
- * @param[in] TargetLink The Link that shall be the recipient of the traffic
- * @param[in] State our global state
- * @param[in] Nb this northbridge
- */
-VOID
-Fam10SetConfigAddrMap (
- IN UINT8 ConfigMapIndex,
- IN UINT8 SecBus,
- IN UINT8 SubBus,
- IN UINT8 TargetNode,
- IN UINT8 TargetLink,
- IN STATE_DATA *State,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT8 CurNode;
- PCI_ADDR Reg;
- UINT32 Temp;
-
- Reg = Nb->MakeLinkBase (TargetNode, TargetLink, Nb);
-
- ASSERT (SecBus <= SubBus);
- ASSERT (TargetNode <= State->NodesDiscovered);
- ASSERT (TargetLink < Nb->MaxLinks);
- Temp = SecBus;
- Reg.Address.Register += HTHOST_ISOC_REG;
- LibAmdPciWriteBits (Reg, 15, 8, &Temp, Nb->ConfigHandle);
-
- Temp = ((UINT32)SubBus << 24) + ((UINT32)SecBus << 16) + ((UINT32)TargetLink << 8) +
- ((UINT32)TargetNode << 4) + (UINT32)3;
- for (CurNode = 0; CurNode < (State->NodesDiscovered + 1); CurNode++) {
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (CurNode),
- MakePciBusFromNode (CurNode),
- MakePciDeviceFromNode (CurNode),
- CPU_ADDR_FUNC_01,
- REG_ADDR_CONFIG_MAP0_1XE0 + (4 * ConfigMapIndex));
- LibAmdPciWrite (AccessWidth32, Reg, &Temp, Nb->ConfigHandle);
- }
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbNonCoherentFam10.h b/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbNonCoherentFam10.h
deleted file mode 100644
index ae9cbe32b3..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbNonCoherentFam10.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Northbridge non-coherent support for Family 10h processors.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/**
- * Enable config access to a non-coherent chain for the given bus range.
- *
- */
-VOID
-Fam10SetConfigAddrMap (
- IN UINT8 ConfigMapIndex,
- IN UINT8 SecBus,
- IN UINT8 SubBus,
- IN UINT8 TargetNode,
- IN UINT8 TargetLink,
- IN STATE_DATA *State,
- IN NORTHBRIDGE *Nb
- );
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbOptimizationFam10.c b/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbOptimizationFam10.c
deleted file mode 100644
index e4a85821be..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbOptimizationFam10.c
+++ /dev/null
@@ -1,221 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Link optimization support specific to family 10h processors.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "htInterface.h"
-#include "htNb.h"
-#include "htNbOptimizationFam10.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_FAM10_HTNBOPTIMIZATIONFAM10_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Northbridge specific Frequency limit.
- *
- * @HtNbMethod{::F_NORTH_BRIDGE_FREQ_MASK}
- *
- * Return a mask that eliminates HT frequencies that cannot be used due to a slow
- * northbridge frequency.
- *
- * @param[in] Node Result could (later) be for a specific Node
- * @param[in] Interface Access to non-HT support functions.
- * @param[in] PlatformConfig Platform profile/build option config structure.
- * @param[in] Nb this northbridge
- *
- * @return Frequency mask
- */
-UINT32
-Fam10NorthBridgeFreqMask (
- IN UINT8 Node,
- IN HT_INTERFACE *Interface,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT32 NbCoreFreq;
- UINT32 Supported;
-
- ASSERT (Node < MAX_NODES);
- ASSERT (Interface != NULL);
- // The interface to power management will return a system based result.
- // So we only need to call it once, not on every link. Save the answer,
- // and check to see if we can use a saved answer on subsequent calls.
- //
- if (Nb->CoreFrequency == 0) {
- NbCoreFreq = Interface->GetMinNbCoreFreq (PlatformConfig, Nb->ConfigHandle);
- NbCoreFreq = (NbCoreFreq / 100);
- ASSERT (NbCoreFreq != 0);
- Nb->CoreFrequency = NbCoreFreq;
- } else {
- NbCoreFreq = Nb->CoreFrequency;
- }
-
- //
- // NbCoreFreq is minimum northbridge speed in hundreds of MHz.
- // HT can not go faster than the minimum speed of the northbridge.
- //
- if ((NbCoreFreq >= 6) && (NbCoreFreq <= 26)) {
- // Convert frequency to bit and all less significant bits,
- // by setting next power of 2 and subtracting 1.
- //
- Supported = ((UINT32)1 << ((NbCoreFreq >> 1) + 2)) - 1;
- } else if ((NbCoreFreq > 26) && (NbCoreFreq <= 32)) {
- // Convert frequency to bit and all less significant bits,
- // by setting next power of 2 and subtracting 1, noting that
- // next power of two is two greater than non-extended frequencies
- // (because of the register break).
- //
- Supported = ((UINT32)1 << ((NbCoreFreq >> 1) + 4)) - 1;
- } else if (NbCoreFreq > 32) {
- Supported = HT_FREQUENCY_LIMIT_MAX;
- } else if (NbCoreFreq == 4) {
- // unlikely cases, but include as a defensive measure, also avoid trick above
- Supported = HT_FREQUENCY_LIMIT_400M;
- } else if (NbCoreFreq == 2) {
- Supported = HT_FREQUENCY_LIMIT_200M;
- } else {
- ASSERT (FALSE);
- Supported = HT_FREQUENCY_LIMIT_200M;
- }
-
- return (Supported);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Northbridge specific Frequency limit.
- *
- * @HtNbMethod{::F_NORTH_BRIDGE_FREQ_MASK}
- *
- * Return a mask that eliminates HT frequencies that cannot be used due to a slow
- * northbridge frequency.
- *
- * @param[in] Node Result could (later) be for a specific Node
- * @param[in] Interface Access to non-HT support functions.
- * @param[in] PlatformConfig Platform profile/build option config structure.
- * @param[in] Nb this northbridge
- *
- * @return Frequency mask
- */
-UINT32
-Fam10RevDNorthBridgeFreqMask (
- IN UINT8 Node,
- IN HT_INTERFACE *Interface,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT32 NbCoreFreq;
- UINT32 Supported;
-
- ASSERT (Node < MAX_NODES);
- ASSERT (Interface != NULL);
- // The interface to power management will return a system based result.
- // So we only need to call it once, not on every link. Save the answer,
- // and check to see if we can use a saved answer on subsequent calls.
- //
- if (Nb->CoreFrequency == 0) {
- NbCoreFreq = Interface->GetMinNbCoreFreq (PlatformConfig, Nb->ConfigHandle);
- NbCoreFreq = (NbCoreFreq / 100);
- ASSERT (NbCoreFreq != 0);
- Nb->CoreFrequency = NbCoreFreq;
- } else {
- NbCoreFreq = Nb->CoreFrequency;
- }
-
- // For Rev D, the Ht frequency can go twice the Nb COF, as long as it's HT3.
- // (side note: we are not speculatively upgrading HT1 at 6 .. 10 to HT3,
- // to avoid complicated recovery if the final speed is HT1.)
- if (NbCoreFreq > 10) {
- NbCoreFreq = NbCoreFreq * 2;
- }
- //
- // NbCoreFreq is minimum northbridge speed in hundreds of MHz.
- // HT can not go faster than the minimum speed of the northbridge.
- //
- if ((NbCoreFreq >= 6) && (NbCoreFreq <= 26)) {
- // Convert frequency to bit and all less significant bits,
- // by setting next power of 2 and subtracting 1.
- //
- Supported = ((UINT32)1 << ((NbCoreFreq >> 1) + 2)) - 1;
- } else if ((NbCoreFreq > 26) && (NbCoreFreq <= 32)) {
- // Convert frequency to bit and all less significant bits,
- // by setting next power of 2 and subtracting 1, noting that
- // next power of two is two greater than non-extended frequencies
- // (because of the register break).
- //
- Supported = ((UINT32)1 << ((NbCoreFreq >> 1) + 4)) - 1;
- } else if (NbCoreFreq > 32) {
- Supported = HT_FREQUENCY_LIMIT_MAX;
- } else if (NbCoreFreq == 4) {
- // unlikely cases, but include as a defensive measure, also avoid trick above
- Supported = HT_FREQUENCY_LIMIT_400M;
- } else if (NbCoreFreq == 2) {
- Supported = HT_FREQUENCY_LIMIT_200M;
- } else {
- ASSERT (FALSE);
- Supported = HT_FREQUENCY_LIMIT_200M;
- }
-
- return (Supported);
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbOptimizationFam10.h b/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbOptimizationFam10.h
deleted file mode 100644
index 24a71e1d1d..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbOptimizationFam10.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Link optimization support specific to family 10h processors.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-/**
- * Northbridge specific Frequency limit.
- *
- */
-UINT32
-Fam10NorthBridgeFreqMask (
- IN UINT8 Node,
- IN HT_INTERFACE *Interface,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Northbridge specific Frequency limit.
- *
- */
-UINT32
-Fam10RevDNorthBridgeFreqMask (
- IN UINT8 Node,
- IN HT_INTERFACE *Interface,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN NORTHBRIDGE *Nb
- );
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbSystemFam10.c b/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbSystemFam10.c
deleted file mode 100644
index bd20f36db2..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbSystemFam10.c
+++ /dev/null
@@ -1,401 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * System Tuning Family 10h specific routines
- *
- * Support for Traffic Distribution and buffer tunings which
- * can not be done in a register table.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "htInterface.h"
-#include "htNb.h"
-#include "htNbCommonHardware.h"
-#include "htNbSystemFam10.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_FAM10_HTNBSYSTEMFAM10_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-/**
- * Register Fields for an individual link pair.
- */
-typedef struct {
- UINT32 Enable:1; ///< Enable distribution on this pair.
- UINT32 Asymmetric:1; ///< Links are different widths.
- UINT32 MasterSelect:3; ///< The master link.
- UINT32 AlternateSelect:3; ///< The alternate link.
-} PAIR_SELECT_FIELDS;
-
-/**
- * Register access union for ::PAIR_SELECT_FIELDS.
- */
-typedef union {
- UINT32 Value; ///< access as a 32 bit value or register.
- PAIR_SELECT_FIELDS Fields; ///< access individual fields.
-} PAIR_SELECT;
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/***************************************************************************
- *** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS ***
- ***************************************************************************/
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Set the traffic distribution register for the Links provided.
- *
- * @HtNbMethod{::F_WRITE_TRAFFIC_DISTRIBUTION}
- *
- * @param[in] Links01 coherent Links from Node 0 to 1
- * @param[in] Links10 coherent Links from Node 1 to 0
- * @param[in] Nb this northbridge
- */
-VOID
-Fam10WriteTrafficDistribution (
- IN UINT32 Links01,
- IN UINT32 Links10,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT32 Temp;
- PCI_ADDR TrafficDistReg;
-
- TrafficDistReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (0),
- MakePciBusFromNode (0),
- MakePciDeviceFromNode (0),
- CPU_HTNB_FUNC_00,
- REG_HT_TRAFFIC_DIST_0X164);
-
- // Node 0
- // DstLnk
- LibAmdPciWriteBits (TrafficDistReg, 23, 16, &Links01, Nb->ConfigHandle);
- // DstNode = 1, cHTPrbDistEn = 1, cHTRspDistEn = 1, cHTReqDistEn = 1
- Temp = 0x0107;
- LibAmdPciWriteBits (TrafficDistReg, 15, 0, &Temp, Nb->ConfigHandle);
-
- TrafficDistReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (1),
- MakePciBusFromNode (1),
- MakePciDeviceFromNode (1),
- CPU_HTNB_FUNC_00,
- REG_HT_TRAFFIC_DIST_0X164);
-
- // Node 1
- // DstLnk
- LibAmdPciWriteBits (TrafficDistReg, 23, 16, &Links10, Nb->ConfigHandle);
- // DstNode = 0, cHTPrbDistEn = 1, cHTRspDistEn = 1, cHTReqDistEn = 1
- Temp = 0x0007;
- LibAmdPciWriteBits (TrafficDistReg, 15, 0, &Temp, Nb->ConfigHandle);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Write a link pair to the link pair distribution and fixups.
- *
- * @HtNbMethod{::F_WRITE_LINK_PAIR_DISTRIBUTION}
- *
- * Set the links as a pair using the link pair index provided. Set asymmetric attribute as
- * provided. If the Master Link is not currently used as the route, fixup the routes for all
- * nodes which specify the alternate link.
- *
- * @param[in] Node Set the pair on this node
- * @param[in] ConnectedNode The Node to which this link pair directly connects.
- * @param[in] Pair Using this pair set in the register
- * @param[in] Asymmetric True if different widths
- * @param[in] MasterLink Set this as the master link and in the route
- * @param[in] AlternateLink Set this as the alternate link
- * @param[in] Nb this northbridge
- *
- */
-VOID
-Fam10WriteLinkPairDistribution (
- IN UINT8 Node,
- IN UINT8 ConnectedNode,
- IN UINT8 Pair,
- IN BOOLEAN Asymmetric,
- IN UINT8 MasterLink,
- IN UINT8 AlternateLink,
- IN NORTHBRIDGE *Nb
- )
-{
- PCI_ADDR Reg;
- UINT32 CurrentRoute;
- UINT32 MasterRoute;
- UINT32 AlternateRoute;
- PAIR_SELECT Selection;
- UINT32 RouteIndex;
-
- ASSERT ((Node < MAX_NODES) && (ConnectedNode < MAX_NODES));
- ASSERT (Pair < MAX_LINK_PAIRS);
- ASSERT (MasterLink < Nb->MaxLinks);
- ASSERT (AlternateLink < Nb->MaxLinks);
-
- // Make the master link the route for all routes to or through NodeB, by replacing all occurrences of
- // Alternate link with Master link. If routing used the master link, no update is necessary.
- MasterRoute = (((1 << Nb->BroadcastSelfBit) | Nb->SelfRouteResponseMask | Nb->SelfRouteRequestMask) << (MasterLink + 1));
- AlternateRoute = (((1 << Nb->BroadcastSelfBit) | Nb->SelfRouteResponseMask | Nb->SelfRouteRequestMask) << (AlternateLink + 1));
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_ROUTE0_0X40);
- for (RouteIndex = 0; RouteIndex < MAX_NODES; RouteIndex++) {
- Reg.Address.Register = REG_ROUTE0_0X40 + (RouteIndex * 4);
- LibAmdPciReadBits (Reg, 31, 0, &CurrentRoute, Nb->ConfigHandle);
- if ((CurrentRoute & AlternateRoute) != 0) {
- // Since Master and Alternate are redundant, the route must use one or the other but not both.
- ASSERT ((CurrentRoute & MasterRoute) == 0);
- // Set the master route for Request, Response or Broadcast only if the alternate was used for that case.
- // Example, use of a link as a broadcast link is typically not the same route register as its use for Request, Response.
- CurrentRoute = ((CurrentRoute & ~AlternateRoute) |
- ((((CurrentRoute & AlternateRoute) >> (AlternateLink + 1)) << (MasterLink + 1)) & MasterRoute));
- LibAmdPciWriteBits (Reg, 31, 0, &CurrentRoute, Nb->ConfigHandle);
- }
- }
-
- // Set the Link Pair and Enable it
- Selection.Fields.Enable = 1;
- Selection.Fields.Asymmetric = Asymmetric;
- Selection.Fields.MasterSelect = MasterLink;
- Selection.Fields.AlternateSelect = AlternateLink;
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_HT_LINK_PAIR_DIST_0X1E0);
- LibAmdPciWriteBits (
- Reg,
- ((PAIR_SELECT_OFFSET * (Pair + 1)) - 1),
- (PAIR_SELECT_OFFSET * Pair),
- &Selection.Value,
- Nb->ConfigHandle
- );
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Family 10h specific tunings.
- *
- * @HtNbMethod{::F_BUFFER_OPTIMIZATIONS}
- *
- * Buffer tunings are inherently northbridge specific. Check for specific configs
- * which require adjustments and apply any standard workarounds to this Node.
- *
- * @param[in] Node the Node to tune
- * @param[in] State global state
- * @param[in] Nb this northbridge
- */
-VOID
-Fam10BufferOptimizations (
- IN UINT8 Node,
- IN STATE_DATA *State,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT32 Temp;
- PCI_ADDR currentPtr;
- PCI_ADDR GangedReg;
- UINT8 i;
-
- ASSERT (Node < MAX_NODES);
-
- //
- // Link to XCS Token Count Tuning
- //
- // For each active Link that we reganged (so this unfortunately can't go into the PCI reg
- // table), we have to switch the Link to XCS Token Counts to the ganged state.
- // We do this here for the non - uma case, which is to write the values that would have
- // been power on defaults if the Link was ganged at cold reset.
- //
- for (i = 0; i < (State->TotalLinks * 2); i++) {
- if (((*State->PortList)[i].NodeID == Node) && ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU)) {
- // If the Link is greater than 4, this is a subLink 1, so it is not reganged.
- if ((*State->PortList)[i].Link < 4) {
- currentPtr.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_NB_FUNC_03,
- REG_NB_LINK_XCS_TOKEN0_3X148 + (4 * (*State->PortList)[i].Link)
- );
- if ((*State->PortList)[i].SelRegang) {
- // Handle all the regang Token count adjustments
-
- // SubLink 0: [Probe0tok] = 2 [Rsp0tok] = 2 [PReq0tok] = 2 [Req0tok] = 2
- Temp = 0xAA;
- LibAmdPciWriteBits (currentPtr, 7, 0, &Temp, Nb->ConfigHandle);
- // SubLink 1: [Probe1tok] = 0 [Rsp1tok] = 0 [PReq1tok] = 0 [Req1tok] = 0
- Temp = 0;
- LibAmdPciWriteBits (currentPtr, 23, 16, &Temp, Nb->ConfigHandle);
- // [FreeTok] = 3
- Temp = 3;
- LibAmdPciWriteBits (currentPtr, 15, 14, &Temp, Nb->ConfigHandle);
-
- } else {
- // Read the regang bit in hardware
- GangedReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode ((*State->PortList)[i].NodeID),
- MakePciBusFromNode ((*State->PortList)[i].NodeID),
- MakePciDeviceFromNode ((*State->PortList)[i].NodeID),
- CPU_HTNB_FUNC_00,
- REG_HT_LINK_EXT_CONTROL0_0X170 + (4 * (*State->PortList)[i].Link));
- LibAmdPciReadBits (GangedReg, 0, 0, &Temp, Nb->ConfigHandle);
- if (Temp == 1) {
- // handle a minor adjustment for strapped ganged Links. If SelRegang is false we
- // didn't do the regang, so if the bit is on then it's hardware strapped.
- //
-
- // [FreeTok] = 3
- Temp = 3;
- LibAmdPciWriteBits (currentPtr, 15, 14, &Temp, Nb->ConfigHandle);
- }
- }
- }
- }
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Family 10h specific tunings.
- *
- * @HtNbMethod{::F_BUFFER_OPTIMIZATIONS}
- *
- * Buffer tunings are inherently northbridge specific. Check for specific configs
- * which require adjustments and apply any standard workarounds to this Node.
- *
- * @param[in] Node the Node to tune
- * @param[in] State global state
- * @param[in] Nb this northbridge
- */
-VOID
-Fam10RevDBufferOptimizations (
- IN UINT8 Node,
- IN STATE_DATA *State,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT32 Temp;
- PCI_ADDR Reg;
- UINT8 i;
- FINAL_LINK_STATE FinalLinkState;
- UINT32 WidthIn;
- UINT32 WidthOut;
-
- ASSERT (Node < MAX_NODES);
-
- //
- // Internal link fixup.
- // When powering off internal link 2, a performance optimization may be possible where its buffers
- // can be made available to the external paired sublink. If the conditions are met, do the fix up here.
- //
- for (i = 0; i < (State->TotalLinks * 2); i++) {
- if (((*State->PortList)[i].NodeID == Node) && ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU)) {
- // Is this a sublink 0 paired with internal link 2?
- if (((*State->PortList)[i].Link < 4) &&
- (Nb->GetPackageLink (Node, ((*State->PortList)[i].Link + 4), Nb) == HT_LIST_MATCH_INTERNAL_LINK_2)) {
- FinalLinkState = State->HtInterface->GetIgnoreLink (Node, ((*State->PortList)[i].Link + 4), Nb->DefaultIgnoreLinkList, State);
- // Are we ignoring the internal link 2 with Power Off?
- if (FinalLinkState == POWERED_OFF) {
- // Read the regang bit in hardware.
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_HT_LINK_EXT_CONTROL0_0X170 + (4 * (*State->PortList)[i].Link));
- LibAmdPciReadBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
- // If it's already ganged, skip to the width fix up.
- if (Temp == 0) {
- // Clear EndOfChain / XmitOff on internal sublink
- Reg = Nb->MakeLinkBase (Node, ((*State->PortList)[i].Link + 4), Nb);
- Reg.Address.Register += HTHOST_LINK_CONTROL_REG;
- Temp = 0;
- State->HtFeatures->SetHtControlRegisterBits (Reg, 7, 6, &Temp, State);
-
- // Gang the link
- Nb->SetLinkRegang (Node, (*State->PortList)[i].Link, Nb);
- }
-
- // Set InLnSt = PHY_OFF in register table.
- // Set sublink 0 widths to 8 bits
- if ((*State->PortList)[i].SelWidthOut > 8) {
- (*State->PortList)[i].SelWidthOut = 8;
- }
- if ((*State->PortList)[i].SelWidthIn > 8) {
- (*State->PortList)[i].SelWidthIn = 8;
- }
- WidthOut = State->HtFeatures->ConvertWidthToBits ((*State->PortList)[i].SelWidthOut);
- WidthIn = State->HtFeatures->ConvertWidthToBits ((*State->PortList)[i].SelWidthIn);
- Temp = (WidthIn & 7) | ((WidthOut & 7) << 4);
- Reg = Nb->MakeLinkBase (Node, (*State->PortList)[i].Link, Nb);
- Reg.Address.Register += HTHOST_LINK_CONTROL_REG;
- State->HtFeatures->SetHtControlRegisterBits (Reg, 31, 24, &Temp, State);
- }
- }
- }
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbSystemFam10.h b/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbSystemFam10.h
deleted file mode 100644
index 6d2bc0294c..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbSystemFam10.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * System Tuning Family 10h specific routines
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/**
- * Set the traffic distribution register for the Links provided.
- *
- */
-VOID
-Fam10WriteTrafficDistribution (
- IN UINT32 Links01,
- IN UINT32 Links10,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Write a link pair to the link pair distribution and fixups.
- *
- */
-VOID
-Fam10WriteLinkPairDistribution (
- IN UINT8 Node,
- IN UINT8 ConnectedNode,
- IN UINT8 Pair,
- IN BOOLEAN Asymmetric,
- IN UINT8 MasterLink,
- IN UINT8 AlternateLink,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Family 10h specific tunings.
- *
- */
-VOID
-Fam10BufferOptimizations (
- IN UINT8 Node,
- IN STATE_DATA *State,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Family 10h Rev D specific tunings.
- *
- */
-VOID
-Fam10RevDBufferOptimizations (
- IN UINT8 Node,
- IN STATE_DATA *State,
- IN NORTHBRIDGE *Nb
- );
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbUtilitiesFam10.c b/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbUtilitiesFam10.c
deleted file mode 100644
index 576a6b142e..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbUtilitiesFam10.c
+++ /dev/null
@@ -1,444 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Northbridge utility routines.
- *
- * These routines are needed for support of more than one feature area.
- * Collect them in this file so build options don't remove them.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "htNb.h"
-#include "htNbCommonHardware.h"
-#include "htNbUtilitiesFam10.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_FAM10_HTNBUTILITIESFAM10_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Return the number of cores (1 based count) on Node.
- *
- * @HtNbMethod{::F_GET_NUM_CORES_ON_NODE}
- *
- * @param[in] Node the Node that will be examined
- * @param[in] Nb this northbridge
- *
- * @return the number of cores
- */
-UINT8
-Fam10GetNumCoresOnNode (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT32 Result;
- UINT32 Leveling;
- UINT32 Cores;
- UINT8 i;
- PCI_ADDR Reg;
-
- ASSERT ((Node < MAX_NODES));
- // Read CmpCap
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_NB_FUNC_03,
- REG_NB_CAPABILITY_3XE8);
-
- LibAmdPciReadBits (Reg, 13, 12, &Cores, Nb->ConfigHandle);
-
- // Support Downcoring
- Result = Cores;
- Cores++;
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_NB_FUNC_03,
- REG_NB_DOWNCORE_3X190);
- LibAmdPciReadBits (Reg, 3, 0, &Leveling, Nb->ConfigHandle);
- for (i = 0; i < Cores; i++) {
- if ((Leveling & ((UINT32) 1 << i)) != 0) {
- Result--;
- }
- }
- return (UINT8) (Result + 1);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Return the number of cores (1 based count) on Node.
- *
- * @HtNbMethod{::F_GET_NUM_CORES_ON_NODE}.
- *
- * @param[in] Node the Node that will be examined
- * @param[in] Nb this northbridge
- *
- * @return the number of cores
- */
-UINT8
-Fam10RevDGetNumCoresOnNode (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT32 Result;
- UINT32 Leveling;
- UINT32 Cores;
- UINT32 Cores2;
- UINT8 i;
- PCI_ADDR Reg;
-
- ASSERT ((Node < MAX_NODES));
- // Read CmpCap
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_NB_FUNC_03,
- REG_NB_CAPABILITY_3XE8);
-
- LibAmdPciReadBits (Reg, 13, 12, &Cores, Nb->ConfigHandle);
- LibAmdPciReadBits (Reg, 15, 15, &Cores2, Nb->ConfigHandle);
- Cores = Cores + (Cores2 << 2);
-
- // Support Downcoring
- Result = Cores;
- Cores++;
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_NB_FUNC_03,
- REG_NB_DOWNCORE_3X190);
- LibAmdPciReadBits (Reg, 5, 0, &Leveling, Nb->ConfigHandle);
- for (i = 0; i < Cores; i++) {
- if ((Leveling & ((UINT32) 1 << i)) != 0) {
- Result--;
- }
- }
- return (UINT8) (Result + 1);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get the next link for iterating over the links on a node in the correct order.
- *
- * @HtNbMethod{::F_GET_NEXT_LINK}
- *
- * Family 10h specific implementation use the Internal Link field in
- * the northbridge to prioritize internal links in the order.
- *
- * @param[in] Node The node on which to iterate links.
- * @param[in,out] Link IN: the current iteration context, OUT: the next link.
- * @param[in] Nb This Northbridge, access to config pointer.
- *
- * @retval LinkIteratorExternal The current Link is an external link.
- * @retval LinkIteratorInternal The current Link is an internal link.
- * @retval LinkIteratorEnd There is no next link (Link is back to BEGIN).
- *
- */
-LINK_ITERATOR_STATUS
-Fam10GetNextLink (
- IN UINT8 Node,
- IN OUT UINT8 *Link,
- IN NORTHBRIDGE *Nb
- )
-{
- PCI_ADDR Reg;
- UINT32 InternalLinks;
- UINT32 ExternalLinks;
- UINT32 HigherLinks;
- BOOLEAN IsInternalLink;
- LINK_ITERATOR_STATUS Status;
-
- ASSERT ((Node < MAX_NODES));
- ASSERT ((*Link < Nb->MaxLinks) || (*Link == LINK_ITERATOR_BEGIN));
- InternalLinks = 0;
- ExternalLinks = 0;
-
- // Read IntLnkRoute from the Link Initialization Status register.
- // (Note that this register field is not reserved prior to rev D, but should be zero.)
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_HT_LINK_INITIALIZATION_0X1A0);
-
- LibAmdPciReadBits (Reg, 23, 16, &InternalLinks, Nb->ConfigHandle);
- // The external links are all possible links which are not Internal
- ExternalLinks = (((1 << Nb->MaxLinks) - 1) ^ InternalLinks);
- // Can't have no possible links!
- ASSERT ((ExternalLinks != 0) || (InternalLinks != 0));
-
-
- if (*Link == LINK_ITERATOR_BEGIN) {
- // If the request is for the first link (BEGIN), get it
- if (InternalLinks != 0) {
- *Link = LibAmdBitScanForward (InternalLinks);
- Status = LinkIteratorInternal;
- } else {
- *Link = LibAmdBitScanForward (ExternalLinks);
- Status = LinkIteratorExternal;
- }
- } else {
- // If the iterator is not at the beginning, search for the next Link starting from the
- // current link.
- HigherLinks = InternalLinks & ~((1 << (*Link + 1)) - 1);
- IsInternalLink = (BOOLEAN) ((InternalLinks & (1 << *Link)) != 0);
- if (IsInternalLink && (HigherLinks != 0)) {
- // We are still on internal links and there are more to do.
- *Link = LibAmdBitScanForward (HigherLinks);
- Status = LinkIteratorInternal;
- } else {
- if (IsInternalLink) {
- // We are transitioning now from internal to external, so get the first external link
- HigherLinks = ExternalLinks;
- } else {
- // We are already iterating over external links, so get the next one
- HigherLinks = ExternalLinks & ~((1 << (*Link + 1)) - 1);
- }
- if (HigherLinks != 0) {
- *Link = LibAmdBitScanForward (HigherLinks);
- Status = LinkIteratorExternal;
- } else {
- // The end of all links
- *Link = LINK_ITERATOR_BEGIN;
- Status = LinkIteratorEnd;
- }
- }
- }
- return Status;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get Info about Module Type of this northbridge
- *
- * @HtNbMethod{::F_GET_MODULE_INFO}
- *
- * Provide the Processor module type, single or multi, and the node's module id.
- *
- * @param[in] Node the Node
- * @param[out] ModuleType 0 for Single, 1 for Multi
- * @param[out] Module The module number of this node (0 if Single)
- * @param[in] Nb this northbridge
- *
- */
-VOID
-Fam10GetModuleInfo (
- IN UINT8 Node,
- OUT UINT8 *ModuleType,
- OUT UINT8 *Module,
- IN NORTHBRIDGE *Nb
- )
-{
- PCI_ADDR Reg;
- UINT32 MultNodeCpu;
- UINT32 IntNodeNum;
-
- ASSERT (Node < MAX_NODES);
-
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_NB_FUNC_03,
- REG_NB_CAPABILITY_3XE8);
- LibAmdPciReadBits (Reg, 29, 29, &MultNodeCpu, Nb->ConfigHandle);
- LibAmdPciReadBits (Reg, 31, 30, &IntNodeNum, Nb->ConfigHandle);
-
- *ModuleType = (UINT8) MultNodeCpu;
- *Module = (UINT8) IntNodeNum;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register.
- *
- * @HtNbMethod{::F_GET_SOCKET}
- *
- * The hardware socket naming method is not available for Family 10h prior to rev D.
- *
- * @param[in] Node The node for which we want the socket id.
- * @param[in] TempNode The temporary node id route where the node can be accessed.
- * @param[in] Nb Our Northbridge.
- *
- * @return The Socket Id
- */
-UINT8
-Fam10GetSocket (
- IN UINT8 Node,
- IN UINT8 TempNode,
- IN NORTHBRIDGE *Nb
- )
-{
- ASSERT ((Node < MAX_NODES));
- ASSERT (TempNode < MAX_NODES);
- ASSERT (Nb != NULL);
- return (Node);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register.
- *
- * @HtNbMethod{::F_GET_SOCKET}
- *
- * The Socket Id is strapped to the Sbi Control Register, F3X1E4[6:4]SbiAddr.
- *
- * @param[in] Node The node for which we want the socket id.
- * @param[in] TempNode The temporary node id route where the node can be accessed.
- * @param[in] Nb Our Northbridge.
- *
- * @return The Socket Id
- */
-UINT8
-Fam10RevDGetSocket (
- IN UINT8 Node,
- IN UINT8 TempNode,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT32 Socket;
- PCI_ADDR Reg;
-
- ASSERT ((TempNode < MAX_NODES));
- ASSERT ((Node < MAX_NODES));
- // Read SbiAddr
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (TempNode),
- MakePciBusFromNode (TempNode),
- MakePciDeviceFromNode (TempNode),
- CPU_NB_FUNC_03,
- REG_NB_SBI_CONTROL_3X1E4);
- LibAmdPciReadBits (Reg, 6, 4, &Socket, Nb->ConfigHandle);
- return ((UINT8) Socket);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Post info to AP cores via a mailbox.
- *
- * @HtNbMethod{::F_POST_MAILBOX}
- *
- * Use the link MCA counter register as a PCI -> MSR mailbox, for info such as node id,
- * and module info.
- *
- * @param[in] Node the Node
- * @param[in] ApMailboxes The info to post
- * @param[in] Nb this northbridge
- *
- */
-VOID
-Fam10PostMailbox (
- IN UINT8 Node,
- IN AP_MAILBOXES ApMailboxes,
- IN NORTHBRIDGE *Nb
- )
-{
- PCI_ADDR Reg;
-
- ASSERT (Node < MAX_NODES);
-
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_NB_FUNC_03,
- REG_NB_MCA_LINK_THRESHOLD_3X168);
- LibAmdPciWriteBits (Reg, 11, 0, &ApMailboxes.ApMailInfo.Info, Nb->ConfigHandle);
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_NB_FUNC_03,
- REG_NB_MCA_L3_THRESHOLD_3X170);
- LibAmdPciWriteBits (Reg, 11, 0, &ApMailboxes.ApMailExtInfo.Info, Nb->ConfigHandle);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Retrieve info from a node's mailbox.
- *
- * @HtNbMethod{::F_RETRIEVE_MAILBOX}
- *
- * Use the link MCA counter register as a PCI -> MSR mailbox, for info such as node id,
- * and module info.
- *
- * @param[in] Node the Node
- * @param[in] Nb this northbridge
- *
- * @return The ap mailbox info
- *
- */
-AP_MAIL_INFO
-Fam10RetrieveMailbox (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- )
-{
- PCI_ADDR Reg;
- AP_MAIL_INFO ApMailInfo;
-
- ASSERT (Node < MAX_NODES);
-
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_NB_FUNC_03,
- REG_NB_MCA_LINK_THRESHOLD_3X168);
- LibAmdPciReadBits (Reg, 11, 0, &ApMailInfo.Info, Nb->ConfigHandle);
- return ApMailInfo;
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbUtilitiesFam10.h b/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbUtilitiesFam10.h
deleted file mode 100644
index 8de7443772..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Fam10/htNbUtilitiesFam10.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Northbridge utility routines.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/**
- * Return the number of cores (1 based count) on Node.
- *
- */
-UINT8
-Fam10GetNumCoresOnNode (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Return the number of cores (1 based count) on Node.
- *
- */
-UINT8
-Fam10RevDGetNumCoresOnNode (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Get the next link for iterating over the links on a node in the correct order.
- *
- */
-LINK_ITERATOR_STATUS
-Fam10GetNextLink (
- IN UINT8 Node,
- IN OUT UINT8 *Link,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Get Info about Module Type of this northbridge
- *
- */
-VOID
-Fam10GetModuleInfo (
- IN UINT8 Node,
- OUT UINT8 *ModuleType,
- OUT UINT8 *Module,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register.
- *
- */
-UINT8
-Fam10GetSocket (
- IN UINT8 Node,
- IN UINT8 TempNode,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register.
- *
- */
-UINT8
-Fam10RevDGetSocket (
- IN UINT8 Node,
- IN UINT8 TempNode,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Post info to AP cores via a mailbox.
- *
- */
-VOID
-Fam10PostMailbox (
- IN UINT8 Node,
- IN AP_MAILBOXES ApMailboxes,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Retrieve info from a node's mailbox.
- *
- */
-AP_MAIL_INFO
-Fam10RetrieveMailbox (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- );
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatDynamicDiscovery.c b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatDynamicDiscovery.c
deleted file mode 100644
index d7b77aa27a..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatDynamicDiscovery.c
+++ /dev/null
@@ -1,782 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Coherent Discovery Routines.
- *
- * Contains routines for discovery, along with Temporary routing.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "htInterface.h"
-#include "htNotify.h"
-#include "htNb.h"
-#include "htFeatDynamicDiscovery.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_FEATURES_HTFEATDYNAMICDISCOVERY_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define LOGICAL_PROCESSOR_NONE 0xFF
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-/**
- * Status result from exploring for a new node on a link.
- */
-typedef enum {
- ExploreNodeStatusNew, ///< A new node was discovered
- ExploreNodeStatusGood, ///< A new link to an already known node was discovered
- ExploreNodeStatusStop, ///< Discovery must halt now.
- ExploreNodeStatusIgnore, ///< A new node was ignored on purpose.
- ExploreNodeStatusMax ///< Use for bounds check and limit only
-} EXPLORE_NODE_STATUS;
-
-/**
- * Save all the information needed about a node at its discovery.
- *
- * When we can access the node at a known temporary route, read everything needed
- * to do node to socket mapping, post to ap mailbox at later times.
- */
-typedef struct {
- UINT8 LogicalProcessor; ///< Independent of Node,Socket group nodes into logical
- ///< processors based on discovery.
- UINT8 CurrentNode; ///< The node from which discovery occurred.
- UINT8 CurrentLink; ///< The link on that node which we explored.
- UINT8 PackageLink; ///< The package level link corresponding to CurrentLink.
- UINT8 CurrentModuleType; ///< The current node's module type, Single or Multiple.
- UINT8 CurrentModule; ///< This current node's module id.
- UINT8 HardwareSocket; ///< Save the hardware socket strap (for hardware socket method).
- UINT8 NewModuleType; ///< The new node's module type, Single or Multiple.
- UINT8 NewModule; ///< The new node's module id.
-} NEW_NODE_SAVED_INFO_ITEM;
-
-/**
- * A "no info" initializer for saved new node info.
- */
-STATIC CONST NEW_NODE_SAVED_INFO_ITEM ROMDATA NoInfoSavedYet =
-{
- LOGICAL_PROCESSOR_NONE, 0, 0, 0, 0, 0, 0, 0
-};
-
-/**
- * A list of all the new node info, indexed by each new node's nodeid.
- */
-typedef NEW_NODE_SAVED_INFO_ITEM (*NEW_NODE_SAVED_INFO_LIST) [MAX_NODES];
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/***************************************************************************
- *** GENERIC HYPERTRANSPORT DISCOVERY CODE ***
- ***************************************************************************/
-
-/*-----------------------------------------------------------------------------------*/
-/**
- * Ensure a request / response route from target Node to bsp.
- *
- * Since target Node is always a predecessor of actual target Node, each Node gets a
- * route to actual target on the Link that goes to target. The routing produced by
- * this routine is adequate for config access during discovery, but NOT for coherency.
- *
- * @param[in] TargetNode the path to actual target goes through target
- * @param[in] ActualTarget the ultimate target being routed to
- * @param[in] State our global state, port config info
- *
- */
-VOID
-STATIC
-routeFromBSP (
- IN UINT8 TargetNode,
- IN UINT8 ActualTarget,
- IN STATE_DATA *State
- )
-{
- UINT8 PredecessorNode;
- UINT8 PredecessorLink;
- UINT8 CurrentPair;
-
- if (TargetNode == 0) {
- return; // BSP has no predecessor, stop
- }
-
- // Search for the Link that connects TargetNode to its predecessor
- CurrentPair = 0;
- while ((*State->PortList)[CurrentPair*2 + 1].NodeID != TargetNode) {
- CurrentPair++;
- ASSERT (CurrentPair < State->TotalLinks);
- }
-
- PredecessorNode = (*State->PortList)[ (CurrentPair * 2)].NodeID;
- PredecessorLink = (*State->PortList)[ (CurrentPair * 2)].Link;
-
- // Recursively call self to ensure the route from the BSP to the Predecessor
- // Node is established
- routeFromBSP (PredecessorNode, ActualTarget, State);
-
- State->Nb->WriteRoutingTable (PredecessorNode, ActualTarget, PredecessorLink, State->Nb);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Test Compatibility of a new node, and handle failure.
- *
- * Make the compatibility test call for the northbridge.
- * If the new node is incompatible, force 1P. Notify the event.
- * Additionally, invoke the northbridge stop link method, to
- * implement isolation of the BSP from any incompatible node.
- *
- * @param[in] CurrentNode The node we are exploring from
- * @param[in] CurrentLink The Link on that node to explore.
- * @param[in] State Access to Northbridge interface.
- *
- * @retval TRUE Check is Ok
- * @retval FALSE Check failed and is handled
- */
-BOOLEAN
-STATIC
-CheckCompatible (
- IN UINT8 CurrentNode,
- IN UINT8 CurrentLink,
- IN STATE_DATA *State
- )
-{
- UINT8 NodeToKill;
- BOOLEAN Result;
-
- Result = TRUE;
-
- // Check the northbridge of the Node we just found, to make sure it is compatible
- // before doing anything else to it.
- //
- if (State->Nb->IsIllegalTypeMix ((CurrentNode + 1), State->Nb)) {
- IDS_ERROR_TRAP;
-
- // Notify BIOS of event
- NotifyFatalCohProcessorTypeMix (
- CurrentNode,
- CurrentLink,
- State->NodesDiscovered,
- State
- );
-
- // If Node is not compatible, force boot to 1P
- // If they are not compatible stop cHT init and:
- // 1. Disable all cHT Links on the BSP
- // 2. Configure the BSP routing tables as a UP.
- // 3. Notify main BIOS.
- //
- State->NodesDiscovered = 0;
- State->TotalLinks = 0;
- // Abandon our coherent Link data structure. At this point there may
- // be coherent Links on the BSP that are not yet in the portList, and
- // we have to turn them off anyway. So depend on the hardware to tell us.
- //
- for (CurrentLink = 0; CurrentLink < State->Nb->MaxLinks; CurrentLink++) {
- // Stop all Links which are connected, coherent, and ready
- if (State->Nb->VerifyLinkIsCoherent (0, CurrentLink, State->Nb)) {
- State->Nb->StopLink (0, CurrentLink, State, State->Nb);
- }
- }
-
- for (NodeToKill = 0; NodeToKill < MAX_NODES; NodeToKill++) {
- State->Nb->WriteFullRoutingTable (0, NodeToKill, ROUTE_TO_SELF, ROUTE_TO_SELF, 0, State->Nb);
- }
-
- State->HtInterface->CleanMapsAfterError (State);
-
- // End Coherent Discovery
- Result = FALSE;
- }
- return Result;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Check the system MP capability with a new node and handle any failure.
- *
- * Invoke the northbridge MP capability check. If it fails, notify the event and force
- * 1P. Should not need to stop links on the BSP.
- *
- * @param[in] CurrentNode The node we are exploring from
- * @param[in] CurrentLink The Link on that node to explore.
- * @param[in] State Access to Northbridge interface.
- *
- * @retval TRUE Check is Ok
- * @retval FALSE Check Failed and is handled
- */
-BOOLEAN
-STATIC
-CheckCapable (
- IN UINT8 CurrentNode,
- IN UINT8 CurrentLink,
- IN STATE_DATA *State
- )
-{
- UINT8 NodeToKill;
- BOOLEAN Result;
-
- Result = TRUE;
-
- // Check the capability of northbridges against the currently known configuration
- if (State->Nb->IsExceededCapable ((CurrentNode + 1), State, State->Nb)) {
- IDS_ERROR_TRAP;
- // Notify BIOS of event
- NotifyFatalCohMpCapMismatch (
- CurrentNode,
- CurrentLink,
- State->SysMpCap,
- State->NodesDiscovered,
- State
- );
-
- State->NodesDiscovered = 0;
- State->TotalLinks = 0;
-
- for (NodeToKill = 0; NodeToKill < MAX_NODES; NodeToKill++) {
- State->Nb->WriteFullRoutingTable (0, NodeToKill, ROUTE_TO_SELF, ROUTE_TO_SELF, 0, State->Nb);
- }
-
- State->HtInterface->CleanMapsAfterError (State);
-
- // End Coherent Discovery
- Result = FALSE;
- }
- return Result;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Make all the tests needed to determine if a link should be added to the system data structure.
- *
- * The link should be added to the system data structure if it is:
- * - not being Ignored on this boot
- * - not having a hard failure
- * - coherent and connected
- * - not already in the system data structure
- * - not subject to some special handling case.
- * .
- *
- * @param[in] CurrentNode The node we are exploring from
- * @param[in] CurrentLink The Link on that node to explore.
- * @param[in] State Access to Northbridge interface.
- *
- * @retval FALSE This link should not be added.
- * @retval TRUE This link should explored and added to the system.
- */
-BOOLEAN
-STATIC
-IsLinkToAdd (
- IN UINT8 CurrentNode,
- IN UINT8 CurrentLink,
- IN STATE_DATA *State
- )
-{
- BOOLEAN Linkfound;
- UINTN Port;
- FINAL_LINK_STATE FinalLinkState;
- BOOLEAN Result;
-
- Result = FALSE;
-
- FinalLinkState = State->HtInterface->GetIgnoreLink (CurrentNode, CurrentLink, State->Nb->DefaultIgnoreLinkList, State);
- if ((FinalLinkState != MATCHED) && (FinalLinkState != POWERED_OFF)) {
- if (!State->Nb->ReadTrueLinkFailStatus (CurrentNode, CurrentLink, State, State->Nb)) {
- // Make sure that the Link is connected, coherent, and ready
- if (State->Nb->VerifyLinkIsCoherent (CurrentNode, CurrentLink, State->Nb)) {
- // Test to see if the CurrentLink has already been explored
- Linkfound = FALSE;
- for (Port = 0; Port < State->TotalLinks; Port++) {
- if ((((*State->PortList)[ (Port * 2 + 1)].NodeID == CurrentNode) &&
- ((*State->PortList)[ (Port * 2 + 1)].Link == CurrentLink)) ||
- (((*State->PortList)[ (Port * 2)].NodeID == CurrentNode) &&
- ((*State->PortList)[ (Port * 2)].Link == CurrentLink))) {
- Linkfound = TRUE;
- break;
- }
- }
- if (!Linkfound) {
- if (!State->Nb->HandleSpecialLinkCase (CurrentNode, CurrentLink, State, State->Nb)) {
- Result = TRUE;
- }
- }
- }
- }
- } else {
- if (FinalLinkState == POWERED_OFF) {
- State->Nb->StopLink (CurrentNode, CurrentLink, State, State->Nb);
- }
- }
- return Result;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Explore for a new node over a link, handling whatever is found.
- *
- * Open a temporary route over a link on the current node.
- * Make checks for compatibility and capability in the proper sequence.
- * If the node found is new, set a token to it, so it will be recognized in the
- * future, and notify an event for finding a new node.
- * If the node is already found (token is set), just return status.
- *
- * @param[in] CurrentNode The node we are exploring from
- * @param[in] CurrentLink The Link on that node to explore.
- * @param[in] LogicalProcessor The processor to update in the maps.
- * @param[in,out] NewNodeSavedInfo The saved info for nodes in that processor.
- * @param[in] State Access to Northbridge interface.
- *
- * @retval ExploreNodeStatusNew A new node was found
- * @retval ExploreNodeStatusGood This is a good link to an already known node
- * @retval ExploreNodeStatusStop Stop Coherent Discovery
- */
-EXPLORE_NODE_STATUS
-STATIC
-ExploreNode (
- IN UINT8 CurrentNode,
- IN UINT8 CurrentLink,
- IN UINT8 LogicalProcessor,
- IN OUT NEW_NODE_SAVED_INFO_LIST NewNodeSavedInfo,
- IN STATE_DATA *State
- )
-{
- UINT8 Token;
- EXPLORE_NODE_STATUS Status;
-
- // Modify CurrentNode's routing table to use CurrentLink to send
- // traffic to CurrentNode + 1
- //
- State->Nb->WriteRoutingTable (CurrentNode, (CurrentNode + 1), CurrentLink, State->Nb);
- if (!State->Nb->HandleSpecialNodeCase ((CurrentNode + 1), CurrentLink, State, State->Nb)) {
- if (CheckCompatible (CurrentNode, CurrentLink, State)) {
- // Read Token from Current + 1
- Token = State->Nb->ReadToken ((CurrentNode + 1), State->Nb);
- ASSERT (Token <= State->NodesDiscovered);
- if (Token == 0) {
- State->NodesDiscovered++;
- ASSERT (State->NodesDiscovered < MAX_NODES);
- if (CheckCapable (CurrentNode, CurrentLink, State)) {
- Token = State->NodesDiscovered;
- State->Nb->WriteToken ((CurrentNode + 1), Token, State->Nb);
- // Fill in Saved New Node info for the discovered node.
- // We do this so we don't have to keep a temporary route open to it.
- // So we save everything that might be needed to set the socket and node
- // maps for either the software or hardware method.
- //
- (*NewNodeSavedInfo)[Token].LogicalProcessor = LogicalProcessor;
- (*NewNodeSavedInfo)[Token].CurrentNode = CurrentNode;
- (*NewNodeSavedInfo)[Token].CurrentLink = CurrentLink;
- (*NewNodeSavedInfo)[Token].PackageLink = State->Nb->GetPackageLink (CurrentNode, CurrentLink, State->Nb);
- (*NewNodeSavedInfo)[Token].HardwareSocket = State->Nb->GetSocket (Token, (CurrentNode + 1), State->Nb);
- State->Nb->GetModuleInfo (
- CurrentNode,
- &((*NewNodeSavedInfo)[Token].CurrentModuleType),
- &((*NewNodeSavedInfo)[Token].CurrentModule),
- State->Nb
- );
- State->Nb->GetModuleInfo (
- (CurrentNode + 1),
- &((*NewNodeSavedInfo)[Token].NewModuleType),
- &((*NewNodeSavedInfo)[Token].NewModule),
- State->Nb
- );
-
- // Notify BIOS with info
- NotifyInfoCohNodeDiscovered (
- CurrentNode,
- CurrentLink,
- Token,
- (CurrentNode + 1),
- State
- );
- Status = ExploreNodeStatusNew;
- } else {
- // Failed Capable
- Status = ExploreNodeStatusStop;
- }
- } else {
- // Not a new node, token already set
- Status = ExploreNodeStatusGood;
- }
- } else {
- // Failed Compatible
- Status = ExploreNodeStatusStop;
- }
- } else {
- // Ignore this node
- Status = ExploreNodeStatusIgnore;
- }
-
- return Status;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Process all the saved new node info for the current processor.
- *
- * When all nodes in the processor have been discovered, we can process all the saved
- * info about the nodes. We add each node to the socket and node maps.
- *
- * @param[in] LogicalProcessor The processor to update in the maps.
- * @param[in] NewNodeSavedInfo The saved info for nodes in that processor.
- * @param[in] State Our system representation.
- */
-VOID
-STATIC
-ProcessSavedNodeInfo (
- IN UINT8 LogicalProcessor,
- IN NEW_NODE_SAVED_INFO_LIST NewNodeSavedInfo,
- IN STATE_DATA *State
- )
-{
- UINT8 NewNode;
- UINT8 HardwareSocket;
-
- // Can't have more processors than nodes, just more (or equal) nodes than processors.
- ASSERT (LogicalProcessor <= (State->NodesDiscovered));
- HardwareSocket = 0xFF;
- // Find the Hardware Socket value to use (if we are using the hardware socket naming method).
- // The new nodes are the ones in this processor, so find the one that is module 0.
- for (NewNode = 0; NewNode < (State->NodesDiscovered + 1); NewNode++) {
- if (((*NewNodeSavedInfo)[NewNode].LogicalProcessor == LogicalProcessor) &&
- ((*NewNodeSavedInfo)[NewNode].NewModule == 0)) {
- HardwareSocket = (*NewNodeSavedInfo)[NewNode].HardwareSocket;
- break;
- }
- }
- // We must have found a result, however, the hardware socket value doesn't have to be correct
- // unless we are using the hardware socket naming method. Northbridge code should return the
- // node number for the hardware socket if hardware socket strapping is not supported (i.e. no sbi).
- ASSERT (HardwareSocket != 0xFF);
-
- // Set the node to socket maps for this processor. Node zero is always handled specially,
- // so skip it in this loop.
- for (NewNode = 1; NewNode < (State->NodesDiscovered + 1); NewNode++) {
- if ((*NewNodeSavedInfo)[NewNode].LogicalProcessor == LogicalProcessor) {
- // For the currently discovered logical processor, update node to socket
- // map for all the processor's nodes.
- State->HtInterface->SetNodeToSocketMap (
- (*NewNodeSavedInfo)[NewNode].CurrentNode,
- (*NewNodeSavedInfo)[NewNode].CurrentModule,
- (*NewNodeSavedInfo)[NewNode].PackageLink,
- NewNode,
- HardwareSocket,
- (*NewNodeSavedInfo)[NewNode].NewModule,
- State);
- }
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Create and add a new link to the system data structure.
- *
- * Add the two port list data structures, source first, initializing
- * the two node ids and the link values. The node id of the remote
- * node is its token value. Also, update the adjacency matrix and
- * node degree table.
- *
- * @param[in] CurrentNode The node we are exploring from
- * @param[in] CurrentLink The Link on that node to explore.
- * @param[in] TempRoute The temporary node route that goes over that link.
- * @param[in] State Access to Northbridge interface.
- *
- */
-VOID
-STATIC
-AddLinkToSystem (
- IN UINT8 CurrentNode,
- IN UINT8 CurrentLink,
- IN UINT8 TempRoute,
- IN STATE_DATA *State
- )
-{
- UINT8 Token;
-
- ASSERT (State->TotalLinks < MAX_PLATFORM_LINKS);
-
- Token = State->Nb->ReadToken (TempRoute, State->Nb);
-
- (*State->PortList)[State->TotalLinks * 2].Type = PORTLIST_TYPE_CPU;
- (*State->PortList)[State->TotalLinks * 2].Link = CurrentLink;
- (*State->PortList)[State->TotalLinks * 2].NodeID = CurrentNode;
-
- (*State->PortList)[State->TotalLinks * 2 + 1].Type = PORTLIST_TYPE_CPU;
- (*State->PortList)[State->TotalLinks * 2 + 1].Link = State->Nb->ReadDefaultLink (TempRoute, State->Nb);
- (*State->PortList)[State->TotalLinks * 2 + 1].NodeID = Token;
-
- State->TotalLinks++;
-
- if ( !State->Fabric->SysMatrix[CurrentNode][Token] ) {
- State->Fabric->SysDegree[CurrentNode]++;
- State->Fabric->SysDegree[Token]++;
- State->Fabric->SysMatrix[CurrentNode][Token] = TRUE;
- State->Fabric->SysMatrix[Token][CurrentNode] = TRUE;
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Start discovery from a new node.
- *
- * If the node is not the BSP, establish a route between the node and the
- * BSP for request/response.
- * Set the node id, and enable routing on this node. This gives us control
- * on that node to isolate links, by specifying each link in turn as the route
- * to a possible new node.
- *
- * @param[in] CurrentNode The node we are exploring from
- * @param[in] State Access to Northbridge interface.
- *
- */
-VOID
-STATIC
-StartFromANewNode (
- IN UINT8 CurrentNode,
- IN STATE_DATA *State
- )
-{
- if (CurrentNode != 0) {
- // Set path from BSP to CurrentNode
- routeFromBSP (CurrentNode, CurrentNode, State);
-
- // Set path from BSP to CurrentNode for CurrentNode + 1 if
- // CurrentNode + 1 != MAX_NODES
- //
- if ((CurrentNode + 1) != MAX_NODES) {
- routeFromBSP (CurrentNode, (CurrentNode + 1), State);
- }
-
- // Configure CurrentNode to route traffic to the BSP through its
- // default Link
- //
- State->Nb->WriteRoutingTable (CurrentNode, 0, State->Nb->ReadDefaultLink (CurrentNode, State->Nb), State->Nb);
- }
-
- // Set CurrentNode's NodeID field to CurrentNode
- State->Nb->WriteNodeID (CurrentNode, CurrentNode, State->Nb);
-
- // Enable routing tables on CurrentNode
- State->Nb->EnableRoutingTables (CurrentNode, State->Nb);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Back up from exploring a one-deep internal node.
- *
- * When a newly discovered node has internal package links to another
- * node in the same processor, discovery moves to that node to do the
- * internal links. Afterwards, this routine provides recovery from that.
- * The node needs to respond again using deflnk rather than routing, so
- * that connections from other nodes to that one can be identified.
- *
- * @param[in] CurrentNode The node we are exploring from
- * @param[in] State Access to Northbridge interface.
- *
- */
-VOID
-STATIC
-BackUpFromANode (
- IN UINT8 CurrentNode,
- IN STATE_DATA *State
- )
-{
- if (CurrentNode != 0) {
- // Disable routing tables on CurrentNode
- State->Nb->DisableRoutingTables (CurrentNode, State->Nb);
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Dynamically Discover all coherent devices in the system.
- *
- * @HtFeatMethod{::F_COHERENT_DISCOVERY}
- *
- * Initialize some basics like Node IDs and total Nodes found in the
- * process. As we go we also build a representation of the discovered
- * system which we will use later to program the routing tables.
- * During this step, the routing is via default Link back to BSP and
- * to each new Node on the Link it was discovered on (no coherency is
- * active yet).
- *
- * In the case of multiple nodes per processor, do a one deep exploration of internal links
- * to ensure those node pairs are always numbered n, n + 1.
- *
- * @param[in,out] State our global state
- *
- */
-VOID
-CoherentDiscovery (
- IN OUT STATE_DATA *State
- )
-{
- UINT8 CurrentNode;
- UINT8 OneDeepNode;
- UINT8 OneDeepLink;
- UINT8 CurrentLink;
- UINT8 LogicalProcessor;
- EXPLORE_NODE_STATUS ExplorationStatus;
- LINK_ITERATOR_STATUS LinkIteratorStatus;
- NEW_NODE_SAVED_INFO_ITEM NewNodeSavedInfoItems [MAX_NODES];
- NEW_NODE_SAVED_INFO_LIST NewNodeSavedInfo;
-
- // Initially no info exists for any node, but the BSP is part of logical processor zero.
- for (CurrentNode = 0; CurrentNode < MAX_NODES; CurrentNode++) {
- NewNodeSavedInfoItems [CurrentNode] = NoInfoSavedYet;
- }
- NewNodeSavedInfoItems[0].LogicalProcessor = 0;
- NewNodeSavedInfoItems[0].HardwareSocket = State->Nb->GetSocket (0, 0, State->Nb);
- State->Nb->GetModuleInfo (0, &NewNodeSavedInfoItems[0].NewModuleType, &NewNodeSavedInfoItems[0].NewModule, State->Nb);
- NewNodeSavedInfo = (NEW_NODE_SAVED_INFO_LIST) NewNodeSavedInfoItems;
-
- CurrentNode = 0;
- CurrentLink = LINK_ITERATOR_BEGIN;
- LogicalProcessor = 0;
- // An initial status, for node zero if you will.
- ExplorationStatus = ExploreNodeStatusGood;
-
- //
- // Entries are always added in pairs, the even indices are the 'source'
- // side closest to the BSP, the odd indices are the 'destination' side
- //
-
- while ((CurrentNode <= State->NodesDiscovered) && (ExplorationStatus != ExploreNodeStatusStop)) {
- StartFromANewNode (CurrentNode, State);
-
- //
- // Explore all internal links
- //
- LinkIteratorStatus = State->Nb->GetNextLink (CurrentNode, &CurrentLink, State->Nb);
-
- while ((LinkIteratorStatus == LinkIteratorInternal) &&
- (ExplorationStatus != ExploreNodeStatusStop)) {
- if (IsLinkToAdd (CurrentNode, CurrentLink, State)) {
- ExplorationStatus = ExploreNode (CurrentNode, CurrentLink, LogicalProcessor, NewNodeSavedInfo, State);
- if ((ExplorationStatus == ExploreNodeStatusGood) ||
- (ExplorationStatus == ExploreNodeStatusNew)) {
- AddLinkToSystem (CurrentNode, CurrentLink, (CurrentNode + 1), State);
- }
- }
- LinkIteratorStatus = State->Nb->GetNextLink (CurrentNode, &CurrentLink, State->Nb);
- }
- if (CurrentNode == 0) {
- // The BSP processor is completely discovered now.
- ProcessSavedNodeInfo (LogicalProcessor, NewNodeSavedInfo, State);
- LogicalProcessor++;
- }
-
- //
- // Explore all the external links from this node.
- //
-
- // Starting this iteration using the link that we last got in the iteration above.
- while ((LinkIteratorStatus == LinkIteratorExternal) &&
- (ExplorationStatus != ExploreNodeStatusStop)) {
- if (IsLinkToAdd (CurrentNode, CurrentLink, State)) {
- ExplorationStatus = ExploreNode (CurrentNode, CurrentLink, LogicalProcessor, NewNodeSavedInfo, State);
- if (ExplorationStatus == ExploreNodeStatusNew) {
- AddLinkToSystem (CurrentNode, CurrentLink, (CurrentNode + 1), State);
- // If this is a new node, we need to explore to its internal mate, if any.
- // This allows us to keep internal node pairs as ids n, n+1
- // We use special link and node variables so we can keep our context.
- OneDeepLink = 0xFF;
- OneDeepNode = State->Nb->ReadToken ((CurrentNode + 1), State->Nb);
- StartFromANewNode (OneDeepNode, State);
- LinkIteratorStatus = State->Nb->GetNextLink (OneDeepNode, &OneDeepLink, State->Nb);
- while ((LinkIteratorStatus == LinkIteratorInternal) &&
- (ExplorationStatus != ExploreNodeStatusStop)) {
- if (IsLinkToAdd (OneDeepNode, OneDeepLink, State)) {
- ExplorationStatus = ExploreNode (OneDeepNode, OneDeepLink, LogicalProcessor, NewNodeSavedInfo, State);
- if ((ExplorationStatus == ExploreNodeStatusGood) ||
- (ExplorationStatus == ExploreNodeStatusNew)) {
- AddLinkToSystem (OneDeepNode, OneDeepLink, (OneDeepNode + 1), State);
- }
- }
- LinkIteratorStatus = State->Nb->GetNextLink (OneDeepNode, &OneDeepLink, State->Nb);
- }
- // Since we completed all the node's internal links, we found all the nodes in that processor.
- ProcessSavedNodeInfo (LogicalProcessor, NewNodeSavedInfo, State);
- LogicalProcessor++;
- // Restore node to discoverable state. Otherwise you can't tell what links it is connected on.
- BackUpFromANode (OneDeepNode, State);
- } else {
- if (ExplorationStatus == ExploreNodeStatusGood) {
- AddLinkToSystem (CurrentNode, CurrentLink, (CurrentNode + 1), State);
- }
- }
- }
- LinkIteratorStatus = State->Nb->GetNextLink (CurrentNode, &CurrentLink, State->Nb);
- }
- CurrentNode++;
- }
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatDynamicDiscovery.h b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatDynamicDiscovery.h
deleted file mode 100644
index 926028cd7b..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatDynamicDiscovery.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Coherent Discovery Interface.
- *
- * Contains interface to the coherent discovery feature.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-#ifndef _HT_FEAT_DYNAMIC_DISCOVERY_H_
-#define _HT_FEAT_DYNAMIC_DISCOVERY_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-/**
- * Dynamically Discover all coherent devices in the system.
- *
- */
-VOID
-CoherentDiscovery (
- IN OUT STATE_DATA *State
- );
-
-#endif /* _HT_FEAT_DYNAMIC_DISCOVERY_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatGanging.c b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatGanging.c
deleted file mode 100644
index 7109374809..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatGanging.c
+++ /dev/null
@@ -1,217 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Routines for re-ganging Links.
- *
- * Implement the reganging feature.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "htInterface.h"
-#include "htNb.h"
-#include "htFeatGanging.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_FEATURES_HTFEATGANGING_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/***************************************************************************
- *** Link Optimization ***
- ***************************************************************************/
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Test the subLinks of a Link to see if they qualify to be reganged.
- *
- * @HtFeatMethod{::F_REGANG_LINKS}
- *
- * If they do, update the port list data to indicate that this should be done.
- * @note no actual hardware state is changed in this routine.
- *
- * @param[in,out] State Our global state
- */
-VOID
-RegangLinks (
- IN OUT STATE_DATA *State
- )
-{
- FINAL_LINK_STATE FinalLinkState;
- UINT8 i;
- UINT8 j;
- for (i = 0; i < (State->TotalLinks * 2); i += 2) {
- // Data validation
- ASSERT ((*State->PortList)[i].Type < 2 && (*State->PortList)[i].Link < State->Nb->MaxLinks);
- ASSERT ((*State->PortList)[i + 1].Type < 2 && (*State->PortList)[i + 1].Link < State->Nb->MaxLinks);
-
- // Regang is false unless we pass all conditions below
- (*State->PortList)[i].SelRegang = FALSE;
- (*State->PortList)[i + 1].SelRegang = FALSE;
-
- // Only process cpu to cpu Links
- if ( ((*State->PortList)[i].Type != PORTLIST_TYPE_CPU) ||
- ((*State->PortList)[i + 1].Type != PORTLIST_TYPE_CPU)) {
- continue;
- }
-
- for (j = i + 2; j < State->TotalLinks*2; j += 2) {
- // Only process cpu to cpu Links
- if ( ((*State->PortList)[j].Type != PORTLIST_TYPE_CPU) ||
- ((*State->PortList)[j + 1].Type != PORTLIST_TYPE_CPU) ) {
- continue;
- }
-
- // Links must be from the same source
- if ((*State->PortList)[i].NodeID != (*State->PortList)[j].NodeID) {
- continue;
- }
-
- // Link must be to the same target
- if ((*State->PortList)[i + 1].NodeID != (*State->PortList)[j + 1].NodeID) {
- continue;
- }
-
- // Ensure same source base port
- if (((*State->PortList)[i].Link & 3) != ((*State->PortList)[j].Link & 3)) {
- continue;
- }
-
- // Ensure same destination base port
- if (((*State->PortList)[i + 1].Link & 3) != ((*State->PortList)[j + 1].Link & 3)) {
- continue;
- }
-
- // Ensure subLink0 routes to subLink0
- if (((*State->PortList)[i].Link & 4) != ((*State->PortList)[i + 1].Link & 4)) {
- continue;
- }
-
- // (therefore subLink1 routes to subLink1)
- ASSERT (((*State->PortList)[j].Link & 4) == ((*State->PortList)[j + 1].Link & 4));
-
- FinalLinkState = State->HtInterface->GetSkipRegang ((*State->PortList)[i].NodeID,
- (*State->PortList)[i].Link & 0x03,
- (*State->PortList)[i + 1].NodeID,
- (*State->PortList)[i + 1].Link & 0x03,
- State);
- if (FinalLinkState == MATCHED) {
- continue;
- } else if (FinalLinkState == POWERED_OFF) {
- // StopLink will be done on the sublink 1, thus OR in 4 to the link to ensure it.
- State->Nb->StopLink ((*State->PortList)[i].NodeID, ((*State->PortList)[i].Link | 4), State, State->Nb);
- State->Nb->StopLink ((*State->PortList)[i + 1].NodeID, ((*State->PortList)[i + 1].Link | 4), State, State->Nb);
- }
-
- //
- // Create a ganged portlist entry for the two regang-able subLinks.
- //
- // All info will be that of subLink zero.
- // (If Link discovery order was other than ascending, fix the .Pointer field too.)
- //
- //
- if (((*State->PortList)[i].Link & 4) != 0) {
- (*State->PortList)[i].Pointer = (*State->PortList)[j].Pointer;
- (*State->PortList)[i + 1].Pointer = (*State->PortList)[j + 1].Pointer;
- }
- (*State->PortList)[i].Link &= 0x03; // Force to point to subLink0
- (*State->PortList)[i + 1].Link &= 0x03;
- // If powered off, sublink 1 is removed but the link is still 8 bits.
- if (FinalLinkState != POWERED_OFF) {
- (*State->PortList)[i].SelRegang = TRUE; // Enable Link reganging
- (*State->PortList)[i + 1].SelRegang = TRUE;
- (*State->PortList)[i].PrvWidthOutCap = HT_WIDTH_16_BITS;
- (*State->PortList)[i + 1].PrvWidthOutCap = HT_WIDTH_16_BITS;
- (*State->PortList)[i].PrvWidthInCap = HT_WIDTH_16_BITS;
- (*State->PortList)[i + 1].PrvWidthInCap = HT_WIDTH_16_BITS;
- }
-
- // Delete PortList[j, j + 1], slow but easy to debug implementation
- State->TotalLinks--;
- LibAmdMemCopy (&((*State->PortList)[j]),
- &((*State->PortList)[j + 2]),
- sizeof (PORT_DESCRIPTOR)*(State->TotalLinks* 2 - j),
- State->ConfigHandle);
- LibAmdMemFill (&((*State->PortList)[State->TotalLinks * 2]), INVALID_LINK, (sizeof (PORT_DESCRIPTOR) * 2), State->ConfigHandle);
-
- break; // Exit loop, advance to PortList[i + 2]
- }
- }
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatGanging.h b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatGanging.h
deleted file mode 100644
index f168f14c8a..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatGanging.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Link Reganging Interface.
- *
- * Contains interface to the Reganging feature.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- *-----------------------------------------------------------------------------
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-
-#ifndef _HT_FEAT_GANGING_H_
-#define _HT_FEAT_GANGING_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-/**
- * Test the subLinks of a Link to see if they qualify to be reganged.
- *
- */
-VOID
-RegangLinks (
- IN OUT STATE_DATA *State
- );
-
-#endif /* _HT_FEAT_GANGING_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatNoncoherent.c b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatNoncoherent.c
deleted file mode 100644
index 90d2240532..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatNoncoherent.c
+++ /dev/null
@@ -1,374 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Non-Coherent Discovery Routines.
- *
- * Contains routines for enumerating and initializing non-coherent devices.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "htInterface.h"
-#include "htNotify.h"
-#include "htNb.h"
-#include "htFeatNoncoherent.h"
-#include "htFeatOptimization.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_FEATURES_HTFEATNONCOHERENT_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define NO_DEVICE 0xFFFFFFFFull
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/***************************************************************************
- *** Non-coherent init code ***
- *** Algorithms ***
- ***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
-/**
- * Process a non-coherent Link.
- *
- * @HtFeatMethod{::F_PROCESS_LINK}
- *
- * Enable a range of bus numbers, and set the device ID for all devices found. Add
- * non-coherent devices, links to the system data structure.
- *
- * @param[in] Node Node on which to process nc init
- * @param[in] Link The non-coherent Link on that Node
- * @param[in] IsCompatChain Is this the chain with the southbridge? TRUE if yes.
- * @param[in,out] State our global state
- */
-VOID
-ProcessLink (
- IN UINT8 Node,
- IN UINT8 Link,
- IN BOOLEAN IsCompatChain,
- IN OUT STATE_DATA *State
- )
-{
- UINT8 SecBus;
- UINT8 SubBus;
- UINT32 CurrentBuid;
- UINT32 Temp;
- UINT32 UnitIdCount;
- PCI_ADDR CurrentPtr;
- PCI_ADDR Link1ControlRegister;
- UINT8 Depth;
- BUID_SWAP_LIST *SwapPtr;
- UINT8 LastLink;
- BOOLEAN IsCaveDevice;
-
- ASSERT ((Node < MAX_NODES) && (Link < State->Nb->MaxLinks));
-
- if (!State->HtInterface->GetOverrideBusNumbers (Node, Link, &SecBus, &SubBus, State)) {
- // Assign Bus numbers
- if (State->AutoBusCurrent >= State->HtBlock->AutoBusMax) {
- // If we run out of Bus Numbers, notify and skip this chain
- //
- IDS_ERROR_TRAP;
- NotifyErrorNcohBusMaxExceed (Node, Link, State->AutoBusCurrent, State);
- return;
- }
-
- if (State->UsedCfgMapEntries >= 4) {
- // If we have used all the PCI Config maps we can't add another chain.
- // Notify and if call back is unimplemented or returns, skip this chain.
- //
- IDS_ERROR_TRAP;
- NotifyErrorNcohCfgMapExceed (Node, Link, State);
- return;
- }
-
- SecBus = State->AutoBusCurrent;
- SubBus = SecBus + State->HtBlock->AutoBusIncrement - 1;
- State->AutoBusCurrent = State->AutoBusCurrent + State->HtBlock->AutoBusIncrement;
- }
-
- State->Nb->SetConfigAddrMap (State->UsedCfgMapEntries, SecBus, SubBus, Node, Link, State, State->Nb);
- State->UsedCfgMapEntries++;
-
- if (State->HtInterface->GetManualBuidSwapList (Node, Link, &SwapPtr, State)) {
- // Manual non-coherent BUID assignment
- AGESA_TESTPOINT (TpProcHtManualNc, State->ConfigHandle);
-
-
- if (!IsCompatChain || !State->IsUsingRecoveryHt) {
- // If this is the not southbridge chain or Recovery HT was not used
- // then we need to assign BUIDs here.
- //
- Depth = 0;
- // Assign BUID's per manual override
- while (SwapPtr->Swaps[Depth].FromId != 0xFF) {
- CurrentPtr.AddressValue = MAKE_SBDFO (0, SecBus, SwapPtr->Swaps[Depth].FromId, 0, 0);
- if (DoesDeviceHaveHtSubtypeCap (CurrentPtr, HT_SLAVE_CAPABILITY, &CurrentPtr, State)) {
- // Set the device's BUID field [20:16] to the current buid
- CurrentBuid = SwapPtr->Swaps[Depth].ToId;
- LibAmdPciWriteBits (CurrentPtr, 20, 16, &CurrentBuid, State->ConfigHandle);
- Depth++;
- } else {
- // All non-coherent devices must have a slave interface capability.
- ASSERT (FALSE);
- break;
- }
- }
- }
-
- // Build chain of devices. Do this even if Recovery HT assign BUIDs for this chain.
- Depth = 0;
- while (SwapPtr->FinalIds[Depth] != 0xFF) {
- ASSERT (State->TotalLinks < MAX_PLATFORM_LINKS);
- (*State->PortList)[(State->TotalLinks * 2)].NodeID = Node;
- // Note: depth == 0 is true before depth > 0. This makes LastLink variable work.
- if (Depth == 0) {
- (*State->PortList)[(State->TotalLinks * 2)].Type = PORTLIST_TYPE_CPU;
- (*State->PortList)[(State->TotalLinks * 2)].Link = Link;
- } else {
- // Fill in the host side port. Link and base pointer can be deduced from the upstream link's
- // downstream port.
- (*State->PortList)[(State->TotalLinks * 2)].Type = PORTLIST_TYPE_IO;
- (*State->PortList)[(State->TotalLinks * 2)].Link = 1 - (*State->PortList)[(((State->TotalLinks - 1) * 2) + 1)].Link;
- (*State->PortList)[(State->TotalLinks * 2)].HostLink = Link;
- (*State->PortList)[(State->TotalLinks * 2)].HostDepth = Depth - 1;
- (*State->PortList)[(State->TotalLinks * 2)].Pointer = (*State->PortList)[(((State->TotalLinks - 1) * 2) + 1)].Pointer;
- }
-
- (*State->PortList)[(State->TotalLinks * 2) + 1].Type = PORTLIST_TYPE_IO;
- (*State->PortList)[(State->TotalLinks * 2) + 1].NodeID = Node;
- (*State->PortList)[(State->TotalLinks * 2) + 1].HostLink = Link;
- (*State->PortList)[(State->TotalLinks * 2) + 1].HostDepth = Depth;
-
- CurrentPtr.AddressValue = MAKE_SBDFO (0, SecBus, (SwapPtr->FinalIds[Depth] & 0x3F), 0, 0);
- if (DoesDeviceHaveHtSubtypeCap (CurrentPtr, HT_SLAVE_CAPABILITY, &CurrentPtr, State)) {
- (*State->PortList)[(State->TotalLinks * 2) + 1].Pointer = CurrentPtr;
- } else {
- // All non-coherent devices must have a slave interface capability.
- ASSERT (FALSE);
- break;
- }
-
- // Bit 6 indicates whether orientation override is desired.
- // Bit 7 indicates the upstream Link if overriding.
- //
- // assert catches at least the one known incorrect setting, that a non-zero link
- // is specified, but override desired is not set.
- ASSERT (((SwapPtr->FinalIds[Depth] & 0x40) != 0) || ((SwapPtr->FinalIds[Depth] & 0x80) == 0));
- if ((SwapPtr->FinalIds[Depth] & 0x40) != 0) {
- // Override the device's orientation
- LastLink = SwapPtr->FinalIds[Depth] >> 7;
- } else {
- // Detect the device's orientation, by reading the Master Host bit [26]
- LibAmdPciReadBits (CurrentPtr, 26, 26, &Temp, State->ConfigHandle);
- LastLink = (UINT8)Temp;
- }
- (*State->PortList)[(State->TotalLinks * 2) + 1].Link = LastLink;
-
- Depth++;
- State->TotalLinks++;
- }
- } else {
- // Automatic non-coherent device detection
- AGESA_TESTPOINT (TpProcHtAutoNc, State->ConfigHandle);
- IDS_HDT_CONSOLE (HT_TRACE, "Auto IO chain init on node=%d, link=%d, secbus=%d, subbus=%d%s.\n",
- Node, Link, SecBus, SubBus, (IsCompatChain ? ", Compat" : ""));
- Depth = 0;
- CurrentBuid = 1;
- for (; ; ) {
- CurrentPtr.AddressValue = MAKE_SBDFO (0, SecBus, 0, 0, 0);
-
- LibAmdPciRead (AccessWidth32, CurrentPtr, &Temp, State->ConfigHandle);
- if (Temp == NO_DEVICE) {
- if (IsCompatChain && State->IsUsingRecoveryHt) {
- // See if the device is aleady at a non-zero BUID because HT Init Reset aleady assigned it.
- CurrentPtr.Address.Device = CurrentBuid;
- LibAmdPciRead (AccessWidth32, CurrentPtr, &Temp, State->ConfigHandle);
- if (Temp == NO_DEVICE) {
- // No more devices already assigned.
- break;
- }
- } else {
- // No more devices found.
- break;
- }
- }
-
- ASSERT (State->TotalLinks < MAX_PLATFORM_LINKS);
-
- (*State->PortList)[(State->TotalLinks * 2)].NodeID = Node;
- if (Depth == 0) {
- (*State->PortList)[(State->TotalLinks * 2)].Type = PORTLIST_TYPE_CPU;
- (*State->PortList)[(State->TotalLinks * 2)].Link = Link;
- } else {
- // Fill in the host side port. Link and base pointer can be deduced from the upstream link's
- // downstream port.
- (*State->PortList)[(State->TotalLinks * 2)].Type = PORTLIST_TYPE_IO;
- (*State->PortList)[(State->TotalLinks * 2)].Link = 1 - (*State->PortList)[((State->TotalLinks - 1) * 2) + 1].Link;
- (*State->PortList)[(State->TotalLinks * 2)].HostLink = Link;
- (*State->PortList)[(State->TotalLinks * 2)].HostDepth = Depth - 1;
- (*State->PortList)[(State->TotalLinks * 2)].Pointer = (*State->PortList)[((State->TotalLinks - 1) * 2) + 1].Pointer;
- }
-
- (*State->PortList)[(State->TotalLinks * 2) + 1].Type = PORTLIST_TYPE_IO;
- (*State->PortList)[(State->TotalLinks * 2) + 1].NodeID = Node;
- (*State->PortList)[(State->TotalLinks * 2) + 1].HostLink = Link;
- (*State->PortList)[(State->TotalLinks * 2) + 1].HostDepth = Depth;
-
- if (DoesDeviceHaveHtSubtypeCap (CurrentPtr, HT_SLAVE_CAPABILITY, &CurrentPtr, State)) {
-
- // Get device's unit id count [25:21]
- LibAmdPciReadBits (CurrentPtr, 25, 21, &UnitIdCount, State->ConfigHandle);
- if (((UnitIdCount + CurrentBuid) > MAX_BUID) || ((SecBus == 0) && ((UnitIdCount + CurrentBuid) > 24))) {
- // An error handler for the case where we run out of BUID's on a chain
- NotifyErrorNcohBuidExceed (Node, Link, Depth, (UINT8)CurrentBuid, (UINT8)UnitIdCount, State);
- IDS_ERROR_TRAP;
- break;
- }
- // While we are still certain we are accessing this device, remember if it is a cave device.
- // This is found by reading EOC from the Link 1 Control Register.
- Link1ControlRegister = CurrentPtr;
- Link1ControlRegister.Address.Register += (HTSLAVE_LINK01_OFFSET + HTSLAVE_LINK_CONTROL_0_REG);
- LibAmdPciReadBits (Link1ControlRegister, 6, 6, &Temp, State->ConfigHandle);
- IsCaveDevice = ((Temp == 0) ? FALSE : TRUE);
-
- // Attempt to write the new BUID. Unless this chain was aleady assigned BUIDs during Init Reset,
- // then just re-discover the chain. Note this may be true whether the device was found at
- // BUID zero or not.
- IDS_HDT_CONSOLE (HT_TRACE, "Found device at depth=%d, BUID=%d.\n", Depth, CurrentPtr.Address.Device);
- if (!IsCompatChain || !State->IsUsingRecoveryHt) {
- IDS_HDT_CONSOLE (HT_TRACE, "Assigning device to BUID=%d.\n", CurrentBuid);
- LibAmdPciWriteBits (CurrentPtr, 20, 16, &CurrentBuid, State->ConfigHandle);
- }
-
- CurrentPtr.Address.Device = CurrentBuid;
- LibAmdPciReadBits (CurrentPtr, 20, 16, &Temp, State->ConfigHandle);
- if (Temp != CurrentBuid) {
- if ((Depth == 0) && IsCaveDevice) {
- // If the chain only consists of a single cave device, that device may have retained zero
- // for it's BUID.
- CurrentPtr.Address.Device = 0;
- LibAmdPciReadBits (CurrentPtr, 20, 16, &Temp, State->ConfigHandle);
- if (Temp == 0) {
- // Per HyperTransport specification, devices not accepting BUID reassignment hardwire BUID to zero.
- (*State->PortList)[(State->TotalLinks * 2) + 1].Link = 0;
- (*State->PortList)[(State->TotalLinks * 2) + 1].Pointer = CurrentPtr;
- State->TotalLinks++;
- Depth++;
- // Success!
- IDS_HDT_CONSOLE (HT_TRACE, "%s Cave left at BUID=0.\n", ((!IsCompatChain || !State->IsUsingRecoveryHt) ? "Compatible" : "Already Assigned"));
- break;
- } else if (Temp == CurrentBuid) {
- // and then, there are the other kind of devices ....
- // Restore the writable BUID field (which contains the value we just wrote) to zero.
- Temp = 0;
- LibAmdPciWriteBits (CurrentPtr, 20, 16, &Temp, State->ConfigHandle);
- (*State->PortList)[(State->TotalLinks * 2) + 1].Link = 0;
- (*State->PortList)[(State->TotalLinks * 2) + 1].Pointer = CurrentPtr;
- State->TotalLinks++;
- Depth++;
- // Success!
- IDS_HDT_CONSOLE (HT_TRACE, "Cave left at BUID=0.\n");
- break;
- }
- }
- // An error handler for this error,
- // this often occurs in new BIOS ports and it means you need to use a Manual BUID Swap List.
- NotifyErrorNcohDeviceFailed (Node, Link, Depth, (UINT8)CurrentBuid, State);
- IDS_ERROR_TRAP;
- break;
- }
-
- LibAmdPciReadBits (CurrentPtr, 26, 26, &Temp, State->ConfigHandle);
- (*State->PortList)[(State->TotalLinks * 2) + 1].Link = (UINT8)Temp;
- (*State->PortList)[(State->TotalLinks * 2) + 1].Pointer = CurrentPtr;
-
- IDS_HDT_CONSOLE (HT_TRACE, "Device assigned.\n");
- Depth++;
- State->TotalLinks++;
- CurrentBuid += UnitIdCount;
- } else {
- // All non-coherent devices must have a slave interface capability.
- ASSERT (FALSE);
- break;
- }
- }
- // Provide information on automatic device results
- NotifyInfoNcohAutoDepth (Node, Link, (Depth - 1), State);
- }
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatNoncoherent.h b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatNoncoherent.h
deleted file mode 100644
index 86ad3840c9..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatNoncoherent.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Non-Coherent Discovery Interface.
- *
- * Contains interface to the Non-Coherent Link processing feature.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-
-#ifndef _HT_FEAT_NONCOHERENT_H_
-#define _HT_FEAT_NONCOHERENT_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-/**
- * Process a non-coherent Link.
- *
- */
-VOID
-ProcessLink (
- IN UINT8 Node,
- IN UINT8 Link,
- IN BOOLEAN IsCompatChain,
- IN OUT STATE_DATA *State
- );
-
-#endif /* _HT_FEAT_NONCOHERENT_H_ */
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatOptimization.c b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatOptimization.c
deleted file mode 100644
index f6ab31ba46..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatOptimization.c
+++ /dev/null
@@ -1,889 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Link Optimization Routines.
- *
- * Contains routines for determining width, frequency, and other
- * Link features
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 47937 $ @e \$Date: 2011-03-02 13:35:06 +0800 (Wed, 02 Mar 2011) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "IdsHt.h"
-#include "htInterface.h"
-#include "htNb.h"
-#include "htFeatOptimization.h"
-#include "htNotify.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_FEATURES_HTFEATOPTIMIZATION_FILECODE
-
-extern CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride;
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define PCI_CONFIG_COMMAND_REG04 4
-#define PCI_CONFIG_REVISION_REG08 8
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/***************************************************************************
- *** Link Optimization ***
- ***************************************************************************/
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Given the bits set in the register field, return the width it represents.
- *
- * As invalid width values or encodings are rare except during debug, catch those using
- * ASSERT(). This means theoretically we are returning an incorrect result if that
- * happens. The default chosen for the result is arbitrarily 8 bits. This is likely
- * not to be the actual correct width and may cause a crash, hang, or incorrect operation.
- * Hardware often ignores writes of invalid width encodings.
- *
- * @note This routine is used for CPUs as well as IO devices, as all comply to the
- * "HyperTransport I/O Link Specification ".
- *
- * @param[in] Value The bits for the register
- *
- * @return The width
- */
-UINT8
-STATIC
-ConvertBitsToWidth (
- IN UINT8 Value
- )
-{
- UINT8 Result;
-
- Result = 0;
-
- switch (Value) {
-
- case 1:
- Result = 16;
- break;
-
- case 0:
- Result = 8;
- break;
-
- case 3:
- Result = 32;
- break;
-
- case 5:
- Result = 4;
- break;
-
- case 4:
- Result = 2;
- break;
-
- default:
- ASSERT (FALSE);
- }
- return Result;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Translate a desired width setting to the bits to set in the register field.
- *
- * As invalid width values or encodings are rare except during debug, catch those using
- * ASSERT(). This means theoretically we are returning an incorrect result if that
- * happens. The default chosen for the result is arbitrarily 8 bits. This is likely
- * not to be the actual correct width and may cause a crash, hang, or incorrect operation.
- * Hardware often ignores writes of invalid width encodings.
- *
- * @note This routine is used for CPUs as well as IO devices, as all comply to the
- * "HyperTransport I/O Link Specification ".
- *
- * @param[in] Value the width Value
- *
- * @return The bits for the register
- */
-UINT8
-ConvertWidthToBits (
- IN UINT8 Value
- )
-{
- UINT8 Result;
-
- Result = 8;
-
- switch (Value) {
-
- case 16:
- Result = 1;
- break;
-
- case 8:
- Result = 0;
- break;
-
- case 32:
- Result = 3;
- break;
-
- case 4:
- Result = 5;
- break;
-
- case 2:
- Result = 4;
- break;
-
- default:
- ASSERT (FALSE);
- }
- return Result;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Access HT Link Control Register.
- *
- * @HtFeatMethod{::F_SET_HT_CONTROL_REGISTER_BITS}
- *
- * Provide a common routine for accessing the HT Link Control registers (84, a4, c4,
- * e4), to enforce not clearing the HT CRC error bits. Replaces direct use of
- * AmdPCIWriteBits().
- *
- * @note: This routine is called for CPUs as well as IO Devices! All comply to the
- * "HyperTransport I/O Link Specification ".
- *
- * @param[in] Reg the PCI config address the control register
- * @param[in] HiBit the high bit number
- * @param[in] LoBit the low bit number
- * @param[in] Value the value to write to that bit range. Bit 0 => loBit.
- * @param[in] State Our state, config handle for lib
- */
-VOID
-SetHtControlRegisterBits (
- IN PCI_ADDR Reg,
- IN UINT8 HiBit,
- IN UINT8 LoBit,
- IN UINT32 *Value,
- IN STATE_DATA *State
- )
-{
- UINT32 Temp;
- UINT32 mask;
-
- ASSERT ((HiBit < 32) && (LoBit < 32) && (HiBit >= LoBit) && ((Reg.AddressValue & 0x3) == 0));
- ASSERT ((HiBit < 8) || (LoBit > 9));
-
- // A 1 << 32 == 1 << 0 due to x86 SHL instruction, so skip if that is the case
- if ((HiBit - LoBit) != 31) {
- mask = (((UINT32)1 << (HiBit - LoBit + 1)) - 1);
- } else {
- mask = (UINT32)0xFFFFFFFF;
- }
-
- LibAmdPciRead (AccessWidth32, Reg, &Temp, State->ConfigHandle);
- Temp &= ~(mask << LoBit);
- Temp |= (*Value & mask) << LoBit;
- Temp &= (UINT32)HT_CONTROL_CLEAR_CRC;
- LibAmdPciWrite (AccessWidth32, Reg, &Temp, State->ConfigHandle);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Set HT Frequency register for IO Devices
- *
- * Provide a common routine for accessing the HT Link Frequency registers at offset 8
- * and 0x10, to enforce not clearing the HT Link error bits. Replaces direct use of
- * AmdPCIWriteBits().
- *
- * @note This routine is called for IO Devices only!! All comply to the
- * "HyperTransport I/O Link Specification ".
- *
- * @param[in] Reg the PCI config address the control register
- * @param[in] Hibit the high bit number
- * @param[in] Lobit the low bit number
- * @param[in] Value the value to write to that bit range. Bit 0 => loBit.
- * @param[in] State Our state, config handle for lib
- */
-VOID
-STATIC
-SetHtIoFrequencyRegisterBits (
- IN PCI_ADDR Reg,
- IN UINT8 Hibit,
- IN UINT8 Lobit,
- IN UINT32 *Value,
- IN STATE_DATA *State
- )
-{
- UINT32 Mask;
- UINT32 Temp;
-
- ASSERT ((Hibit < 32) && (Lobit < 32) && (Hibit >= Lobit) && ((Reg.AddressValue & 0x3) == 0));
- ASSERT ((Hibit < 12) || (Lobit > 14));
-
- // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
- if ((Hibit - Lobit) != 31) {
- Mask = (((UINT32)1 << ((Hibit - Lobit) + 1)) - 1);
- } else {
- Mask = (UINT32)0xFFFFFFFF;
- }
-
- LibAmdPciRead (AccessWidth32, Reg, &Temp, State->ConfigHandle);
- Temp &= ~(Mask << Lobit);
- Temp |= (*Value & Mask) << Lobit;
- Temp &= (UINT32)HT_FREQUENCY_CLEAR_LINK_ERRORS;
- LibAmdPciWrite (AccessWidth32, Reg, &Temp, State->ConfigHandle);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get Link features into system data structure.
- *
- * @HtFeatMethod{::F_GATHER_LINK_DATA}
- *
- * For all discovered Links, populate the port list with the frequency and width
- * capabilities. Gather support data for:
- * - Unit ID Clumping
- *
- * @param[in] State our global state, port list
- */
-VOID
-GatherLinkData (
- IN STATE_DATA *State
- )
-{
- UINT8 i;
- PCI_ADDR LinkBase;
- PCI_ADDR Reg;
- UINT32 Bits;
- UINT8 Revision;
-
- // Get the capability base for whatever device type the link port is on
- for (i = 0; i < (State->TotalLinks * 2); i++) {
- if ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) {
- LinkBase = State->Nb->MakeLinkBase ((*State->PortList)[i].NodeID, (*State->PortList)[i].Link, State->Nb);
- (*State->PortList)[i].Pointer = LinkBase;
- } else {
- LinkBase = (*State->PortList)[i].Pointer;
- if ((*State->PortList)[i].Link == 1) {
- LinkBase.Address.Register += HTSLAVE_LINK01_OFFSET;
- }
- }
-
- // Getting the Width is standard across device types
- Reg = LinkBase;
- Reg.Address.Register += HTSLAVE_LINK_CONTROL_0_REG;
- LibAmdPciReadBits (Reg, 22, 20, &Bits, State->ConfigHandle);
- (*State->PortList)[i].PrvWidthOutCap = ConvertBitsToWidth ((UINT8)Bits);
-
- LibAmdPciReadBits (Reg, 18, 16, &Bits, State->ConfigHandle);
- (*State->PortList)[i].PrvWidthInCap = ConvertBitsToWidth ((UINT8)Bits);
-
- // Get Frequency and other device type specific features
- if ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) {
- State->Nb->GatherLinkFeatures (&(*State->PortList)[i], State->HtInterface, State->PlatformConfiguration, State->Nb);
- } else {
- Reg = LinkBase;
- Reg.Address.Register += HTSLAVE_FREQ_REV_0_REG;
- LibAmdPciReadBits (Reg, 31, 16, &Bits, State->ConfigHandle);
- (*State->PortList)[i].PrvFrequencyCap = Bits;
-
- // Unit ID Clumping Support
- if (State->IsUsingUnitIdClumping) {
- if (DoesDeviceHaveHtSubtypeCap (LinkBase, HT_UNITID_CAPABILITY, &Reg, State)) {
- Reg.Address.Register += HTUNIT_SUPPORT_REG;
- LibAmdPciReadBits (Reg, 31, 0, &Bits, State->ConfigHandle);
- } else {
- // Not there, that's ok, we don't know that it should have one.
- // Check for Passive support. (Bit 0 won't be set if full support is implemented,
- // so we can use it to indicate passive support in our portlist struct).
- Reg = LinkBase;
- Reg.Address.Register += HTSLAVE_FEATURECAP_REG;
- Bits = 1;
- LibAmdPciWriteBits (Reg, 5, 5, &Bits, State->ConfigHandle);
- LibAmdPciReadBits (Reg, 5, 5, &Bits, State->ConfigHandle);
- }
- (*State->PortList)[i].ClumpingSupport = Bits;
- } else {
- (*State->PortList)[i].ClumpingSupport = HT_CLUMPING_DISABLE;
- }
-
- Reg = LinkBase;
- Reg.Address.Register = PCI_CONFIG_REVISION_REG08;
- LibAmdPciReadBits ( LinkBase, 7, 0, &Bits, State->ConfigHandle);
- Revision = (UINT8) Bits;
-
- LinkBase.Address.Register = 0;
- LibAmdPciRead (AccessWidth32, LinkBase, &Bits, State->ConfigHandle);
-
- State->HtInterface->GetDeviceCapOverride ((*State->PortList)[i].NodeID,
- (*State->PortList)[i].HostLink,
- (*State->PortList)[i].HostDepth,
- (*State->PortList)[i].Pointer,
- Bits,
- Revision,
- (*State->PortList)[i].Link,
- &((*State->PortList)[i].PrvWidthInCap),
- &((*State->PortList)[i].PrvWidthOutCap),
- &((*State->PortList)[i].PrvFrequencyCap),
- &((*State->PortList)[i].ClumpingSupport),
- State);
- }
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Optimize Links.
- *
- * @HtFeatMethod{::F_SELECT_OPTIMAL_WIDTH_AND_FREQUENCY}
- *
- * For all Links:
- * Examine both sides of a Link and determine the optimal frequency and width,
- * taking into account externally provided limits and enforcing any other limit
- * or matching rules as applicable except subLink balancing. Update the port
- * list data with the optimal settings.
- *
- * @note no hardware state changes in this routine.
- *
- * @param[in,out] State Process and update portlist
- */
-VOID
-SelectOptimalWidthAndFrequency (
- IN OUT STATE_DATA *State
- )
-{
- UINT8 i;
- UINT8 j;
- UINT8 Freq;
- UINT32 Temp;
- UINT32 CbPcbFreqLimit;
- UINT8 CbPcbABDownstreamWidth;
- UINT8 CbPcbBAUpstreamWidth;
-
- for (i = 0; i < (State->TotalLinks * 2); i += 2) {
- CbPcbFreqLimit = HT_FREQUENCY_NO_LIMIT;
- CbPcbABDownstreamWidth = HT_WIDTH_16_BITS;
- CbPcbBAUpstreamWidth = HT_WIDTH_16_BITS;
-
- if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) && ((*State->PortList)[i + 1].Type == PORTLIST_TYPE_CPU)) {
- State->HtInterface->GetCpu2CpuPcbLimits ((*State->PortList)[i].NodeID,
- (*State->PortList)[i].Link,
- (*State->PortList)[i + 1].NodeID,
- (*State->PortList)[i + 1].Link,
- &CbPcbABDownstreamWidth,
- &CbPcbBAUpstreamWidth,
- &CbPcbFreqLimit,
- State
- );
- } else {
- State->HtInterface->GetIoPcbLimits ((*State->PortList)[i + 1].NodeID,
- (*State->PortList)[i + 1].HostLink,
- (*State->PortList)[i + 1].HostDepth,
- &CbPcbABDownstreamWidth,
- &CbPcbBAUpstreamWidth,
- &CbPcbFreqLimit,
- State
- );
- }
-
- Temp = (*State->PortList)[i].PrvFrequencyCap;
- Temp &= (*State->PortList)[i + 1].PrvFrequencyCap;
- Temp &= CbPcbFreqLimit;
- (*State->PortList)[i].CompositeFrequencyCap = (UINT32)Temp;
- (*State->PortList)[i + 1].CompositeFrequencyCap = (UINT32)Temp;
-
- ASSERT (Temp != 0);
- Freq = LibAmdBitScanReverse (Temp);
- (*State->PortList)[i].SelFrequency = Freq;
- (*State->PortList)[i + 1].SelFrequency = Freq;
-
- Temp = (*State->PortList)[i].PrvWidthOutCap;
- if ((*State->PortList)[i + 1].PrvWidthInCap < Temp) {
- Temp = (*State->PortList)[i + 1].PrvWidthInCap;
- }
- if (CbPcbABDownstreamWidth < Temp) {
- Temp = CbPcbABDownstreamWidth;
- }
- (*State->PortList)[i].SelWidthOut = (UINT8)Temp;
- (*State->PortList)[i + 1].SelWidthIn = (UINT8)Temp;
-
- Temp = (*State->PortList)[i].PrvWidthInCap;
- if ((*State->PortList)[i + 1].PrvWidthOutCap < Temp) {
- Temp = (*State->PortList)[i + 1].PrvWidthOutCap;
- }
- if (CbPcbBAUpstreamWidth < Temp) {
- Temp = CbPcbBAUpstreamWidth;
- }
- (*State->PortList)[i].SelWidthIn = (UINT8)Temp;
- (*State->PortList)[i + 1].SelWidthOut = (UINT8)Temp;
- }
- // Calculate unit id clumping
- //
- // Find the root of each IO Chain, process the chain for clumping support.
- // The root is always the first link of the chain in the port list.
- // Clumping is not device link specific, so we can just look at the upstream ports (j+1). Use ASSERTs to sanity
- // check the downstream ports (j). If any device on the chain does not support clumping, the entire chain will be
- // disabled for clumping.
- // After analyzing the clumping support on the chain the CPU's portlist has the enable mask. Update all the
- // IO Devices on the chain with the enable mask. If any device's only have passive support, that is already enabled.
- //
- if (State->IsUsingUnitIdClumping) {
- for (i = 0; i < (State->TotalLinks * 2); i += 2) {
- if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) && ((*State->PortList)[i + 1].Type == PORTLIST_TYPE_IO)) {
- (*State->PortList)[i].ClumpingSupport = HT_CLUMPING_DISABLE;
- if ((*State->PortList)[i + 1].ClumpingSupport != HT_CLUMPING_DISABLE) {
- (*State->PortList)[i].ClumpingSupport |= (*State->PortList)[i + 1].ClumpingSupport;
- for (j = i + 2; j < (State->TotalLinks * 2); j += 2) {
- if (((*State->PortList)[j].Type == PORTLIST_TYPE_IO) && ((*State->PortList)[j + 1].Type == PORTLIST_TYPE_IO)) {
- if (((*State->PortList)[i].NodeID == (*State->PortList)[j + 1].NodeID) &&
- ((*State->PortList)[i].Link == (*State->PortList)[j + 1].HostLink)) {
- ASSERT (((*State->PortList)[i].NodeID == (*State->PortList)[j + 1].NodeID) &&
- ((*State->PortList)[i].Link == (*State->PortList)[j].HostLink));
- if ((*State->PortList)[j + 1].ClumpingSupport != HT_CLUMPING_DISABLE) {
- ASSERT ((((*State->PortList)[j + 1].ClumpingSupport & HT_CLUMPING_PASSIVE) == 0) ||
- (((*State->PortList)[j + 1].ClumpingSupport & ~(HT_CLUMPING_PASSIVE)) == 0));
- (*State->PortList)[i].ClumpingSupport |= (*State->PortList)[j + 1].ClumpingSupport;
- } else {
- (*State->PortList)[i].ClumpingSupport = HT_CLUMPING_DISABLE;
- break;
- }
- }
- }
- }
- if ((*State->PortList)[i + 1].ClumpingSupport != HT_CLUMPING_PASSIVE) {
- (*State->PortList)[i + 1].ClumpingSupport = (*State->PortList)[i].ClumpingSupport;
- }
- for (j = i + 2; j < (State->TotalLinks * 2); j += 2) {
- if (((*State->PortList)[j].Type == PORTLIST_TYPE_IO) && ((*State->PortList)[j + 1].Type == PORTLIST_TYPE_IO)) {
- if (((*State->PortList)[i].NodeID == (*State->PortList)[j + 1].NodeID) &&
- ((*State->PortList)[i].Link == (*State->PortList)[j + 1].HostLink)) {
- if ((*State->PortList)[j + 1].ClumpingSupport != HT_CLUMPING_PASSIVE) {
- (*State->PortList)[j + 1].ClumpingSupport = (*State->PortList)[i].ClumpingSupport;
- // The downstream isn't really passive, just mark it so in order to write the device only once.
- (*State->PortList)[j].ClumpingSupport = HT_CLUMPING_PASSIVE;
- }
- }
- }
- }
- }
- }
- }
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Change the hardware state for all Links according to the now optimized data in the
- * port list data structure.
- *
- * @HtFeatMethod{::F_SET_LINK_DATA}
- *
- * @param[in] State our global state, port list
- */
-VOID
-SetLinkData (
- IN STATE_DATA *State
- )
-{
- UINT8 i;
- PCI_ADDR LinkBase;
- PCI_ADDR Reg;
- UINT32 Temp;
- UINT32 Widthin;
- UINT32 Widthout;
- UINT32 Bits;
- PCI_ADDR CurrentPtr;
- HTIDS_PORT_OVERRIDE_LIST PortOverrides;
-
- PortOverrides = NULL;
-
- for (i = 0; i < (State->TotalLinks * 2); i++) {
-
- ASSERT ((*State->PortList)[i & 0xFE].SelWidthOut == (*State->PortList)[ (i & 0xFE) + 1].SelWidthIn);
- ASSERT ((*State->PortList)[i & 0xFE].SelWidthIn == (*State->PortList)[ (i & 0xFE) + 1].SelWidthOut);
- ASSERT ((*State->PortList)[i & 0xFE].SelFrequency == (*State->PortList)[ (i & 0xFE) + 1].SelFrequency);
-
- if ((*State->PortList)[i].SelRegang) {
- ASSERT ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU);
- ASSERT ((*State->PortList)[i].Link < 4);
- State->Nb->SetLinkRegang (
- (*State->PortList)[i].NodeID,
- (*State->PortList)[i].Link,
- State->Nb
- );
- }
-
- //
- // IDS port override for CPUs and IO Devices
- //
- pf_HtIdsGetPortOverride ((BOOLEAN) ((i & 1) == 0), &(*State->PortList)[i], &(*State->PortList)[i + 1], &PortOverrides, State);
-
- LinkBase = (*State->PortList)[i].Pointer;
- if (((*State->PortList)[i].Type == PORTLIST_TYPE_IO) && ((*State->PortList)[i].Link == 1)) {
- LinkBase.Address.Register += HTSLAVE_LINK01_OFFSET;
- }
-
- // HT CRC Feature, set if configured. The default is not to set it, because with some chipsets it
- // will lock up if done here.
- if (State->IsSetHtCrcFlood) {
- Temp = 1;
- Reg = LinkBase;
- Reg.Address.Register += HTHOST_LINK_CONTROL_REG;
- State->HtFeatures->SetHtControlRegisterBits (Reg, 1, 1, &Temp, State);
- if ((*State->PortList)[i].Type == PORTLIST_TYPE_IO) {
- // IO Devices also need to have SERR enabled.
- Reg = LinkBase;
- Reg.Address.Register = PCI_CONFIG_COMMAND_REG04;
- LibAmdPciWriteBits (Reg, 8, 8, &Temp, State->ConfigHandle);
- }
- }
-
- // Some IO devices don't work properly when setting widths, so write them in a single operation,
- // rather than individually.
- //
- Widthout = ConvertWidthToBits ((*State->PortList)[i].SelWidthOut);
- ASSERT (Widthout == 1 || Widthout == 0 || Widthout == 5 || Widthout == 4);
- Widthin = ConvertWidthToBits ((*State->PortList)[i].SelWidthIn);
- ASSERT (Widthin == 1 || Widthin == 0 || Widthin == 5 || Widthin == 4);
-
- Temp = (Widthin & 7) | ((Widthout & 7) << 4);
- Reg = LinkBase;
- Reg.Address.Register += HTHOST_LINK_CONTROL_REG;
- State->HtFeatures->SetHtControlRegisterBits (Reg, 31, 24, &Temp, State);
-
- Temp = (*State->PortList)[i].SelFrequency;
- IDS_HDT_CONSOLE (HT_TRACE, "Link Frequency: Node %02d: Link %02d: is running at %2d00MHz\n",
- (*State->PortList)[i].NodeID, (*State->PortList)[i].Link,
- (Temp < HT_FREQUENCY_800M) ? Temp + 2 : ((Temp < HT_FREQUENCY_2800M) ? 2 * (Temp - 1) : 2 * (Temp - 3)));
-
- if ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) {
- State->Nb->SetLinkFrequency (
- (*State->PortList)[i].NodeID,
- (*State->PortList)[i].Link,
- (UINT8)Temp,
- State->Nb
- );
- } else {
- ASSERT (Temp <= HT_FREQUENCY_2600M);
- // Write the frequency setting
- Reg = LinkBase;
- Reg.Address.Register += HTSLAVE_FREQ_REV_0_REG;
- SetHtIoFrequencyRegisterBits (Reg, 11, 8, &Temp, State);
-
- // Handle additional HT3 frequency requirements, if needed,
- // or clear them if switching down to ht1 on a warm reset.
- // Gen1 = 200Mhz -> 1000MHz, Gen3 = 1200MHz -> 2600MHz
- //
- // Even though we assert if debugging, we need to check that the capability was
- // found always, since this is an unknown hardware device, also we are taking
- // unqualified frequency from the external interface (could be trying to do ht3
- // on an ht1 IO device).
- //
-
- if (Temp > HT_FREQUENCY_1000M) {
- // Enabling features if gen 3
- Bits = 1;
- } else {
- // Disabling features if gen 1
- Bits = 0;
- }
-
- // Retry Enable
- if (DoesDeviceHaveHtSubtypeCap (LinkBase, HT_RETRY_CAPABILITY, &CurrentPtr, State)) {
- ASSERT ((*State->PortList)[i].Link < 2);
- CurrentPtr.Address.Register += HTRETRY_CONTROL_REG;
- LibAmdPciWriteBits (CurrentPtr,
- ((*State->PortList)[i].Link * 16),
- ((*State->PortList)[i].Link * 16),
- &Bits,
- State->ConfigHandle);
- } else {
- // If we are turning it off, that may mean the device was only ht1 capable,
- // so don't complain that we can't do it.
- //
- if (Bits != 0) {
- NotifyWarningOptRequiredCapRetry ((*State->PortList)[i].NodeID,
- (*State->PortList)[i].HostLink,
- (*State->PortList)[i].HostDepth,
- State);
- }
- }
-
- // Scrambling enable
- if (DoesDeviceHaveHtSubtypeCap (LinkBase, HT_GEN3_CAPABILITY, &CurrentPtr, State)) {
- ASSERT ((*State->PortList)[i].Link < 2);
- CurrentPtr.Address.Register = CurrentPtr.Address.Register +
- HTGEN3_LINK_TRAINING_0_REG +
- ((*State->PortList)[i].Link * HTGEN3_LINK01_OFFSET);
- LibAmdPciWriteBits (CurrentPtr, 3, 3, &Bits, State->ConfigHandle);
- } else {
- // If we are turning it off, that may mean the device was only ht1 capable,
- // so don't complain that we can't do it.
- //
- if (Bits != 0) {
- NotifyWarningOptRequiredCapGen3 ((*State->PortList)[i].NodeID,
- (*State->PortList)[i].HostLink,
- (*State->PortList)[i].HostDepth,
- State);
- }
- }
- }
- // Enable Unit ID Clumping if supported.
- if (State->IsUsingUnitIdClumping) {
- if (((*State->PortList)[i].ClumpingSupport != HT_CLUMPING_PASSIVE) &&
- ((*State->PortList)[i].ClumpingSupport != HT_CLUMPING_DISABLE)) {
- Bits = (*State->PortList)[i].ClumpingSupport;
- if ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) {
- State->Nb->SetLinkUnitIdClumping (
- (*State->PortList)[i].NodeID,
- (*State->PortList)[i].Link,
- (*State->PortList)[i].ClumpingSupport,
- State->Nb
- );
- } else {
- if (DoesDeviceHaveHtSubtypeCap (LinkBase, HT_UNITID_CAPABILITY, &Reg, State)) {
- Reg.Address.Register += HTUNIT_ENABLE_REG;
- LibAmdPciWriteBits (Reg, 31, 0, &Bits, State->ConfigHandle);
- } else {
- // If we found one when gathering support, we have to find one now.
- ASSERT (FALSE);
- }
- }
- }
- }
- }
-}
-
-/*------------------------------------------------------------------------------------------*/
-/**
- * Find a specific HT capability type.
- *
- * Search all the PCI Config space capabilities on any type of device for an
- * HT capability of the specific subtype.
- *
- * @param[in] DevicePointer A PCI Config address somewhere in the device config space
- * @param[in] CapSubType The HT capability subtype to find
- * @param[out] CapabilityBase The Config space base address of the capability, if found.
- * @param[in] State Our State
- *
- * @retval TRUE the capability was found
- * @retval FALSE the capability was not found
- */
-BOOLEAN
-DoesDeviceHaveHtSubtypeCap (
- IN PCI_ADDR DevicePointer,
- IN UINT8 CapSubType,
- OUT PCI_ADDR *CapabilityBase,
- IN STATE_DATA *State
- )
-{
- BOOLEAN IsFound;
- BOOLEAN IsDone;
- PCI_ADDR Reg;
- UINT32 Temp;
- UINT32 RegSubType;
- UINT32 RegSubTypeMask;
-
- // Set the PCI Config Space base and the match value.
- IsFound = FALSE;
- IsDone = FALSE;
- Reg = DevicePointer;
- Reg.Address.Register = 0;
- if (CapSubType < (HT_HOST_CAPABILITY + 1)) {
- // HT Interface sub type
- RegSubType = ((UINT32) (CapSubType << 29) | (UINT32)8);
- RegSubTypeMask = HT_INTERFACE_CAP_SUBTYPE_MASK;
- } else {
- // Other HT capability subtype
- RegSubType = ((UINT32) (CapSubType << 27) | (UINT32)8);
- RegSubTypeMask = HT_CAP_SUBTYPE_MASK;
- }
- (*CapabilityBase).AddressValue = (UINT32)ILLEGAL_SBDFO;
-
- // Find it
- do {
- LibAmdPciFindNextCap (&Reg, State->ConfigHandle);
- if (Reg.AddressValue != (UINT32)ILLEGAL_SBDFO) {
- LibAmdPciRead (AccessWidth32, Reg, &Temp, State->ConfigHandle);
- // HyperTransport and subtype capability ?
- if ((Temp & RegSubTypeMask) == RegSubType) {
- *CapabilityBase = Reg;
- IsFound = TRUE;
- }
- // Some other capability, keep looking
- } else {
- // Not there
- IsDone = TRUE;
- }
- } while (!IsFound && !IsDone);
-
- return IsFound;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Retry must be enabled on all coherent links if it is enabled on any coherent links.
- *
- * @HtFeatMethod{::F_SET_LINK_DATA}
- *
- * Effectively, this means HT3 on some links cannot be mixed with HT1 on others.
- * Scan the CPU to CPU links for this condition and limit those frequencies to HT1
- * if it is detected.
- * (Non-coherent links are independent.)
- *
- * @param[in,out] State global state, port frequency settings.
- *
- * @retval TRUE Fixup occurred, all coherent links HT1
- * @retval FALSE No changes
- */
-BOOLEAN
-IsCoherentRetryFixup (
- IN STATE_DATA *State
- )
-{
- UINT8 Freq;
- UINT8 i;
- UINT8 DetectedFrequencyState;
- BOOLEAN IsMixed;
- UINT32 Temp;
-
- //
- // detectedFrequencyState:
- // 0 - initial state
- // 1 - HT1 Frequencies detected
- // 2 - HT3 Frequencies detected
- //
- IsMixed = FALSE;
- DetectedFrequencyState = 0;
-
- // Scan coherent links for a mix of HT3 / HT1
- for (i = 0; i < (State->TotalLinks * 2); i += 2) {
- if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) && ((*State->PortList)[i + 1].Type == PORTLIST_TYPE_CPU)) {
- // At this point, Frequency of port [i+1] must equal [i], so just check one of them.
- switch (DetectedFrequencyState) {
- case 0:
- // Set current state to indicate what link frequency we found first
- if ((*State->PortList)[i].SelFrequency > HT_FREQUENCY_1000M) {
- // HT3 frequencies
- DetectedFrequencyState = 2;
- } else {
- // HT1 frequencies
- DetectedFrequencyState = 1;
- }
- break;
- case 1:
- // If HT1 frequency detected, fail any HT3 frequency
- if ((*State->PortList)[i].SelFrequency > HT_FREQUENCY_1000M) {
- IsMixed = TRUE;
- }
- break;
- case 2:
- // If HT3 frequency detected, fail any HT1 frequency
- if ((*State->PortList)[i].SelFrequency <= HT_FREQUENCY_1000M) {
- IsMixed = TRUE;
- }
- break;
- default:
- ASSERT (FALSE);
- }
- if (IsMixed) {
- // Don't need to keep checking after we find a mix.
- break;
- }
- }
- }
-
- if (IsMixed) {
- for (i = 0; i < (State->TotalLinks * 2); i += 2) {
- if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) && ((*State->PortList)[i + 1].Type == PORTLIST_TYPE_CPU)) {
- // Limit coherent links to HT 1 frequencies.
- Temp = (*State->PortList)[i].CompositeFrequencyCap & (*State->PortList)[i + 1].CompositeFrequencyCap;
- Temp &= HT_FREQUENCY_LIMIT_HT1_ONLY;
- ASSERT (Temp != 0);
- (*State->PortList)[i].CompositeFrequencyCap = Temp;
- (*State->PortList)[i + 1].CompositeFrequencyCap = Temp;
- Freq = LibAmdBitScanReverse (Temp);
- (*State->PortList)[i].SelFrequency = Freq;
- (*State->PortList)[i + 1].SelFrequency = Freq;
- }
- }
- }
- return (IsMixed);
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatOptimization.h b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatOptimization.h
deleted file mode 100644
index bbd66b8f15..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatOptimization.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Link Optimization Feature.
- *
- * Contains interface for Link Optimization.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-
-#ifndef _HT_FEAT_OPTIMIZATION_H_
-#define _HT_FEAT_OPTIMIZATION_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-/**
- * Translate a desired width setting to the bits to set in the register field.
- */
-UINT8
-ConvertWidthToBits (
- IN UINT8 Value
- );
-
-/**
- * Access HT Link Control Register.
- *
- */
-VOID
-SetHtControlRegisterBits (
- IN PCI_ADDR Reg,
- IN UINT8 HiBit,
- IN UINT8 LoBit,
- IN UINT32 *Value,
- IN STATE_DATA *State
- );
-
-/**
- * Get Link features into system data structure.
- *
- */
-VOID
-GatherLinkData (
- IN STATE_DATA *State
- );
-
-/**
- * Optimize Links.
- *
- */
-VOID
-SelectOptimalWidthAndFrequency (
- IN OUT STATE_DATA *State
- );
-
-/**
- * Change the hardware state for all Links according to the now optimized data in the
- * port list data structure.
- *
- */
-VOID
-SetLinkData (
- IN STATE_DATA *State
- );
-
-/**
- * Retry must be enabled on all coherent links if it is enabled on any coherent links.
- *
- */
-BOOLEAN
-IsCoherentRetryFixup (
- IN STATE_DATA *State
- );
-
-/**
- * Find a specific HT capability type.
- *
- * @retval FALSE the capability was not found
- */
-BOOLEAN
-DoesDeviceHaveHtSubtypeCap (
- IN PCI_ADDR DevicePointer,
- IN UINT8 CapSubType,
- OUT PCI_ADDR *CapabilityBase,
- IN STATE_DATA *State
- );
-
-#endif /* _HT_FEAT_OPTIMIZATION_H_ */
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatRouting.c b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatRouting.c
deleted file mode 100644
index 6322d389aa..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatRouting.c
+++ /dev/null
@@ -1,492 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Routing Routines
- *
- * Contains routines for isomorphic topology matching,
- * routing determination, and routing initialization.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "htInterface.h"
-#include "htNotify.h"
-#include "htNb.h"
-#include "htGraph.h"
-#include "htFeatRouting.h"
-#include "htTopologies.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_FEATURES_HTFEATROUTING_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-typedef struct {
- UINT8 **CurrentPosition;
- BOOLEAN IsCustomList;
-} TOPOLOGY_CONTEXT;
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/***************************************************************************
- *** ISOMORPHISM BASED ROUTING TABLE GENERATION CODE ***
- ***************************************************************************/
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Return the Link on source Node which connects to target Node
- *
- * @param[in] SourceNode The Node on which to find the Link
- * @param[in] TargetNode The Link will connect to this Node
- * @param[in] State Our global state
- *
- * @return the Link to target
- */
-UINT8
-STATIC
-FindLinkToNode (
- IN UINT8 SourceNode,
- IN UINT8 TargetNode,
- IN STATE_DATA *State
- )
-{
- UINT8 TargetLink;
- UINT8 k;
-
- // A node linked to itself is not a supported topology graph, this is probably an error in the
- // topology data. There is not going to be a portlist match for it.
- ASSERT (SourceNode != TargetNode);
- TargetLink = INVALID_LINK;
- for (k = 0; k < State->TotalLinks*2; k += 2) {
- if (((*State->PortList)[k].NodeID == SourceNode) && ((*State->PortList)[k + 1].NodeID == TargetNode)) {
- TargetLink = (*State->PortList)[k].Link;
- break;
- } else if (((*State->PortList)[k + 1].NodeID == SourceNode) && ((*State->PortList)[k].NodeID == TargetNode)) {
- TargetLink = (*State->PortList)[k + 1].Link;
- break;
- }
- }
- ASSERT (TargetLink != INVALID_LINK);
-
- return TargetLink;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Is graphA isomorphic to graphB?
- *
- * If this function returns true, then Perm will contain the permutation
- * required to transform graphB into graphA.
- * We also use the degree of each Node, that is the number of connections it has, to
- * speed up rejection of non-isomorphic graphs (if there is a Node in graphA with n
- * connections, there must be at least one unmatched in graphB with n connections).
- *
- * @param[in] Node the discovered Node which we are trying to match
- * with a permutation the topology
- * @param[in,out] State our global state, degree and adjacency matrix,
- * output a permutation if successful
- * @retval TRUE the graphs are isomorphic
- * @retval FALSE the graphs are not isomorphic
- *
- */
-BOOLEAN
-STATIC
-IsIsomorphic (
- IN UINT8 Node,
- IN OUT STATE_DATA *State
- )
-{
- UINT8 j;
- UINT8 k;
- UINT8 Nodecnt;
-
- // We have only been called if Nodecnt == pSelected->size !
- Nodecnt = State->NodesDiscovered + 1;
-
- if (Node != Nodecnt) {
- // Keep building the permutation
- for (j = 0; j < Nodecnt; j++) {
- // Make sure the degree matches
- if (State->Fabric->SysDegree[Node] != State->Fabric->DbDegree[j]) {
- continue;
- }
-
- // Make sure that j hasn't been used yet (ought to use a "used"
- // array instead, might be faster)
- for (k = 0; k < Node; k++) {
- if (State->Fabric->Perm[k] == j) {
- break;
- }
- }
- if (k != Node) {
- continue;
- }
- State->Fabric->Perm[Node] = j;
- if (IsIsomorphic (Node + 1, State)) {
- return TRUE;
- }
- }
- return FALSE;
- } else {
- // Test to see if the permutation is isomorphic
- for (j = 0; j < Nodecnt; j++) {
- for (k = 0; k < Nodecnt; k++) {
- if (State->Fabric->SysMatrix[j][k] != State->Fabric->DbMatrix[State->Fabric->Perm[j]][State->Fabric->Perm[k]] ) {
- return FALSE;
- }
- }
- }
- return TRUE;
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Set Topology List iterator context to the Beginning and provide the first topology.
- *
- * Check the interface for a custom topology list. If one is found, set context to the
- * first item, and return that item. Otherwise return the first item in the built in list.
- *
- * @param[in,out] TopologyContextHandle Initialize this context to beginning of lists.
- * @param[out] NextTopology The next topology, NULL if end.
- * @param[in] State Access to interface, handles.
- *
- */
-VOID
-STATIC
-BeginTopologies (
- OUT TOPOLOGY_CONTEXT *TopologyContextHandle,
- OUT UINT8 **NextTopology,
- IN STATE_DATA *State
- )
-{
- if (State->HtBlock->Topolist != NULL) {
- // Start with a custom list
- TopologyContextHandle->CurrentPosition = State->HtBlock->Topolist;
- TopologyContextHandle->IsCustomList = TRUE;
- } else {
- // Start with the built in list
- GetAmdTopolist (&TopologyContextHandle->CurrentPosition);
- TopologyContextHandle->IsCustomList = FALSE;
- }
- *NextTopology = *TopologyContextHandle->CurrentPosition;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Iterate through available topologies.
- *
- * Increment to the next list item. If we are doing a custom list, when we reach the end
- * switch to the built in list.
- *
- * @param[in,out] TopologyContextHandle Maintain iterator's context from one call to the next
- * @param[out] NextTopology The next topology, NULL if end.
- *
- */
-VOID
-STATIC
-GetNextTopology (
- IN OUT TOPOLOGY_CONTEXT *TopologyContextHandle,
- OUT UINT8 **NextTopology
- )
-{
- // Not valid to continue calling this routine after reaching the end.
- ASSERT (TopologyContextHandle->CurrentPosition != NULL);
-
- if (TopologyContextHandle->IsCustomList) {
- // We are iterating the custom list from the interface.
- TopologyContextHandle->CurrentPosition++;
- if (*TopologyContextHandle->CurrentPosition == NULL) {
- // We are at the end of the custom list, switch to the built in list.
- TopologyContextHandle->IsCustomList = FALSE;
- GetAmdTopolist (&TopologyContextHandle->CurrentPosition);
- }
- } else {
- // We are iterating the built in list
- TopologyContextHandle->CurrentPosition++;
- // If we are at the end of the built in list, NextTopology == NULL is the AtEnd.
- }
- *NextTopology = *TopologyContextHandle->CurrentPosition;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Using the description of the fabric topology we discovered, try to find a match
- * among the supported topologies.
- *
- * @HtFeatMethod{::F_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES}
- *
- * A supported topology description matches the discovered fabric if the Nodes can be
- * matched in such a way that all the Nodes connected in one set are exactly the
- * Nodes connected in the other (formally, that the graphs are isomorphic). Which
- * Links are used is not really important to matching. If the graphs match, then
- * there is a permutation of one that translates the Node positions and Linkages to
- * the other.
- *
- * In order to make the isomorphism test efficient, we test for matched number of Nodes
- * (a 4 Node fabric is not isomorphic to a 2 Node topology), and provide degrees of Nodes
- * to the isomorphism test.
- *
- * The generic routing table solution for any topology is predetermined and represented
- * as part of the topology. The permutation we computed tells us how to interpret the
- * routing onto the fabric we discovered. We do this working backward from the last
- * Node discovered to the BSP, writing the routing tables as we go.
- *
- * @param[in,out] State the discovered fabric, degree matrix, permutation
- *
- */
-VOID
-LookupComputeAndLoadRoutingTables (
- IN OUT STATE_DATA *State
- )
-{
- TOPOLOGY_CONTEXT TopologyContextHandle;
- UINT8 *Selected;
- UINT8 Size;
- UINT8 PairCounter;
- UINT8 ReqTargetLink;
- UINT8 RspTargetLink;
- UINT8 ReqTargetNode;
- UINT8 RspTargetNode;
- UINT8 AbstractBcTargetNodes;
- UINT32 BcTargetLinks;
- UINT8 NodeCounter;
- UINT8 NodeBeingRouted;
- UINT8 NodeRoutedTo;
- UINT8 BroadcastSourceNode;
-
- Size = State->NodesDiscovered + 1;
- BeginTopologies (&TopologyContextHandle, &Selected, State);
- while (Selected != NULL) {
- if (GraphHowManyNodes (Selected) == Size) {
- // Build Degree vector and Adjacency Matrix for this entry
- for (NodeCounter = 0; NodeCounter < Size; NodeCounter++) {
- State->Fabric->DbDegree[NodeCounter] = 0;
- for (PairCounter = 0; PairCounter < Size; PairCounter++) {
- if (GraphIsAdjacent (Selected, NodeCounter, PairCounter)) {
- State->Fabric->DbMatrix[NodeCounter][PairCounter] = TRUE;
- State->Fabric->DbDegree[NodeCounter]++;
- } else {
- State->Fabric->DbMatrix[NodeCounter][PairCounter] = FALSE;
- }
- }
- }
-
- if (IsIsomorphic (0, State)) {
- break; // A matching topology was found
- }
- }
- GetNextTopology (&TopologyContextHandle, &Selected);
- }
-
- if (Selected != NULL) {
- // Compute the reverse Permutation
- for (NodeCounter = 0; NodeCounter < Size; NodeCounter++) {
- State->Fabric->ReversePerm[State->Fabric->Perm[NodeCounter]] = NodeCounter;
- }
-
- // Start with the last discovered Node, and move towards the BSP
- for (NodeCounter = 0; NodeCounter < Size; NodeCounter++) {
- NodeBeingRouted = ((Size - 1) - NodeCounter);
- for (NodeRoutedTo = 0; NodeRoutedTo < Size; NodeRoutedTo++) {
- BcTargetLinks = 0;
- AbstractBcTargetNodes = GraphGetBc (Selected, State->Fabric->Perm[NodeBeingRouted], State->Fabric->Perm[NodeRoutedTo]);
-
- for (BroadcastSourceNode = 0; BroadcastSourceNode < MAX_NODES; BroadcastSourceNode++) {
- if ((AbstractBcTargetNodes & ((UINT32)1 << BroadcastSourceNode)) != 0) {
- // Accepting broadcast from yourself is handled in Nb, so in the topology graph it is an error.
- ASSERT (NodeBeingRouted != State->Fabric->ReversePerm[BroadcastSourceNode]);
- BcTargetLinks |= (UINT32)1 << FindLinkToNode (NodeBeingRouted, State->Fabric->ReversePerm[BroadcastSourceNode], State);
- }
- }
-
- if (NodeBeingRouted == NodeRoutedTo) {
- ReqTargetLink = ROUTE_TO_SELF;
- RspTargetLink = ROUTE_TO_SELF;
- } else {
- ReqTargetNode = GraphGetReq (Selected, State->Fabric->Perm[NodeBeingRouted], State->Fabric->Perm[NodeRoutedTo]);
- ReqTargetLink = FindLinkToNode (NodeBeingRouted, State->Fabric->ReversePerm[ReqTargetNode], State);
-
- RspTargetNode = GraphGetRsp (Selected, State->Fabric->Perm[NodeBeingRouted], State->Fabric->Perm[NodeRoutedTo]);
- RspTargetLink = FindLinkToNode (NodeBeingRouted, State->Fabric->ReversePerm[RspTargetNode], State);
- }
- State->Nb->WriteFullRoutingTable (NodeBeingRouted, NodeRoutedTo, ReqTargetLink, RspTargetLink, BcTargetLinks, State->Nb);
- }
- // Clean up discovery 'footprint' that otherwise remains in the routing table. It didn't hurt
- // anything, but might cause confusion during debug and validation. Do this by setting the
- // route back to all self routes. Since it's the Node that would be one more than actually installed,
- // this only applies if less than MaxNodes were found.
- //
- if (Size < MAX_NODES) {
- State->Nb->WriteFullRoutingTable (NodeBeingRouted, Size, ROUTE_TO_SELF, ROUTE_TO_SELF, 0, State->Nb);
- }
- }
- } else {
- //
- // No Matching Topology was found
- // Error Strategy:
- // Auto recovery doesn't seem likely, Force boot as 1P.
- // For reporting, logging, provide number of Nodes
- // If not implemented or returns, boot as BSP uniprocessor.
- //
- // This can be caused by not supplying an additional topology list, if your board is not one of the built-in topologies.
- //
- NotifyErrorCohNoTopology (State->NodesDiscovered, State);
- IDS_ERROR_TRAP;
- // Force 1P
- State->NodesDiscovered = 0;
- State->TotalLinks = 0;
- State->Nb->EnableRoutingTables (0, State->Nb);
- State->HtInterface->CleanMapsAfterError (State);
- }
- // Save the topology pointer, or NULL, for other features
- State->Fabric->MatchedTopology = Selected;
- IDS_HDT_CONSOLE (
- HT_TRACE,
- "System routed as %s.\n",
- ((TopologyContextHandle.IsCustomList) ?
- "custom topology" :
- (((Selected == amdHtTopologySingleNode) || (Selected == NULL)) ?
- "single node" :
- ((Selected == amdHtTopologyDualNode) ?
- "dual node" :
- ((Selected == amdHtTopologyFourSquare) ?
- "four node box" :
- ((Selected == amdHtTopologyFourKite) ?
- "four node kite" :
- ((Selected == amdHtTopologyFourFully) ?
- "fully connected four-way" :
- ((Selected == amdHtTopologyEightDoubloon) ?
- "MCM max performance" :
- ((Selected == amdHtTopologyEightTwinFullyFourWays) ?
- "MCM max I/O" :
- "AMD builtin topology"))))))))
- );
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Make a Hop Count Table for the installed topology.
- *
- * @HtFeatMethod{::F_MAKE_HOP_COUNT_TABLE}
- *
- * For SLIT, create a node x node matrix with the number of hops. We can do this
- * using the topology and the permutation, counting the nodes visited in the routes between
- * nodes.
- *
- * @param[in,out] State access topology, permutation, update hop table
- *
- */
-VOID
-MakeHopCountTable (
- IN OUT STATE_DATA *State
- )
-{
- UINT8 Origin;
- UINT8 Target;
- UINT8 Current;
- UINT8 Hops;
- UINT8 Size;
-
- ASSERT (State->Fabric != NULL);
- if (State->HopCountTable != NULL) {
- if (State->Fabric->MatchedTopology != NULL) {
- Size = GraphHowManyNodes (State->Fabric->MatchedTopology);
- State->HopCountTable->Size = Size;
- //
- // For each node, targeting each node, follow the request path through the database graph,
- // counting the number of edges.
- //
- for (Origin = 0; Origin < Size; Origin++) {
- for (Target = 0; Target < Size; Target++) {
- // If both nodes are the same the answer will be zero
- Hops = 0;
- // Current starts as the database node corresponding to system node Origin.
- Current = State->Fabric->Perm[Origin];
- // Stop if Current is the database node corresponding to system node Target
- while (Current != State->Fabric->Perm[Target]) {
- // This is a hop, so count it. Move Current to the next intermediate database node.
- Hops++;
- Current = GraphGetReq (State->Fabric->MatchedTopology, Current, State->Fabric->Perm[Target]);
- }
- // Put the hop count in the table.
- State->HopCountTable->Hops[ ((Origin * Size) + Target)] = Hops;
- }
- }
- }
- }
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatRouting.h b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatRouting.h
deleted file mode 100644
index 5dbcd6a8fc..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatRouting.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Routing Feature Interface.
- *
- * Interfaces to routing and isomorphism routines.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-
-#ifndef _HT_FEAT_ROUTING_H_
-#define _HT_FEAT_ROUTING_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-/**
- * Using the description of the fabric topology we discovered, try to find a match
- * among the supported topologies.
- *
- */
-VOID
-LookupComputeAndLoadRoutingTables (
- IN OUT STATE_DATA *State
- );
-
-/**
- * Make a Hop Count Table for the installed topology.
- *
- */
-VOID
-MakeHopCountTable (
- IN OUT STATE_DATA *State
- );
-
-#endif /* _HT_FEAT_ROUTING_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatSets.c b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatSets.c
deleted file mode 100644
index 07204597e2..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatSets.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * HyperTransport feature sets initializers.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "OptionsHt.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "CommonReturns.h"
-#include "htFeatDynamicDiscovery.h"
-#include "htFeatRouting.h"
-#include "htFeatNoncoherent.h"
-#include "htFeatOptimization.h"
-#include "htFeatGanging.h"
-#include "htFeatSublinks.h"
-#include "htFeatTrafficDistribution.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_FEATURES_HTFEATSETS_FILECODE
-extern CONST OPTION_HT_CONFIGURATION OptionHtConfiguration;
-
-/**
- * Initializer for the default feature set implementation,
- * full features.
- */
-CONST HT_FEATURES ROMDATA HtFeaturesDefault =
-{
- CoherentDiscovery,
- LookupComputeAndLoadRoutingTables,
- MakeHopCountTable,
- ProcessLink,
- GatherLinkData,
- SelectOptimalWidthAndFrequency,
- RegangLinks,
- SubLinkRatioFixup,
- IsCoherentRetryFixup,
- SetLinkData,
- TrafficDistribution,
- SetHtControlRegisterBits,
- ConvertWidthToBits
-};
-
-/**
- * Initializer for the non-coherent only build option.
- */
-CONST HT_FEATURES ROMDATA HtFeaturesNonCoherentOnly =
-{
- (PF_COHERENT_DISCOVERY)CommonVoid,
- (PF_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES)CommonVoid,
- (PF_MAKE_HOP_COUNT_TABLE)CommonVoid,
- ProcessLink,
- GatherLinkData,
- SelectOptimalWidthAndFrequency,
- (PF_REGANG_LINKS)CommonVoid,
- (PF_SUBLINK_RATIO_FIXUP)CommonVoid,
- (PF_IS_COHERENT_RETRY_FIXUP)CommonReturnFalse,
- SetLinkData,
- (PF_TRAFFIC_DISTRIBUTION)CommonVoid,
- SetHtControlRegisterBits,
- ConvertWidthToBits
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatSublinks.c b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatSublinks.c
deleted file mode 100644
index f2f742320c..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatSublinks.c
+++ /dev/null
@@ -1,231 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * SubLink management Routines.
- *
- * Contains routines for subLink frequency ratios.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "amdlib.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "IdsHt.h"
-#include "htFeatSublinks.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_FEATURES_HTFEATSUBLINKS_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-typedef struct {
- UINT8 HiFreq;
- UINT8 LoFreq;
-} VALID_RATIO_ITEM;
-
-STATIC CONST VALID_RATIO_ITEM ROMDATA ValidRatioList[] =
-{
- {HT_FREQUENCY_3200M, HT_FREQUENCY_1600M}, // 3200MHz / 1600MHz 2:1
- {HT_FREQUENCY_3200M, HT_FREQUENCY_800M}, // 3200MHz / 800MHz 4:1
- {HT_FREQUENCY_3200M, HT_FREQUENCY_400M}, // 3200MHz / 400MHz 8:1
- {HT_FREQUENCY_2800M, HT_FREQUENCY_1400M}, // 2800MHz / 1400MHz 2:1
- {HT_FREQUENCY_2400M, HT_FREQUENCY_1200M}, // 2400MHz / 1200MHz 2:1
- {HT_FREQUENCY_2400M, HT_FREQUENCY_600M}, // 2400MHz / 600MHz 4:1
- {HT_FREQUENCY_2400M, HT_FREQUENCY_400M}, // 2400MHz / 400MHz 6:1
- {HT_FREQUENCY_2000M, HT_FREQUENCY_1000M}, // 2000MHz / 1000MHz 2:1
- {HT_FREQUENCY_1600M, HT_FREQUENCY_800M}, // 1600MHz / 800MHz 2:1
- {HT_FREQUENCY_1600M, HT_FREQUENCY_400M}, // 1600MHz / 400MHz 4:1
- {HT_FREQUENCY_1600M, HT_FREQUENCY_200M}, // 1600MHz / 200Mhz 8:1
- {HT_FREQUENCY_1200M, HT_FREQUENCY_600M}, // 1200MHz / 600MHz 2:1
- {HT_FREQUENCY_1200M, HT_FREQUENCY_200M}, // 1200MHz / 200MHz 6:1
- {HT_FREQUENCY_800M, HT_FREQUENCY_400M}, // 800MHz / 400MHz 2:1
- {HT_FREQUENCY_800M, HT_FREQUENCY_200M}, // 800MHz / 200MHz 4:1
- {HT_FREQUENCY_400M, HT_FREQUENCY_200M} // 400MHz / 200MHz 2:1
-};
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/***************************************************************************
- *** Link Optimization ***
- ***************************************************************************/
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Iterate through all Links, checking the frequency of each subLink pair.
- *
- * @HtFeatMethod{::F_SUBLINK_RATIO_FIXUP}
- *
- * Make the adjustment to the port list data so that the frequencies
- * are at a valid ratio, reducing frequency as needed to achieve
- * this. (All Links support the minimum 200 MHz frequency.) Repeat
- * the above until no adjustments are needed.
- * @note no hardware state changes in this routine.
- *
- * @param[in,out] State Link state and port list
- *
- */
-VOID
-SubLinkRatioFixup (
- IN OUT STATE_DATA *State
- )
-{
- UINT8 i;
- UINT8 j;
- UINT8 ValidRatioItem;
- BOOLEAN Changes;
- BOOLEAN Downgrade;
- UINT8 HiIndex;
- UINT8 HiFreq;
- UINT8 LoFreq;
-
- UINT32 Temp;
-
- do {
- Changes = FALSE;
- for (i = 0; i < State->TotalLinks*2; i++) {
- // Must be a CPU Link
- if ((*State->PortList)[i].Type != PORTLIST_TYPE_CPU) {
- continue;
- }
- // Only look for subLink1's
- if ((*State->PortList)[i].Link < 4) {
- continue;
- }
-
- for (j = 0; j < State->TotalLinks*2; j++) {
- // Step 1. Find the matching subLink0
- if ((*State->PortList)[j].Type != PORTLIST_TYPE_CPU) {
- continue;
- }
- if ((*State->PortList)[j].NodeID != (*State->PortList)[i].NodeID) {
- continue;
- }
- if ((*State->PortList)[j].Link != ((*State->PortList)[i].Link & 0x03)) {
- continue;
- }
-
- // Step 2. Check for an illegal frequency ratio
- if ((*State->PortList)[i].SelFrequency >= (*State->PortList)[j].SelFrequency) {
- HiIndex = i;
- HiFreq = (*State->PortList)[i].SelFrequency;
- LoFreq = (*State->PortList)[j].SelFrequency;
- } else {
- HiIndex = j;
- HiFreq = (*State->PortList)[j].SelFrequency;
- LoFreq = (*State->PortList)[i].SelFrequency;
- }
-
- // The frequencies are 1:1, no need to do anything
- if (HiFreq == LoFreq) {
- break;
- }
-
- Downgrade = TRUE;
-
- for (ValidRatioItem = 0; ValidRatioItem < (sizeof (ValidRatioList) / sizeof (VALID_RATIO_ITEM)); ValidRatioItem++) {
- if ((HiFreq == ValidRatioList[ValidRatioItem].HiFreq) &&
- (LoFreq == ValidRatioList[ValidRatioItem].LoFreq)) {
- Downgrade = FALSE;
- break;
- }
- }
-
- // Step 3. Downgrade the higher of the two frequencies, and set Changes to FALSE
- if (Downgrade) {
- // Although the problem was with the port specified by hiIndex, we need to
- // Downgrade both ends of the Link.
- HiIndex = HiIndex & 0xFE; // Select the 'upstream' (i.e. even) port
-
- Temp = (*State->PortList)[HiIndex].CompositeFrequencyCap;
-
- // Remove HiFreq from the list of valid frequencies
- Temp = Temp & ~((UINT32)1 << HiFreq);
- ASSERT (Temp != 0);
- (*State->PortList)[HiIndex].CompositeFrequencyCap = (UINT32)Temp;
- (*State->PortList)[HiIndex + 1].CompositeFrequencyCap = (UINT32)Temp;
-
- HiFreq = LibAmdBitScanReverse (Temp);
-
- (*State->PortList)[HiIndex].SelFrequency = HiFreq;
- (*State->PortList)[HiIndex + 1].SelFrequency = HiFreq;
-
- Changes = TRUE;
- }
- }
- }
- } while (Changes); // Repeat until a valid configuration is reached
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatSublinks.h b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatSublinks.h
deleted file mode 100644
index 701e3f3c38..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatSublinks.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * SubLink Interface.
- *
- * Contains interface to subLink management feature, for unganged subLinks.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-
-#ifndef _HT_FEAT_SUBLINKS_H_
-#define _HT_FEAT_SUBLINKS_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-/**
- * Iterate through all Links, checking the frequency of each subLink pair.
- *
- */
-VOID
-SubLinkRatioFixup (
- IN OUT STATE_DATA *State
- );
-
-#endif /* _HT_FEAT_SUBLINKS_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatTrafficDistribution.c b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatTrafficDistribution.c
deleted file mode 100644
index bba026f617..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatTrafficDistribution.c
+++ /dev/null
@@ -1,411 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Traffic Distribution Routines.
- *
- * Contains routines for traffic distribution
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44846 $ @e \$Date: 2011-01-07 13:21:05 +0800 (Fri, 07 Jan 2011) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "htInterface.h"
-#include "htNb.h"
-#include "htNotify.h"
-#include "htFeatTrafficDistribution.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_FEATURES_HTFEATTRAFFICDISTRIBUTION_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-/// Enum for the possible link connection status
-typedef enum {
- Unconnected = 0, ///< Nodes have not connected link.
- UngangedLink, ///< Nodes are connected with one unganged link.
- Redundant, ///< Nodes are connected with multi-unganged link.
- GangedLink, ///< Nodes are connected with one or mutiple ganged link.
- MaxLink ///< Max links status.
-} LINK_STATUS;
-
-/// Local port connection state data structure
-typedef struct {
- LINK_STATUS ConnectionState; /**< The link connection state. */
- UINT32 BigLinkPort; /**< The Port number for ganged Link */
-} PORT_CONNECTION_STATE;
-
-/// Local ganged link for Victim Distribution data structure
-typedef struct {
-UINT8 NodeA; ///< Source Node from Node A To Node B and DstNode from Node A To Node B.
-UINT8 NodeB; ///< Source Node from Node B To Node A and DstNode from Node A To Node B.
-UINT32 VictimedLinkFromNodeAToNodeB; ///< Victimed Link from Node A To Node B.
-UINT32 VictimedLinkFromNodeBToNodeA; ///< Victimed Link from Node B To Node A.
-} VICTIM_ROUTED_LINK;
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Identify Links which can have traffic distribution.
- *
- * @HtFeatMethod{::F_TRAFFIC_DISTRIBUTION}
- *
- * If there are redundant links between any nodes, traffic distribution allows the
- * redundant links to be used to improve performance.
- *
- * There are three types of traffic distribution. Their use is mutually exclusive, all
- * can not be used at once.
- *
- * Coherent Traffic Distribution is for systems of exactly two nodes only. All links must
- * be symmetrical (the same width). As many links as are connected can be distributed over.
- *
- * Victim Distribution is a way to direct victim traffic on to ganged links and away from unganged links
- * as a way to reduce unganged link congestion for a system only if 2 processor (4 node) G34 system.
- * A node can enables victim distribution mode only if the node connects to another node directly with
- * only 1 unganged link hop and indirectly through 2 ganged link hops.
- *
- * Link Pair Traffic Distribution works with redundant pairs of links between any two nodes,
- * it does not matter how many nodes are in the system or how many have a redundant link pair.
- * A node can have redundant link pairs with more than one other node.
- * The link pair can be asymmetric, the largest link must be used as the master. However,
- * between any pair of nodes there is only one pair of redundant links, and there is a limit
- * to the total number of pairs each node can have. So not all links will necessarily be
- * made usable.
- *
- * @param[in] State port list data
- */
-VOID
-TrafficDistribution (
- IN STATE_DATA *State
- )
-{
- UINT32 Links01;
- UINT32 Links10;
- UINT8 LinkCount;
- UINT8 i;
- UINT8 LastLink;
- BOOLEAN IsAsymmetric;
- BOOLEAN IsGangedPathFound;
- UINT8 RedundantLinkCount[MAX_NODES][MAX_NODES];
- UINT8 MasterLinkPort[MAX_NODES][MAX_NODES];
- UINT8 AlternateLinkPort[MAX_NODES][MAX_NODES];
- UINT8 NodeA;
- UINT8 NodeB;
- UINT8 PairCount;
- VICTIM_ROUTED_LINK VictimRoutedLink[MAX_NODES];
- PORT_CONNECTION_STATE GangedLinkPort[MAX_NODES][MAX_NODES];
-
- LastLink = 0xFF;
- IsAsymmetric = FALSE;
-
- // Traffic Distribution is only used when there are exactly two Nodes in the system
- // and when all the links are symmetric, same width.
- if ((State->NodesDiscovered + 1) == 2) {
- Links01 = 0;
- Links10 = 0;
- LinkCount = 0;
- for (i = 0; i < (State->TotalLinks * 2); i += 2) {
- if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) &&
- ((*State->PortList)[i + 1].Type == PORTLIST_TYPE_CPU)) {
- if ((LastLink != 0xFF) &&
- ((*State->PortList)[i].SelWidthOut != (*State->PortList)[LastLink].SelWidthOut) &&
- ((*State->PortList)[i + 1].SelWidthOut != (*State->PortList)[LastLink + 1].SelWidthOut)) {
- IsAsymmetric = TRUE;
- break;
- }
- Links01 |= (UINT32)1 << (*State->PortList)[i].Link;
- Links10 |= (UINT32)1 << (*State->PortList)[i + 1].Link;
- LinkCount++;
- LastLink = i;
- }
- }
- ASSERT (LinkCount != 0);
- // Don't setup Traffic Distribution if only one Link is being used or there were asymmetric widths
- if ((LinkCount != 1) && !IsAsymmetric) {
- IDS_HDT_CONSOLE (HT_TRACE, "Applying coherent traffic distribution.\n");
- State->Nb->WriteTrafficDistribution (Links01, Links10, State->Nb);
- // If we did Traffic Distribution, we must not do Link Pair, so get out of here.
- return;
- }
- }
-
- // Victim Distribution is only used when there are exactly two processor (4 node) system
- // and the node connects to another node directly with only 1 unganged link hop and indirectly
- // through 2 ganged link hops.
- if ((State->NodesDiscovered + 1) == 4) {
- LinkCount = 0;
-
- // Initialize the ganged link state data structures
- for (NodeA = 0; NodeA < MAX_NODES; NodeA++) {
- for (NodeB = 0; NodeB < MAX_NODES; NodeB++) {
- GangedLinkPort[NodeA][NodeB].ConnectionState = 0;
- GangedLinkPort[NodeA][NodeB].BigLinkPort = 0;
- }
- }
-
- for (i = 0; i < (State->TotalLinks * 2); i += 2) {
- if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) &&
- ((*State->PortList)[i + 1].Type == PORTLIST_TYPE_CPU)) {
- NodeA = (*State->PortList)[i].NodeID;
- NodeB = (*State->PortList)[i + 1].NodeID;
- if (((*State->PortList)[i].SelRegang == TRUE) &&
- ((*State->PortList)[i].PrvWidthOutCap == HT_WIDTH_16_BITS)) {
- if (GangedLinkPort[NodeA][NodeB].ConnectionState <= Redundant) {
- // Record it if it is the first ganged link between node A and node B.
- GangedLinkPort[NodeA][NodeB].BigLinkPort = (*State->PortList)[i].Link;
- GangedLinkPort[NodeB][NodeA].BigLinkPort = (*State->PortList)[i + 1].Link;
- GangedLinkPort[NodeA][NodeB].ConnectionState = GangedLink;
- GangedLinkPort[NodeB][NodeA].ConnectionState = GangedLink;
- }
- } else {
- if (GangedLinkPort[NodeA][NodeB].ConnectionState == Unconnected) {
- // Record it if it is firstly unganged link and does no exist ganged link between node A and node B.
- GangedLinkPort[NodeA][NodeB].ConnectionState = UngangedLink;
- GangedLinkPort[NodeB][NodeA].ConnectionState = UngangedLink;
-
- // Record the number of ungand link port
- LinkCount++;
- } else if (GangedLinkPort[NodeA][NodeB].ConnectionState == UngangedLink) {
- // There are multi-unganged links and ignore it
- GangedLinkPort[NodeA][NodeB].ConnectionState = Redundant;
- GangedLinkPort[NodeB][NodeA].ConnectionState = Redundant;
-
- // Adjust the number of valid ungand link port
- LinkCount--;
- }
- }
- }
- }
-
- if (LinkCount != 0) {
- LinkCount = 0;
-
- // Check Link by Link if one unganged link can direct victim traffic on to indirectly 2 ganged link hops
- for (NodeA = 0; NodeA <= (State->NodesDiscovered); NodeA++) {
- for (NodeB = NodeA +1; NodeB <= (State->NodesDiscovered); NodeB++) {
- // Check if it is one unganged link
- if (GangedLinkPort[NodeA][NodeB].ConnectionState == UngangedLink) {
- IsGangedPathFound = FALSE;
-
- for (i = 0; i <= (State->NodesDiscovered); i++) {
- // To find the first ganged link hop to Destined Node
- if ((i != NodeA) && (i != NodeB) && (GangedLinkPort[NodeA][i].ConnectionState == GangedLink)) {
- // Record the Source Node and Destined Link
- VictimRoutedLink[LinkCount].NodeA = NodeA;
- VictimRoutedLink[LinkCount].VictimedLinkFromNodeAToNodeB = GangedLinkPort[NodeA][i].BigLinkPort;
- // To find the second ganged link hop to Destined Node
- if (GangedLinkPort[i][NodeB].ConnectionState == GangedLink) {
- // Record the Destined Node and the Reversed Destination Link
- VictimRoutedLink[LinkCount].NodeB = NodeB;
- VictimRoutedLink[LinkCount].VictimedLinkFromNodeBToNodeA = GangedLinkPort[NodeB][i].BigLinkPort;
- if (!IsGangedPathFound) {
- LinkCount++;
-
- // This is first ganged links where there are 2 ganged link hops to DstNode
- IsGangedPathFound = TRUE;
- } else {
- // Find the second ganged link where there are 2 ganged link hops to DstNode
- // Record the new Reversed Destination Link in Full Topology
- VictimRoutedLink[LinkCount - 1].VictimedLinkFromNodeBToNodeA = GangedLinkPort[NodeB][i].BigLinkPort;
- }
- }
- }
- }
- }
- }
- }
-
- // Setup Victim Distribution Mode
- if (LinkCount != 0) {
- IDS_HDT_CONSOLE (HT_TRACE, "Applying coherent Victim distribution.\n");
- for (i = 0; i < LinkCount; i++) {
- State->Nb->WriteVictimDistribution (VictimRoutedLink[i].NodeA,
- VictimRoutedLink[i].NodeB,
- VictimRoutedLink[i].VictimedLinkFromNodeAToNodeB,
- VictimRoutedLink[i].VictimedLinkFromNodeBToNodeA,
- State->Nb);
- }
- // If we did Victim Distribution, we must not do Link Pair when there are more than two nodes, so get out of here.
- return;
- }
- }
- }
-
- // Either there are more than two nodes, Asymmetric links, or no redundant links.
- // See if we can use Link Pair Traffic Distribution
- LibAmdMemFill (&RedundantLinkCount, 0, (MAX_NODES * MAX_NODES), State->ConfigHandle);
- for (i = 0; i < (State->TotalLinks * 2); i += 2) {
- if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) &&
- ((*State->PortList)[i + 1].Type == PORTLIST_TYPE_CPU)) {
- NodeA = (*State->PortList)[i].NodeID;
- NodeB = (*State->PortList)[i + 1].NodeID;
- if (RedundantLinkCount[NodeA][NodeB] == 0) {
- // This is the first link connecting two nodes
- ASSERT (RedundantLinkCount[NodeB][NodeA] == 0);
- MasterLinkPort[NodeA][NodeB] = i;
- MasterLinkPort[NodeB][NodeA] = i + 1;
- } else {
- // This is a redundant link. If it is larger than the current master link,
- // make it the new master link.
- //
- if (((*State->PortList)[MasterLinkPort[NodeA][NodeB]].SelWidthOut < (*State->PortList)[i].SelWidthOut) &&
- ((*State->PortList)[MasterLinkPort[NodeB][NodeA]].SelWidthOut < (*State->PortList)[i + 1].SelWidthOut)) {
- // Make the old master link the alternate, we don't need to check, it is bigger.
- AlternateLinkPort[NodeA][NodeB] = MasterLinkPort[NodeA][NodeB];
- AlternateLinkPort[NodeB][NodeA] = MasterLinkPort[NodeB][NodeA];
- MasterLinkPort[NodeA][NodeB] = i;
- MasterLinkPort[NodeB][NodeA] = i + 1;
- } else {
- // Since the new link isn't bigger than the Master, check if it is bigger than the alternate,
- // if we have an alternate. If we don't have an alternate yet, make this link the alternate.
- if (RedundantLinkCount[NodeA][NodeB] == 1) {
- AlternateLinkPort[NodeA][NodeB] = i;
- AlternateLinkPort[NodeB][NodeA] = i + 1;
- } else {
- if (((*State->PortList)[AlternateLinkPort[NodeA][NodeB]].SelWidthOut < (*State->PortList)[i].SelWidthOut) &&
- ((*State->PortList)[AlternateLinkPort[NodeB][NodeA]].SelWidthOut < (*State->PortList)[i + 1].SelWidthOut)) {
- // Warning: the alternate link is an unusable redundant link
- // Then make the new link the alternate link.
- NotifyWarningOptUnusedLinks (
- NodeA,
- (*State->PortList)[AlternateLinkPort[NodeA][NodeB]].Link,
- NodeB,
- (*State->PortList)[AlternateLinkPort[NodeB][NodeA]].Link,
- State
- );
- ASSERT (RedundantLinkCount[NodeB][NodeA] > 1);
- AlternateLinkPort[NodeA][NodeB] = i;
- AlternateLinkPort[NodeB][NodeA] = i + 1;
- } else {
- // Warning the current link is an unusable redundant link
- NotifyWarningOptUnusedLinks (NodeA, (*State->PortList)[i].Link, NodeB, (*State->PortList)[i].Link, State);
- }
- }
- }
- }
- RedundantLinkCount[NodeA][NodeB]++;
- RedundantLinkCount[NodeB][NodeA]++;
- }
- }
- // If we found any, now apply up to 4 per node
- for (NodeA = 0; NodeA < MAX_NODES; NodeA++) {
- PairCount = 0;
- for (NodeB = 0; NodeB < MAX_NODES; NodeB++) {
- if (RedundantLinkCount[NodeA][NodeB] > 1) {
- // Then there is a pair of links (at least, but we only care about the pair not the extras)
- if (PairCount < MAX_LINK_PAIRS) {
- // Program it
- if ((*State->PortList)[MasterLinkPort[NodeA][NodeB]].SelWidthOut
- != (*State->PortList)[AlternateLinkPort[NodeA][NodeB]].SelWidthOut) {
- IsAsymmetric = TRUE;
- } else {
- IsAsymmetric = FALSE;
- }
- State->Nb->WriteLinkPairDistribution (
- NodeA,
- NodeB,
- PairCount,
- IsAsymmetric,
- (*State->PortList)[MasterLinkPort[NodeA][NodeB]].Link,
- (*State->PortList)[AlternateLinkPort[NodeA][NodeB]].Link,
- State->Nb
- );
- PairCount++;
- } else {
- // Warning: More link pairs than can be distributed
- NotifyWarningOptLinkPairExceed (
- NodeA, NodeB,
- (*State->PortList)[MasterLinkPort[NodeA][NodeB]].Link,
- (*State->PortList)[AlternateLinkPort[NodeA][NodeB]].Link,
- State);
- // Disable the link pair from the other node, the analysis loop made sure there
- // can only be a single link pair between a pair of nodes.
- RedundantLinkCount[NodeB][NodeA] = 1;
- }
- }
- }
- IDS_HDT_CONSOLE (
- HT_TRACE,
- ((PairCount != 0) ?
- "Node %d applying %d link pair distributions.\n" :
- ""),
- NodeA,
- PairCount
- );
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatTrafficDistribution.h b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatTrafficDistribution.h
deleted file mode 100644
index 647de9be51..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htFeatTrafficDistribution.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Traffic Distribution Interface.
- *
- * Interface to traffic distribution feature.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-#ifndef _HT_FEAT_TRAFFIC_DISTRIBUTION_H_
-#define _HT_FEAT_TRAFFIC_DISTRIBUTION_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-/**
- * Identify Links which can have traffic distribution.
- *
- */
-VOID
-TrafficDistribution (
- IN STATE_DATA *State
- );
-
-#endif /* _HT_FEAT_TRAFFIC_DISTRIBUTION_H_ */
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htIds.c b/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htIds.c
deleted file mode 100644
index ab91fe3dc7..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/Features/htIds.c
+++ /dev/null
@@ -1,150 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD IDS HyperTransport Implementation.
- *
- * Contains AMD AGESA Integrated Debug HT related support.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "IdsHt.h"
-#include "htInterface.h"
-#include "htInterfaceGeneral.h"
-#include "htNb.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-#define FILECODE PROC_HT_FEATURES_HTIDS_FILECODE
-
-
-/*-------------------------------------------------------------------------------------*/
-/**
- * Apply an IDS port override to the desired HT link.
- *
- * The IDS port override allows absolute control of a link's frequency and width, such as
- * would be used for board characterization and test. The IDS backend code is responsible
- * for handling the NV items and building them into a port override list. Here we search
- * that list for any overrides which apply, and update the data used by the HT feature code.
- *
- * @param[in] IsSourcePort Since we handle both ports on a match, only do that if TRUE.
- * @param[in,out] Port0 The PORTLIST item for the first endpoint of a link.
- * @param[in,out] Port1 The PORTLIST item for the second endpoint of a link.
- * @param[in,out] PortOverrideList IN: A pointer to the port override list or NULL,
- * OUT: A pointer to the port override list.
- * @param[in] State access to ht interface and nb support methods.
- *
- */
-VOID
-HtIdsGetPortOverride (
- IN BOOLEAN IsSourcePort,
- IN OUT PORT_DESCRIPTOR *Port0,
- IN OUT PORT_DESCRIPTOR *Port1,
- IN OUT HTIDS_PORT_OVERRIDE_LIST *PortOverrideList,
- IN STATE_DATA *State
- )
-{
- LOCATE_HEAP_PTR LocHeapParams;
- UINT8 SocketA;
- UINT8 SocketB;
- UINT8 PackageLinkA;
- UINT8 PackageLinkB;
- HTIDS_PORT_OVERRIDE_LIST p;
-
- if (IsSourcePort) {
- ASSERT (PortOverrideList != NULL);
- // The caller can cache the override list by providing the pointer (to the heap buffer).
- // If the pointer to the port override list is null, then check if it is on the heap,
- // and update the caller's pointer so it is cached.
- // If the buffer is not in heap, call the IDS backend to get the NV data (which is likely also
- // in heap).
- if (*PortOverrideList == NULL) {
- // locate the table in heap
- LocHeapParams.BufferHandle = IDS_HT_DATA_HANDLE;
- if (HeapLocateBuffer (&LocHeapParams, State->ConfigHandle) == AGESA_SUCCESS) {
- *PortOverrideList = (HTIDS_PORT_OVERRIDE_LIST)LocHeapParams.BufferPtr;
- } else {
- // Ask IDS backend code for the list
- IDS_OPTION_HOOK (IDS_HT_CONTROL, PortOverrideList, State->ConfigHandle);
- }
- }
- ASSERT (*PortOverrideList != NULL);
-
- // Search the port override list to see if there is an override that applies to this link.
- // The match criteria are if either endpoint of the current port list item matches
- // port override.
- p = *PortOverrideList;
- SocketA = State->HtInterface->GetSocketFromMap (Port0->NodeID, State);
- PackageLinkA = State->Nb->GetPackageLink (Port0->NodeID, Port0->Link, State->Nb);
- SocketB = State->HtInterface->GetSocketFromMap (Port1->NodeID, State);
- PackageLinkB = State->Nb->GetPackageLink (Port1->NodeID, Port1->Link, State->Nb);
-
- while ((p != NULL) && (p->Socket != HT_LIST_TERMINAL)) {
- if (((p->Socket == SocketA) || (p->Socket == HT_LIST_MATCH_ANY)) &&
- ((p->Link == PackageLinkA) ||
- ((p->Link == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkA))) ||
- ((p->Link == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkA)))) ||
- ((p->Socket == SocketB) || (p->Socket == HT_LIST_MATCH_ANY)) &&
- ((p->Link == PackageLinkB) ||
- ((p->Link == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkA))) ||
- ((p->Link == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkB))))) {
- // Found a match, update width and frequency of both endpoints.
- if (p->WidthIn != HT_LIST_TERMINAL) {
- Port0->SelWidthIn = p->WidthIn;
- Port1->SelWidthOut = p->WidthIn;
- }
- if (p->WidthOut != HT_LIST_TERMINAL) {
- Port0->SelWidthOut = p->WidthOut;
- Port1->SelWidthIn = p->WidthOut;
- }
- if (p->Frequency != HT_LIST_TERMINAL) {
- Port0->SelFrequency = p->Frequency;
- Port1->SelFrequency = p->Frequency;
- }
- break;
- } else {
- p++;
- }
- }
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbCoherent.c b/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbCoherent.c
deleted file mode 100644
index 304888fca6..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbCoherent.c
+++ /dev/null
@@ -1,491 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Coherent Feature Northbridge routines.
- *
- * Provide access to hardware for routing, coherent discovery.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "htNb.h"
-#include "htNbCommonHardware.h"
-#include "htNbCoherent.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_NBCOMMON_HTNBCOHERENT_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/***************************************************************************
- *** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS ***
- ***************************************************************************/
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Establish a Temporary route from one Node to another.
- *
- * @HtNbMethod{::F_WRITE_ROUTING_TABLE}
- *
- * This routine will modify the routing tables on the
- * SourceNode to cause it to route both request and response traffic to the
- * targetNode through the specified Link.
- *
- * @note: This routine is to be used for early discovery and initialization. The
- * final routing tables must be loaded some other way because this
- * routine does not address the issue of probes, or independent request
- * response paths.
- *
- * @param[in] Node the Node that will have it's routing tables modified.
- * @param[in] Target For routing to Node target
- * @param[in] Link Link from Node to target
- * @param[in] Nb this northbridge
- */
-VOID
-WriteRoutingTable (
- IN UINT8 Node,
- IN UINT8 Target,
- IN UINT8 Link,
- IN NORTHBRIDGE *Nb
- )
-{
- PCI_ADDR Reg;
- UINT32 Temp;
-
- ASSERT ((Node < MAX_NODES) && (Target < MAX_NODES) && (Link < Nb->MaxLinks));
- Temp = (Nb->SelfRouteResponseMask | Nb->SelfRouteRequestMask) << (Link + 1);
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_ROUTE0_0X40 + (Target * 4));
- LibAmdPciWrite (AccessWidth32, Reg, &Temp, Nb->ConfigHandle);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Modifies the NodeID register on the target Node
- *
- * @HtNbMethod{::F_WRITE_NODEID}
- *
- * @param[in] Node the Node that will have its NodeID altered.
- * @param[in] NodeID the new value for NodeID
- * @param[in] Nb this northbridge
- */
-VOID
-WriteNodeID (
- IN UINT8 Node,
- IN UINT8 NodeID,
- IN NORTHBRIDGE *Nb
- )
-{
- PCI_ADDR Reg;
- UINT32 Temp;
- Temp = NodeID;
- ASSERT ((Node < MAX_NODES) && (NodeID < MAX_NODES));
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_NODE_ID_0X60);
- LibAmdPciWriteBits (Reg, 2, 0, &Temp, Nb->ConfigHandle);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Read the Default Link
- *
- * @HtNbMethod{::F_READ_DEFAULT_LINK}
- *
- * Read the DefLnk (the source Link of the current packet) from Node. Since this code
- * is running on the BSP, this should be the Link pointing back towards the BSP.
- *
- * @param[in] Node the Node that will have its NodeID altered.
- * @param[in] Nb this northbridge
- *
- * @return The HyperTransport Link where the request to
- * read the default Link came from.
- */
-UINT8
-ReadDefaultLink (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT32 DefaultLink;
- PCI_ADDR Reg;
- UINT32 Temp;
-
- DefaultLink = 0;
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_LINK_INIT_CONTROL_0X6C);
-
- ASSERT ((Node < MAX_NODES));
- LibAmdPciReadBits (Reg, 3, 2, &DefaultLink, Nb->ConfigHandle);
- LibAmdPciReadBits (Reg, 8, 8, &Temp, Nb->ConfigHandle);
- DefaultLink |= (Temp << 2);
- return (UINT8)DefaultLink;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Turns routing tables on for a given Node
- *
- * @HtNbMethod{::F_ENABLE_ROUTING_TABLES}
- *
- * @param[in] Node the Node that will have it's routing tables enabled
- * @param[in] Nb this northbridge
- */
-VOID
-EnableRoutingTables (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- )
-{
- PCI_ADDR Reg;
- UINT32 Temp;
- Temp = 0;
- ASSERT ((Node < MAX_NODES));
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_LINK_INIT_CONTROL_0X6C);
- LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Turns routing tables off for a given Node
- *
- * @HtNbMethod{::F_DISABLE_ROUTING_TABLES}
- *
- * @param[in] Node the Node that will have it's routing tables disabled
- * @param[in] Nb this northbridge
- */
-VOID
-DisableRoutingTables (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- )
-{
- PCI_ADDR Reg;
- UINT32 Temp;
- Temp = 1;
- ASSERT ((Node < MAX_NODES));
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_LINK_INIT_CONTROL_0X6C);
- LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Verify that the Link is coherent, connected, and ready
- *
- * @HtNbMethod{::F_VERIFY_LINK_IS_COHERENT}
- *
- * @param[in] Node the Node that will be examined
- * @param[in] Link the Link on that Node to examine
- * @param[in] Nb this northbridge
- *
- * @retval TRUE The Link has the following status
- * - LinkCon=1, Link is connected
- * - InitComplete=1, Link initialization is complete
- * - NC=0, Link is coherent
- * - UniP-cLDT=0, Link is not Uniprocessor cLDT
- * - LinkConPend=0 Link connection is not pending
- * @retval FALSE The Link has some other status
-*/
-BOOLEAN
-VerifyLinkIsCoherent (
- IN UINT8 Node,
- IN UINT8 Link,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT32 LinkType;
- PCI_ADDR LinkBase;
-
- ASSERT ((Node < MAX_NODES) && (Link < Nb->MaxLinks));
-
- LinkBase = Nb->MakeLinkBase (Node, Link, Nb);
-
- // FN0_98/A4/C4 = LDT Type Register
- LinkBase.Address.Register += HTHOST_LINK_TYPE_REG;
- LibAmdPciRead (AccessWidth32, LinkBase, &LinkType, Nb->ConfigHandle);
-
- // Verify LinkCon = 1, InitComplete = 1, NC = 0, UniP-cLDT = 0, LinkConPend = 0
- return (BOOLEAN) ((LinkType & HTHOST_TYPE_MASK) == HTHOST_TYPE_COHERENT);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Read the token stored in the scratchpad register field.
- *
- * @HtNbMethod{::F_READ_TOKEN}
- *
- * Use the CPU core count as a scratch pad.
- *
- * @note The location used to store the token is arbitrary. The only requirement is
- * that the location warm resets to zero, and that using it will have no ill-effects
- * during HyperTransport initialization.
- *
- * @param[in] Node the Node that will be examined
- * @param[in] Nb this northbridge
- *
- * @return the Token read from the Node
- */
-UINT8
-ReadToken (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT32 Temp;
- PCI_ADDR Reg;
-
- ASSERT ((Node < MAX_NODES));
- // Use CpuCnt as a scratch register
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_NODE_ID_0X60);
- LibAmdPciReadBits (Reg, 19, 16, &Temp, Nb->ConfigHandle);
-
- return (UINT8)Temp;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Write the token stored in the scratchpad register
- *
- * @HtNbMethod{::F_WRITE_TOKEN}
- *
- * Use the CPU core count as a scratch pad.
- *
- * @note The location used to store the token is arbitrary. The only requirement is
- * that the location warm resets to zero, and that using it will have no ill-effects
- * during HyperTransport initialization.
- *
- * @param[in] Node the Node that marked with token
- * @param[in] Value the token Value
- * @param[in] Nb this northbridge
- */
-VOID
-WriteToken (
- IN UINT8 Node,
- IN UINT8 Value,
- IN NORTHBRIDGE *Nb
- )
-{
- PCI_ADDR Reg;
- UINT32 Temp;
- Temp = Value;
- ASSERT ((Node < MAX_NODES));
- // Use CpuCnt as a scratch register
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_NODE_ID_0X60);
- LibAmdPciWriteBits (Reg, 19, 16, &Temp, Nb->ConfigHandle);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Full Routing Table Register initialization
- *
- * @HtNbMethod{::F_WRITE_FULL_ROUTING_TABLE}
- *
- * Write the routing table entry for Node to target, using the request Link, response
- * Link, and broadcast Links provided.
- *
- * @param[in] Node the Node that will be examined
- * @param[in] Target the Target Node for these routes
- * @param[in] ReqLink the Link for requests to Target
- * @param[in] RspLink the Link for responses to Target
- * @param[in] BroadcastLinks the broadcast Links
- * @param[in] Nb this northbridge
- */
-VOID
-WriteFullRoutingTable (
- IN UINT8 Node,
- IN UINT8 Target,
- IN UINT8 ReqLink,
- IN UINT8 RspLink,
- IN UINT32 BroadcastLinks,
- IN NORTHBRIDGE *Nb
- )
-{
- PCI_ADDR Reg;
- UINT32 Value;
-
- Value = 0;
- ASSERT ((Node < MAX_NODES) && (Target < MAX_NODES));
- if (ReqLink == ROUTE_TO_SELF) {
- Value |= Nb->SelfRouteRequestMask;
- } else {
- Value |= Nb->SelfRouteRequestMask << (ReqLink + 1);
- }
-
- if (RspLink == ROUTE_TO_SELF) {
- Value |= Nb->SelfRouteResponseMask;
- } else {
- Value |= Nb->SelfRouteResponseMask << (RspLink + 1);
- }
-
- // Allow us to accept a Broadcast ourselves, then set broadcasts for routes
- Value |= (UINT32)1 << Nb->BroadcastSelfBit;
- Value |= (UINT32)BroadcastLinks << (Nb->BroadcastSelfBit + 1);
-
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_ROUTE0_0X40 + (Target * 4));
- LibAmdPciWrite (AccessWidth32, Reg, &Value, Nb->ConfigHandle);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Determine whether a Node is compatible with the discovered configuration so far.
- *
- * @HtNbMethod{::F_IS_ILLEGAL_TYPE_MIX}.
- *
- * Currently, that means the family, extended family of the new Node are the
- * same as the BSP's.
- *
- * @param[in] Node the Node
- * @param[in] Nb this northbridge
- *
- * @retval TRUE the new node is not compatible
- * @retval FALSE the new node is compatible
- */
-BOOLEAN
-IsIllegalTypeMix (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- )
-{
- return ((BOOLEAN) ((Nb->MakeKey (Node, Nb) & Nb->CompatibleKey) == 0));
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Fix (hopefully) exceptional conditions.
- *
- * @HtNbMethod{::F_HANDLE_SPECIAL_NODE_CASE}.
- *
- * Currently, this routine is implemented for all coherent HT families to check
- * vendor ID of coherent Node. If the vendor ID is 0x1022 then return FALSE,
- * or return TRUE.
- *
- * @param[in] Node The Node which need to be checked.
- * @param[in] Link The link to check for special conditions.
- * @param[in] State our global state.
- * @param[in] Nb this northbridge.
- *
- * @retval TRUE This node received special handling.
- * @retval FALSE This node was not handled specially, handle it normally.
- *
- */
-BOOLEAN
-HandleSpecialNodeCase (
- IN UINT8 Node,
- IN UINT8 Link,
- IN STATE_DATA *State,
- IN NORTHBRIDGE *Nb
- )
-{
- BOOLEAN Result;
- PCI_ADDR Reg;
- UINT32 VendorID;
-
- Result = TRUE;
-
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- 0,
- 0);
-
- LibAmdPciReadBits (Reg, 15, 0, &VendorID, Nb->ConfigHandle);
- if (VendorID == 0x1022) {
- Result = FALSE;
- }
-
- return Result;
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbCoherent.h b/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbCoherent.h
deleted file mode 100644
index 72b8e967f2..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbCoherent.h
+++ /dev/null
@@ -1,177 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Coherent Feature Northbridge common routines.
- *
- * Provide access to hardware for routing, coherent discovery.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-/***************************************************************************
- *** FAMILY/NORTHBRIDGE GENERIC FUNCTIONS ***
- ***************************************************************************/
-
-/**
- * Establish a Temporary route from one Node to another.
- *
- */
-VOID
-WriteRoutingTable (
- IN UINT8 Node,
- IN UINT8 Target,
- IN UINT8 Link,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Modifies the NodeID register on the target Node
- *
- */
-VOID
-WriteNodeID (
- IN UINT8 Node,
- IN UINT8 NodeID,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Read the Default Link
- *
- */
-UINT8
-ReadDefaultLink (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Turns routing tables on for a given Node
- *
- */
-VOID
-EnableRoutingTables (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Turns routing tables off for a given Node
- *
- */
-VOID
-DisableRoutingTables (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Verify that the Link is coherent, connected, and ready
- *
-*/
-BOOLEAN
-VerifyLinkIsCoherent (
- IN UINT8 Node,
- IN UINT8 Link,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Read the token stored in the scratchpad register field.
- *
- */
-UINT8
-ReadToken (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Write the token stored in the scratchpad register
- *
- */
-VOID
-WriteToken (
- IN UINT8 Node,
- IN UINT8 Value,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Full Routing Table Register initialization
- *
- */
-VOID
-WriteFullRoutingTable (
- IN UINT8 Node,
- IN UINT8 Target,
- IN UINT8 ReqLink,
- IN UINT8 RspLink,
- IN UINT32 BroadcastLinks,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Determine whether a Node is compatible with the discovered configuration so far.
- *
- */
-BOOLEAN
-IsIllegalTypeMix (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Fix (hopefully) exceptional conditions.
- *
- */
-BOOLEAN
-HandleSpecialNodeCase (
- IN UINT8 Node,
- IN UINT8 Link,
- IN STATE_DATA *State,
- IN NORTHBRIDGE *Nb
- );
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbNonCoherent.c b/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbNonCoherent.c
deleted file mode 100644
index 5c0dc58731..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbNonCoherent.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Northbridge generic non-coherent support routines.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "htNb.h"
-#include "htNbCommonHardware.h"
-#include "htNbNonCoherent.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_NBCOMMON_HTNBNONCOHERENT_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/***************************************************************************
- *** Non-coherent init code ***
- *** Northbridge access routines ***
- ***************************************************************************/
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Return the Link to the Southbridge
- *
- * @HtNbMethod{::F_READ_SB_LINK}
- *
- * @param[in] Nb this northbridge
- *
- * @return the Link to the southbridge
- */
-UINT8
-ReadSouthbridgeLink (
- IN NORTHBRIDGE *Nb
- )
-{
- UINT32 Temp;
- PCI_ADDR Reg;
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (0),
- MakePciBusFromNode (0),
- MakePciDeviceFromNode (0),
- CPU_HTNB_FUNC_00,
- REG_UNIT_ID_0X64);
- LibAmdPciReadBits (Reg, 10, 8, &Temp, Nb->ConfigHandle);
- return (UINT8)Temp;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Verify that the Link is non-coherent, connected, and ready
- *
- * @HtNbMethod{::F_VERIFY_LINK_IS_NON_COHERENT}
- *
- * @param[in] Node the Node that will be examined
- * @param[in] Link the Link on that Node to examine
- * @param[in] Nb this northbridge
- *
- * @retval TRUE The Link has the following status
- * - LinkCon=1, Link is connected
- * - InitComplete=1, Link initialization is complete
- * - NC=1, Link is noncoherent
- * - UniP-cLDT=0, Link is not Uniprocessor cLDT
- * - LinkConPend=0 Link connection is not pending
- * @retval FALSE The Link has some other status
- */
-BOOLEAN
-VerifyLinkIsNonCoherent (
- IN UINT8 Node,
- IN UINT8 Link,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT32 LinkType;
- PCI_ADDR LinkBase;
-
- ASSERT ((Node < MAX_NODES) && (Link < MAX_NODES));
-
- LinkBase = Nb->MakeLinkBase (Node, Link, Nb);
- LinkBase.Address.Register += HTHOST_LINK_TYPE_REG;
-
- // FN0_98/A4/C4 = LDT Type Register
- LibAmdPciRead (AccessWidth32, LinkBase, &LinkType, Nb->ConfigHandle);
-
- // Verify LinkCon = 1, InitComplete = 1, NC = 1, UniP-cLDT = 0, LinkConPend = 0
- return (BOOLEAN) ((LinkType & HTHOST_TYPE_MASK) == HTHOST_TYPE_NONCOHERENT);
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbNonCoherent.h b/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbNonCoherent.h
deleted file mode 100644
index f73fe1a032..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbNonCoherent.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Northbridge generic non-coherent support routines.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/**
- * Return the Link to the Southbridge
- */
-UINT8
-ReadSouthbridgeLink (
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Verify that the Link is non-coherent, connected, and ready
- *
- */
-BOOLEAN
-VerifyLinkIsNonCoherent (
- IN UINT8 Node,
- IN UINT8 Link,
- IN NORTHBRIDGE *Nb
- );
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbOptimization.c b/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbOptimization.c
deleted file mode 100644
index 9915b36098..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbOptimization.c
+++ /dev/null
@@ -1,257 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Link optimization support.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "IdsHt.h"
-#include "htInterface.h"
-#include "htInterfaceGeneral.h"
-#include "htNotify.h"
-#include "htNb.h"
-#include "htNbCommonHardware.h"
-#include "htNbOptimization.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_NBCOMMON_HTNBOPTIMIZATION_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/***************************************************************************
- *** Link Optimization ***
- ***************************************************************************/
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get Link features into system data structure.
- *
- * @HtNbMethod{::F_GATHER_LINK_FEATURES}
- *
- * For a specific discovered CPU Link, populate the port list with the frequency
- * capabilities. Support for other link oriented capabilities, currently:
- * - Unit ID Clumping. Set to disabled. This doesn't mean the CPU doesn't support clumping,
- * it just means:
- * - The CPU doesn't clump its host unit ids, and
- * - We don't have to check as carefully in SetLinkData whether the port is an IO host link.
- *
- * @param[in,out] ThisPort The PortList structure entry for this link's port
- * @param[in] Interface Access to non-HT support functions.
- * @param[in] PlatformConfig Platform profile/build option config structure.
- * @param[in] Nb this northbridge
- */
-VOID
-GatherLinkFeatures (
- IN OUT PORT_DESCRIPTOR *ThisPort,
- IN HT_INTERFACE *Interface,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN NORTHBRIDGE *Nb
- )
-{
- PCI_ADDR Reg;
- UINT32 Frequency;
- UINT32 ExtendedFrequency;
-
- Reg = ThisPort->Pointer;
- Reg.Address.Register += HTHOST_FREQ_REV_REG;
- LibAmdPciReadBits (Reg, 30, 16, &Frequency, Nb->ConfigHandle);
- Reg = ThisPort->Pointer;
- Reg.Address.Register += HTHOST_FREQ_EXTENSION;
- LibAmdPciReadBits (Reg, 15, 1, &ExtendedFrequency, Nb->ConfigHandle);
- ThisPort->PrvFrequencyCap = ((Frequency | (ExtendedFrequency << HT_FREQUENCY_2800M)) &
- Nb->NorthBridgeFreqMask (ThisPort->NodeID, Interface, PlatformConfig, Nb));
- // Check for Internal link restriction not to run at 1000 MHz (but allow lower)
- if (IsPackageLinkInternal (Nb->GetPackageLink (ThisPort->NodeID, ThisPort->Link, Nb))) {
- ThisPort->PrvFrequencyCap &= ~(HT_FREQUENCY_LIMIT_1000M & ~HT_FREQUENCY_LIMIT_800M);
- }
- ThisPort->ClumpingSupport = HT_CLUMPING_DISABLE;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Change the hardware state for all Links according to the now optimized data in the
- * port list data structure for link reganging.
- *
- * @HtNbMethod{::F_SET_LINK_REGANG}
- *
- * @param[in] Node the node on which to regang a link
- * @param[in] Link the sublink 0 of the sublink pair to regang
- * @param[in] Nb this northbridge
- */
-VOID
-SetLinkRegang (
- IN UINT8 Node,
- IN UINT8 Link,
- IN NORTHBRIDGE *Nb
- )
-{
- PCI_ADDR Reg;
- UINT32 Temp;
-
- Temp = 1;
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_HT_LINK_EXT_CONTROL0_0X170 + (4 * Link));
-
- LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Change the hardware state for all Links according to the now optimized data in the
- * port list data structure for Unit Id Clumping.
- *
- * @HtNbMethod{::F_SET_LINK_UNITID_CLUMPING}
- *
- * This applies to the host root of a non-coherent chain.
- *
- * @param[in] Node the node on which to enable clumping
- * @param[in] Link the link for which to enable clumping
- * @param[in] ClumpingEnables the unit id clumping enables
- * @param[in] Nb this northbridge
- */
-VOID
-SetLinkUnitIdClumping (
- IN UINT8 Node,
- IN UINT8 Link,
- IN UINT32 ClumpingEnables,
- IN NORTHBRIDGE *Nb
- )
-{
- PCI_ADDR Reg;
-
- // Host Unit Ids are not clumped.
- ASSERT ((ClumpingEnables & 0x3) == 0);
-
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_HT_LINK_CLUMPING0_0X110 + (4 * Link));
-
- LibAmdPciWriteBits (Reg, 31, 0, &ClumpingEnables, Nb->ConfigHandle);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Change the hardware state for all Links according to the now optimized data in the
- * port list data structure for link frequency.
- *
- * @HtNbMethod{::F_SET_LINK_FREQUENCY}
- *
- * Handle extended frequencies. For HT3 frequencies, ensure Retry and Scrambling are
- * set. For HT1, clear them.
- *
- * @param[in] Node the node on which to set frequency for a link
- * @param[in] Link the link to set frequency
- * @param[in] Frequency the frequency to set
- * @param[in] Nb this northbridge
- */
-VOID
-SetLinkFrequency (
- IN UINT8 Node,
- IN UINT8 Link,
- IN UINT8 Frequency,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT32 Temp;
- PCI_ADDR Reg;
-
- ASSERT ((Frequency >= HT_FREQUENCY_600M && Frequency <= HT_FREQUENCY_3200M)
- || (Frequency == HT_FREQUENCY_200M) || (Frequency == HT_FREQUENCY_400M));
-
- // Handle extended frequencies, 2800 MHz and above. 31 > Frequency > 16 in this case.
- if (Frequency > HT_FREQUENCY_2600M) {
- Temp = 1;
- } else {
- // Clear it if not extended.
- Temp = 0;
- }
- Reg = Nb->MakeLinkBase (Node, Link, Nb);
- Reg.Address.Register += HTHOST_FREQ_EXTENSION;
- LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
- Reg = Nb->MakeLinkBase (Node, Link, Nb);
- Reg.Address.Register += HTHOST_FREQ_REV_REG;
- Temp = (Frequency & 0x0F);
- LibAmdPciWriteBits (Reg, 11, 8, &Temp, Nb->ConfigHandle);
- // Gen1 = 200Mhz -> 1000MHz, Gen3 = 1200MHz -> 2600MHz
- if (Frequency > HT_FREQUENCY_1000M) {
- // Enable for Gen3 frequencies
- Temp = 1;
- } else {
- // Disable for Gen1 frequencies
- Temp = 0;
- }
- // HT3 retry mode enable / disable
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_HT_LINK_RETRY0_0X130 + (4 * Link));
- LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
- // and Scrambling enable / disable
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_HT_LINK_EXT_CONTROL0_0X170 + (4 * Link));
- LibAmdPciWriteBits (Reg, 3, 3, &Temp, Nb->ConfigHandle);
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbOptimization.h b/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbOptimization.h
deleted file mode 100644
index 3a273a4e4f..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbOptimization.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Link optimization generic support.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/**
- * Get Link features into system data structure.
- *
- */
-VOID
-GatherLinkFeatures (
- IN OUT PORT_DESCRIPTOR *ThisPort,
- IN HT_INTERFACE *Interface,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Change the hardware state for all Links according to the now optimized data in the
- * port list data structure.
- *
- */
-VOID
-SetLinkRegang (
- IN UINT8 Node,
- IN UINT8 Link,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Set the link's Unit Id Clumping enable.
- *
- */
-VOID
-SetLinkUnitIdClumping (
- IN UINT8 Node,
- IN UINT8 Link,
- IN UINT32 ClumpingEnables,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Change the hardware state for all Links according to the now optimized data in the
- * port list data structure.
- */
-VOID
-SetLinkFrequency (
- IN UINT8 Node,
- IN UINT8 Link,
- IN UINT8 Frequency,
- IN NORTHBRIDGE *Nb
- );
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbUtilities.c b/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbUtilities.c
deleted file mode 100644
index 6320085f65..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbUtilities.c
+++ /dev/null
@@ -1,334 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Northbridge utility routines.
- *
- * These routines are needed for support of more than one feature area.
- * Collect them in this file so build options don't remove them.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "htNotify.h"
-#include "htNb.h"
-#include "htNbCommonHardware.h"
-#include "htNbUtilities.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_NBCOMMON_HTNBUTILITIES_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Return the HT Host capability base PCI config address for a Link.
- *
- * @HtNbMethod{::F_MAKE_LINK_BASE}
- *
- * @param[in] Node the Node this Link is on
- * @param[in] Link the Link
- * @param[in] Nb this northbridge
- *
- * @return the pci config address
- */
-PCI_ADDR
-MakeLinkBase (
- IN UINT8 Node,
- IN UINT8 Link,
- IN NORTHBRIDGE *Nb
- )
-{
- PCI_ADDR LinkBase;
-
- ASSERT (Nb != NULL);
- if (Link < 4) {
- LinkBase.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_HT_CAP_BASE_0X80 + Link*HT_HOST_CAP_SIZE);
- } else {
- LinkBase.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_04,
- REG_HT_CAP_BASE_0X80 + (Link - 4)*HT_HOST_CAP_SIZE);
- }
- return LinkBase;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Return the LinkFailed status AFTER an attempt is made to clear the bit.
- *
- * @HtNbMethod{::F_READ_TRUE_LINK_FAIL_STATUS}
- *
- * Dependency!: HT_FEATURES::SetHtControlRegisterBits
- *
- * Also, call event notify if a Hardware Fault caused a sync flood on a previous boot.
- *
- * The table below summarizes correct responses of this routine.
- * <TABLE>
- * <TR><TD> Family </TD> <TD> before </TD> <TD> after </TD> <TD> unconnected </TD> <TD> Notify? </TD> <TD> return </TD></TR>
- * <TR><TD> 10 </TD> <TD> 0 </TD> <TD> 0 </TD> <TD> 0 </TD> <TD> No </TD> <TD> FALSE </TD></TR>
- * <TR><TD> 10 </TD> <TD> 1 </TD> <TD> 0 </TD> <TD> 0 </TD> <TD> Yes </TD> <TD> FALSE </TD></TR>
- * <TR><TD> 10 </TD> <TD> 1 </TD> <TD> 0 </TD> <TD> 3 </TD> <TD> No </TD> <TD> TRUE </TD></TR>
- * </TABLE>
- *
- * @param[in] Node the Node that will be examined
- * @param[in] Link the Link on that Node to examine
- * @param[in] State access to call back routine
- * @param[in] Nb this northbridge
- *
- * @retval TRUE the Link is not connected or has hard error
- * @retval FALSE the Link is connected
- */
-BOOLEAN
-ReadTrueLinkFailStatus (
- IN UINT8 Node,
- IN UINT8 Link,
- IN STATE_DATA *State,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT32 Before;
- UINT32 After;
- UINT32 Unconnected;
- UINT32 Crc;
- PCI_ADDR Reg;
-
- ASSERT ((Node < MAX_NODES) && (Link < Nb->MaxLinks));
-
- Reg = Nb->MakeLinkBase (Node, Link, Nb);
- Reg.Address.Register += HTHOST_LINK_CONTROL_REG;
-
- // Save the CRC status before doing anything else.
- // Read, Clear, re-read the error bits in the Link Control Register
- // (FN0_84/A4/C4[4] = LinkFail bit),
- // and check the connection status, TransOff and EndOfChain.
- //
- LibAmdPciReadBits (Reg, 9, 8, &Crc, Nb->ConfigHandle);
- LibAmdPciReadBits (Reg, 4, 4, &Before, Nb->ConfigHandle);
- State->HtFeatures->SetHtControlRegisterBits (Reg, 4, 4, &Before, State);
- LibAmdPciReadBits (Reg, 4, 4, &After, Nb->ConfigHandle);
- LibAmdPciReadBits (Reg, 7, 6, &Unconnected, Nb->ConfigHandle);
-
- if (Before != After) {
- if (Unconnected == 0) {
- if (Crc != 0) {
- // A sync flood occurred due to HT CRC
- // Pass the Node and Link on which the generic sync flood event occurred.
- NotifyAlertHwHtCrc (Node, Link, (UINT8)Crc, State);
- } else {
- // Some sync flood occurred
- // Pass the Node and Link on which the generic sync flood event occurred.
- NotifyAlertHwSyncFlood (Node, Link, State);
- }
- }
- }
- return (BOOLEAN) ((After != 0) || (Unconnected != 0));
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Write the total number of cores and Nodes to the Node
- *
- * @HtNbMethod{::F_SET_TOTAL_NODES_AND_CORES}
- *
- * @param[in] Node the Node that will be examined
- * @param[in] TotalNodes the total number of Nodes
- * @param[in] TotalCores the total number of cores
- * @param[in] Nb this northbridge
- */
-VOID
-SetTotalNodesAndCores (
- IN UINT8 Node,
- IN UINT8 TotalNodes,
- IN UINT8 TotalCores,
- IN NORTHBRIDGE *Nb
- )
-{
- PCI_ADDR NodeIDReg;
- UINT32 Temp;
-
- ASSERT ((Node < MAX_NODES) && (TotalNodes <= MAX_NODES));
- NodeIDReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_NODE_ID_0X60);
-
- Temp = ((TotalCores - 1) & HTREG_NODE_CPUCNT_4_0);
- LibAmdPciWriteBits (NodeIDReg, 20, 16, &Temp, Nb->ConfigHandle);
- Temp = TotalNodes - 1;
- LibAmdPciWriteBits (NodeIDReg, 6, 4, &Temp, Nb->ConfigHandle);
-
- NodeIDReg.Address.Register = REG_HT_EXTENDED_NODE_ID_F0X160;
-
- Temp = (((TotalCores - 1) & HTREG_EXTNODE_CPUCNT_7_5) >> 5);
- LibAmdPciWriteBits (NodeIDReg, 18, 16, &Temp, Nb->ConfigHandle);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get the Count (1 based) of Nodes in the system.
- *
- * @HtNbMethod{::F_GET_NODE_COUNT}
- *
- * This is intended to support AP Core HT init, since the Discovery State data is not
- * available (State->NodesDiscovered), there needs to be this way to find the number
- * of Nodes. The Node count can be read from the BSP.
- *
- * @param[in] Nb this northbridge
- *
- * @return The number of nodes
- */
-UINT8
-GetNodeCount (
- IN NORTHBRIDGE *Nb
- )
-{
- PCI_ADDR NodeIDReg;
- UINT32 Temp;
-
- NodeIDReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (0),
- MakePciBusFromNode (0),
- MakePciDeviceFromNode (0),
- CPU_HTNB_FUNC_00,
- REG_NODE_ID_0X60);
- LibAmdPciReadBits (NodeIDReg, 6, 4, &Temp, Nb->ConfigHandle);
- return ((UINT8) (++Temp));
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Limit coherent config accesses to cpus as indicated by Nodecnt.
- *
- * @HtNbMethod{::F_LIMIT_NODES}
- *
- * @param[in] Node the Node that will be examined
- * @param[in] Nb this northbridge
- */
-VOID
-LimitNodes (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT32 Temp;
- PCI_ADDR Reg;
-
- Temp = 1;
- ASSERT ((Node < MAX_NODES));
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_LINK_TRANS_CONTROL_0X68);
- LibAmdPciWriteBits (Reg, 15, 15, &Temp, Nb->ConfigHandle);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get the Package Link number, given the node and real link number.
- *
- * @HtNbMethod{::F_GET_PACKAGE_LINK}
- *
- * Based on the link to package link mapping from BKDG, look up package link for
- * the input link on the internal node number corresponding to Node id.
- *
- * @param[in] Node the node which has this link
- * @param[in] Link the link on that node
- * @param[in] Nb this northbridge
- *
- * @return the Package Link, HT_LIST_TERMINAL Not connected in package, HT_LIST_MATCH_INTERNAL_LINK package internal link.
- *
- */
-UINT8
-GetPackageLink (
- IN UINT8 Node,
- IN UINT8 Link,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT8 ModuleType;
- UINT8 Module;
- UINTN PackageLinkMapItem;
- UINT8 PackageLink;
-
- ASSERT ((Node < MAX_NODES) && (Link < Nb->MaxLinks));
- PackageLink = HT_LIST_TERMINAL;
-
- Nb->GetModuleInfo (Node, &ModuleType, &Module, Nb);
-
- if (ModuleType != 0) {
- ASSERT (Nb->PackageLinkMap != NULL);
- // Use table to find this module's package link
- PackageLinkMapItem = 0;
- while ((*Nb->PackageLinkMap)[PackageLinkMapItem].Link != HT_LIST_TERMINAL) {
- if (((*Nb->PackageLinkMap)[PackageLinkMapItem].Module == Module) &&
- ((*Nb->PackageLinkMap)[PackageLinkMapItem].Link == Link)) {
- PackageLink = (*Nb->PackageLinkMap)[PackageLinkMapItem].PackageLink;
- break;
- }
- PackageLinkMapItem++;
- }
- } else {
- PackageLink = Link;
- }
- return PackageLink;
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbUtilities.h b/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbUtilities.h
deleted file mode 100644
index 896915a9df..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/NbCommon/htNbUtilities.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Northbridge utility routines.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/**
- * Return the HT Host capability base PCI config address for a Link.
- *
- */
-PCI_ADDR
-MakeLinkBase (
- IN UINT8 Node,
- IN UINT8 Link,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Return the LinkFailed status AFTER an attempt is made to clear the bit.
- *
- */
-BOOLEAN
-ReadTrueLinkFailStatus (
- IN UINT8 Node,
- IN UINT8 Link,
- IN STATE_DATA *State,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Write the total number of cores and Nodes to the Node
- *
- */
-VOID
-SetTotalNodesAndCores (
- IN UINT8 Node,
- IN UINT8 TotalNodes,
- IN UINT8 TotalCores,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Get the Count (1 based) of Nodes in the system.
- *
- */
-UINT8
-GetNodeCount (
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Limit coherent config accesses to cpus as indicated by Nodecnt.
- *
- */
-VOID
-LimitNodes (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Get the Package Link number, given the node and real link number.
- *
- */
-UINT8
-GetPackageLink (
- IN UINT8 Node,
- IN UINT8 Link,
- IN NORTHBRIDGE *Nb
- );
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph.c
deleted file mode 100644
index 5b5517b443..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Routines to deal with topology data.
- *
- * Access the topologies and information about a topology.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
-*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "htGraph.h"
-#include "OptionsHt.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_HTGRAPH_HTGRAPH_FILECODE
-
-extern OPTION_HT_CONFIGURATION OptionHtConfiguration;
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Returns the AGESA built in topology list
- *
- * @param[out] List a pointer to the built in topology list
- */
-VOID
-GetAmdTopolist (
- OUT UINT8 ***List
- )
-{
- // Cast below to hush CONST warning. The built in list must be CONST to be in ROM statically.
- // The caller of this routine may get a topolist pointer from the interface, however, and
- // that is not CONST, since it could be on the stack.
- //
- *List = (UINT8 **)OptionHtConfiguration.HtOptionBuiltinTopologies;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Returns the number of Nodes in the compressed graph
- *
- * @param[in] Graph a compressed graph
- *
- * @return the number of Nodes in the graph
- */
-UINT8
-GraphHowManyNodes (
- IN UINT8 *Graph
- )
-{
- return Graph[0];
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Returns true if NodeA is directly connected to NodeB, false otherwise
- *
- * if NodeA == NodeB also returns false.
- * Relies on rule that directly connected Nodes always route requests directly.
- *
- * @param[in] Graph the graph to examine
- * @param[in] NodeA the Node number of the first Node
- * @param[in] NodeB the Node number of the second Node
- *
- * @retval TRUE NodeA connects to NodeB
- * @retval FALSE NodeA does not connect to NodeB
- */
-BOOLEAN
-GraphIsAdjacent (
- IN UINT8 *Graph,
- IN UINT8 NodeA,
- IN UINT8 NodeB
- )
-{
- UINT8 size;
- size = Graph[0];
- ASSERT ((NodeA < size) && (NodeB < size));
- return (Graph[1 + (NodeA*size + NodeB)*2 + 1] & 0x0F) == NodeB;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Returns the graph Node used by NodeA to route responses targeted at NodeB.
- *
- * This will be a Node directly connected to NodeA (possibly NodeB itself),
- * or "Route to Self" if NodeA and NodeB are the same Node.
- * Note that all Node numbers are abstract Node numbers of the topology graph,
- * it is the responsibility of the caller to apply any permutation needed.
- *
- * @param[in] Graph the graph to examine
- * @param[in] NodeA the Node number of the first Node
- * @param[in] NodeB the Node number of the second Node
- *
- * @return The response route Node
- */
-UINT8
-GraphGetRsp (
- IN UINT8 *Graph,
- IN UINT8 NodeA,
- IN UINT8 NodeB
- )
-{
- UINT8 size;
- size = Graph[0];
- ASSERT ((NodeA < size) && (NodeB < size));
- return (Graph[1 + (NodeA*size + NodeB)*2 + 1] & 0xF0) >> 4;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Returns the graph Node used by NodeA to route requests targeted at NodeB.
- *
- * This will be a Node directly connected to NodeA (possibly NodeB itself),
- * or "Route to Self" if NodeA and NodeB are the same Node.
- * Note that all Node numbers are abstract Node numbers of the topology graph,
- * it is the responsibility of the caller to apply any permutation needed.
- *
- * @param[in] Graph the graph to examine
- * @param[in] NodeA the Node number of the first Node
- * @param[in] NodeB the Node number of the second Node
- *
- * @return The request route Node
- */
-UINT8
-GraphGetReq (
- IN UINT8 *Graph,
- IN UINT8 NodeA,
- IN UINT8 NodeB
- )
-{
- UINT8 size;
- size = Graph[0];
- ASSERT ((NodeA < size) && (NodeB < size));
- return (Graph[1 + (NodeA*size + NodeB)*2 + 1] & 0x0F);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Returns a bit vector of Nodes that NodeA should forward a broadcast from
- * NodeB towards
- *
- * @param[in] Graph the graph to examine
- * @param[in] NodeA the Node number of the first Node
- * @param[in] NodeB the Node number of the second Node
- *
- * @return the broadcast routes for NodeA from NodeB
- */
-UINT8
-GraphGetBc (
- IN UINT8 *Graph,
- IN UINT8 NodeA,
- IN UINT8 NodeB
- )
-{
- UINT8 size;
- size = Graph[0];
- ASSERT ((NodeA < size) && (NodeB < size));
- return Graph[1 + (NodeA*size + NodeB)*2];
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph1.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph1.c
deleted file mode 100644
index bb024b92f4..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph1.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Single node topology
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/*
- * 0
- */
-/**
- * single node
- */
-/**
- * @dot
- strict graph one {
- node [shape="plaintext"];
- 0;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologySingleNode[] =
-{
- 0x01,
- 0x00, 0xFF // Node 0
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph2.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph2.c
deleted file mode 100644
index 2c4f0d40d4..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph2.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Two nodes.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/*
- * 0---1
- */
-/**
- * Two Nodes.
- */
-/**
- * @dot
- strict graph two {
- node [shape="plaintext"];
- 0 -- 1 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologyDualNode[] =
-{
- 0x02,
- 0x02, 0xFF, 0x00, 0x11, // Node 0
- 0x00, 0x00, 0x01, 0xFF // Node 1
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph3Line.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph3Line.c
deleted file mode 100644
index 5c7909dc03..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph3Line.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Three Line.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/*
- * 2
- * |
- * |
- * 0---1
- */
-/**
- * Three Line
- */
-/**
- * @dot
- strict graph three {
- node [shape="plaintext"];
- 0 -- 1 ;
- 0 -- 2 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologyThreeLine[] =
-{
- 0x03,
- 0x06, 0xFF, 0x04, 0x11, 0x02, 0x22, // Node 0
- 0x00, 0x00, 0x01, 0xFF, 0x00, 0x00, // Node 1
- 0x00, 0x00, 0x00, 0x00, 0x01, 0xFF // Node 2
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph3Triangle.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph3Triangle.c
deleted file mode 100644
index ab01e2c3f3..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph3Triangle.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Three Triangle Topology.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/*
- * 2
- * |\
- * | \
- * 0---1
- */
-/**
- * Three triangle
- */
-/**
- * @dot
- strict graph triangle {
- node [shape="plaintext"];
- 0 -- 1 ;
- 0 -- 2 ;
- 1 -- 2 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologyTriangle[] =
-{
- 0x03,
- 0x06, 0xFF, 0x00, 0x11, 0x00, 0x22, // Node 0
- 0x00, 0x00, 0x05, 0xFF, 0x00, 0x22, // Node 1
- 0x00, 0x00, 0x00, 0x11, 0x03, 0xFF // Node 2
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph4Degenerate.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph4Degenerate.c
deleted file mode 100644
index 828873ee7d..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph4Degenerate.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Four node degenerate.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-/*
- * 2 3
- * |\ |
- * | \|
- * 0---1
- */
-/**
- * Four Node degenerate
- */
-/**
- * @dot
- strict graph degen4 {
- node [shape="plaintext"];
- {rank=same; 0; 1}
- {rank=same; 2; 3}
- 0 -- 1 ;
- 0 -- 2 ;
- 1 -- 2 ;
- 1 -- 3 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologyFourDegenerate[] =
-{
- 0x04,
- 0x06, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x11, // Node 0
- 0x08, 0x00, 0x0D, 0xFF, 0x08, 0x22, 0x05, 0x33, // Node 1
- 0x00, 0x00, 0x00, 0x11, 0x03, 0xFF, 0x00, 0x11, // Node 2
- 0x00, 0x11, 0x00, 0x11, 0x00, 0x11, 0x02, 0xFF // Node 3
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph4FullyConnected.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph4FullyConnected.c
deleted file mode 100644
index 7942efa403..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph4FullyConnected.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Four node fully connected.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/*
- * 2---3
- * |\ /|
- * |/ \|
- * 0---1
- */
-/**
- * Four Node Fully
- */
-/**
- * @dot
- strict graph full4 {
- node [shape="plaintext"];
- {rank=same; 0; 1}
- {rank=same; 2; 3}
- 0 -- 1 ;
- 0 -- 2 ;
- 0 -- 3 ;
- 1 -- 2 ;
- 1 -- 3 ;
- 2 -- 3 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologyFourFully[] =
-{
- 0x04,
- 0x0E, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, // Node 0
- 0x00, 0x00, 0x0D, 0xFF, 0x00, 0x22, 0x00, 0x33, // Node 1
- 0x00, 0x00, 0x00, 0x11, 0x0B, 0xFF, 0x00, 0x33, // Node 2
- 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x07, 0xFF // Node 3
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph4Kite.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph4Kite.c
deleted file mode 100644
index afed99310a..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph4Kite.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Four node kite Topology.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-/*
- * 2---3
- * |\ |
- * | \|
- * 0---1
- */
-/**
- * Four Node kite
- */
-/**
- * @dot
- strict graph kite4 {
- node [shape="plaintext"];
- {rank=same; 0; 1}
- {rank=same; 2; 3}
- 0 -- 1 ;
- 0 -- 2 ;
- 1 -- 2 ;
- 1 -- 3 ;
- 2 -- 3 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologyFourKite[] =
-{
- 0x04,
- 0x06, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x11, // Node 0
- 0x08, 0x00, 0x0D, 0xFF, 0x00, 0x22, 0x00, 0x33, // Node 1
- 0x00, 0x00, 0x00, 0x11, 0x0B, 0xFF, 0x01, 0x33, // Node 2
- 0x00, 0x22, 0x00, 0x11, 0x00, 0x22, 0x06, 0xFF // Node 3
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph4Line.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph4Line.c
deleted file mode 100644
index c1d4859cd4..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph4Line.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Four node Line Topology.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/*
- * 2 3
- * | |
- * | |
- * 0---1
- */
-/**
- * Four Node line
- */
-/**
- * @dot
- strict graph line4 {
- node [shape="plaintext"];
- {rank=same; 0; 1}
- {rank=same; 2; 3}
- 0 -- 1 ;
- 0 -- 2 ;
- 1 -- 3 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologyFourLine[] =
-{
- 0x04,
- 0x06, 0xFF, 0x04, 0x11, 0x02, 0x22, 0x04, 0x11, // Node 0
- 0x08, 0x00, 0x09, 0xFF, 0x08, 0x00, 0x01, 0x33, // Node 1
- 0x00, 0x00, 0x00, 0x00, 0x01, 0xFF, 0x00, 0x00, // Node 2
- 0x00, 0x11, 0x00, 0x11, 0x00, 0x11, 0x02, 0xFF // Node 3
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph4Square.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph4Square.c
deleted file mode 100644
index 2a4d5b5513..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph4Square.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Four node Square Topology.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-/*
- * 2---3
- * | |
- * | |
- * 0---1
- */
-/**
- * Four Node square
- */
-/**
- * @dot
- strict graph square4 {
- node [shape="plaintext"];
- {rank=same; 0; 1}
- {rank=same; 2; 3}
- 0 -- 1 ;
- 0 -- 2 ;
- 1 -- 3 ;
- 2 -- 3 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologyFourSquare[] =
-{
- 0x04,
- 0x06, 0xFF, 0x00, 0x11, 0x02, 0x22, 0x00, 0x22, // Node 0
- 0x00, 0x00, 0x09, 0xFF, 0x00, 0x33, 0x01, 0x33, // Node 1
- 0x08, 0x00, 0x00, 0x00, 0x09, 0xFF, 0x00, 0x33, // Node 2
- 0x00, 0x11, 0x04, 0x11, 0x00, 0x22, 0x06, 0xFF // Node 3
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph4Star.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph4Star.c
deleted file mode 100644
index af9c759988..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph4Star.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Four node Star Topology.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/*
- * 2---3
- * |\
- * | \
- * 0 1
- */
-/**
- * Four Node Star
- */
-/**
- * @dot
- strict graph star4 {
- node [shape="plaintext"];
- {rank=same; 0; 1}
- {rank=same; 2; 3}
- 0 -- 2 ;
- 1 -- 2 ;
- 2 -- 3 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologyFourStar[] =
-{
- 0x04,
- 0x04, 0xFF, 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, // Node 0
- 0x00, 0x22, 0x04, 0xFF, 0x00, 0x22, 0x00, 0x22, // Node 1
- 0x0A, 0x00, 0x09, 0x11, 0x0B, 0xFF, 0x03, 0x33, // Node 2
- 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, 0x04, 0xFF // Node 3
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph5FullyConnected.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph5FullyConnected.c
deleted file mode 100644
index e522d6810a..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph5FullyConnected.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Five node Fully Connected Topology.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/**
- * Five node fully connected
- */
-/**
- * @dot
- strict graph full5 {
- node [shape="plaintext"];
- 0 -- 1 ;
- 0 -- 2 ;
- 0 -- 3 ;
- 0 -- 4 ;
- 1 -- 2 ;
- 1 -- 3 ;
- 1 -- 4 ;
- 2 -- 3 ;
- 2 -- 4 ;
- 3 -- 4 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologyFiveFully[] =
-{
- 0x05,
- 0x1E, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, // Node 0
- 0x00, 0x00, 0x1D, 0xFF, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, // Node 1
- 0x00, 0x00, 0x00, 0x11, 0x1B, 0xFF, 0x00, 0x33, 0x00, 0x44, // Node 2
- 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x17, 0xFF, 0x00, 0x44, // Node 3
- 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x0F, 0xFF // Node 4
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph5TwistedLadder.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph5TwistedLadder.c
deleted file mode 100644
index a31c00ae94..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph5TwistedLadder.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Five node pop order twisted ladder Topology.
- *
- * The population order fall back to five nodes on a twisted ladder.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/*
- *
- * 4
- * |\
- * | \
- * 2 3
- * | |
- * 0---1
- */
-/**
- * Five node twisted ladder
- */
-/**
- * @dot
- strict graph twl5 {
- node [shape="plaintext"];
- {rank=same; 0; 1}
- {rank=same; 2; 3}
- {rank=same; 4}
- 0 -- 1 ;
- 0 -- 2 ;
- 1 -- 3 ;
- 2 -- 4 ;
- 3 -- 4 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologyFiveTwistedLadder[] =
-{
- 0x05,
- 0x06, 0xFF, 0x04, 0x11, 0x02, 0x22, 0x00, 0x11, 0x00, 0x22, // Node0
- 0x08, 0x00, 0x09, 0xFF, 0x08, 0x00, 0x01, 0x33, 0x00, 0x30, // Node1
- 0x10, 0x00, 0x10, 0x00, 0x11, 0xFF, 0x00, 0x40, 0x01, 0x44, // Node2
- 0x00, 0x11, 0x00, 0x11, 0x00, 0x14, 0x12, 0xFF, 0x02, 0x44, // Node3
- 0x00, 0x22, 0x00, 0x23, 0x00, 0x22, 0x04, 0x33, 0x0C, 0xFF // Node4
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph6DoubloonLower.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph6DoubloonLower.c
deleted file mode 100644
index 7efe144894..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph6DoubloonLower.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Six node hydra Topology using "Doubloon/Drachma", Lower nodes remain.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/**
- * 6 node hydra doubloon lower nodes, 3 MCM processors.
- * For partial populations, note nodes are removed in pairs.
- */
-/**
- * @dot
- strict graph doubloon8lower {
- node [shape="plaintext"];
- 0 -- 1 ; 2 -- 3 ; 4 -- 5 ;
- 0 -- 2 ; 1 -- 2 ; 2 -- 4 ; 3 -- 5 ;
- 0 -- 4 ; 1 -- 5 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologySixDoubloonLower[] =
-{
- 0x06,
- 0x16, 0xFF, 0x00, 0x11, 0x02, 0x22, 0x00, 0x22, 0x02, 0x44, 0x00, 0x44, // Node 0
- 0x00, 0x00, 0x25, 0xFF, 0x00, 0x22, 0x00, 0x22, 0x00, 0x55, 0x01, 0x55, // Node 1
- 0x08, 0x00, 0x08, 0x11, 0x19, 0xFF, 0x03, 0x33, 0x08, 0x44, 0x00, 0x44, // Node 2
- 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, 0x24, 0xFF, 0x00, 0x55, 0x04, 0x55, // Node 3
- 0x20, 0x00, 0x00, 0x00, 0x20, 0x22, 0x00, 0x22, 0x25, 0xFF, 0x00, 0x55, // Node 4
- 0x00, 0x11, 0x10, 0x11, 0x00, 0x33, 0x10, 0x33, 0x00, 0x44, 0x1A, 0xFF, // Node 5
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph6DoubloonUpper.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph6DoubloonUpper.c
deleted file mode 100644
index aca978fe9c..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph6DoubloonUpper.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Six node hydra Topology using "Doubloon/Drachma", Upper nodes remain.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/**
- * 6 node hydra drachma, upper nodes remain, 3 MCM processors.
- * For partial population cases, note that nodes are removed in pairs.
- */
-/**
- * @dot
- strict graph doubloon6upper {
- node [shape="plaintext"];
- 0 -- 1 ; 2 -- 3 ; 4 -- 5 ;
- 0 -- 2 ; 1 -- 2 ; 2 -- 4 ; 3 -- 5 ;
- 0 -- 4 ; 1 -- 5 ; 2 -- 5 ; 3 -- 4 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologySixDoubloonUpper[] =
-{
- 0x06,
- 0x16, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x22, 0x02, 0x44, 0x00, 0x44, // Node 0
- 0x00, 0x00, 0x25, 0xFF, 0x00, 0x22, 0x00, 0x22, 0x00, 0x55, 0x01, 0x55, // Node 1
- 0x08, 0x00, 0x08, 0x11, 0x3B, 0xFF, 0x03, 0x33, 0x00, 0x44, 0x00, 0x55, // Node 2
- 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, 0x34, 0xFF, 0x00, 0x44, 0x00, 0x55, // Node 3
- 0x20, 0x00, 0x00, 0x00, 0x00, 0x22, 0x00, 0x33, 0x2D, 0xFF, 0x00, 0x55, // Node 4
- 0x00, 0x11, 0x10, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x1E, 0xFF, // Node 5
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph6FullyConnected.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph6FullyConnected.c
deleted file mode 100644
index f0d019189f..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph6FullyConnected.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Six node Fully Connected Topology.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/**
- * 6 node fully connected
- */
-/**
- * @dot
- strict graph full6 {
- node [shape="plaintext"];
- 0 -- 1 ;
- 0 -- 2 ;
- 0 -- 3 ;
- 0 -- 4 ;
- 0 -- 5 ;
- 1 -- 2 ;
- 1 -- 3 ;
- 1 -- 4 ;
- 1 -- 5 ;
- 2 -- 3 ;
- 2 -- 4 ;
- 2 -- 5 ;
- 3 -- 4 ;
- 3 -- 5 ;
- 4 -- 5 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologySixFully[] =
-{
- 0x06,
- 0x3E, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, // Node 0
- 0x00, 0x00, 0x3D, 0xFF, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, // Node 1
- 0x00, 0x00, 0x00, 0x11, 0x3B, 0xFF, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, // Node 2
- 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x37, 0xFF, 0x00, 0x44, 0x00, 0x55, // Node 3
- 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x2F, 0xFF, 0x00, 0x55, // Node 4
- 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x1F, 0xFF // Node 5
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph6TwinTriangles.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph6TwinTriangles.c
deleted file mode 100644
index a5c55bbba1..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph6TwinTriangles.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * A six node Topology of three MCMs.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/* (2 fully connected three ways connected at the 'corners')
- *
- * 5
- * /| \
- * / 1 - 3
- * / / /
- * 4 / /
- * | \ /
- * 0 - 2-
- */
-/**
- * Six Node hydra
- */
-/**
- * @dot
- strict graph hmcm6 {
- node [shape="plaintext"];
- subgraph even {
- 0 -- 2 ; 2 -- 4 ;
- 0 -- 4 ;
- }
- subgraph odd {
- 1 -- 3 ; 3 -- 5
- 1 -- 5 ;
- }
- {rank=same; 0; 2; 1; 3}
- {rank=same; 4; 5}
- 0 -- 1 ; 2 -- 3 ; 4 -- 5 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologySixTwinTriangles[] =
-{
- 0x06,
- 0x16, 0xFF, 0x00, 0x11, 0x02, 0x22, 0x00, 0x22, 0x02, 0x44, 0x00, 0x44, // Node 0
- 0x00, 0x00, 0x29, 0xFF, 0x00, 0x33, 0x01, 0x33, 0x00, 0x55, 0x01, 0x55, // Node 1
- 0x08, 0x00, 0x00, 0x00, 0x19, 0xFF, 0x00, 0x33, 0x08, 0x44, 0x00, 0x44, // Node 2
- 0x00, 0x11, 0x04, 0x11, 0x00, 0x22, 0x26, 0xFF, 0x00, 0x55, 0x04, 0x55, // Node 3
- 0x20, 0x00, 0x00, 0x00, 0x20, 0x22, 0x00, 0x22, 0x25, 0xFF, 0x00, 0x55, // Node 4
- 0x00, 0x11, 0x10, 0x11, 0x00, 0x33, 0x10, 0x33, 0x00, 0x44, 0x1A, 0xFF, // Node 5
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph6TwistedLadder.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph6TwistedLadder.c
deleted file mode 100644
index 4fa90eb89d..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph6TwistedLadder.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Six node pop order twisted ladder Topology.
- *
- * The population order fall back to Six nodes on a twisted ladder.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/*
- *
- * 4 5
- * |\ /|
- * |/ \|
- * 2 3
- * | |
- * 0---1
- */
-/**
- * 6 node twisted ladder
- */
-/**
- * @dot
- strict graph twl6 {
- node [shape="plaintext"];
- {rank=same; 0; 1}
- {rank=same; 2; 3}
- {rank=same; 4; 5}
- 0 -- 1 ;
- 0 -- 2 ;
- 1 -- 3 ;
- 2 -- 4 ;
- 2 -- 5 ;
- 3 -- 4 ;
- 3 -- 5 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologySixTwistedLadder[] =
-{
- 0x06,
- 0x06, 0xFF, 0x04, 0x11, 0x02, 0x22, 0x00, 0x11, 0x02, 0x22, 0x00, 0x12, // Node0
- 0x08, 0x00, 0x09, 0xFF, 0x00, 0x00, 0x01, 0x33, 0x00, 0x03, 0x01, 0x33, // Node1
- 0x30, 0x00, 0x00, 0x00, 0x31, 0xFF, 0x00, 0x54, 0x21, 0x44, 0x00, 0x55, // Node2
- 0x00, 0x11, 0x30, 0x11, 0x00, 0x45, 0x32, 0xFF, 0x00, 0x44, 0x12, 0x55, // Node3
- 0x00, 0x22, 0x00, 0x32, 0x08, 0x22, 0x00, 0x33, 0x0C, 0xFF, 0x00, 0x32, // Node4
- 0x00, 0x23, 0x00, 0x33, 0x00, 0x22, 0x04, 0x33, 0x00, 0x23, 0x0C, 0xFF // Node5
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph7FullyConnected.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph7FullyConnected.c
deleted file mode 100644
index 7c82c61436..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph7FullyConnected.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Seven node Fully Connected Topology.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/**
- * 7 node fully connected
- */
-/**
- * @dot
- strict graph full7 {
- node [shape="plaintext"];
- 0 -- 1 ; 1 -- 2 ; 2 -- 3 ; 3 -- 4 ; 4 -- 5 ; 5 -- 6 ;
- 0 -- 2 ; 1 -- 3 ; 2 -- 4 ; 3 -- 5 ; 4 -- 6 ;
- 0 -- 3 ; 1 -- 4 ; 2 -- 5 ; 3 -- 6 ;
- 0 -- 4 ; 1 -- 5 ; 2 -- 6 ;
- 0 -- 5 ; 1 -- 6 ;
- 0 -- 6 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologySevenFully[] =
-{
- 0x07,
- 0x7E, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, // Node 0
- 0x00, 0x00, 0x7D, 0xFF, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, // Node 1
- 0x00, 0x00, 0x00, 0x11, 0x7B, 0xFF, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, // Node 2
- 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x77, 0xFF, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, // Node 3
- 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x6F, 0xFF, 0x00, 0x55, 0x00, 0x66, // Node 4
- 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x5F, 0xFF, 0x00, 0x66, // Node 5
- 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x3F, 0xFF // Node 6
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph7TwistedLadder.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph7TwistedLadder.c
deleted file mode 100644
index 1021aa2e46..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph7TwistedLadder.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Seven node pop order twisted ladder Topology.
- *
- * The population order fall back to Seven nodes on a twisted ladder.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/* 6
- * |
- * 4 5
- * |\ /|
- * |/ \|
- * 2 3
- * | |
- * 0---1
- */
-/**
- * 7 node twisted ladder
- */
-/**
- * @dot
- strict graph twl7 {
- node [shape="plaintext"];
- {rank=same; 0; 1}
- {rank=same; 2; 3}
- {rank=same; 4; 5}
- {rank=same; 6}
- 0 -- 1 ;
- 0 -- 2 ;
- 1 -- 3 ;
- 2 -- 4 ;
- 2 -- 5 ;
- 3 -- 4 ;
- 3 -- 5 ;
- 4 -- 6 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologySevenTwistedLadder[] =
-{
- 0x07,
- 0x06, 0xFF, 0x00, 0x11, 0x02, 0x22, 0x00, 0x12, 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, // Node0
- 0x00, 0x00, 0x09, 0xFF, 0x00, 0x03, 0x01, 0x33, 0x00, 0x33, 0x00, 0x33, 0x00, 0x33, // Node1
- 0x30, 0x00, 0x00, 0x50, 0x31, 0xFF, 0x00, 0x54, 0x21, 0x44, 0x01, 0x55, 0x21, 0x44, // Node2
- 0x00, 0x41, 0x30, 0x11, 0x00, 0x45, 0x32, 0xFF, 0x02, 0x44, 0x12, 0x55, 0x02, 0x44, // Node3
- 0x48, 0x22, 0x40, 0x33, 0x48, 0x22, 0x40, 0x33, 0x4C, 0xFF, 0x40, 0x32, 0x0C, 0x66, // Node4
- 0x00, 0x22, 0x04, 0x33, 0x00, 0x22, 0x04, 0x33, 0x00, 0x23, 0x0C, 0xFF, 0x00, 0x23, // Node5
- 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x10, 0xFF // Node6
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph8DoubloonM.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph8DoubloonM.c
deleted file mode 100644
index 8da6f561bb..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph8DoubloonM.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Eight node hydra Topology using "Doubloon/Drachma".
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-/**
- * 8 node hydra doubloon, 4 MCM processors.
- */
-/**
- * @dot
- strict graph doubloon8 {
- node [shape="plaintext"];
- 0 -- 1 ; 2 -- 3 ; 4 -- 5 ; 6 -- 7 ;
- 0 -- 2 ; 1 -- 2 ; 2 -- 4 ; 3 -- 5 ; 4 -- 6 ; 5 -- 6 ;
- 0 -- 4 ; 1 -- 5 ; 2 -- 6 ; 3 -- 7 ;
- 0 -- 6 ; 1 -- 7 ; 2 -- 7 ; 3 -- 6
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologyEightDoubloon[] =
-{
- 0x08,
- 0x56, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x22, 0x02, 0x44, 0x00, 0x44, 0x02, 0x66, 0x00, 0x66, // Node 0
- 0x00, 0x00, 0xA5, 0xFF, 0x00, 0x22, 0x00, 0x22, 0x00, 0x55, 0x01, 0x55, 0x00, 0x77, 0x01, 0x77, // Node 1
- 0x08, 0x00, 0x08, 0x11, 0xDB, 0xFF, 0x03, 0x33, 0x08, 0x44, 0x00, 0x44, 0x00, 0x66, 0x00, 0x77, // Node 2
- 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, 0xE4, 0xFF, 0x00, 0x55, 0x04, 0x55, 0x00, 0x66, 0x00, 0x77, // Node 3
- 0x20, 0x00, 0x00, 0x00, 0x20, 0x22, 0x00, 0x22, 0x65, 0xFF, 0x00, 0x55, 0x00, 0x66, 0x00, 0x66, // Node 4
- 0x00, 0x11, 0x10, 0x11, 0x00, 0x33, 0x10, 0x33, 0x00, 0x44, 0x5A, 0xFF, 0x00, 0x66, 0x00, 0x66, // Node 5
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x22, 0x00, 0x33, 0x80, 0x44, 0x80, 0x55, 0xBD, 0xFF, 0x30, 0x77, // Node 6
- 0x00, 0x11, 0x40, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x66, 0x00, 0x66, 0x00, 0x66, 0x4E, 0xFF // Node 7
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph8FullyConnected.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph8FullyConnected.c
deleted file mode 100644
index 824d5fa3a2..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph8FullyConnected.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Eight node Fully Connected Topology.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-/**
- * 8 node fully connected
- */
-/**
- * @dot
- strict graph full8 {
- node [shape="plaintext"];
- 0 -- 1 ; 1 -- 2 ; 2 -- 3 ; 3 -- 4 ; 4 -- 5 ; 5 -- 6 ; 6 -- 7 ;
- 0 -- 2 ; 1 -- 3 ; 2 -- 4 ; 3 -- 5 ; 4 -- 6 ; 5 -- 7 ;
- 0 -- 3 ; 1 -- 4 ; 2 -- 5 ; 3 -- 6 ; 4 -- 7 ;
- 0 -- 4 ; 1 -- 5 ; 2 -- 6 ; 3 -- 7 ;
- 0 -- 5 ; 1 -- 6 ; 2 -- 7 ;
- 0 -- 6 ; 1 -- 7 ;
- 0 -- 7 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologyEightFully[] =
-{
- 0x08,
- 0xFE, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, 0x00, 0x77, // Node 0
- 0x00, 0x00, 0xFD, 0xFF, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, 0x00, 0x77, // Node 1
- 0x00, 0x00, 0x00, 0x11, 0xFB, 0xFF, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, 0x00, 0x77, // Node 2
- 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0xF7, 0xFF, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, 0x00, 0x77, // Node 3
- 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0xEF, 0xFF, 0x00, 0x55, 0x00, 0x66, 0x00, 0x77, // Node 4
- 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0xDF, 0xFF, 0x00, 0x66, 0x00, 0x77, // Node 5
- 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0xBF, 0xFF, 0x00, 0x77, // Node 6
- 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, 0x7F, 0xFF // Node 7
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph8Ladder.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph8Ladder.c
deleted file mode 100644
index eec64bd3e7..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph8Ladder.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Eight node Ladder Topology.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/* 6---7
- * | |
- * 4---5
- * | |
- * 2---3
- * | |
- * 0---1
- */
-/**
- * 8 node ladder
- */
-/**
- * @dot
- strict graph ladder8 {
- node [shape="plaintext"];
- {rank=same; 0; 1}
- {rank=same; 2; 3}
- {rank=same; 4; 5}
- {rank=same; 6; 7}
- 0 -- 1 ;
- 0 -- 2 ;
- 1 -- 3 ;
- 2 -- 4 ;
- 2 -- 3 ;
- 3 -- 5 ;
- 4 -- 5 ;
- 4 -- 6 ;
- 5 -- 7 ;
- 6 -- 7 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologyEightStraightLadder[] =
-{
- 0x08,
- 0x06, 0xFF, 0x00, 0x11, 0x02, 0x22, 0x00, 0x22, 0x02, 0x22, 0x00, 0x22, 0x02, 0x22, 0x00, 0x22, // Node0
- 0x00, 0x00, 0x09, 0xFF, 0x00, 0x33, 0x01, 0x33, 0x00, 0x33, 0x01, 0x33, 0x00, 0x33, 0x01, 0x33, // Node1
- 0x18, 0x00, 0x00, 0x00, 0x19, 0xFF, 0x00, 0x33, 0x09, 0x44, 0x00, 0x44, 0x09, 0x44, 0x00, 0x44, // Node2
- 0x00, 0x11, 0x24, 0x11, 0x00, 0x22, 0x26, 0xFF, 0x00, 0x55, 0x06, 0x55, 0x00, 0x55, 0x06, 0x55, // Node3
- 0x60, 0x22, 0x00, 0x22, 0x60, 0x22, 0x00, 0x22, 0x64, 0xFF, 0x00, 0x55, 0x24, 0x66, 0x00, 0x66, // Node4
- 0x00, 0x33, 0x90, 0x33, 0x00, 0x33, 0x90, 0x33, 0x00, 0x44, 0x98, 0xFF, 0x00, 0x77, 0x18, 0x77, // Node5
- 0x80, 0x44, 0x00, 0x44, 0x80, 0x44, 0x00, 0x44, 0x80, 0x44, 0x00, 0x44, 0x90, 0xFF, 0x00, 0x77, // Node6
- 0x00, 0x55, 0x40, 0x55, 0x00, 0x55, 0x40, 0x55, 0x00, 0x55, 0x40, 0x55, 0x00, 0x66, 0x60, 0xFF // Node7
-};
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph8TwinFullyFourWays.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph8TwinFullyFourWays.c
deleted file mode 100644
index 6c4a245687..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph8TwinFullyFourWays.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Eight node Topology of two fully connected four ways.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/* (2 fully connected four ways connected at the 'corners')
- *
- * 5 - 7
- * /| X |
- * / 1 - 3
- * / / / /
- * 4 - 6 /
- * | X | /
- * 0 - 2-
- */
-/**
- * 8 node twin fully connected four ways, connected by the MCM internal links.
- */
-/**
- * @dot
- strict graph hydra8 {
- node [shape="plaintext"];
- subgraph even {
- 0 -- 2 ; 2 -- 4 ; 4 -- 6 ;
- 0 -- 4 ; 2 -- 6 ;
- 0 -- 6 ;
- }
- subgraph odd {
- 1 -- 3 ; 3 -- 5 ; 5 -- 7 ;
- 1 -- 5 ; 3 -- 7 ;
- 1 -- 7 ;
- }
- {rank=same; 0; 2; 1; 3}
- {rank=same; 4; 6; 5; 7}
- 0 -- 1 ; 2 -- 3 ; 4 -- 5 ; 6 -- 7 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologyEightTwinFullyFourWays[] =
-{
- 0x08,
- 0x56, 0xFF, 0x00, 0x11, 0x02, 0x22, 0x00, 0x22, 0x02, 0x44, 0x00, 0x44, 0x02, 0x66, 0x00, 0x66, // Node 0
- 0x00, 0x00, 0xA9, 0xFF, 0x00, 0x33, 0x01, 0x33, 0x00, 0x55, 0x01, 0x55, 0x00, 0x77, 0x01, 0x77, // Node 1
- 0x08, 0x00, 0x00, 0x00, 0x59, 0xFF, 0x00, 0x33, 0x08, 0x44, 0x00, 0x44, 0x08, 0x66, 0x00, 0x66, // Node 2
- 0x00, 0x11, 0x04, 0x11, 0x00, 0x22, 0xA6, 0xFF, 0x00, 0x55, 0x04, 0x55, 0x00, 0x77, 0x04, 0x77, // Node 3
- 0x20, 0x00, 0x00, 0x00, 0x20, 0x22, 0x00, 0x22, 0x65, 0xFF, 0x00, 0x55, 0x20, 0x66, 0x00, 0x66, // Node 4
- 0x00, 0x11, 0x10, 0x11, 0x00, 0x33, 0x10, 0x33, 0x00, 0x44, 0x9A, 0xFF, 0x00, 0x77, 0x10, 0x77, // Node 5
- 0x80, 0x00, 0x00, 0x00, 0x80, 0x22, 0x00, 0x22, 0x80, 0x44, 0x00, 0x44, 0x95, 0xFF, 0x00, 0x77, // Node 6
- 0x00, 0x11, 0x40, 0x11, 0x00, 0x33, 0x40, 0x33, 0x00, 0x55, 0x40, 0x55, 0x00, 0x66, 0x6A, 0xFF // Node 7
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph8TwistedLadder.c b/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph8TwistedLadder.c
deleted file mode 100644
index 14076b298e..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/HT/htGraph/htGraph8TwistedLadder.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Eight node twisted ladder Topology.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-/* 6---7
- * | |
- * 4 5
- * |\ /|
- * |/ \|
- * 2 3
- * | |
- * 0---1
- */
-/**
- * 8 node twisted ladder
- */
-/**
- * @dot
- strict graph twl8 {
- node [shape="plaintext"];
- {rank=same; 0; 1}
- {rank=same; 2; 3}
- {rank=same; 4; 5}
- {rank=same; 6; 7}
- 0 -- 1 ;
- 0 -- 2 ;
- 1 -- 3 ;
- 2 -- 4 ;
- 2 -- 5 ;
- 3 -- 4 ;
- 3 -- 5 ;
- 4 -- 6 ;
- 5 -- 7 ;
- 6 -- 7 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologyEightTwistedLadder[] =
-{
- 0x08,
- 0x06, 0xFF, 0x00, 0x11, 0x02, 0x22, 0x00, 0x12, 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, // Node0
- 0x00, 0x00, 0x09, 0xFF, 0x00, 0x03, 0x01, 0x33, 0x00, 0x33, 0x00, 0x33, 0x00, 0x33, 0x00, 0x33, // Node1
- 0x30, 0x00, 0x00, 0x50, 0x31, 0xFF, 0x00, 0x54, 0x21, 0x44, 0x01, 0x55, 0x21, 0x44, 0x01, 0x55, // Node2
- 0x00, 0x41, 0x30, 0x11, 0x00, 0x45, 0x32, 0xFF, 0x02, 0x44, 0x12, 0x55, 0x02, 0x44, 0x12, 0x55, // Node3
- 0x48, 0x22, 0x40, 0x33, 0x48, 0x22, 0x40, 0x33, 0x4C, 0xFF, 0x00, 0x32, 0x0C, 0x66, 0x00, 0x36, // Node4
- 0x80, 0x22, 0x84, 0x33, 0x80, 0x22, 0x84, 0x33, 0x00, 0x23, 0x8C, 0xFF, 0x00, 0x27, 0x0C, 0x77, // Node5
- 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x80, 0x44, 0x00, 0x74, 0x90, 0xFF, 0x00, 0x77, // Node6
- 0x00, 0x55, 0x00, 0x55, 0x00, 0x55, 0x00, 0x55, 0x00, 0x65, 0x40, 0x55, 0x00, 0x66, 0x60, 0xFF // Node7
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/NDINTLV/mfndi.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/NDINTLV/mfndi.c
deleted file mode 100644
index 93189b6766..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/NDINTLV/mfndi.c
+++ /dev/null
@@ -1,238 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mfndi.c
- *
- * Feature applies Node memory interleaving
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Feat/Ndintlv)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "mm.h"
-#include "mn.h"
-#include "mport.h"
-#include "mfndi.h"
-#include "Ids.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_FEAT_NDINTLV_MFNDI_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define _4GB_ (0x10000)
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Perform a check to see if node interleaving can be enabled on each node.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - Node interleaving can be enabled.
- * @return FALSE - Node interleaving cannot be enabled.
- */
-
-BOOLEAN
-MemFCheckInterleaveNodes (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- DIE_STRUCT *MCTPtr;
-
- ASSERT (NBPtr != NULL);
-
- MCTPtr = NBPtr->MCTPtr;
-
- if (MCTPtr->NodeMemSize != 0) {
- if (!NBPtr->SharedPtr->NodeIntlv.IsValid) {
- NBPtr->SharedPtr->NodeIntlv.NodeMemSize = MCTPtr->NodeMemSize;
- NBPtr->SharedPtr->NodeIntlv.Dct0MemSize = MCTPtr->DctData[0].Timings.DctMemSize;
- NBPtr->SharedPtr->NodeIntlv.IsValid = TRUE;
- } else {
- if ((NBPtr->SharedPtr->NodeIntlv.NodeMemSize != MCTPtr->NodeMemSize) ||
- (NBPtr->SharedPtr->NodeIntlv.Dct0MemSize != MCTPtr->DctData[0].Timings.DctMemSize)) {
- return FALSE;
- }
- }
- }
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Applies Node memory interleaving for each node.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - This feature is enabled.
- * @return FALSE - This feature is not enabled.
- */
-
-BOOLEAN
-MemFInterleaveNodes (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 NodeCnt;
- UINT8 BitShift;
- UINT32 MemSize;
- UINT32 Dct0MemSize;
- UINT32 NodeSysBase;
- UINT32 NodeSysLimit;
- UINT32 HoleBase;
- UINT32 HoleSize;
- UINT32 HoleOffset;
- S_UINT64 SMsr;
- MEM_PARAMETER_STRUCT *RefPtr;
- DIE_STRUCT *MCTPtr;
-
- ASSERT (NBPtr != NULL);
-
- RefPtr = NBPtr->RefPtr;
- MCTPtr = NBPtr->MCTPtr;
- if (RefPtr->GStatus[GsbSoftHole] || RefPtr->GStatus[GsbHWHole]) {
- HoleBase = RefPtr->HoleBase;
- HoleSize = _4GB_ - HoleBase;
- } else {
- HoleBase = 0;
- HoleSize = 0;
- }
-
- NodeCnt = NBPtr->SharedPtr->NodeIntlv.NodeCnt;
- Dct0MemSize = NBPtr->SharedPtr->NodeIntlv.Dct0MemSize;
- MemSize = NBPtr->SharedPtr->NodeIntlv.NodeMemSize;
-
- BitShift = LibAmdBitScanForward (NodeCnt);
- Dct0MemSize <<= BitShift;
- if (HoleSize != 0) {
- RefPtr->GStatus[GsbHWHole] = TRUE;
- HoleOffset = HoleSize;
- if (Dct0MemSize >= HoleBase) {
- Dct0MemSize += HoleSize;
- } else {
- HoleOffset += Dct0MemSize;
- }
- } else {
- HoleOffset = 0;
- }
-
- MemSize = (MemSize << BitShift) + HoleSize;
-
- MCTPtr->NodeSysBase = 0;
- MCTPtr->NodeSysLimit = MemSize - 1;
- RefPtr->SysLimit = MemSize - 1;
-
- // When node interleaving is enabled with larger than 1012GB memory,
- // system memory limit will be lowered to fill in HT reserved region.
- // TOP_MEM2 was set in CpuMemTyping and needs to be updated as well.
- if (RefPtr->SysLimit >= HT_REGION_BASE_RJ16) {
- if (RefPtr->LimitMemoryToBelow1Tb) {
- SMsr.hi = HT_REGION_BASE_RJ16 >> (32 - 16);
- SMsr.lo = HT_REGION_BASE_RJ16 << 16;
- } else {
- SMsr.hi = MemSize >> (32 - 16);
- SMsr.lo = MemSize << 16;
- }
- LibAmdMsrWrite (TOP_MEM2, (UINT64 *)&SMsr, &(NBPtr->MemPtr->StdHeader));
- IDS_HDT_CONSOLE (MEM_FLOW, "TOP_MEM2: %08x0000\n", MemSize);
- RefPtr->Sub1THoleBase = HT_REGION_BASE_RJ16;
- RefPtr->SysLimit = HT_REGION_BASE_RJ16 - 1;
- } else {
- RefPtr->Sub1THoleBase = RefPtr->SysLimit + 1;
- }
-
- NBPtr->SetBitField (NBPtr, BFDramIntlvSel, NBPtr->SharedPtr->NodeIntlv.NodeIntlvSel);
- NBPtr->SetBitField (NBPtr, BFDramBaseAddr, 0);
- NBPtr->SetBitField (NBPtr, BFDramIntlvEn, NodeCnt - 1);
- NBPtr->SetBitField (NBPtr, BFDramLimitAddr, (MemSize - 1) >> (27 - 16));
-
- if (HoleSize != 0) {
- MCTPtr->Status[SbHWHole] = TRUE;
- // DramHoleBase will be set when sync address map to other nodes.
- NBPtr->SetBitField (NBPtr, BFDramHoleOffset, HoleOffset >> (23 - 16));
- NBPtr->SetBitField (NBPtr, BFDramHoleValid, 1);
- }
-
- if ((MCTPtr->DctData[1].Timings.DctMemSize != 0) && (!NBPtr->Ganged)) {
- NBPtr->SetBitField (NBPtr, BFDctSelBaseAddr, Dct0MemSize >> (27 - 16));
- NBPtr->SetBitField (NBPtr, BFDctSelBaseOffset, Dct0MemSize >> (26 - 16));
- }
-
- NodeSysBase = NodeCnt - 1;
- NodeSysLimit = ((MemSize - 1)& 0xFFFFFF00) | NBPtr->SharedPtr->NodeIntlv.NodeIntlvSel;
- NBPtr->SharedPtr->NodeMap[NBPtr->Node].IsValid = TRUE;
- NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysBase = NodeSysBase;
- NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysLimit = NodeSysLimit;
-
- NBPtr->SharedPtr->NodeIntlv.NodeIntlvSel++;
- return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/NDINTLV/mfndi.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/NDINTLV/mfndi.h
deleted file mode 100644
index 218f475d67..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/NDINTLV/mfndi.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mfndi.h
- *
- * Feature node interleaving
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-#ifndef _MFNDI_H_
-#define _MFNDI_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemFInterleaveNodes (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-#endif /* _MFNDI_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/OLSPARE/mfspr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/OLSPARE/mfspr.c
deleted file mode 100644
index 9482537ab1..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/OLSPARE/mfspr.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mfspr.c
- *
- * Feature enable online spare
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Feat/Olspare)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "mm.h"
-#include "mn.h"
-#include "mfspr.h"
-#include "Ids.h"
-#include "amdlib.h"
-#include "Filecode.h"
-#include "GeneralServices.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_FEAT_OLSPARE_MFSPR_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Enable online spare on current node if it is requested.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - This feature is enabled.
- * @return FALSE - This feature is not enabled.
- */
-
-BOOLEAN
-MemFOnlineSpare (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 Dct;
- UINT8 q;
- UINT8 Value8;
- BOOLEAN Flag;
- BOOLEAN OnlineSprEnabled[MAX_CHANNELS_PER_SOCKET];
-
- MEM_PARAMETER_STRUCT *RefPtr;
- DIE_STRUCT *MCTPtr;
-
- ASSERT (NBPtr != NULL);
-
- RefPtr = NBPtr->RefPtr;
- Flag = FALSE;
- if (RefPtr->EnableOnLineSpareCtl != 0) {
- RefPtr->GStatus[GsbEnDIMMSpareNW] = TRUE;
- MCTPtr = NBPtr->MCTPtr;
-
- // Check if online spare can be enabled on current node
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- ASSERT (Dct < sizeof (OnlineSprEnabled));
- NBPtr->SwitchDCT (NBPtr, Dct);
- OnlineSprEnabled[Dct] = FALSE;
- if ((MCTPtr->GangedMode == 0) || (MCTPtr->Dct == 0)) {
- if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
- // Make sure at least two chip-selects are available
- Value8 = LibAmdBitScanReverse (NBPtr->DCTPtr->Timings.CsEnabled);
- if (Value8 > LibAmdBitScanForward (NBPtr->DCTPtr->Timings.CsEnabled)) {
- OnlineSprEnabled[Dct] = TRUE;
- Flag = TRUE;
- } else {
- PutEventLog (AGESA_ERROR, MEM_ERROR_DIMM_SPARING_NOT_ENABLED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- MCTPtr->ErrStatus[EsbSpareDis] = TRUE;
- }
- }
- }
- }
-
- // If we don't have spared rank on any DCT, we don't run the rest part of the code.
- if (!Flag) {
- return FALSE;
- }
-
- MCTPtr->NodeMemSize = 0;
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- if (OnlineSprEnabled[Dct]) {
- // Only run StitchMemory if we need to set a spare rank.
- NBPtr->DCTPtr->Timings.DctMemSize = 0;
- for (q = 0; q < MAX_CS_PER_CHANNEL; q++) {
- NBPtr->SetBitField (NBPtr, BFCSBaseAddr0Reg + q, 0);
- }
- Flag = NBPtr->StitchMemory (NBPtr);
- ASSERT (Flag == TRUE);
- } else if ((MCTPtr->GangedMode == 0) && (NBPtr->DCTPtr->Timings.DctMemSize != 0)) {
- // Otherwise, need to adjust the memory size on the node.
- MCTPtr->NodeMemSize += NBPtr->DCTPtr->Timings.DctMemSize;
- MCTPtr->NodeSysLimit = MCTPtr->NodeMemSize - 1;
- }
- }
- return TRUE;
- } else {
- return FALSE;
- }
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/OLSPARE/mfspr.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/OLSPARE/mfspr.h
deleted file mode 100644
index bfad4eb3c3..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/OLSPARE/mfspr.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mfspr.h
- *
- * Feature enable Online spare
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-
-#ifndef _MFSPR_H_
-#define _MFSPR_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemFOnlineSpare (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-#endif /* _MFSPR_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mt2.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mt2.c
deleted file mode 100644
index be9033a6dc..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mt2.c
+++ /dev/null
@@ -1,232 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mt2.c
- *
- * Common Technology functions for DDR2
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR2)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "AdvancedApi.h"
-#include "mm.h"
-#include "mn.h"
-#include "mu.h"
-#include "mt.h"
-#include "mt2.h"
-#include "mtspd2.h"
-#include "mtot2.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-/* features */
-#include "mftds.h"
-#define FILECODE PROC_MEM_TECH_DDR2_MT2_FILECODE
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function Constructs the technology block
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-BOOLEAN
-MemConstructTechBlock2 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- TECHNOLOGY_TYPE *TechTypePtr;
- UINT8 Dct;
- UINT8 Channel;
- UINT8 i;
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- CH_DEF_STRUCT *ChannelPtr;
- UINT8 DimmSlots;
-
- TechTypePtr = (TECHNOLOGY_TYPE *) FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MEM_TECH, NBPtr->MCTPtr->SocketId, 0);
- if (TechTypePtr != NULL) {
- // Ensure the platform override value is valid
- ASSERT ((*TechTypePtr == DDR3_TECHNOLOGY) || (*TechTypePtr == DDR2_TECHNOLOGY));
- if (*TechTypePtr != DDR2_TECHNOLOGY) {
- return FALSE;
- }
- }
-
-
- TechPtr->NBPtr = NBPtr;
- TechPtr->RefPtr = NBPtr->RefPtr;
- MCTPtr = NBPtr->MCTPtr;
-
- TechPtr->NBPtr = NBPtr;
- TechPtr->RefPtr = NBPtr->RefPtr;
-
- TechPtr->SetDramMode = MemTSetDramMode2;
- TechPtr->DimmPresence = MemTDIMMPresence2;
- TechPtr->SpdCalcWidth = MemTSPDCalcWidth2;
- TechPtr->SpdGetTargetSpeed = MemTSPDGetTargetSpeed2;
- TechPtr->AutoCycTiming = MemTAutoCycTiming2;
- TechPtr->SpdSetBanks = MemTSPDSetBanks2;
- TechPtr->SetDqsEccTmgs = MemTSetDQSEccTmgs;
- TechPtr->GetCSIntLvAddr = MemTGetCSIntLvAddr2;
- TechPtr->AdjustTwrwr = MemTAdjustTwrwr2;
- TechPtr->AdjustTwrrd = MemTAdjustTwrrd2;
- TechPtr->GetDimmSpdBuffer = MemTGetDimmSpdBuffer2;
- TechPtr->GetLD = MemTGetLD2;
- TechPtr->MaxFilterDly = 0;
-
- //
- // Map the Logical Dimms on this channel to the SPD that should be used for that logical DIMM.
- // The pointers to the DIMM SPD information is as follows (2 Dimm/Ch and 3 Dimm/Ch examples).
- //
- // DIMM Spd Buffer Current Channel DimmSpdPtr[MAX_DIMMS_PER_CHANNEL] array
- // (Number of dimms varies by platform) (Array size is determined in AGESA.H) Dimm operations loop
- // on this array only)
- // 2 DIMMS PER CHANNEL
- //
- // Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
- // Dimm 1 SR/DR DIMM <--------------DimmSpdPtr[1]
- // DimmSpdPtr[2]------->NULL
- // DimmSpdPtr[3]------->NULL
- //
- // Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
- // Dimm 1 QR DIMM <---------+----DimmSpdPtr[1]
- // | DimmSpdPtr[2]------->NULL
- // +----DimmSpdPtr[3]
- //
- // Socket N Channel N Dimm 0 QR DIMM <-----+--------DimmSpdPtr[0]
- // Dimm 1 QR DIMM <-----|---+----DimmSpdPtr[1]
- // +-- | ---DimmSpdPtr[2]
- // +----DimmSpdPtr[3]
- //
- // 3 DIMMS PER CHANNEL
- //
- // Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
- // Dimm 1 SR/DR DIMM <--------------DimmSpdPtr[1]
- // Dimm 3 SR/DR DIMM <--------------DimmSpdPtr[2]
- // DimmSpdPtr[3]------->NULL
- //
- // Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
- // Dimm 1 QR DIMM <---------+----DimmSpdPtr[1]
- // Dimm 3 SR/DR DIMM <-------- | ---DimmSpdPtr[2]
- // +----DimmSpdPtr[3]
- //
- //
-
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- DCTPtr = NBPtr->DCTPtr;
- for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) {
- NBPtr->SwitchChannel (NBPtr, Channel);
- ChannelPtr = NBPtr->ChannelPtr;
- ChannelPtr->TechType = DDR2_TECHNOLOGY;
- ChannelPtr->MCTPtr = MCTPtr;
- ChannelPtr->DCTPtr = DCTPtr;
-
- DimmSlots = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration,
- MCTPtr->SocketId,
- NBPtr->GetSocketRelativeChannel (NBPtr, Dct, Channel)
- );
- //
- // Initialize the SPD pointers for each Dimm
- //
- for (i = 0 ; i < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0])) ; i++) {
- ChannelPtr->DimmSpdPtr[i] = NULL;
- }
- for (i = 0 ; i < DimmSlots; i++) {
- ChannelPtr->DimmSpdPtr[i] = &(ChannelPtr->SpdPtr[i]);
- if ( (i + 2) < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0]))) {
- if (ChannelPtr->DimmSpdPtr[i]->DimmPresent) {
- if ((((ChannelPtr->DimmSpdPtr[i]->Data[SPD_DM_BANKS] >> 3) & 0x07) + 1) > 2) {
- ChannelPtr->DimmSpdPtr[i + 2] = &(ChannelPtr->SpdPtr[i]);
- }
- }
- }
- }
- }
- }
- return TRUE;
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mt2.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mt2.h
deleted file mode 100644
index 6966a7b985..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mt2.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mt2.h
- *
- * Common Technology
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR2)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-
-#ifndef _MT2_H_
-#define _MT2_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemConstructTechBlock2 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemTSetDramMode2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTDIMMPresence2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTSPDCalcWidth2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTSPDGetTargetSpeed2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTAutoCycTiming2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTSPDSetBanks2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-VOID
-MemTGetCSIntLvAddr2 (
- IN UINT8 BankEnc,
- OUT UINT8 *LowBit,
- OUT UINT8 *HiBit
- );
-
-BOOLEAN
-MemTGetDimmSpdBuffer2 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT UINT8 **SpdBuffer,
- IN UINT8 Dimm
- );
-
-#endif /* _MT2_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mtot2.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mtot2.c
deleted file mode 100644
index a45a970e35..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mtot2.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mtot2.c
- *
- * Technology Non-SPD Timings for DDR2
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR2)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "mm.h"
-#include "mn.h"
-#include "mu.h"
-#include "mt.h"
-#include "mtot2.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_TECH_DDR2_MTOT2_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function adjusts the Twrwr value for DDR2.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-MemTAdjustTwrwr2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- DCT_STRUCT *DCTPtr;
-
- DCTPtr = TechPtr->NBPtr->DCTPtr;
-
- // For DDR2, 1 clock has encoded value of 0.
- // Need to transfer clk value to encoded value.
- if (DCTPtr->Timings.Twrwr >= 1) {
- DCTPtr->Timings.Twrwr -= 1;
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function adjusts the Twrrd value for DDR2.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-MemTAdjustTwrrd2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- DCT_STRUCT *DCTPtr;
-
- DCTPtr = TechPtr->NBPtr->DCTPtr;
-
- // For DDR2, 1 clock has encoded value of 0.
- // Need to transfer clk value to encoded value.
- if (DCTPtr->Timings.Twrrd >= 1) {
- DCTPtr->Timings.Twrrd -= 1;
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function gets the LD value for DDR2
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return value of LD
- */
-
-INT8
-MemTGetLD2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- INT8 LD;
-
- // For DDR2, LD is always one clock (For DDR2, Tcwl is always Tcl minus 1).
- LD = 1;
-
- return LD;
-}
-
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mtot2.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mtot2.h
deleted file mode 100644
index ac52ffec0f..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mtot2.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mtot2.h
- *
- * Technology Non-SPD timings for DDR2
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR2)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-
-#ifndef _MTOT2_H_
-#define _MTOT2_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-VOID
-MemTAdjustTwrwr2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-VOID
-MemTAdjustTwrrd2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-INT8
-MemTGetLD2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-#endif /* _MTOT2_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mtspd2.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mtspd2.c
deleted file mode 100644
index 680ecab671..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mtspd2.c
+++ /dev/null
@@ -1,1115 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mtspd2.c
- *
- * Technology SPD supporting functions for DDR2
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR2)
- * @e \$Revision: 45911 $ @e \$Date: 2011-01-25 04:55:11 +0800 (Tue, 25 Jan 2011) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mport.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mu.h"
-#include "mt2.h"
-#include "mtspd2.h"
-#include "mftds.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_TECH_DDR2_MTSPD2_FILECODE
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-UINT8
-STATIC
-MemTSPDGetTCL2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-STATIC
-MemTSysCapability2 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 k,
- IN UINT16 j
- );
-
-BOOLEAN
-STATIC
-MemTDimmSupports2 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 k,
- IN UINT8 j,
- IN UINT8 i
- );
-
-UINT8
-STATIC
-MemTGetTk2 (
- IN UINT8 k
- );
-
-UINT8
-STATIC
-MemTGetBankAddr2 (
- IN UINT8 k
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the DRAM mode
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - indicates that the DRAM mode is set to DDR2
- */
-
-BOOLEAN
-MemTSetDramMode2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- TechPtr->NBPtr->SetBitField (TechPtr->NBPtr, BFLegacyBiosMode, 0);
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function determines if DIMMs are present. It checks checksum and interrogates the SPDs
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - indicates that a FATAL error has not occurred
- * @return FALSE - indicates that a FATAL error has occurred
- */
-
-BOOLEAN
-MemTDIMMPresence2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 *SpdBufferPtr;
- MEM_PARAMETER_STRUCT *RefPtr;
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- CH_DEF_STRUCT *ChannelPtr;
- MEM_NB_BLOCK *NBPtr;
- UINT16 Checksum;
- UINT16 Value16;
- UINT8 Dct;
- UINT8 Channel;
- UINT8 i;
- UINT8 ByteNum;
- UINT8 Devwidth;
- UINT8 Value8;
- UINT8 MaxDimms;
- UINT8 DimmSlots;
- UINT16 DimmMask;
- BOOLEAN SPDCtrl;
-
- NBPtr = TechPtr->NBPtr;
- RefPtr = NBPtr->RefPtr;
- MCTPtr = NBPtr->MCTPtr;
-
- SPDCtrl = UserOptions.CfgIgnoreSpdChecksum;
-
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- DCTPtr = NBPtr->DCTPtr;
- for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) {
- NBPtr->SwitchChannel (NBPtr, Channel);
- ChannelPtr = NBPtr->ChannelPtr;
- ChannelPtr->DimmQrPresent = 0;
-
- // Get the maximum number of DIMMs
- DimmSlots = GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration,
- MCTPtr->SocketId,
- NBPtr->GetSocketRelativeChannel (NBPtr, Dct, Channel)
- );
- MaxDimms = MAX_DIMMS_PER_CHANNEL;
- for (i = 0; i < MaxDimms; i++) {
- // Bitmask representing dimm #i.
- DimmMask = (UINT16)1 << i;
-
- if ((ChannelPtr->DimmQrPresent & DimmMask) || (i < DimmSlots)) {
- if (MemTGetDimmSpdBuffer2 (TechPtr, &SpdBufferPtr, i)) {
- MCTPtr->DimmPresent |= DimmMask;
-
- // Start by computing checksum for this SPD
- Checksum = 0;
- for (ByteNum = 0; ByteNum < SPD_CHECKSUM; ByteNum++) {
- Checksum = Checksum + (UINT16) SpdBufferPtr[ByteNum];
- }
- // Check for valid checksum value
- AGESA_TESTPOINT (TpProcMemSPDChecking, &(NBPtr->MemPtr->StdHeader));
-
- if (SpdBufferPtr[SPD_TYPE] == JED_DDR2_SDRAM) {
- ChannelPtr->ChDimmValid |= DimmMask;
- MCTPtr->DimmValid |= DimmMask;
- } else {
- // Current socket is set up to only support DDR2 dimms.
- IDS_ERROR_TRAP;
- }
- if ((SpdBufferPtr[SPD_CHECKSUM] != (UINT8)Checksum) && !SPDCtrl) {
- //
- // if NV_SPDCHK_RESTRT is set to 0,
- // cannot ignore faulty SPD checksum
- //
- // Indicate checksum error
- ChannelPtr->DimmSpdCse |= DimmMask;
- PutEventLog (AGESA_ERROR, MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_ERROR, MCTPtr);
- }
-
- // Check module type information.
- if (SpdBufferPtr[SPD_DIMM_TYPE] & JED_REG_ADC_MSK) {
- ChannelPtr->RegDimmPresent |= DimmMask;
- MCTPtr->RegDimmPresent |= DimmMask;
- }
-
- if (SpdBufferPtr[SPD_DIMM_TYPE] & JED_SODIMM) {
- ChannelPtr->SODimmPresent |= DimmMask;
- }
-
- // Check error correction type
- if (SpdBufferPtr[SPD_EDC_TYPE] & JED_ECC) {
- MCTPtr->DimmEccPresent |= DimmMask; // Dimm has ECC
- }
- if (SpdBufferPtr[SPD_EDC_TYPE] & JED_ADRC_PAR) {
- MCTPtr->DimmParPresent |= DimmMask; // Dimm has parity
- }
-
- // Get the Dimm width data
- Devwidth = SpdBufferPtr[SPD_DEV_WIDTH] & 0xFE;
- if (Devwidth == 4) {
- ChannelPtr->Dimmx4Present |= DimmMask; // Dimm has parity
- } else if (Devwidth == 8) {
- ChannelPtr->Dimmx8Present |= DimmMask; // Dimm has parity
- } else if (Devwidth == 16) {
- ChannelPtr->Dimmx16Present |= DimmMask; // Dimm has parity
- }
-
- // Determine the page size.
- // page_size = 2^COLBITS * Devwidth/8
- //
- Value16 = (((UINT16)1 << SpdBufferPtr[SPD_COL_SZ]) * Devwidth) / 8;
- if (!(Value16 >> 11)) {
- DCTPtr->Timings.DIMM1KPage |= DimmMask;
- }
-
- // Check for 'analysis probe installed'
- if (SpdBufferPtr[SPD_ATTRIB] & JED_PROBE_MSK) {
- MCTPtr->Status[SbDiagClks] = TRUE;
- }
-
- // Determine the geometry of the DIMM module
- if (SpdBufferPtr[SPD_DM_BANKS] & SP_DPL_BIT) {
- ChannelPtr->DimmPlPresent |= DimmMask; // Dimm is planar
- }
-
- // specify the number of ranks
- Value8 = (SpdBufferPtr[SPD_DM_BANKS] & 0x07) + 1;
- if (Value8 > 2) {
- if (ChannelPtr->DimmQrPresent == 0) {
- // if any DIMMs are QR,
- // we have to make two passes through DIMMs
- //
- MaxDimms = MaxDimms << 1;
- }
-
- if (i < DimmSlots) {
- ChannelPtr->DimmQrPresent |= DimmMask;
- ChannelPtr->DimmQrPresent |= (DimmMask << 2);
- }
- Value8 = 2;
- } else if (Value8 == 2) {
- ChannelPtr->DimmDrPresent |= DimmMask; // Dual rank dimms
- }
-
- // Calculate bus loading per Channel
- if (Devwidth == 16) {
- Devwidth = 4;
- } else if (Devwidth == 4) {
- Devwidth = 16;
- }
- // double Addr bus load value for dual rank DIMMs
- if (Value8 == 2) {
- Devwidth = Devwidth << 1;
- }
-
- ChannelPtr->Ranks = ChannelPtr->Ranks + Value8;
- ChannelPtr->Loads = ChannelPtr->Loads + Devwidth;
- ChannelPtr->Dimms++;
-
- // Now examine the dimm packaging dates
- Value8 = SpdBufferPtr[SPD_MAN_DATE_YR];
- if (Value8 < M_YEAR_06) {
- ChannelPtr->DimmYr06 |= DimmMask; // Built before end of 2006
- ChannelPtr->DimmWk2406 |= DimmMask; // Built before end of week 24,2006
- } else if (Value8 == M_YEAR_06) {
- ChannelPtr->DimmYr06 |= DimmMask; // Built before end of 2006
- if (SpdBufferPtr[SPD_MAN_DATE_WK] <= M_WEEK_24) {
- ChannelPtr->DimmWk2406 |= DimmMask; // Built before end of week 24,2006
- }
- }
- } // if DIMM present
- } // Quadrank
- } // Dimm loop
-
- if (Channel == 0) {
- DCTPtr->Timings.DctDimmValid = ChannelPtr->ChDimmValid;
- DCTPtr->Timings.DimmSpdCse = ChannelPtr->DimmSpdCse;
- DCTPtr->Timings.DimmQrPresent = ChannelPtr->DimmQrPresent;
- DCTPtr->Timings.DimmDrPresent = ChannelPtr->DimmDrPresent;
- DCTPtr->Timings.Dimmx4Present = ChannelPtr->Dimmx4Present;
- DCTPtr->Timings.Dimmx8Present = ChannelPtr->Dimmx8Present;
- DCTPtr->Timings.Dimmx16Present = ChannelPtr->Dimmx16Present;
- }
- if ((Channel != 1) || (Dct != 1)) {
- MCTPtr->DimmPresent <<= 8;
- MCTPtr->DimmValid <<= 8;
- MCTPtr->RegDimmPresent <<= 8;
- MCTPtr->DimmEccPresent <<= 8;
- MCTPtr->DimmParPresent <<= 8;
- }
- } // Channel loop
- } // DCT loop
-
-
- // If we have DIMMs, some further general characteristics checking
- if (MCTPtr->DimmValid) {
- // If there are registered dimms, all the dimms must be registered
- if (MCTPtr->RegDimmPresent == MCTPtr->DimmValid) {
- // All dimms registered
- MCTPtr->Status[SbRegistered] = TRUE;
- } else if (MCTPtr->RegDimmPresent) {
- // We have an illegal DIMM mismatch
- PutEventLog (AGESA_FATAL, MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_FATAL, MCTPtr);
- }
-
- // check the ECC capability of the DIMMs
- if (MCTPtr->DimmEccPresent == MCTPtr->DimmValid) {
- MCTPtr->Status[SbEccDimms] = TRUE; // All dimms ECC capable
- }
-
- // check the parity capability of the DIMMs
- if (MCTPtr->DimmParPresent == MCTPtr->DimmValid) {
- MCTPtr->Status[SbParDimms] = TRUE; // All dimms parity capable
- }
- } else {
- }
-
- NBPtr->SwitchDCT (NBPtr, 0);
- NBPtr->SwitchChannel (NBPtr, 0);
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function finds the best T and CL primary timing parameter pair, per Mfg.,for the given
- * set of DIMMs, and store into DIE_STRUCT(.Speed and .Casl).
- * See "Global relationship between index values and item values" for definition of
- * CAS latency index (j) and Frequency index (k).
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - indicates that a FATAL error has not occurred
- * @return FALSE - indicates that a FATAL error has occurred
- */
-
-BOOLEAN
-MemTSPDGetTargetSpeed2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- CONST UINT16 SpeedCvt[] = {
- DDR400_FREQUENCY,
- DDR533_FREQUENCY,
- DDR667_FREQUENCY,
- DDR800_FREQUENCY,
- DDR1066_FREQUENCY
- };
- INT8 i;
- INT8 j;
- INT8 k;
- INT8 Dct;
- INT8 Channel;
- UINT8 T1min;
- UINT8 CL1min;
- BOOLEAN IsSupported;
- MEM_NB_BLOCK *NBPtr;
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- CH_DEF_STRUCT *ChannelPtr;
-
- NBPtr = TechPtr->NBPtr;
- MCTPtr = TechPtr->NBPtr->MCTPtr;
-
- CL1min = 0xFF;
- T1min = 0xFF;
-
- // For DDR2, run SyncTargetSpeed first to get frequency limit into DCTPtr->Timings.Speed
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- NBPtr->DCTPtr->Timings.TargetSpeed = 16; // initialized with big number
- }
- NBPtr->SyncTargetSpeed (NBPtr);
-
- // Find target frequency and Tcl
- for (k = K_MAX; k >= K_MIN; k--) {
- for (j = J_MIN; j <= J_MAX; j++) {
- if (MemTSysCapability2 (TechPtr, k, j)) {
- IsSupported = TRUE;
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) {
- NBPtr->SwitchChannel (NBPtr, Channel);
- ChannelPtr = NBPtr->ChannelPtr;
- for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) {
- if (ChannelPtr->ChDimmValid & ((UINT8)1 << i)) {
- if (!MemTDimmSupports2 (TechPtr, k, j, i)) {
- IsSupported = FALSE;
- Dct = NBPtr->DctCount;
- Channel = NBPtr->ChannelCount;
- break;
- }
- }
- }
- }
- }
-
- if (IsSupported) {
- T1min = k;
- CL1min = j;
- // Kill the loops...
- k = K_MIN - 1;
- j = J_MAX + 1;
- }
- }
- }
- }
-
- if (T1min == 0xFF) {
- // Failsafe values, running in minimum mode
- PutEventLog (AGESA_FATAL, MEM_ERROR_MISMATCH_DIMM_CLOCKS, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- PutEventLog (AGESA_FATAL, MEM_ERROR_MINIMUM_MODE, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_ERROR, MCTPtr);
-
- T1min = T_DEF;
- CL1min = CL_DEF;
- }
-
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- DCTPtr = NBPtr->DCTPtr;
- DCTPtr->Timings.TargetSpeed = SpeedCvt[T1min - 1];
- }
-
- // Ensure the target speed can be applied to all channels of the current node
- NBPtr->SyncTargetSpeed (NBPtr);
-
- // Set the start-up frequency
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- DCTPtr = NBPtr->DCTPtr;
- DCTPtr->Timings.Speed = DCTPtr->Timings.TargetSpeed;
- DCTPtr->Timings.CasL = CL1min + 2; // Convert to clocks
- }
-
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function check the symmetry of DIMM pairs (DIMM on Channel A matching with
- * DIMM on Channel B), the overall DIMM population, and determine the width mode:
- * 64-bit, 64-bit muxed, 128-bit.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - indicates that a FATAL error has not occurred
- * @return FALSE - indicates that a FATAL error has occurred
- */
-
-BOOLEAN
-MemTSPDCalcWidth2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 *SpdBufferAPtr;
- UINT8 *SpdBufferBPtr;
- MEM_NB_BLOCK *NBPtr;
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- UINT8 i;
- UINT16 DimmMask;
- UINT8 UngangMode;
-
- NBPtr = TechPtr->NBPtr;
- MCTPtr = NBPtr->MCTPtr;
- DCTPtr = NBPtr->DCTPtr;
-
- UngangMode = UserOptions.CfgMemoryModeUnganged;
- IDS_OPTION_HOOK (IDS_GANGING_MODE, &UngangMode, &(NBPtr->MemPtr->StdHeader));
-
- // Check symmetry of channel A and channel B dimms for 128-bit mode
- // capability.
- //
- AGESA_TESTPOINT (TpProcMemModeChecking, &(NBPtr->MemPtr->StdHeader));
- i = 0;
- if (MCTPtr->DctData[0].Timings.DctDimmValid == MCTPtr->DctData[1].Timings.DctDimmValid) {
- for (; i < MAX_DIMMS_PER_CHANNEL; i++) {
- DimmMask = (UINT16)1 << i;
- if (DCTPtr->Timings.DctDimmValid & DimmMask) {
- NBPtr->SwitchDCT (NBPtr, 0);
- MemTGetDimmSpdBuffer2 (TechPtr, &SpdBufferAPtr, i);
- NBPtr->SwitchDCT (NBPtr, 1);
- MemTGetDimmSpdBuffer2 (TechPtr, &SpdBufferBPtr, i);
-
- if ((SpdBufferAPtr[SPD_ROW_SZ]&0x1F) != (SpdBufferBPtr[SPD_ROW_SZ]&0x1F)) {
- break;
- }
-
- if ((SpdBufferAPtr[SPD_COL_SZ]&0x1F) != (SpdBufferBPtr[SPD_COL_SZ]&0x1F)) {
- break;
- }
-
- if (SpdBufferAPtr[SPD_BANK_SZ] != SpdBufferBPtr[SPD_BANK_SZ]) {
- break;
- }
-
- if ((SpdBufferAPtr[SPD_DEV_WIDTH]&0x7F) != (SpdBufferBPtr[SPD_DEV_WIDTH]&0x7F)) {
- break;
- }
-
- if ((SpdBufferAPtr[SPD_DM_BANKS]&0x07) != (SpdBufferBPtr[SPD_DM_BANKS]&0x07)) {
- break;
- }
- }
- }
- }
- if (i < MAX_DIMMS_PER_CHANNEL) {
- PutEventLog (AGESA_ALERT, MEM_ALERT_ORG_MISMATCH_DIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_ALERT, MCTPtr);
- } else if (!UngangMode) {
- NBPtr->Ganged = TRUE;
- MCTPtr->GangedMode = TRUE;
- MCTPtr->Status[Sb128bitmode] = TRUE;
- NBPtr->SetBitField (NBPtr, BFDctGangEn, 1);
- }
-
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Initialize DCT Timing registers as per DIMM SPD.
- * For primary timing (T, CL) use best case T value.
- * For secondary timing params., use most aggressive settings
- * of slowest DIMM.
- *
- * Note:
- * There are three components to determining "maximum frequency": SPD component,
- * Bus load component, and "Preset" max frequency component.
- * The SPD component is a function of the min cycle time specified by each DIMM,
- * and the interaction of cycle times from all DIMMs in conjunction with CAS
- * latency. The SPD component only applies when user timing mode is 'Auto'.
- *
- * The Bus load component is a limiting factor determined by electrical
- * characteristics on the bus as a result of varying number of device loads. The
- * Bus load component is specific to each platform but may also be a function of
- * other factors. The bus load component only applies when user timing mode is
- * ' Auto'.
- *
- * The Preset component is subdivided into three items and is the minimum of
- * the set: Silicon revision, user limit setting when user timing mode is 'Auto' and
- * memclock mode is 'Limit', OEM build specification of the maximum frequency.
- * The Preset component only applies when user timing mode is 'Auto'.
-
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - indicates that a FATAL error has not occurred
- * @return FALSE - indicates that a FATAL error has occurred
- */
-
-BOOLEAN
-MemTAutoCycTiming2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- CONST UINT8 SpdIndexes[] = {
- SPD_TRCD,
- SPD_TRP,
- SPD_TRTP,
- SPD_TRAS,
- SPD_TRC,
- SPD_TWR,
- SPD_TRRD,
- SPD_TWTR
- };
- CONST UINT8 Multiples[] = {10, 10, 10, 40, 40, 10, 10, 10};
-
- CONST UINT8 Tab1KTfawTK[] = {8, 10, 13, 14, 0, 20};
- CONST UINT8 Tab2KTfawTK[] = {10, 14, 17, 18, 0, 24};
- CONST UINT8 TabDefTrcK[] = {0x41, 0x3C, 0x3C, 0x3A, 0, 0x3A};
-
- UINT8 MiniMaxTmg[GET_SIZE_OF (SpdIndexes)];
- UINT8 MiniMaxTrfc[4];
-
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- MEM_NB_BLOCK *NBPtr;
- UINT16 DimmMask;
- UINT16 Value16;
- UINT16 Tk40;
- UINT8 i;
- UINT8 j;
- UINT8 Value8;
- UINT8 Temp8;
- UINT8 *StatTmgPtr;
- UINT16 *StatDimmTmgPtr;
- BOOLEAN Is1066;
- UINT8 *SpdBufferPtr;
-
- NBPtr = TechPtr->NBPtr;
- MCTPtr = NBPtr->MCTPtr;
- DCTPtr = NBPtr->DCTPtr;
-
- // initialize mini-max arrays
- for (j = 0; j < GET_SIZE_OF (MiniMaxTmg); j++) {
- MiniMaxTmg[j] = 0;
- }
- for (j = 0; j < GET_SIZE_OF (MiniMaxTrfc); j++) {
- MiniMaxTrfc[j] = 0;
- }
-
- // ======================================================================
- // Get primary timing (CAS Latency and Cycle Time)
- // ======================================================================
- // Get OEM specific load variant max
- //
-
- //======================================================================
- // Gather all DIMM mini-max values for cycle timing data
- //======================================================================
- //
- DimmMask = 1;
- for (i = 0; i < (MAX_CS_PER_CHANNEL / 2); i++) {
- if (DCTPtr->Timings.DctDimmValid & DimmMask) {
- MemTGetDimmSpdBuffer2 (TechPtr, &SpdBufferPtr, i);
- for (j = 0; j < GET_SIZE_OF (SpdIndexes); j++) {
- Value8 = SpdBufferPtr[SpdIndexes[j]];
- if (SpdIndexes[j] == SPD_TRC) {
- if (Value8 == 0 || Value8 == 0xFF) {
- PutEventLog (AGESA_WARNING, MEM_WARNING_NO_SPDTRC_FOUND, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, i, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_WARNING, MCTPtr);
- Value8 = TabDefTrcK[(DCTPtr->Timings.Speed / 66) - 3];
- }
- }
- if (MiniMaxTmg[j] < Value8) {
- MiniMaxTmg[j] = Value8;
- }
- }
-
- // get Trfc0 - Trfc3 values
- Value8 = SpdBufferPtr[SPD_BANK_SZ];
- Temp8 = (Value8 << 3) | (Value8 >> 5);
- Value8 = SpdBufferPtr[SPD_DEV_WIDTH];
- ASSERT (LibAmdBitScanReverse ((UINT32)Value8) <= 4);
- Temp8 >>= 4 - LibAmdBitScanReverse ((UINT32)Value8);
- Value8 = LibAmdBitScanReverse ((UINT32)Temp8);
- if (MiniMaxTrfc[i] < Value8) {
- MiniMaxTrfc[i] = Value8;
- }
- }
- DimmMask <<= 1;
- }
-
- // ======================================================================
- // Convert DRAM CycleTiming values and store into DCT structure
- // ======================================================================
- //
- Tk40 = 40000 / DCTPtr->Timings.Speed;
- if (DCTPtr->Timings.Speed == DDR1066_FREQUENCY) {
- Is1066 = TRUE;
- } else {
- Is1066 = FALSE;
- }
- // Notes:
- // 1. All secondary time values given in SPDs are in binary with UINTs of ns.
- // 2. Some time values are scaled by four, in order to have least count of 0.25 ns
- // (more accuracy). JEDEC SPD spec. shows which ones are x1 and x4.
- // 3. Internally to this SW, cycle time, Tk, is scaled by 10 to affect a
- // least count of 0.1 ns (more accuracy).
- // 4. SPD values not scaled are multiplied by 10 and then divided by 10T to find
- // equivalent minimum number of bus clocks (a remainder causes round-up of clocks).
- // 5. SPD values that are prescaled by 4 are multiplied by 10 and then divided by 40T to find
- // equivalent minimum number of bus clocks (a remainder causes round-up of clocks).
- //
- StatDimmTmgPtr = &DCTPtr->Timings.DIMMTrcd;
- StatTmgPtr = &DCTPtr->Timings.Trcd;
- for (j = 0; j < GET_SIZE_OF (SpdIndexes); j++) {
- Value16 = (UINT16)MiniMaxTmg[j] * Multiples[j];
- StatDimmTmgPtr[j] = Value16;
-
- MiniMaxTmg[j] = (UINT8) ((Value16 + Tk40 - 1) / Tk40);
- if (SpdIndexes[j] == SPD_TRTP) {
- MiniMaxTmg[j] = (DCTPtr->Timings.Speed <= DDR533_FREQUENCY) ? 2 : 3; // based on BL of 32 bytes
- }
-
- StatTmgPtr[j] = MiniMaxTmg[j];
- }
- DCTPtr->Timings.Trfc0 = MiniMaxTrfc[0];
- DCTPtr->Timings.Trfc1 = MiniMaxTrfc[1];
- DCTPtr->Timings.Trfc2 = MiniMaxTrfc[2];
- DCTPtr->Timings.Trfc3 = MiniMaxTrfc[3];
-
- DCTPtr->Timings.CasL = MemTSPDGetTCL2 (TechPtr);
-
- if (DCTPtr->Timings.DIMM1KPage) {
- DCTPtr->Timings.Tfaw = Tab1KTfawTK[(DCTPtr->Timings.Speed / 66) - 3];
- } else {
- DCTPtr->Timings.Tfaw = Tab2KTfawTK[(DCTPtr->Timings.Speed / 66) - 3];
- }
- if (Is1066) {
- DCTPtr->Timings.Tfaw >>= 1;
- }
-
- //======================================================================
- // Program DRAM Timing values
- //======================================================================
- //
- NBPtr->ProgramCycTimings (NBPtr);
-
- MemFInitTableDrive (NBPtr, MTAfterAutoCycTiming);
-
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the bank addressing, program Mask values and build a chip-select population map.
- * This routine programs PCI 0:24N:2x80 config register.
- * This routine programs PCI 0:24N:2x60,64,68,6C config registers (CS Mask 0-3)
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - indicates that a FATAL error has not occurred
- * @return FALSE - indicates that a FATAL error has occurred
- */
-
-BOOLEAN
-MemTSPDSetBanks2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 *SpdBufferPtr;
- UINT8 i;
- UINT8 ChipSel;
- UINT8 DimmID;
- UINT8 Value8;
- UINT8 Rows;
- UINT8 Cols;
- UINT8 Ranks;
- UINT8 Banks;
- UINT32 BankAddrReg;
- UINT32 CsMask;
- UINT16 CSSpdCSE;
- UINT16 CSExclude;
- UINT16 DimmQRDR;
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
- MCTPtr = NBPtr->MCTPtr;
- DCTPtr = NBPtr->DCTPtr;
-
- BankAddrReg = 0;
- CSSpdCSE = 0;
- CSExclude = 0;
- for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) {
- DimmID = ChipSel >> 1;
-
- DimmQRDR = (DCTPtr->Timings.DimmQrPresent) | (DCTPtr->Timings.DimmDrPresent);
- if (DCTPtr->Timings.DimmSpdCse & (UINT16) 1 << DimmID) {
- CSSpdCSE |= (UINT16) ((DimmQRDR & (UINT16) 1 << DimmID) ? 3 : 1) << ChipSel;
- }
- if ((DCTPtr->Timings.DimmExclude & ((UINT16) 1 << DimmID)) != 0) {
- CSExclude |= (UINT16) ((DimmQRDR & (UINT16) 1 << DimmID) ? 3: 1) << ChipSel;
- }
-
- if (DCTPtr->Timings.DctDimmValid & ((UINT16)1 << DimmID)) {
- MemTGetDimmSpdBuffer2 (TechPtr, &SpdBufferPtr, DimmID);
-
- // Get the basic data
- Rows = SpdBufferPtr[SPD_ROW_SZ] & 0x1F;
- Cols = SpdBufferPtr[SPD_COL_SZ] & 0x1F;
- Banks = SpdBufferPtr[SPD_L_BANKS];
- Ranks = (SpdBufferPtr[SPD_DM_BANKS] & 0x07) + 1;
-
- // Configure the bank encoding
- Value8 = (Cols - 9) << 3;
- Value8 |= (Banks == 8) ? 4 : 0;
- Value8 |= (Rows - 13);
-
- for (i = 0; i < 12; i++) {
- if (Value8 == MemTGetBankAddr2 (i)) {
- break;
- }
- }
-
- if (i < 12) {
- BankAddrReg |= ((UINT32)i << (ChipSel << 1));
-
- // Mask value=(2pow(rows+cols+banks+3)-1)>>8,
- // or 2pow(rows+cols+banks-5)-1
- //
- Value8 = Rows + Cols;
- Value8 -= (Banks == 8) ? 2:3;
- if (MCTPtr->Status[Sb128bitmode]) {
- Value8++;
- }
- CsMask = ((UINT32)1 << Value8) - 1;
- DCTPtr->Timings.CsPresent |= (UINT16)1 << ChipSel;
-
- if (Ranks >= 2) {
- DCTPtr->Timings.CsPresent |= (UINT16)1 << (ChipSel + 1);
- }
-
- // Update the DRAM CS Mask for this chipselect
- NBPtr->SetBitField (NBPtr, BFCSMask0Reg + (ChipSel >> 1), (CsMask & NBPtr->CsRegMsk));
- }
- }
- }
- // For ranks that need to be excluded, the loading of this rank should be considered
- // in timing, so need to set CsPresent before setting CsTestFail
- if ((CSSpdCSE != 0) || (CSExclude != 0)) {
- NBPtr->MemPtr->ErrorHandling (MCTPtr, NBPtr->Dct, (CSSpdCSE | CSExclude), &NBPtr->MemPtr->StdHeader);
- }
-
- // If there are no chip selects, we have an error situation.
- if (DCTPtr->Timings.CsPresent == 0) {
- PutEventLog (AGESA_ERROR, MEM_ERROR_NO_CHIPSELECT, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_ERROR, MCTPtr);
- }
-
- NBPtr->SetBitField (NBPtr, BFDramBankAddrReg, BankAddrReg);
-
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function returns the low bit that will be swapped to enable CS interleaving
- *
- * @param[in] BankEnc - AddrMap Bank encoding from F2x80
- * @param[in] *LowBit - pointer to low bit
- * @param[in] *HiBit - pointer hight bit
- *
- */
-
-VOID
-MemTGetCSIntLvAddr2 (
- IN UINT8 BankEnc,
- OUT UINT8 *LowBit,
- OUT UINT8 *HiBit
- )
-{
- CONST UINT8 ArrCodesLo[] = {6, 7, 7, 8, 8, 8, 8, 8, 9, 9, 8, 9};
- CONST UINT8 ArrCodesHi[] = {19, 20, 21, 21, 21, 22, 22, 23, 23, 24, 24, 25};
- ASSERT (BankEnc < GET_SIZE_OF (ArrCodesLo));
- ASSERT (BankEnc < GET_SIZE_OF (ArrCodesHi));
- // return ArrCodes[BankEnc];
- *LowBit = ArrCodesLo[BankEnc];
- *HiBit = ArrCodesHi[BankEnc];
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function returns the CAS latency of the current frequency.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return CAS Latency
- */
-UINT8
-STATIC
-MemTSPDGetTCL2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- return TechPtr->NBPtr->DCTPtr->Timings.CasL;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Get max frequency from OEM platform definition, from
- * any user override (limiting) of max frequency, and
- * from any Si Revision Specific information. Return
- * the least of these three in DIE_STRUCT.PresetmaxFreq.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] k - Frequency index
- * @param[in] j - CAS Latency index
- *
- * @return TRUE - (k << 8) | j
- * @return FALSE - 0
- */
-
-BOOLEAN
-STATIC
-MemTSysCapability2 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 k,
- IN UINT16 j
- )
-{
- if ((k > TechPtr->NBPtr->DCTPtr->Timings.TargetSpeed) || (j > J_MAX)) {
- return FALSE;
- }
-
- return TRUE; //(k << 8) | j;
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Determine whether dimm(b,i) supports CL(j) and F(k)
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] k - Frequency index
- * @param[in] j - CAS Latency index
- * @param[in] i - DIMM number
- *
- * @return TRUE - DIMM supports
- * @return FALSE - DIMM does not support
- */
-
-BOOLEAN
-STATIC
-MemTDimmSupports2 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 k,
- IN UINT8 j,
- IN UINT8 i
- )
-{
- CONST UINT8 SpdBytesForCL[3] = { 9, 23, 25}; // SPD bytes for CL X, CL X-.5, and CL X-1
- UINT8 CLj;
- UINT8 CLi;
- UINT8 T1;
- UINT8 T2;
- UINT8 Tk;
- UINT8 *SpdBufferPtr;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
-
- MemTGetDimmSpdBuffer2 (TechPtr, &SpdBufferPtr, i);
- CLj = (UINT8) 1 << (j + 2);
- CLi = SpdBufferPtr[SPD_CAS_LAT];
-
- if (CLj & CLi) {
- // If this dimm supports the desired CAS latency...
- // Determine the SPD location of the dimm speed UINT8 appropriate
- // to the CAS latency indicated by Table_CL2_j.
- //
- T1 = LibAmdBitScanReverse ((UINT32)CLj);
- T2 = LibAmdBitScanReverse ((UINT32)CLi);
- ASSERT ((T2 - T1) < 3);
- CLi = SpdBufferPtr[SpdBytesForCL[(T2 - T1)]];
- Tk = MemTGetTk2 (k);
- if (CLi == 0) {
- PutEventLog (AGESA_FATAL, MEM_ERROR_NO_CYC_TIME, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_WARNING, NBPtr->MCTPtr);
- } else if (Tk >= CLi) {
- return TRUE;
- }
- }
- return FALSE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function returns the cycle time
- *
- * @param[in] k - CAS Latency index
- *
- * @return Tk as specified by JEDEC SPD byte 9.
- */
-
-UINT8
-STATIC
-MemTGetTk2 (
- IN UINT8 k
- )
-{
- CONST UINT8 TableTK[] = {0x00, 0x50, 0x3D, 0x30, 0x25, 0x18};
- ASSERT (k < GET_SIZE_OF (TableTK));
- return TableTK[k];
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function returns the encoded value of bank address.
- *
- * @param[in] k value
- *
- * @return RRRBCC, where CC is the number of Columns minus 9,
- * RRR is the number of Rows minus 12, and B is the number of banks
- * minus 3.
- */
-
-UINT8
-STATIC
-MemTGetBankAddr2 (
- IN UINT8 k
- )
-{
- CONST UINT8 TabBankAddr[] = {
- 0x00, 0x08, 0x09, 0x10, 0x0C, 0x0D,
- 0x11, 0x0E, 0x15, 0x16, 0x0F, 0x17
- };
- ASSERT (k < GET_SIZE_OF (TabBankAddr));
- return TabBankAddr[k];
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function returns a pointer to the SPD Buffer of a specific dimm on
- * the current channel.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in,out] **SpdBuffer - Pointer to a pointer to a UINT8 Buffer
- * @param[in] Dimm - Dimm number
- *
- *
- * @return BOOLEAN - Value of DimmPresent
- * TRUE = Dimm is present, pointer is valid
- * FALSE = Dimm is not present, pointer has not been modified.
- */
-
-BOOLEAN
-MemTGetDimmSpdBuffer2 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT UINT8 **SpdBuffer,
- IN UINT8 Dimm
- )
-{
- CH_DEF_STRUCT *ChannelPtr;
- SPD_DEF_STRUCT *SPDPtr;
- BOOLEAN DimmPresent;
-
- DimmPresent = FALSE;
- ChannelPtr = TechPtr->NBPtr->ChannelPtr;
- ASSERT (Dimm < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0])))
- SPDPtr = ChannelPtr->DimmSpdPtr[Dimm];
-
-
- if (SPDPtr != NULL) {
- DimmPresent = SPDPtr->DimmPresent;
- if (DimmPresent) {
- *SpdBuffer = SPDPtr->Data;
- }
- }
- return DimmPresent;
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mtspd2.h b/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mtspd2.h
deleted file mode 100644
index bd212d9eb0..0000000000
--- a/src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR2/mtspd2.h
+++ /dev/null
@@ -1,182 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mtspd2.h
- *
- * Technology SPD support for DDR2
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR2)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ***************************************************************************
- *
- */
-
-#ifndef _MTSPD2_H_
-#define _MTSPD2_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*===============================================================================
- * Jedec DDR II
- *===============================================================================
- */
-#define SPD_TYPE 2 /* SPD byte read location */
-#define JED_DDR_SDRAM 7 /* Jedec defined bit field */
-#define JED_DDR2_SDRAM 8 /* Jedec defined bit field */
-
-#define SPD_DIMM_TYPE 20
-#define SPD_ATTRIB 21
-#define JED_DIF_CK_MSK 0x20 /* Differential Clock Input */
-#define JED_REG_ADC_MSK 0x11 /* Registered Address/Control */
-#define JED_PROBE_MSK 0x40 /* Analysis Probe installed */
-#define JED_SODIMM 0x04 /* SO-DIMM */
-#define SPD_DEV_ATTRIB 22
-#define SPD_EDC_TYPE 11
-#define JED_ECC 2
-#define JED_ADRC_PAR 4
-#define SPD_ROW_SZ 3
-#define SPD_COL_SZ 4
-#define SPD_L_BANKS 17 /* number of [logical] banks on each device */
-#define SPD_DM_BANKS 5 /* number of physical banks on dimm */
-#define SP_DPL_BIT 4 /* Dram package bit */
-#define SPD_BANK_SZ 31 /* capacity of physical bank */
-#define SPD_DEV_WIDTH 13
-#define SPD_CAS_LAT 18
-#define SPD_TRP 27
-#define SPD_TRRD 28
-#define SPD_TRCD 29
-#define SPD_TRAS 30
-#define SPD_TWR 36
-#define SPD_TWTR 37
-#define SPD_TRTP 38
-#define SPD_TRC 41
-#define SPD_TRFC 42
-#define SPD_CHECKSUM 63
-#define SPD_MAN_DATE_YR 93 /* Module Manufacturing Year (BCD) */
-
-#define SPD_MAN_DATE_WK 94 /* Module Manufacturing Week (BCD) */
-
-/*-----------------------------
- * Jedec DDR II related equates
- *-----------------------------
- */
-#define M_YEAR_06 0x06 /* Manufacturing Year BCD encoding of 2006 - 06d */
-#define M_WEEK_24 0x24 /* Manufacturing Week BCD encoding of June - 24d */
-
-#define J_MIN 0 /* j loop constraint. 1=CL 2.0 T */
-#define J_MAX 5 /* j loop constraint. 5=CL 7.0 T */
-#define K_MIN 1 /* k loop constraint. 1=200 MHz */
-#define K_MAX 5 /* k loop constraint. 5=533 MHz */
-#define CL_DEF 2 /* Default value for failsafe operation. 2=CL 4.0 T */
-#define T_DEF 1 /* Default value for failsafe operation. 1=5ns (cycle time) */
-
-
-#define BIAS_TCL_T 1
-#define BIAS_TRP_T 3 /* bias to convert bus clocks to bit field value */
-#define BIAS_TRRD_T 2
-#define BIAS_TRCD_T 3
-#define BIAS_TRAS_T 3
-#define BIAS_TRC_T 11
-#define BIAS_TRTP_T 1
-#define BIAS_TWR_T 3
-#define BIAS_TWTR_T 0
-#define BIAS_TFAW_T 7
-
-#define MIN_TRP_T 3 /* min programmable value in busclocks */
-#define MAX_TRP_T 6 /* max programmable value in busclocks */
-#define MIN_TRRD_T 2
-#define MAX_TRRD_T 5
-#define MIN_TRCD_T 3
-#define MAX_TRCD_T 6
-#define MIN_TRAS_T 5
-#define MAX_TRAS_T 18
-#define MIN_TRC_T 11
-#define MAX_TRC_T 26
-#define MIN_TRTP_T 2
-#define MAX_TRTP_T 4
-#define MIN_TWR_T 3
-#define MAX_TWR_T 6
-#define MIN_TWTR_T 1
-#define MAX_TWTR_T 3
-
-/* DDR2-1066 support */
-#define BIAS_TRCD_T_1066 5
-#define BIAS_TRAS_T_1066 15
-#define BIAS_TRRD_T_1066 4
-#define BIAS_TWR_T_1066 4
-#define BIAS_TRP_T_1066 5
-#define BIAS_TWTR_T_1066 4
-
-#define MIN_TRCD_T_1066 5
-#define MAX_TRCD_T_1066 12
-#define MIN_TRAS_T_1066 15
-#define MAX_TRAS_T_1066 30
-#define MIN_TRC_T_1066 11
-#define MAX_TRC_T_1066 42
-#define MIN_TRRD_T_1066 4
-#define MAX_TRRD_T_1066 7
-#define MIN_TWR_T_1066 5
-#define MAX_TWR_T_1066 8
-#define MIN_TRP_T_1066 5
-#define MAX_TRP_T_1066 12
-#define MIN_TWTR_T_1066 4
-#define MAX_TWTR_T_1066 7
-
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-
-#endif /* _MTSPD2_H_ */
-
-