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authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-12-23 23:48:01 +1100
committerEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-12-26 09:16:29 +0100
commitf679cfe429637ab5171a6c3453971ceb8da82800 (patch)
tree07f6dece91d0d2288b4c7443fa8d012adc3db1dc /src
parent5b63dc1ff822e56ebabcb60fa4afd46f7f7e08c3 (diff)
soc/samsung/exynos: Sync 'power.c' between chip variants
Change-Id: I06d83be840b49ee7523b34e1dba5ec038256b3f4 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7918 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/samsung/exynos5250/power.c6
-rw-r--r--src/soc/samsung/exynos5250/power.h2
2 files changed, 5 insertions, 3 deletions
diff --git a/src/soc/samsung/exynos5250/power.c b/src/soc/samsung/exynos5250/power.c
index 27089c66d9..7d947121de 100644
--- a/src/soc/samsung/exynos5250/power.c
+++ b/src/soc/samsung/exynos5250/power.c
@@ -22,7 +22,9 @@
#include <arch/io.h>
#include <console/console.h>
#include <halt.h>
+#include "dmc.h"
#include "power.h"
+#include "setup.h"
/* Set the PS-Hold drive value */
static void ps_hold_setup(void)
@@ -51,7 +53,7 @@ void power_shutdown(void)
void power_enable_dp_phy(void)
{
- setbits_le32(&exynos_power->dptx_phy_control, DPTX_PHY_ENABLE);
+ setbits_le32(&exynos_power->dptx_phy_control, EXYNOS_DP_PHY_ENABLE);
}
void power_enable_hw_thermal_trip(void)
@@ -82,7 +84,7 @@ void power_enable_xclkout(void)
{
/* use xxti for xclk out */
clrsetbits_le32(&exynos_power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK,
- PMU_DEBUG_XXTI);
+ PMU_DEBUG_XXTI);
}
void power_release_uart_retention(void)
diff --git a/src/soc/samsung/exynos5250/power.h b/src/soc/samsung/exynos5250/power.h
index 734bb29661..28f25a6ec1 100644
--- a/src/soc/samsung/exynos5250/power.h
+++ b/src/soc/samsung/exynos5250/power.h
@@ -34,7 +34,7 @@ void power_enable_hw_thermal_trip(void);
#define POWER_PS_HOLD_CONTROL_DATA_HIGH (1 << 8)
#define POWER_ENABLE_HW_TRIP (1UL << 31)
-#define DPTX_PHY_ENABLE (1 << 0)
+#define EXYNOS_DP_PHY_ENABLE (1 << 0)
/* PMU_DEBUG bits [12:8] = 0x1000 selects XXTI clock source */
#define PMU_DEBUG_XXTI 0x1000