diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-26 19:18:09 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-01-27 21:28:18 +0000 |
| commit | e2ec60f28b06c17c6d1c5c3ecf01ae5cefb4d9a6 (patch) | |
| tree | 0d1bf97618d4dfbc07f01d78b0c7b9d8fad6da57 /src | |
| parent | cbd5bb9cc755ad406e7e13572ff104af1f8b269d (diff) | |
nb/intel/haswell/haswell.h: Do not include `pch.h`
Avoid indirect header inclusion, include `pch.h` where necessary.
Change-Id: I6b72976a28ffaad68bcf558c8a13b5c221070522
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/intel/haswell/gma.c | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/haswell.h | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/northbridge.c | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/acpi/lpc.asl | 2 |
4 files changed, 4 insertions, 2 deletions
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 21053ec1c0..3746fe35cc 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -15,6 +15,7 @@ #include <drivers/intel/gma/libgfxinit.h> #include <cpu/intel/haswell/haswell.h> #include <drivers/intel/gma/opregion.h> +#include <southbridge/intel/lynxpoint/pch.h> #include <string.h> #include <types.h> diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index edca2b6330..d28c7d4fc0 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -10,8 +10,6 @@ #include "memmap.h" -#include <southbridge/intel/lynxpoint/pch.h> - /* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__ diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 2d19ccdda5..d25338033d 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -13,6 +13,7 @@ #include <device/pci_ops.h> #include <boot/tables.h> #include <security/intel/txt/txt_register.h> +#include <southbridge/intel/lynxpoint/pch.h> #include "chip.h" #include "haswell.h" diff --git a/src/southbridge/intel/lynxpoint/acpi/lpc.asl b/src/southbridge/intel/lynxpoint/acpi/lpc.asl index a823b7084b..2e230ea47d 100644 --- a/src/southbridge/intel/lynxpoint/acpi/lpc.asl +++ b/src/southbridge/intel/lynxpoint/acpi/lpc.asl @@ -2,6 +2,8 @@ // Intel LPC Bus Device - 0:1f.0 +#include <southbridge/intel/lynxpoint/pch.h> + Device (LPCB) { Name (_ADR, 0x001f0000) |