Various minor cosmetics and coding style fixes (trivial).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

25 files changed, 657 insertions, 645 deletions

diff --git a/src/mainboard/asus/mew-vm/auto.c b/src/mainboard/asus/mew-vm/auto.c
index 3c993f1fbe..63c5e82704 100644
--- a/src/mainboard/asus/mew-vm/auto.c
+++ b/src/mainboard/asus/mew-vm/auto.c
@@ -38,10 +38,11 @@
 
 #include "southbridge/intel/i82801xx/i82801xx_early_smbus.c"
 
+/* TODO: Not needed? */
 void udelay(int usecs) 
 {
 	int i;
-	for(i = 0; i < usecs; i++)
+	for (i = 0; i < usecs; i++)
 		outb(i&0xff, 0x80);
 }
 
@@ -57,50 +58,31 @@ static void main(unsigned long bist)
 	static const struct mem_controller memctrl[] = {
 		{
 		 .d0 = PCI_DEV(0, 0, 0),
-		 .channel0 = {
-			      (0xa << 3) | 0,
-			      (0xa << 3) | 1,
-			      },
+		 .channel0 = {0x50, 0x51},
 		 }
 	};
-	
-	if (bist == 0) {
+
+	if (bist == 0)
 		early_mtrr_init();
-	}
-	
+
 	enable_smbus();
-	
+
 	lpc47b272_enable_serial(SERIAL_DEV, TTYS0_BASE);
 	uart_init();
 	console_init();
 
-	/* Halt if there was a built in self test failure */
+	/* Halt if there was a built in self test failure. */
 	report_bist_failure(bist);
 
-	//enable_shadow_ram();
+	/* dump_spd_registers(&memctrl[0]); */
 
-	//dump_spd_registers(&memctrl[0]);
+	/* sdram_initialize() runs out of registers. */
+	/* sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); */
 
-	/* sdram_initialize runs out of registers */
-	//sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl);
-	
 	sdram_set_registers(memctrl);
 	sdram_set_spd_registers(memctrl);
 	sdram_enable(0, memctrl);
 
-	/* Check whether RAM is working.
-	 *
-	 * Do _not_ check the area from 640 KB - 1 MB, as that's not really
-	 * RAM, but rather reserved for various other things:
-	 *
-	 *  - 640 KB - 768 KB: Video Buffer Area
-	 *  - 768 KB - 896 KB: Expansion Area
-	 *  - 896 KB - 960 KB: Extended System BIOS Area
-	 *  - 960 KB - 1 MB:   Memory (BIOS Area) - System BIOS Area
-	 *
-	 * Trying to check these areas will fail.
-	 */
-	/* TODO: This is currently hardcoded to check 64 MB. */
-	//ram_check(0x00000000, 0x0009ffff);	/* 0 - 640 KB */
-	//ram_check(0x00100000, 0x007c0000);	/* 1 MB - 64 MB */
+	/* Check RAM. */
+	/* ram_check(0, 640 * 1024); */
 }
diff --git a/src/mainboard/asus/mew-vm/irq_tables.c b/src/mainboard/asus/mew-vm/irq_tables.c
index 5794344137..49a3652564 100644
--- a/src/mainboard/asus/mew-vm/irq_tables.c
+++ b/src/mainboard/asus/mew-vm/irq_tables.c
@@ -38,5 +38,5 @@ that would give 0 after the sum of all bytes for this structure (including check
 
 unsigned long write_pirq_routing_table(unsigned long addr)
 {
-        return copy_pirq_routing_table(addr);
+	return copy_pirq_routing_table(addr);
 }
diff --git a/src/mainboard/asus/mew-vm/mainboard.c b/src/mainboard/asus/mew-vm/mainboard.c
index 62d18c2cfe..4e03be0fea 100644
--- a/src/mainboard/asus/mew-vm/mainboard.c
+++ b/src/mainboard/asus/mew-vm/mainboard.c
@@ -4,4 +4,3 @@
 struct chip_operations mainboard_asus_mew_vm_ops = {
 	CHIP_NAME("ASUS MEW-VM Mainboard")
 };
-
diff --git a/src/northbridge/intel/i82810/chip.h b/src/northbridge/intel/i82810/chip.h
index 6187fde469..3e7e1eb0da 100644
--- a/src/northbridge/intel/i82810/chip.h
+++ b/src/northbridge/intel/i82810/chip.h
@@ -18,8 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-struct northbridge_intel_i82810_config
-{
+struct northbridge_intel_i82810_config {
 };
 
 extern struct chip_operations northbridge_intel_i82810_ops;
diff --git a/src/northbridge/intel/i82810/i82810.h b/src/northbridge/intel/i82810/i82810.h
index 0b406cead4..d5979787cb 100644
--- a/src/northbridge/intel/i82810/i82810.h
+++ b/src/northbridge/intel/i82810/i82810.h
@@ -34,26 +34,26 @@
  * should not be touched.
  */
 
-#define VID	0x00 /* Vendor Identification   */
-#define DID	0x02 /* Device Identification   */
-#define PCICMD	0x04 /* PCI Command Register    */
-#define PCISTS	0x06 /* PCI Status Register     */
-#define RID	0x08 /* Revision Identification */
-#define SUBC	0x0a /* Sub-Class Code          */
-#define BCC	0x0b /* Base Class Code         */
-#define MLT	0x0d /* Master Latency Timer    */
-#define HDR	0x0e /* Header Type             */
-#define SVID	0x2c /* Subsystem Vendor Identification  */
-#define SID	0x2e /* Subsystem Identification         */
-#define CAPPTR	0x34 /* Capabilities Pointer             */
+#define VID	0x00		/* Vendor Identification */
+#define DID	0x02		/* Device Identification */
+#define PCICMD	0x04		/* PCI Command Register */
+#define PCISTS	0x06		/* PCI Status Register */
+#define RID	0x08		/* Revision Identification */
+#define SUBC	0x0a		/* Sub-Class Code */
+#define BCC	0x0b		/* Base Class Code */
+#define MLT	0x0d		/* Master Latency Timer */
+#define HDR	0x0e		/* Header Type */
+#define SVID	0x2c		/* Subsystem Vendor Identification */
+#define SID	0x2e		/* Subsystem Identification */
+#define CAPPTR	0x34		/* Capabilities Pointer */
 
-/* TODO: Descriptions  */
+/* TODO: Descriptions. */
 #define GMCHCFG	0x50
 #define PAM	0x51
 #define DRP	0x52
 #define DRAMT	0x53
 #define FDHC	0x58
-#define SMRAM	0x70 /* System Management RAM Control */
+#define SMRAM	0x70		/* System Management RAM Control */
 #define MISSC	0x72
 #define MISSC2	0x80
 #define BUFF_SC	0x92
diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c
index 9758be39f7..29ace6e776 100644
--- a/src/northbridge/intel/i82810/northbridge.c
+++ b/src/northbridge/intel/i82810/northbridge.c
@@ -31,24 +31,24 @@
 #include "northbridge.h"
 #include "i82810.h"
 
-static void northbridge_init(device_t dev) 
+static void northbridge_init(device_t dev)
 {
 	printk_spew("Northbridge init\n");
 }
 
 static struct device_operations northbridge_operations = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init             = northbridge_init,
-	.enable           = 0,
-	.ops_pci          = 0,
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= northbridge_init,
+	.enable			= 0,
+	.ops_pci		= 0,
 };
 
 static struct pci_driver northbridge_driver __pci_driver = {
-	.ops = &northbridge_operations,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x7120,
+	.ops	= &northbridge_operations,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x7120,
 };
 
 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
@@ -62,16 +62,18 @@ static void pci_domain_read_resources(device_t dev)
 	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
 	resource->base = 0x400;
 	resource->limit = 0xffffUL;
-	resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	resource->flags =
+	    IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 
 	/* Initialize the system wide memory resources constraints */
 	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
 	resource->limit = 0xffffffffULL;
-	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	resource->flags =
+	    IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 }
 
 static void ram_resource(device_t dev, unsigned long index,
-        unsigned long basek, unsigned long sizek)
+			 unsigned long basek, unsigned long sizek)
 {
 	struct resource *resource;
 
@@ -79,10 +81,10 @@ static void ram_resource(device_t dev, unsigned long index,
 		return;
 	}
 	resource = new_resource(dev, index);
-	resource->base  = ((resource_t)basek) << 10;
-	resource->size  = ((resource_t)sizek) << 10;
-	resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
-		IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+	resource->base = ((resource_t) basek) << 10;
+	resource->size = ((resource_t) sizek) << 10;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE |
+	    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 }
 
 static void tolm_test(void *gp, struct device *dev, struct resource *new)
@@ -101,7 +103,8 @@ static uint32_t find_pci_tolm(struct bus *bus)
 	struct resource *min;
 	uint32_t tolm;
 	min = 0;
-	search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
+	search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test,
+			     &min);
 	tolm = 0xffffffffUL;
 	if (min && tolm > min->base) {
 		tolm = min->base;
@@ -143,7 +146,7 @@ static void pci_domain_set_resources(device_t dev)
 		/* Translate it to MB and add to tomk. */
 		tomk = (unsigned long)(translate_i82810_to_mb[drp_value & 0xf]);
 		/* Now do the same for DIMM 1. */
-		drp_value = drp_value >> 4; // >>= 4; //? mess with later
+		drp_value = drp_value >> 4;	// >>= 4; //? mess with later
 		tomk += (unsigned long)(translate_i82810_to_mb[drp_value]);
 
 		printk_debug("Setting RAM size to %d MB\n", tomk);
@@ -173,11 +176,11 @@ static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
 }
 
 static struct device_operations pci_domain_ops = {
-	.read_resources   = pci_domain_read_resources,
-	.set_resources    = pci_domain_set_resources,
-	.enable_resources = enable_childrens_resources,
-	.init             = 0,
-	.scan_bus         = pci_domain_scan_bus,
+	.read_resources		= pci_domain_read_resources,
+	.set_resources		= pci_domain_set_resources,
+	.enable_resources	= enable_childrens_resources,
+	.init			= 0,
+	.scan_bus		= pci_domain_scan_bus,
 };
 
 static void cpu_bus_init(device_t dev)
@@ -190,11 +193,11 @@ static void cpu_bus_noop(device_t dev)
 }
 
 static struct device_operations cpu_bus_ops = {
-	.read_resources   = cpu_bus_noop,
-	.set_resources    = cpu_bus_noop,
-	.enable_resources = cpu_bus_noop,
-	.init             = cpu_bus_init,
-	.scan_bus         = 0,
+	.read_resources		= cpu_bus_noop,
+	.set_resources		= cpu_bus_noop,
+	.enable_resources	= cpu_bus_noop,
+	.init			= cpu_bus_init,
+	.scan_bus		= 0,
 };
 
 static void enable_dev(struct device *dev)
@@ -205,8 +208,7 @@ static void enable_dev(struct device *dev)
 	if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 		dev->ops = &pci_domain_ops;
 		pci_set_method(dev);
-	}
-	else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
+	} else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 		dev->ops = &cpu_bus_ops;
 	}
 }
diff --git a/src/northbridge/intel/i82810/raminit.c b/src/northbridge/intel/i82810/raminit.c
index 8ebb25f89c..f0d5cb71e6 100644
--- a/src/northbridge/intel/i82810/raminit.c
+++ b/src/northbridge/intel/i82810/raminit.c
@@ -47,9 +47,9 @@ Macros and definitions.
 #endif
 
 /* DRAMT[7:5] - SDRAM Mode Select (SMS). */
-#define RAM_COMMAND_SELF_REFRESH 0x0 /* IE disable refresh */
-#define RAM_COMMAND_NORMAL	 0x1 /* Normal refresh, 15.6us/11.7us for 100/133MHz */
-#define RAM_COMMAND_NORMAL_FR	 0x2 /* Fast refresh, 7.8us/5.85us for 100/133MHz */
+#define RAM_COMMAND_SELF_REFRESH 0x0	/* IE disable refresh */
+#define RAM_COMMAND_NORMAL	 0x1	/* Normal refresh, 15.6us/11.7us for 100/133MHz */
+#define RAM_COMMAND_NORMAL_FR	 0x2	/* Fast refresh, 7.8us/5.85us for 100/133MHz */
 #define RAM_COMMAND_NOP		 0x4
 #define RAM_COMMAND_PRECHARGE	 0x5
 #define RAM_COMMAND_MRS		 0x6
@@ -86,7 +86,7 @@ static void do_ram_command(const struct mem_controller *ctrl, uint32_t command,
 	PRINT_DEBUG("    Sending RAM command 0x");
 	PRINT_DEBUG_HEX8(reg);
 	PRINT_DEBUG(" to 0x");
-	PRINT_DEBUG_HEX32(0 + addr_offset); // FIXME
+	PRINT_DEBUG_HEX32(0 + addr_offset);	// FIXME
 	PRINT_DEBUG("\r\n");
 
 	/* Read from (DIMM start address + addr_offset). */
@@ -98,7 +98,8 @@ static void do_ram_command(const struct mem_controller *ctrl, uint32_t command,
 DIMM-independant configuration functions.
 -----------------------------------------------------------------------------*/
 
-static void spd_set_dram_size(const struct mem_controller *ctrl, uint32_t row_offset)
+static void spd_set_dram_size(const struct mem_controller *ctrl,
+			      uint32_t row_offset)
 {
 	/* The variables drp and dimm_size have to be ints since all the
 	 * SMBus-related functions return ints, and its just easier this way.
@@ -106,9 +107,8 @@ static void spd_set_dram_size(const struct mem_controller *ctrl, uint32_t row_of
 	int i, drp, dimm_size;
 
 	drp = 0x00;
-	
-	for (i = 0; i < DIMM_SOCKETS; i++)
-	{
+
+	for (i = 0; i < DIMM_SOCKETS; i++) {
 		/* First check if a DIMM is actually present. */
 		if (smbus_read_byte(ctrl->channel0[i], 2) == 4) {
 			print_debug("Found DIMM in slot ");
@@ -126,37 +126,45 @@ static void spd_set_dram_size(const struct mem_controller *ctrl, uint32_t row_of
 			 * side. This will fail if the DIMM uses a
 			 * non-supported DRAM tech, and can't be used until
 			 * buffers are done dynamically.
-			 * Note: the factory BIOS just dies if it spots
-			 * this :D
+			 * Note: the factory BIOS just dies if it spots this :D
 			 */
-			if(dimm_size > 32) {
-				print_err("DIMM row sizes larger than 128MB not" 
-							"supported on i810\r\n");
-				print_err("Attempting to treat as 128MB DIMM\r\n");
+			if (dimm_size > 32) {
+				print_err("DIMM row sizes larger than 128MB not"
+					  "supported on i810\r\n");
+				print_err
+				    ("Attempting to treat as 128MB DIMM\r\n");
 				dimm_size = 32;
 			}
 
-			/* Set the row offset, in KBytes (should this be Kbits?) */
-			/* Note that this offset is the start of the next row. */
+			/* Set the row offset, in KBytes (should this be
+			 * Kbits?). Note that this offset is the start of the
+			 * next row.
+			 */
 			row_offset = (dimm_size * 4 * 1024);
 
-			/* This is the way I was doing this, it's provided mainly
-			 * as an alternative to the "new" way.
+			/* This is the way I was doing this, it's provided
+			 * mainly as an alternative to the "new" way.
 			 */
 
-			#if 0
+#if 0
 			/* 8MB */
-			if(dimm_size == 0x2) dimm_size = 0x1;
+			if (dimm_size == 0x2)
+				dimm_size = 0x1;
 			/* 16MB */
-			else if(dimm_size == 0x4) dimm_size = 0x4;
+			else if (dimm_size == 0x4)
+				dimm_size = 0x4;
 			/* 32MB */
-			else if(dimm_size == 0x8) dimm_size = 0x7;
+			else if (dimm_size == 0x8)
+				dimm_size = 0x7;
 			/* 64 MB */
-			else if(dimm_size == 0x10) dimm_size = 0xa;
+			else if (dimm_size == 0x10)
+				dimm_size = 0xa;
 			/* 128 MB */
-			else if(dimm_size == 0x20) dimm_size = 0xd;
-			else print_debug("Ram Size not supported\r\n");
-			#endif
+			else if (dimm_size == 0x20)
+				dimm_size = 0xd;
+			else
+				print_debug("Ram Size not supported\r\n");
+#endif
 
 			/* This array is provided in raminit.h, because it got
 			 * extremely messy. The above way is cleaner, but
@@ -169,8 +177,9 @@ static void spd_set_dram_size(const struct mem_controller *ctrl, uint32_t row_of
 			print_debug("\r\n");
 
 			/* If the DIMM is dual-sided, the DRP value is +2 */
-			/* TODO: Figure out asymetrical configurations */
-			if ((smbus_read_byte(ctrl->channel0[i], 127) | 0xf) == 0xff) {
+			/* TODO: Figure out asymetrical configurations. */
+			if ((smbus_read_byte(ctrl->channel0[i], 127) | 0xf) ==
+			    0xff) {
 				print_debug("DIMM is dual-sided\r\n");
 				dimm_size += 2;
 			}
@@ -179,7 +188,7 @@ static void spd_set_dram_size(const struct mem_controller *ctrl, uint32_t row_of
 			print_debug_hex8(i);
 			print_debug("\r\n");
 
-			/* If there's no DIMM in the slot, set the value to 0. */
+			/* If there's no DIMM in the slot, set value to 0. */
 			dimm_size = 0x00;
 		}
 
@@ -233,11 +242,11 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
 	 * 10 = Write Only
 	 * 11 = Read/Write
 
-	 * Bit	Range
-	 * 7:6	000F0000 - 000FFFFF
-	 * 5:4	000E0000 - 000EFFFF
-	 * 3:2	000D0000 - 000DFFFF
-	 * 1:0	000C0000 - 000CFFFF
+	 * Bit  Range
+	 * 7:6  000F0000 - 000FFFFF
+	 * 5:4  000E0000 - 000EFFFF
+	 * 3:2  000D0000 - 000DFFFF
+	 * 1:0  000C0000 - 000CFFFF
 	 */
 
 	/* Ideally, this should be R/W for as many ranges as possible. */
@@ -293,7 +302,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	 */
 	uint32_t row_offset;
 
-	spd_set_dram_size(ctrl, row_offset); 
+	spd_set_dram_size(ctrl, row_offset);
 
 	/* 1. Apply NOP. */
 	PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n");
diff --git a/src/northbridge/intel/i82810/raminit.h b/src/northbridge/intel/i82810/raminit.h
index 43edd837d6..08d9a63908 100644
--- a/src/northbridge/intel/i82810/raminit.h
+++ b/src/northbridge/intel/i82810/raminit.h
@@ -21,7 +21,7 @@
 #ifndef NORTHBRIDGE_INTEL_I82810_RAMINIT_H
 #define NORTHBRIDGE_INTEL_I82810_RAMINIT_H
 
-/* The i810 supports max 2 dual-sided DIMMs. */
+/* The 82810 supports max. 2 dual-sided DIMMs. */
 #define DIMM_SOCKETS	2
 
 struct mem_controller {
@@ -29,9 +29,6 @@ struct mem_controller {
 	uint16_t channel0[DIMM_SOCKETS];
 };
 
-
-#endif				/* NORTHBRIDGE_INTEL_I82810_RAMINIT_H */
-
 /* The following table has been bumped over to this header to avoid clutter in 
  * raminit.c. It's used to translate the value read from SPD Byte 31 to a value
  * the northbridge can understand in DRP, aka Rx52[7:4], [3:0]. Where most
@@ -40,7 +37,7 @@ struct mem_controller {
  * this table is necessary.
  */
 
-/* TODO: Find a better way of doing this */
+/* TODO: Find a better way of doing this. */
 
 static const uint8_t translate_spd_to_i82810[] = {
 	/* Note: 4MB sizes are not supported, so dual-sided DIMMs with a 4MB 
@@ -86,5 +83,7 @@ static const uint8_t translate_spd_to_i82810[] = {
 	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 	0xff, 0xff, 0xff, /* 0x31-3f	Invalid		*/
 	0x0f,	/*	0x40		256/0 or 256	*/
-	/* Anything larger is not supported by the i810 */
+	/* Anything larger is not supported by the 82810. */
 };
+
+#endif				/* NORTHBRIDGE_INTEL_I82810_RAMINIT_H */
diff --git a/src/southbridge/intel/i82801xx/chip.h b/src/southbridge/intel/i82801xx/chip.h
index 3c1a3fd6d9..8896e3af56 100644
--- a/src/southbridge/intel/i82801xx/chip.h
+++ b/src/southbridge/intel/i82801xx/chip.h
@@ -19,21 +19,20 @@
  */
 
 #ifndef IGNORE_I82801XX_DEVICE_LIST
-#warning "The i82801xx code currently supports, on a testing/experimental basis," 
-#warning "these devices:"
-#warning "i82801aa, i82801ab, i82801ba, i82801ca, i82801db, i82801dbm, i82801eb,"
-#warning "and i82801er."
-#warning "Using this without modification on any other i82801 version will probably"
-#warning "work until ram init, but will fail after that"
+#warning "The i82801xx code currently supports, on a testing/experimental"
+#warning "basis, these devices:"
+#warning "i82801aa, i82801ab, i82801ba, i82801ca, i82801db, i82801dbm,"
+#warning "i82801eb, and i82801er."
+#warning "Using this without modification on any other i82801 version will"
+#warning "probably work until RAM init, but will fail after that."
 #endif
 
 #ifndef SOUTHBRIDGE_INTEL_I82801XX_CHIP_H
 #define SOUTHBRIDGE_INTEL_I82801XX_CHIP_H
 
-struct southbridge_intel_i82801xx_config 
-{
+struct southbridge_intel_i82801xx_config {
 };
 
 extern struct chip_operations southbridge_intel_i82801xx_ops;
 
-#endif /* SOUTHBRIDGE_INTEL_I82801XX_CHIP_H */
+#endif				/* SOUTHBRIDGE_INTEL_I82801XX_CHIP_H */
diff --git a/src/southbridge/intel/i82801xx/cmos_failover.c b/src/southbridge/intel/i82801xx/cmos_failover.c
index 2e1d84adb8..79c3ce13d4 100644
--- a/src/southbridge/intel/i82801xx/cmos_failover.c
+++ b/src/southbridge/intel/i82801xx/cmos_failover.c
@@ -18,11 +18,11 @@
 
 #include "i82801xx.h"
 
-static void check_cmos_failed(void) 
+static void check_cmos_failed(void)
 {
 	uint8_t byte;
 	byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
-	if( byte & RTC_FAILED) {
+	if (byte & RTC_FAILED) {
 		//clear bit 1 and bit 2
 		byte = cmos_read(RTC_BOOT_BYTE);
 		byte &= 0x0c;
diff --git a/src/southbridge/intel/i82801xx/i82801xx.c b/src/southbridge/intel/i82801xx/i82801xx.c
index 5cceab9b9b..c2ff949734 100644
--- a/src/southbridge/intel/i82801xx/i82801xx.c
+++ b/src/southbridge/intel/i82801xx/i82801xx.c
@@ -2,7 +2,7 @@
  * This file is part of the LinuxBIOS project.
  *
  * Copyright (C) 2005 Digital Design Corporation
- * (Written by Steven J. Magnani <steve@digidescorp.com> for Digital Design Corp)
+ * (Written by Steven J. Magnani <steve@digidescorp.com> for Digital Design)
  * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
@@ -30,31 +30,30 @@ void i82801xx_enable(device_t dev)
 	unsigned int index = 0;
 	uint16_t cur_disable_mask, new_disable_mask;
 
-	// All 82801 devices should be on bus 0
-	unsigned int devfn = PCI_DEVFN(0x1f, 0); // lpc
-	device_t lpc_dev = dev_find_slot(0, devfn); // 0
+	/* All 82801 devices should be on bus 0. */
+	unsigned int devfn = PCI_DEVFN(0x1f, 0);	// LPC
+	device_t lpc_dev = dev_find_slot(0, devfn);	// 0
 	if (!lpc_dev)
 		return;
 
-	/* We're going to assume, perhaps incorrectly, that if a function exists
-	it can be disabled. Workarounds for ICH variants that don't follow this 
-	should be done by checking the device ID */
-
+	/* We're going to assume, perhaps incorrectly, that if a function
+	 * exists it can be disabled. Workarounds for ICH variants that don't
+	 * follow this should be done by checking the device ID.
+	 */
 	if (PCI_SLOT(dev->path.u.pci.devfn) == 31) {
 		index = PCI_FUNC(dev->path.u.pci.devfn);
 	} else if (PCI_SLOT(dev->path.u.pci.devfn) == 29) {
 		index = 8 + PCI_FUNC(dev->path.u.pci.devfn);
 	}
-	
-	/* Function 0 is a bit of an exception */
-	if(index == 0)
-	{
+
+	/* Function 0 is a bit of an exception. */
+	if (index == 0) {
 		index = 14;
 	}
 	cur_disable_mask = pci_read_config16(lpc_dev, FUNC_DIS);
-	new_disable_mask = cur_disable_mask & ~(1 << index); // enable it
+	new_disable_mask = cur_disable_mask & ~(1 << index);	// enable it
 	if (!dev->enabled) {
-		new_disable_mask |= (1 << index);  // disable it, if desired
+		new_disable_mask |= (1 << index); // disable it, if desired
 	}
 	if (new_disable_mask != cur_disable_mask) {
 		pci_write_config16(lpc_dev, FUNC_DIS, new_disable_mask);
diff --git a/src/southbridge/intel/i82801xx/i82801xx.h b/src/southbridge/intel/i82801xx/i82801xx.h
index 273767949e..fa306bc0a4 100644
--- a/src/southbridge/intel/i82801xx/i82801xx.h
+++ b/src/southbridge/intel/i82801xx/i82801xx.h
@@ -18,89 +18,90 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#ifndef I82801XX_H
-#define I82801XX_H
+#ifndef SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H
+#define SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H
 
 #ifndef __ROMCC__
 #include "chip.h"
 extern void i82801xx_enable(device_t dev);
 #endif
 
-#define PCI_DMA_CFG     0x90
-#define SERIRQ_CNTL     0x64
-#define GEN_CNTL        0xd0
-#define GEN_STS         0xd4
-#define RTC_CONF        0xd8
-#define GEN_PMCON_3     0xa4
+#define PCI_DMA_CFG		0x90
+#define SERIRQ_CNTL		0x64
+#define GEN_CNTL		0xd0
+#define GEN_STS			0xd4
+#define RTC_CONF		0xd8
+#define GEN_PMCON_3		0xa4
 
-#define PCICMD          0x04
-#define PMBASE          0x40
-#define PM_BASE_ADDR	0x1100
-#define ACPI_CNTL       0x44
-#define BIOS_CNTL       0x4E
-#define GPIO_BASE	0x58
-#define GPIO_BASE_ADDR	0x1180
-#define GPIO_CNTL       0x5C
-#define PIRQA_ROUT      0x60
-#define PIRQE_ROUT      0x68
-#define COM_DEC         0xE0
-#define LPC_EN          0xE6
-#define FUNC_DIS        0xF2
+#define PCICMD			0x04
+#define PMBASE			0x40
+#define PM_BASE_ADDR		0x1100
+#define ACPI_CNTL		0x44
+#define BIOS_CNTL		0x4E
+#define GPIO_BASE		0x58
+#define GPIO_BASE_ADDR		0x1180
+#define GPIO_CNTL		0x5C
+#define PIRQA_ROUT		0x60
+#define PIRQE_ROUT		0x68
+#define COM_DEC			0xE0
+#define LPC_EN			0xE6
+#define FUNC_DIS		0xF2
 
-#define CMD		0x04
-#define SBUS_NUM	0x19
-#define SUB_BUS_NUM	0x1A
-#define SMLT		0x1B
-#define IOBASE		0x1C
-#define IOLIM		0x1D
-#define MEMBASE		0x20
-#define MEMLIM		0x22
-#define CNF		0x50
-#define MTT		0x70
-#define PCI_MAST_STS	0x82
+#define CMD			0x04
+#define SBUS_NUM		0x19
+#define SUB_BUS_NUM		0x1A
+#define SMLT			0x1B
+#define IOBASE			0x1C
+#define IOLIM			0x1D
+#define MEMBASE			0x20
+#define MEMLIM			0x22
+#define CNF			0x50
+#define MTT			0x70
+#define PCI_MAST_STS		0x82
 
-// GEN_PMCON_3 bits
+/* GEN_PMCON_3 bits */
 #define RTC_BATTERY_DEAD	(1 << 2)
 #define RTC_POWER_FAILED	(1 << 1)
 #define SLEEP_AFTER_POWER_FAIL	(1 << 0)
 
-// PCI Configuration Space (D31:F1)
-#define IDE_TIM_PRI		0x40	// IDE timings, primary
-#define IDE_TIM_SEC		0x42	// IDE timings, secondary
+/* PCI Configuration Space (D31:F1) */
+#define IDE_TIM_PRI		0x40	/* IDE timings, primary */
+#define IDE_TIM_SEC		0x42	/* IDE timings, secondary */
 
-// IDE_TIM bits
+/* IDE_TIM bits */
 #define IDE_DECODE_ENABLE	(1 << 15)
 
-// PCI Configuration Space (D31:F3)
-#define SMB_BASE	0x20
-#define HOSTC		0x40
+/* PCI Configuration Space (D31:F3) */
+#define SMB_BASE		0x20
+#define HOSTC			0x40
 
-// HOSTC bits
-#define I2C_EN		(1 << 2)
-#define SMB_SMI_EN	(1 << 1)
-#define HST_EN		(1 << 0)
+/* HOSTC bits */
+#define I2C_EN			(1 << 2)
+#define SMB_SMI_EN		(1 << 1)
+#define HST_EN			(1 << 0)
 
-// SMBus IO bits
-/* TODO: Does it matter where we put the SMBus IO base, as long as we keep 
-   consistent and don't interfere with anything else? */
-//#define SMBUS_IO_BASE 0x1000
-#define SMBUS_IO_BASE	0x0f00
+/* SMBus I/O bits.
+ * TODO: Does it matter where we put the SMBus IO base, as long as we keep
+ * consistent and don't interfere with anything else?
+ */
+/* #define SMBUS_IO_BASE 0x1000 */
+#define SMBUS_IO_BASE		0x0f00
 
-#define SMBHSTSTAT	0x0
-#define SMBHSTCTL	0x2
-#define SMBHSTCMD	0x3
-#define SMBXMITADD	0x4
-#define SMBHSTDAT0	0x5
-#define SMBHSTDAT1	0x6
-#define SMBBLKDAT	0x7
-#define SMBTRNSADD	0x9
-#define SMBSLVDATA	0xa
-#define SMLINK_PIN_CTL	0xe
-#define SMBUS_PIN_CTL	0xf 
+#define SMBHSTSTAT		0x0
+#define SMBHSTCTL		0x2
+#define SMBHSTCMD		0x3
+#define SMBXMITADD		0x4
+#define SMBHSTDAT0		0x5
+#define SMBHSTDAT1		0x6
+#define SMBBLKDAT		0x7
+#define SMBTRNSADD		0x9
+#define SMBSLVDATA		0xa
+#define SMLINK_PIN_CTL		0xe
+#define SMBUS_PIN_CTL		0xf
 
-#define SMBUS_TIMEOUT	(10 * 1000 * 100)
+#define SMBUS_TIMEOUT		(10 * 1000 * 100)
 
-//HPET, if present
+/* HPET, if present */
 #define HPET_ADDR		0xfed0000
 
-#endif /* I82801XX_H */
+#endif				/* SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H */
diff --git a/src/southbridge/intel/i82801xx/i82801xx_ac97.c b/src/southbridge/intel/i82801xx/i82801xx_ac97.c
index f61e069e96..2befe4f1ba 100644
--- a/src/southbridge/intel/i82801xx/i82801xx_ac97.c
+++ b/src/southbridge/intel/i82801xx/i82801xx_ac97.c
@@ -25,89 +25,89 @@
 #include <device/pci_ids.h>
 #include "i82801xx.h"
 
-static struct device_operations ac97_ops  = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init             = 0,
-	.scan_bus         = 0,
-	.enable           = i82801xx_enable,
+static struct device_operations ac97_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= 0,
+	.scan_bus		= 0,
+	.enable			= i82801xx_enable,
 };
 
-/* i82801aa */
+/* 82801AA */
 static struct pci_driver i82801aa_ac97_audio __pci_driver = {
-	.ops    = &ac97_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x2415,
+	.ops	= &ac97_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2415,
 };
 
 static struct pci_driver i82801aa_ac97_modem __pci_driver = {
-	.ops    = &ac97_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x2416,
+	.ops	= &ac97_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2416,
 };
 
-/* i82801ab */
+/* 82801AB */
 static struct pci_driver i82801ab_ac97_audio __pci_driver = {
-	.ops    = &ac97_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x2425,
+	.ops	= &ac97_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2425,
 };
 
 static struct pci_driver i82801ab_ac97_modem __pci_driver = {
-	.ops    = &ac97_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x2426,
+	.ops	= &ac97_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2426,
 };
 
-/* i82801ba */
+/* 82801BA */
 static struct pci_driver i82801ba_ac97_audio __pci_driver = {
-	.ops    = &ac97_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x2445,
+	.ops	= &ac97_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2445,
 };
 
 static struct pci_driver i82801ba_ac97_modem __pci_driver = {
-	.ops    = &ac97_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x2446,
+	.ops	= &ac97_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2446,
 };
 
-/* i82801ca */
+/* 82801CA */
 static struct pci_driver i82801ca_ac97_audio __pci_driver = {
-	.ops    = &ac97_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x2485,
+	.ops	= &ac97_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2485,
 };
 
 static struct pci_driver i82801ca_ac97_modem __pci_driver = {
-	.ops    = &ac97_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x2486,
+	.ops	= &ac97_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2486,
 };
 
-/* i82801db & i82801dbm */
+/* 82801DB & 82801DBM */
 static struct pci_driver i82801db_ac97_audio __pci_driver = {
-	.ops    = &ac97_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x24c5,
+	.ops	= &ac97_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x24c5,
 };
 
 static struct pci_driver i82801db_ac97_modem __pci_driver = {
-	.ops    = &ac97_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x24c6,
+	.ops	= &ac97_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x24c6,
 };
 
-/* i82801eb & i82801er */
+/* 82801EB & 82801ER */
 static struct pci_driver i82801ex_ac97_audio __pci_driver = {
-	.ops    = &ac97_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x24d5,
+	.ops	= &ac97_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x24d5,
 };
 
 static struct pci_driver i82801ex_ac97_modem __pci_driver = {
-	.ops    = &ac97_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x24d6,
+	.ops	= &ac97_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x24d6,
 };
diff --git a/src/southbridge/intel/i82801xx/i82801xx_early_smbus.c b/src/southbridge/intel/i82801xx/i82801xx_early_smbus.c
index 070cc22a00..214ca0834e 100644
--- a/src/southbridge/intel/i82801xx/i82801xx_early_smbus.c
+++ b/src/southbridge/intel/i82801xx/i82801xx_early_smbus.c
@@ -28,31 +28,36 @@ static void enable_smbus(void)
 {
 	device_t dev;
 	uint16_t device_id;
-	
-	/* Set the SMBus device staticly */
+
+	/* Set the SMBus device staticly. */
 	dev = PCI_DEV(0x0, 0x1f, 0x3);
-	
-	/* Check to make sure we've got the right device */
+
+	/* Check to make sure we've got the right device. */
 	device_id = pci_read_config16(dev, 0x2);
-	
-	/* Clear bits 7-4, since those are the only bits that vary between models */
+
+	/* Clear bits 7-4 (the only bits that vary between models). */
 	device_id &= 0xff0f;
-	
-	if(device_id != 0x2403)
-	{
+
+	if (device_id != 0x2403) {
 		die("Device not found, Corey probably screwed up!");
 	}
-	
-	/* Set SMBus I/O base */
-	pci_write_config32(dev, SMB_BASE, SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
-	/* Set SMBus enable */
+
+	/* Set SMBus I/O base. */
+	pci_write_config32(dev, SMB_BASE,
+			   SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
+
+	/* Set SMBus enable. */
 	pci_write_config8(dev, HOSTC, HST_EN);
-	/* Set SMBus I/O space enable */ 
+
+	/* Set SMBus I/O space enable. */
 	pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
-	/* Disable interrupt generation */ 
+
+	/* Disable interrupt generation. */
 	outb(0, SMBUS_IO_BASE + SMBHSTCTL);
-	/* Clear any lingering errors, so transactions can run */
+
+	/* Clear any lingering errors, so transactions can run. */
 	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
+
 	print_debug("SMBus controller enabled\r\n");
 }
 
@@ -61,14 +66,16 @@ static inline int smbus_read_byte(unsigned device, unsigned address)
 	return do_smbus_read_byte(device, address);
 }
 
-static void smbus_write_byte(unsigned device, unsigned address, unsigned char val)
+static void smbus_write_byte(unsigned device, unsigned address,
+			     unsigned char val)
 {
 	print_err("Unimplemented smbus_write_byte() called\r\n");
 	return;
 }
 
-static inline int smbus_write_block(unsigned device, unsigned length, unsigned cmd, 
-		 unsigned data1, unsigned data2)
+static inline int smbus_write_block(unsigned device, unsigned length,
+				    unsigned cmd, unsigned data1,
+				    unsigned data2)
 {
 	return do_smbus_write_block(device, length, cmd, data1, data2);
 }
diff --git a/src/southbridge/intel/i82801xx/i82801xx_ide.c b/src/southbridge/intel/i82801xx/i82801xx_ide.c
index f9bb403014..6867106eca 100644
--- a/src/southbridge/intel/i82801xx/i82801xx_ide.c
+++ b/src/southbridge/intel/i82801xx/i82801xx_ide.c
@@ -4,7 +4,7 @@
  * Copyright (C) 2005 Tyan Computer
  * (Written by Yinghai Lu <yinghailu@gmail.com> for Tyan Computer)
  * Copyright (C) 2005 Digital Design Corporation
- * (Written by Steven J. Magnani <steve@digidescorp.com> for Digital Design Corp)
+ * (Written by Steven J. Magnani <steve@digidescorp.com> for Digital Design)
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -29,8 +29,8 @@
 
 static void ide_init(struct device *dev)
 {
-	/* TODO: Needs to be tested for compatibility with ICH5(R) */
-	/* Enable ide devices so the linux ide driver will work */
+	/* TODO: Needs to be tested for compatibility with ICH5(R). */
+	/* Enable IDE devices so the Linux IDE driver will work. */
 	uint16_t ideTimingConfig;
 	int enable_primary = 1;
 	int enable_secondary = 1;
@@ -38,7 +38,7 @@ static void ide_init(struct device *dev)
 	ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI);
 	ideTimingConfig &= ~IDE_DECODE_ENABLE;
 	if (enable_primary) {
-		/* Enable primary ide interface */
+		/* Enable primary IDE interface. */
 		ideTimingConfig |= IDE_DECODE_ENABLE;
 		printk_debug("IDE0 ");
 	}
@@ -47,67 +47,67 @@ static void ide_init(struct device *dev)
 	ideTimingConfig = pci_read_config16(dev, IDE_TIM_SEC);
 	ideTimingConfig &= ~IDE_DECODE_ENABLE;
 	if (enable_secondary) {
-		/* Enable secondary ide interface */
+		/* Enable secondary IDE interface. */
 		ideTimingConfig |= IDE_DECODE_ENABLE;
 		printk_debug("IDE1 ");
 	}
 	pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig);
 }
 
-static struct device_operations ide_ops  = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init             = ide_init,
-	.scan_bus         = 0,
-	.enable           = i82801xx_enable,
+static struct device_operations ide_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= ide_init,
+	.scan_bus		= 0,
+	.enable			= i82801xx_enable,
 };
 
-/* i82801aa */
+/* 82801AA */
 static struct pci_driver i82801aa_ide __pci_driver = {
-	.ops    = &ide_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x2411,
+	.ops	= &ide_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2411,
 };
 
-/* i82801ab */
+/* 82801AB */
 static struct pci_driver i82801ab_ide __pci_driver = {
-	.ops    = &ide_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x2421,
+	.ops	= &ide_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2421,
 };
 
-/* i82801ba */
+/* 82801BA */
 static struct pci_driver i82801ba_ide __pci_driver = {
-	.ops    = &ide_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x244b,
+	.ops	= &ide_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x244b,
 };
 
-/* i82801ca */
+/* 82801CA */
 static struct pci_driver i82801ca_ide __pci_driver = {
-	.ops    = &ide_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x248b,
+	.ops	= &ide_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x248b,
 };
 
-/* i82801db */
+/* 82801DB */
 static struct pci_driver i82801db_ide __pci_driver = {
-	.ops    = &ide_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x24cb,
+	.ops	= &ide_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x24cb,
 };
 
-/* i82801dbm */
+/* 82801DBM */
 static struct pci_driver i82801dbm_ide __pci_driver = {
-	.ops    = &ide_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x24ca,
+	.ops	= &ide_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x24ca,
 };
 
-/* i82801eb & i82801er */
+/* 82801EB & 82801ER */
 static struct pci_driver i82801ex_ide __pci_driver = {
-	.ops    = &ide_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x24db,
+	.ops	= &ide_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x24db,
 };
diff --git a/src/southbridge/intel/i82801xx/i82801xx_lpc.c b/src/southbridge/intel/i82801xx/i82801xx_lpc.c
index c0d783d9a9..e2ae3725a0 100644
--- a/src/southbridge/intel/i82801xx/i82801xx_lpc.c
+++ b/src/southbridge/intel/i82801xx/i82801xx_lpc.c
@@ -20,8 +20,8 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
- 
-/* from i82801dbm, needs to be fixed to support everything the i82801er does */
+
+/* From 82801DBM, needs to be fixed to support everything the 82801ER does. */
 
 #include <console/console.h>
 #include <device/device.h>
@@ -34,17 +34,17 @@
 
 #define NMI_OFF 0
 
-void i82801xx_enable_ioapic( struct device *dev) 
+void i82801xx_enable_ioapic(struct device *dev)
 {
 	uint32_t reg32;
 	volatile uint32_t *ioapic_index = (volatile uint32_t *)0xfec00000;
 	volatile uint32_t *ioapic_data = (volatile uint32_t *)0xfec00010;
 
 	reg32 = pci_read_config32(dev, GEN_CNTL);
-	reg32 |= (3 << 7); /* Enable IOAPIC */
-	reg32 |= (1 << 13); /* Coprocessor error enable */
-	reg32 |= (1 << 1); /* Delayed transaction enable */
-	reg32 |= (1 << 2); /* DMA collection buffer enable */
+	reg32 |= (3 << 7);	/* Enable IOAPIC */
+	reg32 |= (1 << 13);	/* Coprocessor error enable */
+	reg32 |= (1 << 1);	/* Delayed transaction enable */
+	reg32 |= (1 << 2);	/* DMA collection buffer enable */
 	pci_write_config32(dev, GEN_CNTL, reg32);
 	printk_debug("IOAPIC Southbridge enabled %x\n", reg32);
 
@@ -54,7 +54,7 @@ void i82801xx_enable_ioapic( struct device *dev)
 	*ioapic_index = 0;
 	reg32 = *ioapic_data;
 	printk_debug("Southbridge APIC ID = %x\n", reg32);
-	if(reg32 != (1 << 25))
+	if (reg32 != (1 << 25))
 		die("APIC Error\n");
 
 	/* TODO: From i82801ca, needed/useful on other ICH? */
@@ -62,44 +62,48 @@ void i82801xx_enable_ioapic( struct device *dev)
 	*ioapic_data = 1;	// Use Processor System Bus to deliver interrupts
 }
 
-void i82801xx_enable_serial_irqs( struct device *dev)
+void i82801xx_enable_serial_irqs(struct device *dev)
 {
-	/* set packet length and toggle silent mode bit */
-	pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0));
-	pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(0 << 6)|((21 - 17) << 2)|(0 << 0));
-	/* TODO: Explain/#define the real meaning of these magic numbers ^^^ */
+	/* Set packet length and toggle silent mode bit. */
+	pci_write_config8(dev, SERIRQ_CNTL,
+			  (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
+	pci_write_config8(dev, SERIRQ_CNTL,
+			  (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
+	/* TODO: Explain/#define the real meaning of these magic numbers. */
 }
 
-void i82801xx_lpc_route_dma( struct device *dev, uint8_t mask) 
+void i82801xx_lpc_route_dma(struct device *dev, uint8_t mask)
 {
-        uint16_t reg16;
-        int i;
-        reg16 = pci_read_config16(dev, PCI_DMA_CFG);
-        reg16 &= 0x300;
-        for(i = 0; i < 8; i++) {
-                if (i == 4)
-                        continue;
-                reg16 |= ((mask & (1 << i))? 3:1) << (i * 2);
-        }
-        pci_write_config16(dev, PCI_DMA_CFG, reg16);
+	uint16_t reg16;
+	int i;
+
+	reg16 = pci_read_config16(dev, PCI_DMA_CFG);
+	reg16 &= 0x300;
+	for (i = 0; i < 8; i++) {
+		if (i == 4)
+			continue;
+		reg16 |= ((mask & (1 << i)) ? 3 : 1) << (i * 2);
+	}
+	pci_write_config16(dev, PCI_DMA_CFG, reg16);
 }
 
+/* TODO: Needs serious cleanup/comments. */
 void i82801xx_rtc_init(struct device *dev)
-{//todo:needs serious cleanup/comments
-        uint8_t reg8;
-        uint32_t reg32;
-        int rtc_failed;
-        reg8 = pci_read_config8(dev, GEN_PMCON_3);
-        rtc_failed = reg8 & RTC_BATTERY_DEAD;
-        if (rtc_failed) {
-                reg8 &= ~(1 << 1); /* preserve the power fail state */
-                pci_write_config8(dev, GEN_PMCON_3, reg8);
-        }
-        reg32 = pci_read_config32(dev, GEN_STS);
-        rtc_failed |= reg32 & (1 << 2);
-        rtc_init(rtc_failed);
-}
+{
+	uint8_t reg8;
+	uint32_t reg32;
+	int rtc_failed;
 
+	reg8 = pci_read_config8(dev, GEN_PMCON_3);
+	rtc_failed = reg8 & RTC_BATTERY_DEAD;
+	if (rtc_failed) {
+		reg8 &= ~(1 << 1);	/* preserve the power fail state */
+		pci_write_config8(dev, GEN_PMCON_3, reg8);
+	}
+	reg32 = pci_read_config32(dev, GEN_STS);
+	rtc_failed |= reg32 & (1 << 2);
+	rtc_init(rtc_failed);
+}
 
 void i82801xx_1f0_misc(struct device *dev)
 {
@@ -114,13 +118,13 @@ void i82801xx_1f0_misc(struct device *dev)
 	pci_write_config32(dev, GPIO_BASE, GPIO_BASE_ADDR | 1);
 	/* Enable GPIO */
 	pci_write_config8(dev, GPIO_CNTL, 0x10);
-	
+
 	//get rid of?
 	/* Route PIRQA to IRQ11, PIRQB to IRQ3, PIRQC to IRQ5, PIRQD to IRQ10 */
 	pci_write_config32(dev, PIRQA_ROUT, 0x0A05030B);
 	/* Route PIRQE to IRQ7. Leave PIRQF - PIRQH unrouted */
 	pci_write_config8(dev, PIRQE_ROUT, 0x07);
-	
+
 	//move to i82801xx_init
 	/* Prevent LPC disabling, enable parity errors, and SERR# (System Error) */
 	pci_write_config16(dev, PCI_COMMAND, 0x014f);
@@ -142,21 +146,21 @@ static void enable_hpet(struct device *dev)
 	uint32_t code = (0 & 0x3);
 
 	reg32 = pci_read_config32(dev, GEN_CNTL);
-	reg32 |= (1 << 17); /* Enable HPET */
-	/*Bits [16:15]Memory Address Range
-	00 FED0_0000h - FED0_03FFh
-	01 FED0_1000h - FED0_13FFh
-	10 FED0_2000h - FED0_23FFh
-	11 FED0_3000h - FED0_33FFh*/
-
-	reg32 &= ~(3 << 15); /* Clear it */
+	reg32 |= (1 << 17);	/* Enable HPET */
+	/*
+	 * Bits [16:15]	Memory Address Range
+	 * 00		FED0_0000h - FED0_03FFh
+	 * 01		FED0_1000h - FED0_13FFh
+	 * 10		FED0_2000h - FED0_23FFh
+	 * 11		FED0_3000h - FED0_33FFh
+	 */
+	reg32 &= ~(3 << 15);	/* Clear it */
 	reg32 |= (code << 15);
-	/* reg32 is never written to anywhere?? */
+	/* reg32 is never written to anywhere? */
 	printk_debug("Enabling HPET @0x%x\n", HPET_ADDR | (code << 12));
 #endif
 }
 
-
 static void lpc_init(struct device *dev)
 {
 	uint8_t byte;
@@ -169,14 +173,15 @@ static void lpc_init(struct device *dev)
 	i82801xx_enable_serial_irqs(dev);
 
 	/* TODO: Find out if this is being used/works */
-#ifdef SUSPICIOUS_LOOKING_CODE	
-	/* The ICH-4 datasheet does not mention this configuration register. */ 
-	/* This code may have been inherited (incorrectly) from code for 
-	the AMD 766 southbridge, which *does* support this functionality. */
+#ifdef SUSPICIOUS_LOOKING_CODE
+	/* The ICH-4 datasheet does not mention this configuration register.
+	 * This code may have been inherited (incorrectly) from code for
+	 * the AMD 766 southbridge, which *does* support this functionality.
+	 */
 
 	/* Posted memory write enable */
 	byte = pci_read_config8(dev, 0x46);
-	pci_write_config8(dev, 0x46, byte | (1<<0)); 
+	pci_write_config8(dev, 0x46, byte | (1 << 0));
 #endif
 
 	/* power after power fail */
@@ -185,23 +190,23 @@ static void lpc_init(struct device *dev)
 	 * 0 == S0 Full On
 	 * 1 == S5 Soft Off
 	 */
-        pci_write_config8(dev, GEN_PMCON_3, pwr_on?0:1);
-        printk_info("Set power %s if power fails\n", pwr_on?"on":"off");
+	pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1);
+	printk_info("Set power %s if power fails\n", pwr_on ? "on" : "off");
 
 	/* Set up NMI on errors */
 	byte = inb(0x61);
-	byte &= ~(1 << 3); /* IOCHK# NMI Enable */
-	byte &= ~(1 << 2); /* PCI SERR# Enable */
+	byte &= ~(1 << 3);	/* IOCHK# NMI Enable */
+	byte &= ~(1 << 2);	/* PCI SERR# Enable */
 	outb(byte, 0x61);
 	byte = inb(0x70);
 
 	nmi_option = NMI_OFF;
 	get_option(&nmi_option, "nmi");
-	if (nmi_option) {			
-		byte &= ~(1 << 7); /* set NMI */
+	if (nmi_option) {
+		byte &= ~(1 << 7);	/* Set NMI */
 		outb(byte, 0x70);
 	}
-	
+
 	/* Initialize the real time clock */
 	i82801xx_rtc_init(dev);
 
@@ -224,10 +229,12 @@ static void i82801xx_lpc_read_resources(device_t dev)
 
 	/* Add an extra subtractive resource for both memory and I/O */
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->flags =
+	    IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->flags =
+	    IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 }
 
 static void i82801xx_lpc_enable_resources(device_t dev)
@@ -236,54 +243,54 @@ static void i82801xx_lpc_enable_resources(device_t dev)
 	enable_childrens_resources(dev);
 }
 
-static struct device_operations lpc_ops  = {
-	.read_resources   = i82801xx_lpc_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = i82801xx_lpc_enable_resources,
-	.init             = lpc_init,
-	.scan_bus         = scan_static_bus,
-	.enable           = i82801xx_enable,
+static struct device_operations lpc_ops = {
+	.read_resources		= i82801xx_lpc_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= i82801xx_lpc_enable_resources,
+	.init			= lpc_init,
+	.scan_bus		= scan_static_bus,
+	.enable			= i82801xx_enable,
 };
 
 static struct pci_driver i82801aa_lpc __pci_driver = {
-	.ops    = &lpc_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x2410,
+	.ops	= &lpc_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2410,
 };
 
 static struct pci_driver i82801ab_lpc __pci_driver = {
-	.ops    = &lpc_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x2420,
+	.ops	= &lpc_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2420,
 };
 
 static struct pci_driver i82801ba_lpc __pci_driver = {
-	.ops    = &lpc_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x2440,
+	.ops	= &lpc_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2440,
 };
 
 static struct pci_driver i82801ca_lpc __pci_driver = {
-	.ops    = &lpc_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x2480,
+	.ops	= &lpc_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2480,
 };
 
 static struct pci_driver i82801db_lpc __pci_driver = {
-	.ops    = &lpc_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x24c0,
+	.ops	= &lpc_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x24c0,
 };
 
 static struct pci_driver i82801dbm_lpc __pci_driver = {
-	.ops    = &lpc_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x24cc,
+	.ops	= &lpc_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x24cc,
 };
 
-/* i82801eb and er */
+/* 82801EB and 82801ER */
 static struct pci_driver i82801ex_lpc __pci_driver = {
-	.ops    = &lpc_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x24d0,
+	.ops	= &lpc_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x24d0,
 };
diff --git a/src/southbridge/intel/i82801xx/i82801xx_nic.c b/src/southbridge/intel/i82801xx/i82801xx_nic.c
index fe2ee9fbb3..cdba646849 100644
--- a/src/southbridge/intel/i82801xx/i82801xx_nic.c
+++ b/src/southbridge/intel/i82801xx/i82801xx_nic.c
@@ -23,22 +23,22 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 
-static struct device_operations nic_ops  = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init             = 0,
-	.scan_bus         = 0,
+static struct device_operations nic_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= 0,
+	.scan_bus		= 0,
 };
 
 static struct pci_driver i82801dbm_nic __pci_driver = {
-	.ops    = &nic_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x103a,
+	.ops	= &nic_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x103a,
 };
 
 static struct pci_driver i82801ex_nic __pci_driver = {
-	.ops    = &nic_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x1051,
+	.ops	= &nic_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1051,
 };
diff --git a/src/southbridge/intel/i82801xx/i82801xx_pci.c b/src/southbridge/intel/i82801xx/i82801xx_pci.c
index 3d27f7f545..0b8b5425fc 100644
--- a/src/southbridge/intel/i82801xx/i82801xx_pci.c
+++ b/src/southbridge/intel/i82801xx/i82801xx_pci.c
@@ -31,50 +31,50 @@ static void pci_init(struct device *dev)
 
 	/* Clear system errors */
 	reg16 = pci_read_config16(dev, 0x06);
-	reg16 |= 0xf900; /* Clear possible errors */
+	reg16 |= 0xf900;	/* Clear possible errors */
 	pci_write_config16(dev, 0x06, reg16);
 
 	/* i82801er has this commented out, wonder why? */
 	/* System error enable */
 	reg32 = pci_read_config32(dev, 0x04);
-	reg32 |= (1 << 8); /* SERR# Enable */
-	reg32 |= (1 << 6); /* Parity Error Response */
+	reg32 |= (1 << 8);	/* SERR# Enable */
+	reg32 |= (1 << 6);	/* Parity Error Response */
 	pci_write_config32(dev, 0x04, reg32);
-	
+
 	reg16 = pci_read_config16(dev, 0x1e);
-	reg16 |= 0xf800; /* Clear possible errors */
+	reg16 |= 0xf800;	/* Clear possible errors */
 	pci_write_config16(dev, 0x1e, reg16);
 }
 
-static struct device_operations pci_ops  = {
-	.read_resources   = pci_bus_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_bus_enable_resources,
-	.init             = pci_init,
-	.scan_bus         = pci_scan_bridge,
+static struct device_operations pci_ops = {
+	.read_resources		= pci_bus_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_bus_enable_resources,
+	.init			= pci_init,
+	.scan_bus		= pci_scan_bridge,
 };
 
 static struct pci_driver i82801aa_pci __pci_driver = {
-	.ops    = &pci_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x2418,
+	.ops	= &pci_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2418,
 };
 
 static struct pci_driver i82801ab_pci __pci_driver = {
-	.ops    = &pci_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x2428,
+	.ops	= &pci_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2428,
 };
 
-/* i82801ba, ca, db, eb, and er */
+/* 82801BA, 82801CA, 82801DB, 82801EB, and 82801ER */
 static struct pci_driver i82801misc_pci __pci_driver = {
-	.ops    = &pci_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x244e,
+	.ops	= &pci_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x244e,
 };
 
 static struct pci_driver i82801dbm_pci __pci_driver = {
-	.ops    = &pci_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x2448,
+	.ops	= &pci_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2448,
 };
diff --git a/src/southbridge/intel/i82801xx/i82801xx_reset.c b/src/southbridge/intel/i82801xx/i82801xx_reset.c
index 7a9f6de492..75a057a820 100644
--- a/src/southbridge/intel/i82801xx/i82801xx_reset.c
+++ b/src/southbridge/intel/i82801xx/i82801xx_reset.c
@@ -22,6 +22,6 @@
 
 void hard_reset(void)
 {
-        /* Try rebooting through port 0xcf9 */
-        outb((1 << 2)|(1 << 1), 0xcf9);
+	/* Try rebooting through port 0xcf9. */
+	outb((1 << 2) | (1 << 1), 0xcf9);
 }
diff --git a/src/southbridge/intel/i82801xx/i82801xx_sata.c b/src/southbridge/intel/i82801xx/i82801xx_sata.c
index 33dfc329ac..62542a5b41 100644
--- a/src/southbridge/intel/i82801xx/i82801xx_sata.c
+++ b/src/southbridge/intel/i82801xx/i82801xx_sata.c
@@ -26,14 +26,15 @@
 #include <device/pci_ops.h>
 #include "i82801xx.h"
 
-/* TODO: set dynamically, if the user only wants one sata channel or none at all */
-
+/* TODO: Set dynamically, if the user only wants one SATA channel or none
+ * at all.
+ */
 static void sata_init(struct device *dev)
 {
 	/* SATA configuration */
 	pci_write_config8(dev, 0x04, 0x07);
 	pci_write_config8(dev, 0x09, 0x8f);
-	
+
 	/* Set timmings */
 	pci_write_config16(dev, 0x40, 0x0a307);
 	pci_write_config16(dev, 0x42, 0x0a307);
@@ -42,41 +43,41 @@ static void sata_init(struct device *dev)
 	pci_write_config16(dev, 0x48, 0x000f);
 	pci_write_config16(dev, 0x4a, 0x1111);
 
-	/* 66 mhz */
+	/* 66 MHz */
 	pci_write_config16(dev, 0x54, 0xf00f);
 
-	/* Combine ide - sata configuration */
+	/* Combine IDE - SATA configuration */
 	pci_write_config8(dev, 0x90, 0x0);
-	
-	/* port 0 & 1 enable */
+
+	/* Port 0 & 1 enable */
 	pci_write_config8(dev, 0x92, 0x33);
-	
-	/* initialize SATA  */
+
+	/* Initialize SATA. */
 	pci_write_config16(dev, 0xa0, 0x0018);
 	pci_write_config32(dev, 0xa4, 0x00000264);
 	pci_write_config16(dev, 0xa0, 0x0040);
 	pci_write_config32(dev, 0xa4, 0x00220043);
 }
 
-static struct device_operations sata_ops  = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init             = sata_init,
-	.scan_bus         = 0,
-	.enable           = i82801xx_enable,
+static struct device_operations sata_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= sata_init,
+	.scan_bus		= 0,
+	.enable			= i82801xx_enable,
 };
 
-/* i82801eb */
+/* 82801EB */
 static struct pci_driver i82801eb_sata_driver __pci_driver = {
-	.ops    = &sata_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x24d1,
+	.ops	= &sata_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x24d1,
 };
 
-/* i82801er */
+/* 82801ER */
 static struct pci_driver i82801er_sata_driver __pci_driver = {
-	.ops    = &sata_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x24df,
+	.ops	= &sata_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x24df,
 };
diff --git a/src/southbridge/intel/i82801xx/i82801xx_smbus.c b/src/southbridge/intel/i82801xx/i82801xx_smbus.c
index 67a746666c..3218ef3567 100644
--- a/src/southbridge/intel/i82801xx/i82801xx_smbus.c
+++ b/src/southbridge/intel/i82801xx/i82801xx_smbus.c
@@ -32,63 +32,62 @@ static int smbus_read_byte(struct bus *bus, device_t dev, uint8_t address)
 
 	device = dev->path.u.i2c.device;
 	res = find_resource(bus->dev, 0x20);
-	
+
 	return do_smbus_read_byte(res->base, device, address);
 }
 
 static struct smbus_bus_operations lops_smbus_bus = {
-	.read_byte  = smbus_read_byte,
+	.read_byte	= smbus_read_byte,
 };
 
 static struct device_operations smbus_ops = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init             = 0,
-	.scan_bus         = scan_static_bus,
-	.enable           = i82801er_enable,
-	.ops_smbus_bus    = &lops_smbus_bus,
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= 0,
+	.scan_bus		= scan_static_bus,
+	.enable			= i82801er_enable,
+	.ops_smbus_bus		= &lops_smbus_bus,
 };
 
-/* i82801aa */
+/* 82801AA */
 static struct pci_driver smbus_driver __pci_driver = {
-	.ops    = &smbus_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x2413,
+	.ops	= &smbus_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2413,
 };
 
-/* i82801ab */
+/* 82801AB */
 static struct pci_driver smbus_driver __pci_driver = {
-	.ops    = &smbus_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x2423,
+	.ops	= &smbus_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2423,
 };
 
-/* i82801ba */
+/* 82801BA */
 static struct pci_driver smbus_driver __pci_driver = {
-	.ops    = &smbus_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x2443,
+	.ops	= &smbus_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2443,
 };
 
-/* i82801ca */
+/* 82801CA */
 static struct pci_driver smbus_driver __pci_driver = {
-	.ops    = &smbus_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x2483,
+	.ops	= &smbus_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2483,
 };
 
-/* i82801db and i82801dbm */
+/* 82801DB and 82801DBM */
 static struct pci_driver smbus_driver __pci_driver = {
-	.ops    = &smbus_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x24c3,
+	.ops	= &smbus_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x24c3,
 };
 
-/* i82801eb and i82801er */
+/* 82801EB and 82801ER */
 static struct pci_driver smbus_driver __pci_driver = {
-	.ops    = &smbus_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x24d3,
+	.ops	= &smbus_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x24d3,
 };
-
diff --git a/src/southbridge/intel/i82801xx/i82801xx_smbus.h b/src/southbridge/intel/i82801xx/i82801xx_smbus.h
index d0226046da..2c2676e728 100644
--- a/src/southbridge/intel/i82801xx/i82801xx_smbus.h
+++ b/src/southbridge/intel/i82801xx/i82801xx_smbus.h
@@ -34,8 +34,8 @@ static int smbus_wait_until_ready(void)
 		if (--loops == 0)
 			break;
 		byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
-	} while(byte & 1);
-	return loops?0:-1;
+	} while (byte & 1);
+	return loops ? 0 : -1;
 }
 
 static int smbus_wait_until_done(void)
@@ -43,12 +43,12 @@ static int smbus_wait_until_done(void)
 	unsigned loops = SMBUS_TIMEOUT;
 	unsigned char byte;
 	do {
-	        smbus_delay();
-	        if (--loops == 0)
-	               break;
-	        byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
-	} while((byte & 1) || (byte & ~((1<<6)|(1<<0))) == 0);
-	return loops?0:-1;
+		smbus_delay();
+		if (--loops == 0)
+			break;
+		byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
+	} while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0);
+	return loops ? 0 : -1;
 }
 
 static int smbus_wait_until_blk_done(void)
@@ -56,12 +56,12 @@ static int smbus_wait_until_blk_done(void)
 	unsigned loops = SMBUS_TIMEOUT;
 	unsigned char byte;
 	do {
-	        smbus_delay();
-	        if (--loops == 0)
-	               break;
-	        byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
-	} while((byte & (1 << 7)) == 0);
-	return loops?0:-1;
+		smbus_delay();
+		if (--loops == 0)
+			break;
+		byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
+	} while ((byte & (1 << 7)) == 0);
+	return loops ? 0 : -1;
 }
 
 static int do_smbus_read_byte(unsigned device, unsigned address)
@@ -80,15 +80,17 @@ static int do_smbus_read_byte(unsigned device, unsigned address)
 	/* Set the command/address... */
 	outb(address & 0xff, SMBUS_IO_BASE + SMBHSTCMD);
 	/* Set up for a byte data read */
-	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2), (SMBUS_IO_BASE + SMBHSTCTL));
+	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2),
+	     (SMBUS_IO_BASE + SMBHSTCTL));
 	/* Clear any lingering errors, so the transaction will run */
 	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
 
-	/* Clear the data byte...*/
+	/* Clear the data byte... */
 	outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
 
 	/* Start the command */
-	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
+	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40),
+	     SMBUS_IO_BASE + SMBHSTCTL);
 
 	/* Poll for transaction completion */
 	if (smbus_wait_until_done() < 0) {
@@ -110,8 +112,8 @@ static int do_smbus_read_byte(unsigned device, unsigned address)
 
 /* This function is neither used nor tested by me (Corey Osgood), the author 
 (Yinghai) probably tested/used it on i82801er */
-static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd, 
-		 unsigned data1, unsigned data2)
+static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd,
+				unsigned data1, unsigned data2)
 {
 #warning "do_smbus_write_block is commented out"
 	print_err("Untested smbus_write_block called\r\n");
@@ -124,55 +126,55 @@ static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd,
 
 	/* Clear the PM timeout flags, SECOND_TO_STS */
 	outw(inw(0x0400 + 0x66), 0x0400 + 0x66);
-	
+
 	if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) {
 		return -2;
 	}
-	
+
 	/* Setup transaction */
 	/* Obtain ownership */
 	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
-	for(stat = 0; (stat & 0x40) == 0; ) {
-	stat = inb(SMBUS_IO_BASE + SMBHSTSTAT);
+	for (stat = 0; (stat & 0x40) == 0;) {
+		stat = inb(SMBUS_IO_BASE + SMBHSTSTAT);
 	}
 	/* Clear the done bit */
 	outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT);
 	/* Disable interrupts */
 	outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
-	
+
 	/* Set the device I'm talking too */
 	outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD);
-	
+
 	/* Set the command address */
 	outb(cmd & 0xff, SMBUS_IO_BASE + SMBHSTCMD);
-	
+
 	/* Set the block length */
 	outb(length & 0xff, SMBUS_IO_BASE + SMBHSTDAT0);
-	
+
 	/* Try sending out the first byte of data here */
 	byte = (data1 >> (0)) & 0x0ff;
 	outb(byte, SMBUS_IO_BASE + SMBBLKDAT);
 	/* Issue a block write command */
-	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x5 << 2) | 0x40, 
-			SMBUS_IO_BASE + SMBHSTCTL);
+	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x5 << 2) | 0x40,
+	     SMBUS_IO_BASE + SMBHSTCTL);
+
+	for (i = 0; i < length; i++) {
 
-	for(i = 0;i < length; i++) {
-		
 		/* Poll for transaction completion */
 		if (smbus_wait_until_blk_done(SMBUS_IO_BASE) < 0) {
 			return -3;
 		}
-		
+
 		/* Load the next byte */
-		if(i > 3)
+		if (i > 3)
 			byte = (data2 >> (i % 4)) & 0x0ff;
 		else
 			byte = (data1 >> (i)) & 0x0ff;
 		outb(byte, SMBUS_IO_BASE + SMBBLKDAT);
-		
+
 		/* Clear the done bit */
-		outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), 
-				SMBUS_IO_BASE + SMBHSTSTAT);
+		outb(inb(SMBUS_IO_BASE + SMBHSTSTAT),
+		     SMBUS_IO_BASE + SMBHSTSTAT);
 	}
 
 	print_debug("SMBUS Block complete\r\n");
diff --git a/src/southbridge/intel/i82801xx/i82801xx_usb.c b/src/southbridge/intel/i82801xx/i82801xx_usb.c
index 27c09e089e..3fc689db24 100644
--- a/src/southbridge/intel/i82801xx/i82801xx_usb.c
+++ b/src/southbridge/intel/i82801xx/i82801xx_usb.c
@@ -27,104 +27,104 @@
 
 static void usb_init(struct device *dev)
 {
-/* TODO: Any init needed? Some ports have it, others don't */
+	/* TODO: Any init needed? Some ports have it, others don't. */
 }
 
-static struct device_operations usb_ops  = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init             = usb_init,
-	.scan_bus         = 0,
-	.enable           = i82801xx_enable,
+static struct device_operations usb_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= usb_init,
+	.scan_bus		= 0,
+	.enable			= i82801xx_enable,
 };
 
-/* i82801aa */
+/* 82801AA */
 static struct pci_driver i82801aa_usb_1 __pci_driver = {
-	.ops    = &usb_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x2412,
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2412,
 };
 
-/* i82801ab */
+/* 82801AB */
 static struct pci_driver i82801ab_usb_1 __pci_driver = {
-        .ops    = &usb_ops,
-        .vendor = PCI_VENDOR_ID_INTEL,
-        .device = 0x2422,
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2422,
 };
 
-/* i82801ba */
+/* 82801BA */
 static struct pci_driver i82801ba_usb_1 __pci_driver = {
-        .ops    = &usb_ops,
-        .vendor = PCI_VENDOR_ID_INTEL,
-        .device = 0x2442,
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2442,
 };
 
 static struct pci_driver i82801ba_usb_2 __pci_driver = {
-        .ops    = &usb_ops,
-        .vendor = PCI_VENDOR_ID_INTEL,
-        .device = 0x2444,
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2444,
 };
 
-/* i82801ca */
+/* 82801CA */
 static struct pci_driver i82801ca_usb_1 __pci_driver = {
-        .ops    = &usb_ops,
-        .vendor = PCI_VENDOR_ID_INTEL,
-        .device = 0x2482,
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2482,
 };
 
 static struct pci_driver i82801ca_usb_2 __pci_driver = {
-        .ops    = &usb_ops,
-        .vendor = PCI_VENDOR_ID_INTEL,
-        .device = 0x2484,
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2484,
 };
 
 static struct pci_driver i82801ca_usb_3 __pci_driver = {
-        .ops    = &usb_ops,
-        .vendor = PCI_VENDOR_ID_INTEL,
-        .device = 0x2487,
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2487,
 };
 
-/* i82801db and i82801dbm */
+/* 82801DB and 82801DBM */
 static struct pci_driver i82801db_usb_1 __pci_driver = {
-        .ops    = &usb_ops,
-        .vendor = PCI_VENDOR_ID_INTEL,
-        .device = 0x24c2,
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x24c2,
 };
 
 static struct pci_driver i82801db_usb_2 __pci_driver = {
-        .ops    = &usb_ops,
-        .vendor = PCI_VENDOR_ID_INTEL,
-        .device = 0x24c4,
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x24c4,
 };
 
 static struct pci_driver i82801db_usb_3 __pci_driver = {
-        .ops    = &usb_ops,
-        .vendor = PCI_VENDOR_ID_INTEL,
-        .device = 0x24c7,
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x24c7,
 };
 
-/* i82801eb and i82801er */
+/* 82801EB and 82801ER */
 static struct pci_driver i82801ex_usb_1 __pci_driver = {
-        .ops    = &usb_ops,
-        .vendor = PCI_VENDOR_ID_INTEL,
-        .device = 0x24d2,
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x24d2,
 };
 
 static struct pci_driver i82801ex_usb_2 __pci_driver = {
-        .ops    = &usb_ops,
-        .vendor = PCI_VENDOR_ID_INTEL,
-        .device = 0x24d4,
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x24d4,
 };
 
 static struct pci_driver i82801ex_usb_3 __pci_driver = {
-        .ops    = &usb_ops,
-        .vendor = PCI_VENDOR_ID_INTEL,
-        .device = 0x24d7,
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x24d7,
 };
 
 static struct pci_driver i82801ex_usb_4 __pci_driver = {
-        .ops    = &usb_ops,
-        .vendor = PCI_VENDOR_ID_INTEL,
-        .device = 0x24de,
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x24de,
 };
diff --git a/src/southbridge/intel/i82801xx/i82801xx_usb_ehci.c b/src/southbridge/intel/i82801xx/i82801xx_usb_ehci.c
index 7577da19df..fd8acc28d8 100644
--- a/src/southbridge/intel/i82801xx/i82801xx_usb_ehci.c
+++ b/src/southbridge/intel/i82801xx/i82801xx_usb_ehci.c
@@ -33,49 +33,53 @@ static void usb_ehci_init(struct device *dev)
 
 	printk_debug("EHCI: Setting up controller.. ");
 	cmd = pci_read_config32(dev, PCI_COMMAND);
-	pci_write_config32(dev, PCI_COMMAND, 
-		cmd | PCI_COMMAND_MASTER);
+	pci_write_config32(dev, PCI_COMMAND, cmd | PCI_COMMAND_MASTER);
 
 	printk_debug("done.\n");
 }
 
-static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void usb_ehci_set_subsystem(device_t dev, unsigned vendor,
+				   unsigned device)
 {
 	uint8_t access_cntl;
+
 	access_cntl = pci_read_config8(dev, 0x80);
-	/* Enable writes to protected registers */
+
+	/* Enable writes to protected registers. */
 	pci_write_config8(dev, 0x80, access_cntl | 1);
-	/* Write the subsystem vendor and device id */
-	pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, 
-		((device & 0xffff) << 16) | (vendor & 0xffff));
-	/* Restore protection */
+
+	/* Write the subsystem vendor and device ID. */
+	pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+			   ((device & 0xffff) << 16) | (vendor & 0xffff));
+
+	/* Restore protection. */
 	pci_write_config8(dev, 0x80, access_cntl);
 }
 
 static struct pci_operations lops_pci = {
-	.set_subsystem = &usb_ehci_set_subsystem,
+	.set_subsystem	= &usb_ehci_set_subsystem,
 };
 
-static struct device_operations usb_ehci_ops  = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init             = usb_ehci_init,
-	.scan_bus         = 0,
-	.enable           = i82801xx_enable,
-	.ops_pci          = &lops_pci,
+static struct device_operations usb_ehci_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= usb_ehci_init,
+	.scan_bus		= 0,
+	.enable			= i82801xx_enable,
+	.ops_pci		= &lops_pci,
 };
 
-/* i82801db and i82801dbm */
+/* 82801DB and 82801DBM */
 static struct pci_driver i82801db_usb_ehci __pci_driver = {
-	.ops    = &usb_ehci_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x24cd,
+	.ops	= &usb_ehci_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x24cd,
 };
 
-/* i82801eb and i82801er */
+/* 82801EB and 82801ER */
 static struct pci_driver i82801ex_usb_ehci __pci_driver = {
-	.ops    = &usb_ehci_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x24dd,
+	.ops	= &usb_ehci_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x24dd,
 };
diff --git a/src/southbridge/intel/i82801xx/i82801xx_watchdog.c b/src/southbridge/intel/i82801xx/i82801xx_watchdog.c
index e2a95156eb..58fed673c6 100644
--- a/src/southbridge/intel/i82801xx/i82801xx_watchdog.c
+++ b/src/southbridge/intel/i82801xx/i82801xx_watchdog.c
@@ -17,35 +17,38 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
+
 #include <console/console.h>
 #include <arch/io.h>
 #include <device/device.h>
 #include <device/pci.h>
 
-/* TODO: I'm fairly sure the same functionality is provided elsewhere */
+/* TODO: I'm fairly sure the same functionality is provided elsewhere. */
 
 void watchdog_off(void)
 {
-        device_t dev;
-        unsigned long value,base;
-
-	/* turn off the ICH5 watchdog */
-        dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
-        
-        /* Enable I/O space */
-        value = pci_read_config16(dev, 0x04);
-        value |= (1 << 10);
-        pci_write_config16(dev, 0x04, value);
-        /* Get TCO base */
-        base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
-        /* Disable the watchdog timer */
-        value = inw(base + 0x08);
-        value |= 1 << 11;
-        outw(value, base + 0x08);
-        /* Clear TCO timeout status */
-        outw(0x0008, base + 0x04);
-        outw(0x0002, base + 0x06);
-        printk_debug("ICH Watchdog disabled\r\n");
-}
+	device_t dev;
+	unsigned long value, base;
+
+	/* Turn off the ICH5 watchdog. */
+	dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
+
+	/* Enable I/O space. */
+	value = pci_read_config16(dev, 0x04);
+	value |= (1 << 10);
+	pci_write_config16(dev, 0x04, value);
 
+	/* Get TCO base. */
+	base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
 
+	/* Disable the watchdog timer. */
+	value = inw(base + 0x08);
+	value |= 1 << 11;
+	outw(value, base + 0x08);
+
+	/* Clear TCO timeout status. */
+	outw(0x0008, base + 0x04);
+	outw(0x0002, base + 0x06);
+
+	printk_debug("ICH Watchdog disabled\r\n");
+}