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authorDuncan Laurie <dlaurie@chromium.org>2014-01-16 11:18:36 -0800
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-05-15 05:07:07 +0200
commitc6313db34f26bcb8bdbb5ff04ebc9c9e7193cf0f (patch)
treea669b481993366ae2268630ab55ab1d3ef572dd5 /src
parent3549462a95c5d7b9450924a1c0ca54b992c81211 (diff)
baytrail: Enable PCIe common clock and ASPM
Enable the config options to have the device enumeration layer configure common clock and ASPM for endpoints. BUG=chrome-os-partner:23629 BRANCH=baytrail TEST=build and boot on rambi, check PCIe for ASPM and common clock: lspci -vv -s 0:1c.0 | grep LnkCtl: LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ lspci -vv -s 1:00.0 | grep LnkCtl: LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ Change-Id: I2477e3cada0732dc71db0d6692ff5b6159ed269f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182860 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5051 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/baytrail/Kconfig2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 9a3fa920be..a93b487b87 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -24,6 +24,8 @@ config CPU_SPECIFIC_OPTIONS
select MMCONF_SUPPORT_DEFAULT
select RELOCATABLE_MODULES
select PARALLEL_MP
+ select PCIEXP_ASPM
+ select PCIEXP_COMMON_CLOCK
select SMM_MODULES
select SMM_TSEG
select SMP