Add support for "Stout" Chromebook

We're happy to announce coreboot support for the "Stout"
Chromebook, a.k.a Lenovo X131e Chromebook.

Change-Id: I9b995f8d0dd48e41c788b7c3d35b4fac5840e425
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2636
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

29 files changed, 10162 insertions, 2 deletions

diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig
index 3398cc11fc..8d1fd567e6 100644
--- a/src/mainboard/google/Kconfig
+++ b/src/mainboard/google/Kconfig
@@ -23,18 +23,22 @@ choice
 
 config BOARD_GOOGLE_BUTTERFLY
 	bool "Butterfly"
-config BOARD_GOOGLE_PARROT
-	bool "Parrot"
 config BOARD_GOOGLE_LINK
 	bool "Link"
+config BOARD_GOOGLE_PARROT
+	bool "Parrot"
 config BOARD_GOOGLE_SNOW
 	bool "Snow"
+config BOARD_GOOGLE_STOUT
+	bool "Stout"
+
 endchoice
 
 source "src/mainboard/google/butterfly/Kconfig"
 source "src/mainboard/google/link/Kconfig"
 source "src/mainboard/google/parrot/Kconfig"
 source "src/mainboard/google/snow/Kconfig"
+source "src/mainboard/google/stout/Kconfig"
 
 config MAINBOARD_VENDOR
 	string
diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig
new file mode 100644
index 0000000000..f6ac5b961a
--- /dev/null
+++ b/src/mainboard/google/stout/Kconfig
@@ -0,0 +1,53 @@
+if BOARD_GOOGLE_STOUT
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select ARCH_X86
+	select CPU_INTEL_SOCKET_RPGA989
+	select NORTHBRIDGE_INTEL_IVYBRIDGE
+	select SOUTHBRIDGE_INTEL_C216
+	select EC_QUANTA_IT8518
+	select BOARD_HAS_FADT
+	select BOARD_ROMSIZE_KB_8192
+	select HAVE_ACPI_TABLES
+	select HAVE_OPTION_TABLE
+	select HAVE_ACPI_RESUME
+	select MMCONF_SUPPORT
+	select HAVE_SMI_HANDLER
+	select GFXUMA
+	select CHROMEOS
+	select EXTERNAL_MRC_BLOB
+
+config MAINBOARD_DIR
+	string
+	default google/stout
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Stout"
+
+config MMCONF_BASE_ADDRESS
+	hex
+	default 0xf0000000
+
+config IRQ_SLOT_COUNT
+	int
+	default 18
+
+config MAX_CPUS
+	int
+	default 8
+
+config VGA_BIOS_FILE
+	string
+	default "pci8086,0106.rom"
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+	hex
+	default 0x1ae0
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+	hex
+	default 0xc000
+
+endif # BOARD_GOOGLE_STOUT
diff --git a/src/mainboard/google/stout/Makefile.inc b/src/mainboard/google/stout/Makefile.inc
new file mode 100644
index 0000000000..2ebf74b67f
--- /dev/null
+++ b/src/mainboard/google/stout/Makefile.inc
@@ -0,0 +1,28 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+ramstage-y += ec.c
+
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += ec.c
+
+SRC_ROOT = $(src)/mainboard/google/stout
diff --git a/src/mainboard/google/stout/acpi/chromeos.asl b/src/mainboard/google/stout/acpi/chromeos.asl
new file mode 100644
index 0000000000..b69aff1bf4
--- /dev/null
+++ b/src/mainboard/google/stout/acpi/chromeos.asl
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+Name(OIPG, Package() {
+	// No GPIO for recovery mode, developer mode, or firmware write protect
+	// on stout - note: all virtual pins are active HIGH polarity on stout.
+	Package() { 0x001, 1, 0xFF, "PantherPoint" }, // recovery button
+	Package() { 0x002, 1, 0xFF, "PantherPoint" }, // developer button
+	Package() { 0x003, 0, 7, "PantherPoint" }, // firmware write protect
+})
+
diff --git a/src/mainboard/google/stout/acpi/ec.asl b/src/mainboard/google/stout/acpi/ec.asl
new file mode 100644
index 0000000000..b807894aca
--- /dev/null
+++ b/src/mainboard/google/stout/acpi/ec.asl
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* mainboard configuration */
+#include "../ec.h"
+
+/* ACPI code for EC functions */
+#include <ec/quanta/it8518/acpi/ec.asl>
diff --git a/src/mainboard/google/stout/acpi/mainboard.asl b/src/mainboard/google/stout/acpi/mainboard.asl
new file mode 100644
index 0000000000..4ea4a09766
--- /dev/null
+++ b/src/mainboard/google/stout/acpi/mainboard.asl
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Scope (\_SB)
+{
+	Device (LID0)
+	{
+		Name (_HID, EisaId("PNP0C0D"))
+		Name (_PRW, Package() {0x18, 4})
+
+		Method (_LID, 0)
+		{
+			Store (\_SB.PCI0.LPCB.EC0.HPLD, \LIDS)
+			Return (\LIDS)
+		}
+
+		Method (_PSW, 1)
+		{
+			// Enable/Disable LID as a wake source
+			Store (Arg0, \_SB.PCI0.LPCB.EC0.HWLO)
+		}
+	}
+
+	Device (PWRB)
+	{
+		Name (_HID, EisaId("PNP0C0C"))
+	}
+}
diff --git a/src/mainboard/google/stout/acpi/platform.asl b/src/mainboard/google/stout/acpi/platform.asl
new file mode 100644
index 0000000000..a90a16eb30
--- /dev/null
+++ b/src/mainboard/google/stout/acpi/platform.asl
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+	APMC, 8,	// APM command
+	APMS, 8		// APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+	DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+	Store (Arg0, SMIF)	// SMI Function
+	Store (0, TRP0)		// Generate trap
+	Return (SMIF)		// Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+	// Remember the OS' IRQ routing choice.
+	Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+	// Notify EC to enter S3
+	Store(0x01, \_SB.PCI0.LPCB.EC0.S3FG)
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+	/* Update AC status */
+	Store (\_SB.PCI0.LPCB.EC0.ACPW, Local0)
+	if (LNotEqual (Local0, \PWRS)) {
+		Store (Local0, \PWRS)
+		Notify (\_SB.PCI0.LPCB.EC0.AC, 0x80)
+	}
+
+	/* Update LID status */
+	Store (NOT(\_SB.PCI0.LPCB.EC0.HPLD), Local0)
+	if (LNotEqual (Local0, \LIDS)) {
+		Store (Local0, \LIDS)
+		Notify (\_SB.LID0, 0x80)
+	}
+
+	Return(Package(){0,0})
+}
+
diff --git a/src/mainboard/google/stout/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/stout/acpi/sandybridge_pci_irqs.asl
new file mode 100644
index 0000000000..7ce8cd85fb
--- /dev/null
+++ b/src/mainboard/google/stout/acpi/sandybridge_pci_irqs.asl
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for Sandybridge */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, 0, 16 },
+			// XHCI	0:14.0
+			Package() { 0x0014ffff, 0, 0, 19 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, 0, 16 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, 0, 19 },
+			Package() { 0x001cffff, 1, 0, 20 },
+			Package() { 0x001cffff, 2, 0, 17 },
+			Package() { 0x001cffff, 3, 0, 18 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, 0, 19 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, 0, 21 },
+			// LPC devices			0:1f.0
+			Package() { 0x001fffff, 0, 0, 17 },
+			Package() { 0x001fffff, 1, 0, 23 },
+			Package() { 0x001fffff, 2, 0, 16 },
+			Package() { 0x001fffff, 3, 0, 18 },
+		})
+	} Else {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// XHCI   0:14.0
+			Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
+			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
+			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
+		})
+	}
+}
+
diff --git a/src/mainboard/google/stout/acpi/superio.asl b/src/mainboard/google/stout/acpi/superio.asl
new file mode 100644
index 0000000000..feb4210fbc
--- /dev/null
+++ b/src/mainboard/google/stout/acpi/superio.asl
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* mainboard configuration */
+#include "../ec.h"
+
+#define SIO_EC_ENABLE_PS2K       // Enable PS/2 Keyboard
+#define SIO_ENABLE_PS2M          // Enable PS/2 Mouse
+
+/* ACPI code for EC SuperIO functions */
+#include <ec/quanta/it8518/acpi/superio.asl>
diff --git a/src/mainboard/google/stout/acpi/thermal.asl b/src/mainboard/google/stout/acpi/thermal.asl
new file mode 100644
index 0000000000..0db4d133ec
--- /dev/null
+++ b/src/mainboard/google/stout/acpi/thermal.asl
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Thermal Zone
+
+Scope (\_TZ)
+{
+	ThermalZone (THRM)
+	{
+		Name (_TC1, 0x02)
+		Name (_TC2, 0x03)
+
+		// Thermal zone polling frequency: 10 seconds
+		Name (_TZP, 100)
+
+		// Thermal sampling period for passive cooling: 10 seconds
+		Name (_TSP, 100)
+
+		// Convert from Degrees C to 1/10 Kelvin for ACPI
+		Method (CTOK, 1)
+		{
+			// 10th of Degrees C
+			Multiply (Arg0, 10, Local0)
+
+			// Convert to Kelvin
+			Add (Local0, 2732, Local0)
+
+			Return (Local0)
+		}
+
+		// Threshold for OS to shutdown
+		Method (_CRT, 0, Serialized)
+		{
+			Return (CTOK (\TCRT))
+		}
+
+		// Threshold for passive cooling
+		Method (_PSV, 0, Serialized)
+		{
+			Return (CTOK (\TPSV))
+		}
+
+		// Processors used for passive cooling
+		Method (_PSL, 0, Serialized)
+		{
+			Return (\PPKG ())
+		}
+
+		Method (_TMP, 0, Serialized)
+		{
+			// Returns Higher of the two readings for CPU & VGA Temperature
+			If (LGreater (\_SB.PCI0.LPCB.EC0.TMP2, \_SB.PCI0.LPCB.EC0.TMP1))
+			{
+				// CPU high temperature
+				Store (\_SB.PCI0.LPCB.EC0.TMP2, Local0)
+			}
+			Else
+			{
+				// VGA high temperature
+				Store (\_SB.PCI0.LPCB.EC0.TMP1, Local0)
+			}
+
+			// If temp less 35 or great then 115, set default 35
+			If (Or (LLess (Local0, 35), LGreater (Local0, 115)))
+			{
+				Store (35, Local0)
+			}
+
+			Return (CTOK (Local0))
+		}
+	}
+}
diff --git a/src/mainboard/google/stout/acpi/video.asl b/src/mainboard/google/stout/acpi/video.asl
new file mode 100644
index 0000000000..3ececa912b
--- /dev/null
+++ b/src/mainboard/google/stout/acpi/video.asl
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Brightness write
+Method (BRTW, 1, Serialized)
+{
+	// TODO
+}
+
+// Hot Key Display Switch
+Method (HKDS, 1, Serialized)
+{
+	// TODO
+}
+
+// Lid Switch Display Switch
+Method (LSDS, 1, Serialized)
+{
+	// TODO
+}
+
+// Brightness Notification
+Method(BRTN,1,Serialized)
+{
+	// TODO (no displays defined yet)
+}
+
diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c
new file mode 100644
index 0000000000..62d589145e
--- /dev/null
+++ b/src/mainboard/google/stout/acpi_tables.c
@@ -0,0 +1,274 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/msr.h>
+#include <vendorcode/google/chromeos/gnvs.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <ec/quanta/it8518/ec.h>
+#include "ec.h"
+#include "onboard.h"
+
+extern const unsigned char AmlCode[];
+#if CONFIG_HAVE_ACPI_SLIC
+unsigned long acpi_create_slic(unsigned long current);
+#endif
+
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/nvs.h>
+#include "thermal.h"
+
+static void acpi_update_thermal_table(global_nvs_t *gnvs)
+{
+	/* EC handles all thermal and fan control on Stout. */
+	gnvs->tcrt = CRITICAL_TEMPERATURE;
+	gnvs->tpsv = PASSIVE_TEMPERATURE;
+	gnvs->tmax = MAX_TEMPERATURE;
+}
+
+static void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+	memset((void *)gnvs, 0, sizeof(*gnvs));
+	gnvs->apic = 1;
+	gnvs->mpen = 1; /* Enable Multi Processing */
+	gnvs->pcnt = dev_count_cpu();
+
+	/* Disable USB ports in S3 by default */
+	gnvs->s3u0 = 0;
+	gnvs->s3u1 = 0;
+
+	/* Disable USB ports in S5 by default */
+	gnvs->s5u0 = 0;
+	gnvs->s5u1 = 0;
+
+	/* CBMEM TOC */
+	gnvs->cmem = (u32)get_cbmem_toc();
+
+	/* IGD Displays */
+	gnvs->ndid = 3;
+	gnvs->did[0] = 0x80000100;
+	gnvs->did[1] = 0x80000240;
+	gnvs->did[2] = 0x80000410;
+	gnvs->did[3] = 0x80000410;
+	gnvs->did[4] = 0x00000005;
+
+#if CONFIG_CHROMEOS
+	// TODO(reinauer) this could move elsewhere?
+	chromeos_init_vboot(&(gnvs->chromeos));
+
+	gnvs->chromeos.vbt2 = get_recovery_mode_switch() ?
+			ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
+#endif
+
+	acpi_update_thermal_table(gnvs);
+
+	// the lid is open by default.
+	gnvs->lids = 1;
+
+	/* XHCI Mode */
+	gnvs->xhci = XHCI_MODE;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* Local APICs */
+	current = acpi_create_madt_lapics(current);
+
+	/* IOAPIC */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+				2, IO_APIC_ADDR, 0);
+
+	/* INT_SRC_OVR */
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+		 current, 0, 0, 2, 0);
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+		 current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
+
+	return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current,
+					const char *oem_table_id)
+{
+	generate_cpu_entries();
+	return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+	// Not implemented
+	return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+	/* No NUMA, no SRAT */
+	return current;
+}
+
+#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10)
+unsigned long write_acpi_tables(unsigned long start)
+{
+	unsigned long current;
+	int i;
+	acpi_rsdp_t *rsdp;
+	acpi_rsdt_t *rsdt;
+	acpi_xsdt_t *xsdt;
+	acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_mcfg_t *mcfg;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+#if CONFIG_HAVE_ACPI_SLIC
+	acpi_header_t *slic;
+#endif
+	acpi_header_t *ssdt;
+	acpi_header_t *dsdt;
+
+	current = start;
+
+	/* Align ACPI tables to 16byte */
+	ALIGN_CURRENT;
+
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
+
+	/* We need at least an RSDP and an RSDT Table */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	ALIGN_CURRENT;
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+	ALIGN_CURRENT;
+	xsdt = (acpi_xsdt_t *) current;
+	current += sizeof(acpi_xsdt_t);
+	ALIGN_CURRENT;
+
+	/* clear all table memory */
+	memset((void *) start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt, xsdt);
+	acpi_write_rsdt(rsdt);
+	acpi_write_xsdt(xsdt);
+
+	printk(BIOS_DEBUG, "ACPI:    * FACS\n");
+	facs = (acpi_facs_t *) current;
+	current += sizeof(acpi_facs_t);
+	ALIGN_CURRENT;
+	acpi_create_facs(facs);
+
+	printk(BIOS_DEBUG, "ACPI:    * DSDT\n");
+	dsdt = (acpi_header_t *) current;
+	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+	current += dsdt->length;
+	memcpy(dsdt, &AmlCode, dsdt->length);
+
+	ALIGN_CURRENT;
+
+	printk(BIOS_DEBUG, "ACPI:    * FADT\n");
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+	ALIGN_CURRENT;
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdp, fadt);
+
+	/*
+	 * We explicitly add these tables later on:
+	 */
+	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
+
+	hpet = (acpi_hpet_t *) current;
+	current += sizeof(acpi_hpet_t);
+	ALIGN_CURRENT;
+	acpi_create_hpet(hpet);
+	acpi_add_table(rsdp, hpet);
+
+	/* If we want to use HPET Timers Linux wants an MADT */
+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
+
+	madt = (acpi_madt_t *) current;
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, madt);
+
+	printk(BIOS_DEBUG, "ACPI:    * MCFG\n");
+	mcfg = (acpi_mcfg_t *) current;
+	acpi_create_mcfg(mcfg);
+	current += mcfg->header.length;
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, mcfg);
+
+	/* Pack GNVS into the ACPI table area */
+	for (i=0; i < dsdt->length; i++) {
+		if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
+			printk(BIOS_DEBUG, "ACPI: Patching up global NVS in "
+			     "DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
+			*(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
+			acpi_save_gnvs(current);
+			break;
+		}
+	}
+
+	/* And fill it */
+	acpi_create_gnvs((global_nvs_t *)current);
+
+	/* And tell SMI about it */
+	smm_setup_structures((void *)current, NULL, NULL);
+
+	current += sizeof(global_nvs_t);
+	ALIGN_CURRENT;
+
+	/* We patched up the DSDT, so we need to recalculate the checksum */
+	dsdt->checksum = 0;
+	dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
+
+	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt,
+		     dsdt->length);
+
+#if CONFIG_HAVE_ACPI_SLIC
+	printk(BIOS_DEBUG, "ACPI:     * SLIC\n");
+	slic = (acpi_header_t *)current;
+	current += acpi_create_slic(current);
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, slic);
+#endif
+
+	printk(BIOS_DEBUG, "ACPI:     * SSDT\n");
+	ssdt = (acpi_header_t *)current;
+	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
+	current += ssdt->length;
+	acpi_add_table(rsdp, ssdt);
+	ALIGN_CURRENT;
+
+	printk(BIOS_DEBUG, "current = %lx\n", current);
+	printk(BIOS_INFO, "ACPI: done.\n");
+	return current;
+}
diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c
new file mode 100644
index 0000000000..db94cb7f47
--- /dev/null
+++ b/src/mainboard/google/stout/chromeos.c
@@ -0,0 +1,143 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011-2012 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <arch/io.h>
+#include <console/console.h>
+#ifdef __PRE_RAM__
+#include <arch/romcc_io.h>
+#else
+#include <device/device.h>
+#include <device/pci.h>
+#endif
+
+#include <southbridge/intel/bd82x6x/pch.h>
+#include "ec.h"
+#include <ec/quanta/it8518/ec.h>
+
+#ifndef __PRE_RAM__
+#include <boot/coreboot_tables.h>
+#include <arch/coreboot_tables.h>
+
+#define GPIO_COUNT	7
+#define ACTIVE_LOW	0
+#define ACTIVE_HIGH	1
+
+static int ec_in_rec_mode;
+static int ec_rec_flag_good;
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+	device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+	u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
+
+	if (!gpio_base)
+		return;
+
+	u32 gp_lvl = inl(gpio_base + GP_LVL);
+
+	gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
+	gpios->count = GPIO_COUNT;
+
+	/* Write Protect: GPIO7 */
+	gpios->gpios[0].port = 7;
+	gpios->gpios[0].polarity = ACTIVE_LOW;
+	gpios->gpios[0].value = (gp_lvl >> 7) & 1;
+	strncpy((char *)gpios->gpios[0].name,"write protect",
+							GPIO_MAX_NAME_LENGTH);
+
+	/* Recovery: Virtual switch */
+	gpios->gpios[1].port = -1;
+	gpios->gpios[1].polarity = ACTIVE_HIGH;
+	gpios->gpios[1].value = get_recovery_mode_switch();
+	strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH);
+
+	/* Developer: Virtual switch */
+	gpios->gpios[2].port = -1;
+	gpios->gpios[2].polarity = ACTIVE_HIGH;
+	gpios->gpios[2].value = get_developer_mode_switch();
+	strncpy((char *)gpios->gpios[2].name,"developer", GPIO_MAX_NAME_LENGTH);
+
+	/* Lid Switch: Virtual switch */
+	gpios->gpios[3].port = -1;
+	gpios->gpios[3].polarity = ACTIVE_HIGH;
+	gpios->gpios[3].value = 1; /* Hard-code to open */
+	strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH);
+
+	/* Power Button: Virtual switch */
+	gpios->gpios[4].port = -1;
+	gpios->gpios[4].polarity = ACTIVE_HIGH;
+	gpios->gpios[4].value = 0; /* Hard-code to de-asserted */
+	strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH);
+
+	/* Was VGA Option ROM loaded? */
+	gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */
+	gpios->gpios[5].polarity = ACTIVE_HIGH;
+	gpios->gpios[5].value = oprom_is_loaded;
+	strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH);
+
+	/* EC is in RW mode when it isn't in recovery mode. */
+	gpios->gpios[6].port = -1;
+	gpios->gpios[6].polarity = ACTIVE_HIGH;
+	gpios->gpios[6].value = !get_recovery_mode_switch();
+	strncpy((char *)gpios->gpios[6].name,"ec_in_rw", GPIO_MAX_NAME_LENGTH);
+}
+#endif
+
+/* The dev-switch is virtual on Stout (and so handled elsewhere). */
+int get_developer_mode_switch(void)
+{
+	return 0;
+}
+
+/*
+ * The recovery-switch is virtual on Stout and is handled via the EC.
+ * Stout recovery mode is only valid if RTC_PWR_STS is set and the EC
+ * indicated the recovery keys were pressed. We use a global flag for
+ * rec_mode to be used after RTC_POWER_STS has been cleared. This function
+ * is complicated by romstage support, which can't use a global variable.
+ * Note, rec_mode is the only time the EC is in RO mode, otherwise, RW.
+ */
+int get_recovery_mode_switch(void)
+{
+#ifdef __PRE_RAM__
+	device_t dev = PCI_DEV(0, 0x1f, 0);
+#else
+	device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+#endif
+
+	u8 ec_status = ec_read(EC_STATUS_REG);
+	u8 reg8 = pci_read_config8(dev, GEN_PMCON_3);
+
+	printk(BIOS_SPEW,"%s:  EC status:%#x   RTC_BAT: %x\n",
+			__func__, ec_status, reg8 & RTC_BATTERY_DEAD);
+
+#ifdef __PRE_RAM__
+	return (((reg8 & RTC_BATTERY_DEAD) != 0) &&
+	         ((ec_status & 0x3) == EC_IN_RECOVERY_MODE));
+#else
+	if (!ec_rec_flag_good) {
+		ec_in_rec_mode = (((reg8 & RTC_BATTERY_DEAD) != 0) &&
+		                     ((ec_status & 0x3) == EC_IN_RECOVERY_MODE));
+		ec_rec_flag_good = 1;
+	}
+	return ec_in_rec_mode;
+#endif
+}
diff --git a/src/mainboard/google/stout/cmos.layout b/src/mainboard/google/stout/cmos.layout
new file mode 100644
index 0000000000..afdd3c66ca
--- /dev/null
+++ b/src/mainboard/google/stout/cmos.layout
@@ -0,0 +1,139 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+# -----------------------------------------------------------------
+# Status Register A
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96           4       r       0        status_c_rsvd
+#100          1       r       0        uf_flag
+#101          1       r       0        af_flag
+#102          1       r       0        pf_flag
+#103          1       r       0        irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104          7       r       0        status_d_rsvd
+#111          1       r       0        valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112          8       r       0        diag_rsvd1
+
+# -----------------------------------------------------------------
+0          120       r       0        reserved_memory
+#120        264       r       0        unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+388          4       r       0        reboot_bits
+#390          2       r       0        unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392          3       e       5        baud_rate
+395          4       e       6        debug_level
+#399          1       r       0        unused
+
+# coreboot config options: cpu
+400          1       e       2        hyper_threading
+#401          7       r       0        unused
+
+# coreboot config options: southbridge
+408          1       e       1        nmi
+409          2       e       7        power_on_after_fail
+#411          5       r       0        unused
+
+# coreboot config options: bootloader
+#Used by ChromeOS:
+416        128       r        0        vbnv
+#544        440       r       0        unused
+
+# SandyBridge MRC Scrambler Seed values
+896         32        r       0        mrc_scrambler_seed
+928         32        r       0        mrc_scrambler_seed_s3
+
+# coreboot config options: check sums
+984         16       h       0        check_sum
+#1000        24       r       0        amd_reserved
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     1     Emergency
+6     2     Alert
+6     3     Critical
+6     4     Error
+6     5     Warning
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Disable
+7     1     Enable
+7     2     Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
+
+
diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb
new file mode 100644
index 0000000000..c58a8d69e9
--- /dev/null
+++ b/src/mainboard/google/stout/devicetree.cb
@@ -0,0 +1,108 @@
+chip northbridge/intel/sandybridge
+
+	# Enable DisplayPort Hotplug with 6ms pulse
+	register "gpu_dp_d_hotplug" = "0x06"
+
+	# Enable Panel as LVDS and configure power delays
+	register "gpu_panel_port_select" = "0"                  # LVDS
+	register "gpu_panel_power_cycle_delay" = "5"            # T4: 400ms
+	register "gpu_panel_power_up_delay" = "400"             # T1+T2: 40ms
+	register "gpu_panel_power_down_delay" = "150"           # T3: 15ms
+	register "gpu_panel_power_backlight_on_delay" = "2100"  # T5: 210ms
+	register "gpu_panel_power_backlight_off_delay" = "2100" # TD: 210ms
+
+	device cpu_cluster 0 on
+		chip cpu/intel/socket_rPGA989
+			device lapic 0 on end
+		end
+		chip cpu/intel/model_206ax
+			# Magic APIC ID to locate this chip
+			device lapic 0xACAC off end
+
+			# Coordinate with HW_ALL
+			register "pstate_coord_type" = "0xfe"
+
+			register "tcc_offset" = "5"	# TCC of 95C
+
+			register "c1_acpower" = "1"	# ACPI(C1) = MWAIT(C1)
+			register "c2_acpower" = "3"	# ACPI(C2) = MWAIT(C3)
+			register "c3_acpower" = "5"	# ACPI(C3) = MWAIT(C7)
+
+			register "c1_battery" = "1"	# ACPI(C1) = MWAIT(C1)
+			register "c2_battery" = "3"	# ACPI(C2) = MWAIT(C3)
+			register "c3_battery" = "5"	# ACPI(C3) = MWAIT(C7)
+		end
+	end
+
+	device domain 0 on
+		subsystemid 0x1ae0 0xc000 inherit
+		device pci 00.0 on end # host bridge
+		device pci 02.0 on end # vga controller
+
+		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+			register "pirqa_routing" = "0x8b"
+			register "pirqb_routing" = "0x8a"
+			register "pirqc_routing" = "0x8b"
+			register "pirqd_routing" = "0x8b"
+			register "pirqe_routing" = "0x80"
+			register "pirqf_routing" = "0x80"
+			register "pirqg_routing" = "0x80"
+			register "pirqh_routing" = "0x80"
+
+			# GPI routing
+			#  0 No effect (default)
+			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+			#  2 SCI (if corresponding GPIO_EN bit is also set)
+			register "alt_gp_smi_en" = "0x0002"
+			register "gpi1_routing" = "1"
+			register "gpi6_routing" = "2"
+
+			register "ide_legacy_combined" = "0x0"
+			register "sata_ahci" = "0x1"
+			register "sata_port_map" = "0x3"
+
+			# Enable EC Port 0x68/0x6C
+			register "gen1_dec" = "0x00040069"
+
+			# EC range is 0x800-0x9ff
+			register "gen2_dec" = "0x00fc0901"
+
+			# EC range is 0x1610-0x161F
+			register "gen3_dec" = "0x0001C1611"
+
+			# Enable zero-based linear PCIe root port functions
+			register "pcie_port_coalesce" = "1"
+
+			device pci 14.0 on end # USB 3.0 Controller
+			device pci 16.0 on end # Management Engine Interface 1
+			device pci 16.1 off end # Management Engine Interface 2
+			device pci 16.2 off end # Management Engine IDE-R
+			device pci 16.3 off end # Management Engine KT
+			device pci 19.0 off end # Intel Gigabit Ethernet
+			device pci 1a.0 on end # USB2 EHCI #2 (AUO4, BlueTooth)
+			device pci 1b.0 on end # High Definition Audio
+			device pci 1c.0 on end # PCIe Port #1
+			device pci 1c.1 on end # PCIe Port #2 (WLAN)
+			device pci 1c.2 on end # PCIe Port #3 (Card Reader)
+				register "pcie_aspm_f2" = "0x3"
+			device pci 1c.3 off end # PCIe Port #4
+			device pci 1c.4 off end # PCIe Port #5
+			device pci 1c.5 on end # PCIe Port #6 (LAN)
+			device pci 1c.6 off end # PCIe Port #7
+			device pci 1c.7 off end # PCIe Port #8
+			device pci 1d.0 on end # USB2 EHCI #1 (Camera, WLAN, WWAN)
+			device pci 1e.0 off end # PCI bridge
+			device pci 1f.0 on
+				chip ec/quanta/it8518
+					# 60h/64h KBC
+					device pnp ff.1 on # dummy address
+					end
+				end
+			end # LPC bridge
+			device pci 1f.2 on end # SATA Controller 1 (HDD/SSD)
+			device pci 1f.3 on end # SMBus Controller
+			device pci 1f.5 off end # SATA Controller 2 (MSATA)
+			device pci 1f.6 off end # Thermal
+		end
+	end
+end
diff --git a/src/mainboard/google/stout/dsdt.asl b/src/mainboard/google/stout/dsdt.asl
new file mode 100644
index 0000000000..925dfd1052
--- /dev/null
+++ b/src/mainboard/google/stout/dsdt.asl
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,       // DSDT revision: ACPI v2.0
+	"COREv4",   // OEM id
+	"COREBOOT", // OEM table id
+	0x20110725  // OEM revision
+)
+{
+	// Some generic macros
+	#include "acpi/platform.asl"
+	#include "acpi/mainboard.asl"
+
+	// global NVS and variables
+	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+
+	// General Purpose Events
+	//#include "acpi/gpe.asl"
+
+	#include "acpi/thermal.asl"
+
+	#include <cpu/intel/model_206ax/acpi/cpu.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
+		}
+	}
+
+	#include "acpi/chromeos.asl"
+	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
+
+	/* Chipset specific sleep states */
+	#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c
new file mode 100644
index 0000000000..474d96f2fb
--- /dev/null
+++ b/src/mainboard/google/stout/ec.c
@@ -0,0 +1,127 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <types.h>
+#include <console/console.h>
+#include <ec/quanta/it8518/ec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <elog.h>
+#include "ec.h"
+
+#ifdef __SMM__
+#include <cpu/x86/smm.h>
+#endif
+
+#ifndef __SMM__
+void stout_ec_init(void)
+{
+
+	printk(BIOS_DEBUG,"%s: EC FW version %x%x\n", __func__,
+			ec_read(EC_FW_VER), ec_read(EC_FW_VER + 1));
+
+	/*
+	 *  Important: get_recovery_mode_switch() must be called in EC init.
+	 */
+	get_recovery_mode_switch();
+
+	/* Unmute */
+	ec_kbc_write_cmd(EC_KBD_CMD_UNMUTE);
+
+	/*
+	 * Set USB Power off in S3 (enabled in S3 path if requested in gnvs)
+	 * Bit0 of 0x0D/Bit0 of 0x26
+	 * 0/0 All USB port off
+	 * 1/0 USB on, all USB port didn’t support wake up
+	 * 0/1 USB on, yellow port support wake up charge, but may not support
+	 *             charge smart phone.
+	 * 1/1 USB on, yellow port in AUTO mode and didn’t support wake up system.
+	 */
+	ec_write(EC_PERIPH_CNTL_3, ec_read(EC_PERIPH_CNTL_3) & 0xE);
+	ec_write(EC_USB_S3_EN, ec_read(EC_USB_S3_EN) & 0xE);
+
+	// TODO: Power Limit Setting
+}
+
+#else // SMM
+
+void stout_ec_finalize_smm(void)
+{
+	u8 ec_reg, critical_shutdown = 0;
+	u32 pm1_cnt;
+
+	/*
+	 * Check EC for error conditions.
+	 */
+
+	/* Fan Error : Peripheral Status 3 (0x35) bit 4 */
+	ec_reg = ec_read(EC_PERIPH_STAT_3);
+
+	if (ec_reg & 0x8) {
+		printk(BIOS_ERR, "  EC Fan Error\n");
+		critical_shutdown = 1;
+#if CONFIG_ELOG
+		elog_add_event_word(EC_EVENT_BATTERY_CRITICAL, EC_EVENT_FAN_ERROR);
+#endif
+	}
+
+
+	/* Thermal Device Error : Peripheral Status 3 (0x35) bit 8 */
+	if (ec_reg & 0x80) {
+		printk(BIOS_ERR, "  EC Thermal Device Error\n");
+		critical_shutdown = 1;
+#if CONFIG_ELOG
+		elog_add_event_word(EC_EVENT_BATTERY_CRITICAL, EC_EVENT_THERMAL);
+#endif
+	}
+
+
+	/* Critical Battery Error */
+	ec_reg = ec_read(EC_MBAT_STATUS);
+
+	if ((ec_reg & 0xCF) == 0xC0) {
+		printk(BIOS_ERR, "  EC Critical Battery Error\n");
+		critical_shutdown = 1;
+#if CONFIG_ELOG
+		elog_add_event_word(ELOG_TYPE_EC_EVENT, EC_EVENT_BATTERY_CRITICAL);
+#endif
+	}
+
+	if ((ec_reg & 0x8F) == 0x8F) {
+		printk(BIOS_ERR, "  EC Read Battery Error\n");
+#if CONFIG_ELOG
+		elog_add_event_word(ELOG_TYPE_EC_EVENT, EC_EVENT_BATTERY);
+#endif
+	}
+
+
+	if (critical_shutdown) {
+		printk(BIOS_ERR, "EC critical_shutdown");
+
+		/* Go to S5 */
+		pm1_cnt = inl(smm_get_pmbase() + PM1_CNT);
+		pm1_cnt |= (0xf << 10);
+		outl(pm1_cnt, smm_get_pmbase() + PM1_CNT);
+	}
+}
+#endif //__SMM__
diff --git a/src/mainboard/google/stout/ec.h b/src/mainboard/google/stout/ec.h
new file mode 100644
index 0000000000..6a9ef4f478
--- /dev/null
+++ b/src/mainboard/google/stout/ec.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef STOUT_EC_H
+#define STOUT_EC_H
+
+#define EC_SCI_GPI  6   /* GPIO6 is EC_SCI# */
+#define EC_SMI_GPI  1   /* GPIO1 is EC_SMI# */
+
+#define EC_SMI_LID_CLOSED	0x2B
+
+#ifndef __ACPI__
+extern void stout_ec_init(void);
+#endif
+
+#ifdef __SMM__
+void stout_ec_finalize_smm(void);
+#endif
+
+#endif // STOUT_EC_H
diff --git a/src/mainboard/google/stout/fadt.c b/src/mainboard/google/stout/fadt.c
new file mode 100644
index 0000000000..5ce9ab11db
--- /dev/null
+++ b/src/mainboard/google/stout/fadt.c
@@ -0,0 +1,166 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <device/pci.h>
+#include <arch/acpi.h>
+
+/* FIXME: This needs to go into a separate .h file
+ * to be included by the ich7 smi handler, ich7 smi init
+ * code and the mainboard fadt.
+ */
+#define APM_CNT		0xb2
+#define   CST_CONTROL	0x85
+#define   PST_CONTROL	0x80
+#define   ACPI_DISABLE	0x1e
+#define   ACPI_ENABLE	0xe1
+#define   GNVS_UPDATE   0xea
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+	u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)),
+								0x40) & 0xfffe;
+
+	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+	header->length = sizeof(acpi_fadt_t);
+	header->revision = 3;
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+	memcpy(header->asl_compiler_id, "CORE", 4);
+	header->asl_compiler_revision = 1;
+
+	fadt->firmware_ctrl = (unsigned long) facs;
+	fadt->dsdt = (unsigned long) dsdt;
+	fadt->model = 1;
+	fadt->preferred_pm_profile = PM_DESKTOP;
+
+	fadt->sci_int = 0x9;
+	fadt->smi_cmd = APM_CNT;
+	fadt->acpi_enable = ACPI_ENABLE;
+	fadt->acpi_disable = ACPI_DISABLE;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = 0;
+
+	fadt->pm1a_evt_blk = pmbase;
+	fadt->pm1b_evt_blk = 0x0;
+	fadt->pm1a_cnt_blk = pmbase + 0x4;
+	fadt->pm1b_cnt_blk = 0x0;
+	fadt->pm2_cnt_blk = pmbase + 0x50;
+	fadt->pm_tmr_blk = pmbase + 0x8;
+	fadt->gpe0_blk = pmbase + 0x20;
+	fadt->gpe1_blk = 0;
+
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 1;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 16;
+	fadt->gpe1_blk_len = 0;
+	fadt->gpe1_base = 0;
+	fadt->cst_cnt = 0;
+	fadt->p_lvl2_lat = 1;
+	fadt->p_lvl3_lat = 87;
+	fadt->flush_size = 1024;
+	fadt->flush_stride = 16;
+	fadt->duty_offset = 1;
+	fadt->duty_width = 0;
+	fadt->day_alrm = 0xd;
+	fadt->mon_alrm = 0x00;
+	fadt->century = 0x00;
+	fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+
+	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+			ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
+			ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
+			ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
+
+	fadt->reset_reg.space_id = 1;
+	fadt->reset_reg.bit_width = 8;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0xcf9;
+	fadt->reset_reg.addrh = 0;
+
+	fadt->reset_value = 6;
+	fadt->x_firmware_ctl_l = (unsigned long)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (unsigned long)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 32;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = pmbase;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = 0;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 16;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = 0;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 8;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 32;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 64;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = pmbase + 0x20;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = 0x0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum =
+	    acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/google/stout/gpio.h b/src/mainboard/google/stout/gpio.h
new file mode 100644
index 0000000000..7bc4667e2e
--- /dev/null
+++ b/src/mainboard/google/stout/gpio.h
@@ -0,0 +1,292 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef STOUT_GPIO_H
+#define STOUT_GPIO_H
+
+#include "southbridge/intel/bd82x6x/gpio.h"
+
+const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0  = GPIO_MODE_GPIO,	/* GPIO0 */
+	.gpio1  = GPIO_MODE_GPIO,	/* SIO_EXT_SMI# */
+	.gpio2  = GPIO_MODE_NONE,	/* NOT USED */
+	.gpio3  = GPIO_MODE_NONE,	/* NOT USED */
+	.gpio4  = GPIO_MODE_NONE,	/* NOT USED */
+	.gpio5  = GPIO_MODE_GPIO,	/* INTH# */
+	.gpio6  = GPIO_MODE_GPIO,	/* SIO_EXT_SCI# */
+	.gpio7  = GPIO_MODE_GPIO,	/* GE_SCR_WP# */
+	.gpio8  = GPIO_MODE_NONE,	/* NOT USED */
+	.gpio9  = GPIO_MODE_NATIVE,	/* USB_OC5# */
+	.gpio10 = GPIO_MODE_NATIVE,	/* USB_OC6# */
+	.gpio11 = GPIO_MODE_NATIVE,	/* SMBALERT# */
+	.gpio12 = GPIO_MODE_GPIO,	/* GPIO12 */
+	.gpio13 = GPIO_MODE_GPIO,	/* GPIO13 */
+	.gpio14 = GPIO_MODE_NATIVE,	/* USB_OC7# */
+	.gpio15 = GPIO_MODE_GPIO,	/* GPIO15 */
+	.gpio16 = GPIO_MODE_GPIO,	/* WWAN_LED_ON */
+	.gpio17 = GPIO_MODE_GPIO,	/* WLAN_LED_ON */
+	.gpio18 = GPIO_MODE_NATIVE,	/* PCIE_CLKREQ_WLAN# */
+	.gpio19 = GPIO_MODE_GPIO,	/* BBS_BIT0 */
+	.gpio20 = GPIO_MODE_NATIVE,	/* PCIE_CLKREQ_CARD# */
+	.gpio21 = GPIO_MODE_GPIO,	/* BT_DET# / TP29 */
+	.gpio22 = GPIO_MODE_GPIO,	/* MODEL_ID0 */
+	.gpio23 = GPIO_MODE_GPIO,	/* LCD_BK_OFF */
+	.gpio24 = GPIO_MODE_NATIVE,	/* GPIO24 */
+	.gpio25 = GPIO_MODE_NATIVE,	/* PCIE_REQ_WWAN# / TP89 */
+	.gpio26 = GPIO_MODE_NATIVE,	/* CLK_PCIE_REQ4# / TP59 */
+	.gpio27 = GPIO_MODE_GPIO,	/* MSATA_DTCT# */
+	.gpio28 = GPIO_MODE_GPIO,	/* PLL_ODVR_EN */
+	.gpio29 = GPIO_MODE_GPIO,	/* WLAN_AOAC_ON */
+	.gpio30 = GPIO_MODE_NATIVE,	/* SUS_PWR_ACK */
+	.gpio31 = GPIO_MODE_NATIVE,	/* AC_PRESENT */
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	/*
+	 * Note: Only gpio configured as "gpio" or "none" need to have the
+	 *       direction configured.
+	 */
+	.gpio0  = GPIO_DIR_OUTPUT,
+	.gpio1  = GPIO_DIR_INPUT,
+	.gpio2  = GPIO_DIR_INPUT,
+	.gpio3  = GPIO_DIR_INPUT,
+	.gpio4  = GPIO_DIR_INPUT,
+	.gpio5  = GPIO_DIR_OUTPUT,
+	.gpio6  = GPIO_DIR_INPUT,
+	.gpio7  = GPIO_DIR_INPUT,
+	.gpio8  = GPIO_DIR_INPUT,
+
+	.gpio12 = GPIO_DIR_OUTPUT,
+	.gpio13 = GPIO_DIR_OUTPUT,
+
+	.gpio15 = GPIO_DIR_INPUT,
+	.gpio16 = GPIO_DIR_OUTPUT,
+	.gpio17 = GPIO_DIR_OUTPUT,
+
+	.gpio19 = GPIO_DIR_OUTPUT,
+
+	.gpio21 = GPIO_DIR_OUTPUT,
+	.gpio22 = GPIO_DIR_INPUT,
+	.gpio23 = GPIO_DIR_OUTPUT,
+
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+	.gpio29 = GPIO_DIR_OUTPUT,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_level = {
+	/*
+	 * Note: Only gpio configured as "gpio" or "none" need to have the
+	 *       level set.
+	 */
+	.gpio0  = GPIO_LEVEL_HIGH,
+	.gpio1  = GPIO_LEVEL_LOW,
+	.gpio2  = GPIO_LEVEL_LOW,
+	.gpio3  = GPIO_LEVEL_LOW,
+	.gpio4  = GPIO_LEVEL_LOW,
+	.gpio5  = GPIO_LEVEL_HIGH,
+	.gpio6  = GPIO_LEVEL_LOW,
+	.gpio7  = GPIO_LEVEL_HIGH,
+	.gpio8  = GPIO_LEVEL_LOW,
+
+	.gpio12 = GPIO_LEVEL_LOW,
+	.gpio13 = GPIO_LEVEL_LOW,
+
+	.gpio15 = GPIO_LEVEL_LOW,
+	.gpio16 = GPIO_LEVEL_HIGH,
+	.gpio17 = GPIO_LEVEL_LOW,
+
+	.gpio19 = GPIO_LEVEL_LOW,
+
+	.gpio21 = GPIO_LEVEL_LOW,
+	.gpio22 = GPIO_LEVEL_LOW,
+	.gpio23 = GPIO_LEVEL_LOW,
+
+	.gpio27 = GPIO_LEVEL_LOW,
+	.gpio28 = GPIO_LEVEL_HIGH,
+	.gpio29 = GPIO_LEVEL_HIGH,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio1 = GPIO_INVERT,
+	.gpio6 = GPIO_INVERT,
+	.gpio8 = GPIO_INVERT,
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_NATIVE, /* PCI_CLKRUN# */
+	.gpio33 = GPIO_MODE_GPIO,   /* GPIO33 */
+	.gpio34 = GPIO_MODE_GPIO,   /* CCD_ON */
+	.gpio35 = GPIO_MODE_GPIO,   /* BT_ON */
+	.gpio36 = GPIO_MODE_NONE,   /* NOT USED */
+	.gpio37 = GPIO_MODE_NONE,   /* NOT USED */
+	.gpio38 = GPIO_MODE_NONE,   /* NOT USED */
+	.gpio39 = GPIO_MODE_NONE,   /* NOT USED */
+	.gpio40 = GPIO_MODE_GPIO,   /* USB_OC1# */
+	.gpio41 = GPIO_MODE_GPIO,   /* USB_OC2# */
+	.gpio42 = GPIO_MODE_NATIVE, /* USB_OC3# */
+	.gpio43 = GPIO_MODE_NATIVE, /* USB_OC4_AUO4# */
+	.gpio44 = GPIO_MODE_NATIVE, /* PCIE_CLKREQ_LAN# */
+	.gpio45 = GPIO_MODE_NATIVE, /* PCIECLKRQ6# / TP48 */
+	.gpio46 = GPIO_MODE_NATIVE, /* PCIECLKRQ7# / TP57 */
+	.gpio47 = GPIO_MODE_NATIVE, /* CLK_PEGA_REQ# */
+	.gpio48 = GPIO_MODE_GPIO,   /* DIS_BT_ON# */
+	.gpio49 = GPIO_MODE_GPIO,   /* GPIO49 */
+	.gpio50 = GPIO_MODE_NATIVE, /* PCI_REQ1# */
+	.gpio51 = GPIO_MODE_GPIO,   /* BBS_BIT1 */
+	.gpio52 = GPIO_MODE_NATIVE, /* PCI_REQ2# */
+	.gpio53 = GPIO_MODE_GPIO,   /* PWM_SELECT# / TP44 */
+	.gpio54 = GPIO_MODE_GPIO,   /* PCI_REQ3# */
+	.gpio55 = GPIO_MODE_NATIVE, /* PCI_GNT3# */
+	.gpio56 = GPIO_MODE_NATIVE, /* CLK_PEGB_REQ# / TP60 */
+	.gpio57 = GPIO_MODE_GPIO,   /* PCH_GPIO57 */
+	.gpio58 = GPIO_MODE_NATIVE, /* SMB_ME1_CLK */
+	.gpio59 = GPIO_MODE_GPIO,   /* USB_OC0_1# */
+	.gpio60 = GPIO_MODE_GPIO,   /* DRAMRST_CNTRL_PCH */
+	.gpio61 = GPIO_MODE_GPIO,   /* LPCPD# */
+	.gpio62 = GPIO_MODE_NATIVE, /* PCH_SUSCLK_L / TP54 */
+	.gpio63 = GPIO_MODE_NATIVE, /* TP51 */
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	/*
+	 * Note: Only gpio configured as "gpio" or "none" need to have the
+	 *       direction configured.
+	 */
+	.gpio33 = GPIO_DIR_OUTPUT,
+	.gpio34 = GPIO_DIR_OUTPUT,
+	.gpio35 = GPIO_DIR_OUTPUT,
+	.gpio36 = GPIO_DIR_INPUT,
+	.gpio37 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio40 = GPIO_DIR_INPUT,
+	.gpio41 = GPIO_DIR_INPUT,
+
+	.gpio48 = GPIO_DIR_OUTPUT,
+	.gpio49 = GPIO_DIR_INPUT,
+
+	.gpio51 = GPIO_DIR_OUTPUT,
+
+	.gpio53 = GPIO_DIR_OUTPUT,
+	.gpio54 = GPIO_DIR_INPUT,
+
+	.gpio57 = GPIO_DIR_INPUT,
+
+	.gpio59 = GPIO_DIR_INPUT,
+	.gpio60 = GPIO_DIR_OUTPUT,
+	.gpio61 = GPIO_DIR_OUTPUT,
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_level = {
+	/*
+	 * Note: Only gpio configured as "gpio" or "none" need to have the
+	 *       level set.
+	 */
+	.gpio33 = GPIO_LEVEL_LOW,
+	.gpio34 = GPIO_LEVEL_HIGH,
+	.gpio35 = GPIO_LEVEL_HIGH,
+	.gpio36 = GPIO_LEVEL_LOW,
+	.gpio37 = GPIO_LEVEL_LOW,
+	.gpio38 = GPIO_LEVEL_LOW,
+	.gpio39 = GPIO_LEVEL_LOW,
+	.gpio40 = GPIO_LEVEL_HIGH,
+	.gpio41 = GPIO_LEVEL_LOW,
+
+	.gpio48 = GPIO_LEVEL_LOW,
+	.gpio49 = GPIO_LEVEL_HIGH,
+
+	.gpio51 = GPIO_LEVEL_HIGH,
+
+	.gpio53 = GPIO_LEVEL_HIGH,
+	.gpio54 = GPIO_LEVEL_LOW,
+
+	.gpio57 = GPIO_LEVEL_LOW,
+
+	.gpio59 = GPIO_LEVEL_HIGH,
+	.gpio60 = GPIO_LEVEL_HIGH,
+	.gpio61 = GPIO_LEVEL_LOW,
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_GPIO,	/* CLK_FLEX0 / TP38 */
+	.gpio65 = GPIO_MODE_GPIO,	/* CLK_FLEX1 / TP45 */
+	.gpio66 = GPIO_MODE_GPIO,	/* CLK_FLEX2 / TP83 */
+	.gpio67 = GPIO_MODE_GPIO,	/* CLK_FLEX3 / TP82 */
+	.gpio68 = GPIO_MODE_GPIO,	/* WWAN_DTCT# */
+	.gpio69 = GPIO_MODE_GPIO,	/* GPIO69 */
+	.gpio70 = GPIO_MODE_GPIO,	/* WLAN_OFF# */
+	.gpio71 = GPIO_MODE_GPIO,	/* WWAN_OFF# */
+	.gpio72 = GPIO_MODE_GPIO,	/* PM_BATLOW# */
+	.gpio73 = GPIO_MODE_NATIVE,	/* PCIECLKRQ0# / TP39 */
+	.gpio74 = GPIO_MODE_NATIVE,	/* SML1ALERT#_R / TP56 */
+	.gpio75 = GPIO_MODE_NATIVE,	/* SMB_ME1_DAT */
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	/*
+	 * Note: Only gpio configured as "gpio" or "none" need to have the
+	 *       direction configured.
+	 */
+	.gpio64 = GPIO_DIR_OUTPUT,
+	.gpio65 = GPIO_DIR_OUTPUT,
+	.gpio66 = GPIO_DIR_OUTPUT,
+	.gpio67 = GPIO_DIR_INPUT,
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_OUTPUT,
+	.gpio70 = GPIO_DIR_OUTPUT,
+	.gpio71 = GPIO_DIR_OUTPUT,
+	.gpio72 = GPIO_DIR_OUTPUT,
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_level = {
+	/*
+	 * Note: Only gpio configured as "gpio" or "none" need to have the
+	 *       level set.
+	 */
+	.gpio64 = GPIO_LEVEL_HIGH,
+	.gpio65 = GPIO_LEVEL_LOW,
+	.gpio66 = GPIO_LEVEL_HIGH,
+	.gpio67 = GPIO_LEVEL_LOW,
+	.gpio68 = GPIO_LEVEL_HIGH,
+	.gpio69 = GPIO_LEVEL_LOW,
+	.gpio70 = GPIO_LEVEL_HIGH,
+	.gpio71 = GPIO_LEVEL_HIGH,
+	.gpio72 = GPIO_LEVEL_HIGH,
+};
+
+const struct pch_gpio_map stout_gpio_map = {
+	.set1 = {
+		.mode      = &pch_gpio_set1_mode,
+		.direction = &pch_gpio_set1_direction,
+		.level     = &pch_gpio_set1_level,
+		.invert    = &pch_gpio_set1_invert,
+	},
+	.set2 = {
+		.mode      = &pch_gpio_set2_mode,
+		.direction = &pch_gpio_set2_direction,
+		.level     = &pch_gpio_set2_level,
+	},
+	.set3 = {
+		.mode      = &pch_gpio_set3_mode,
+		.direction = &pch_gpio_set3_direction,
+		.level     = &pch_gpio_set3_level,
+	},
+};
+#endif
diff --git a/src/mainboard/google/stout/hda_verb.h b/src/mainboard/google/stout/hda_verb.h
new file mode 100644
index 0000000000..dc6009b9bb
--- /dev/null
+++ b/src/mainboard/google/stout/hda_verb.h
@@ -0,0 +1,139 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+static const u32 mainboard_cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0269,	// Codec Vendor / Device ID: Realtek
+	0x17aa21fe,	// Subsystem ID
+	0x0000000c,	// Number of jacks
+
+	/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x17aa21fe */
+	0x001720fe,
+	0x00172121,
+	0x001722aa,
+	0x00172317,
+
+	/* Pin Widget Verb Table */
+
+	/* Pin Complex (NID 0x12): 0x90a60930 DMIC */
+	0x01271c30,
+	0x01271d09,
+	0x01271ea6,
+	0x01271f90,
+
+	/* Pin Complex (NID 0x14): 0x90170110 SPEAKER-OUT (Port-D) */
+	0x01471c10,
+	0x01471d01,
+	0x01471e17,
+	0x01471f90,
+
+	/* Pin Complex (NID 0x15): 0x0321101f HP-OUT (Port-A) */
+	0x01571c1f,
+	0x01571d10,
+	0x01571e21,
+	0x01571f03,
+
+	/* Pin Complex (NID 0x17): 0x411111f0 MONO-OUT (Port-H) */
+	0x01771cf0,
+	0x01771d11,
+	0x01771e11,
+	0x01771f41,
+
+	/* Pin Complex (NID 0x18): 0x03a11820 MIC1 (Port-B) */
+	0x01871c20,
+	0x01871d18,
+	0x01871ea1,
+	0x01871f03,
+
+	/* Pin Complex (NID 0x19): 0x411111f0 MIC2 (Port-F) */
+	0x01971cf0,
+	0x01971d11,
+	0x01971e11,
+	0x01971f41,
+
+	/* Pin Complex (NID 0x1a): 0x411111f0 LINE1 (Port-C) */
+	0x01a71cf0,
+	0x01a71d11,
+	0x01a71e11,
+	0x01a71f41,
+
+	/* Pin Complex (NID 0x1b): 0x411111f0 LINE2 (Port-E) */
+	0x01b71cf0,
+	0x01b71d11,
+	0x01b71e11,
+	0x01b71f41,
+
+	/* Pin Complex (NID 0x1d): 0x4016862d PC-BEEP */
+	0x01d71c2d,
+	0x01d71d86,
+	0x01d71e16,
+	0x01d71f40,
+
+	/* Pin Complex (NID 0x1e): 0x411111f0 S/PDIF-OUT */
+	0x01e71cf0,
+	0x01e71d11,
+	0x01e71e11,
+	0x01e71f41,
+
+	/* Stout MIC detect setup */
+	0x02050018,
+	0x02045184,
+	0x02050008,
+	0x02040300,
+
+	/* coreboot specific header */
+	0x80862806,	// Codec Vendor / Device ID: Intel PantherPoint HDMI
+	0x80860101,	// Subsystem ID
+	0x00000004,	// Number of jacks
+
+	/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */
+	0x30172001,
+	0x30172101,
+	0x30172286,
+	0x30172380,
+
+	/* Pin Complex (NID 0x05) Digital Out at Int HDMI */
+	0x30571c10,
+	0x30571d00,
+	0x30571e56,
+	0x30571f18,
+
+	/* Pin Complex (NID 0x06) Not Connected */
+	0x30671c20,
+	0x30671d00,
+	0x30671e56,
+	0x30671f58,
+
+	/* Pin Complex (NID 0x07) Not Connected */
+	0x30771c30,
+	0x30771d00,
+	0x30771e56,
+	0x30771f58
+};
+
+static const u32 mainboard_pc_beep_verbs[] = {
+	0x00170500,	/* power up everything (codec, dac, adc, mixers)  */
+	0x01470740,	/* enable speaker out */
+	0x01470c02,	/* set speaker EAPD pin */
+	0x0143b01f,	/* unmute speaker */
+	0x00c37100,	/* unmute mixer nid 0xc input 1 */
+	0x00b37410,	/* unmute mixer nid 0xb beep input and set volume */
+};
+static const u32 mainboard_pc_beep_verbs_size =
+	sizeof(mainboard_pc_beep_verbs) / sizeof(mainboard_pc_beep_verbs[0]);
diff --git a/src/mainboard/google/stout/i915.c b/src/mainboard/google/stout/i915.c
new file mode 100644
index 0000000000..309d18c35f
--- /dev/null
+++ b/src/mainboard/google/stout/i915.c
@@ -0,0 +1,283 @@
+#include <types.h>
+#include <string.h>
+#include <device/device.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#include <delay.h>
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL)&&CONFIG_PCI_OPTION_ROM_RUN_YABEL
+#include <x86emu/x86emu.h>
+#endif
+#include <pc80/mc146818rtc.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <arch/coreboot_tables.h>
+#include "hda_verb.h"
+#include "onboard.h"
+#include "ec.h"
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <smbios.h>
+#include <device/pci.h>
+#include <ec/google/chromeec/ec.h>
+#include <cbfs_core.h>
+
+#include <cpu/x86/tsc.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/amd/mtrr.h>
+#include <cpu/x86/msr.h>
+#include "i915_reg.h"
+
+enum {
+	vmsg = 1, vio = 2, vspin = 4,
+};
+
+static int verbose = 0; //vmsg ;
+
+static unsigned int *mmio;
+static unsigned int graphics;
+static unsigned short addrport;
+static unsigned short dataport;
+static unsigned int physbase;
+extern int oprom_is_loaded;
+
+#define READ32(addr) io_i915_READ32(addr)
+#define WRITE32(val, addr) io_i915_WRITE32(val, addr)
+
+static unsigned long io_i915_READ32(unsigned long addr)
+{
+       unsigned long val;
+       outl(addr, addrport);
+       val = inl(dataport);
+       return val;
+}
+
+static void io_i915_WRITE32(unsigned long val, unsigned long addr)
+{
+       outl(addr, addrport);
+       outl(val, dataport);
+}
+
+
+/*
+2560
+4 words per
+4 *p
+10240
+4k bytes per page
+4096/p
+2.50
+1700 lines
+1700 * p
+4250.00
+PTEs
+*/
+static void
+setgtt(int start, int end, unsigned long base, int inc)
+{
+        int i;
+
+	for(i = start; i < end; i++){
+                u32 word = base + i*inc;
+                WRITE32(word|1,(i*4)|1);
+        }
+}
+
+static char *regname(unsigned long addr)
+{
+	static char name[16];
+	sprintf(name, "0x%lx", addr);
+	return name;
+}
+
+static unsigned long tickspermicrosecond = 1795;
+static unsigned long long globalstart;
+
+static unsigned long
+microseconds(unsigned long long start, unsigned long long end)
+{
+	unsigned long ret;
+	ret = ((end - start)/tickspermicrosecond);
+	return ret;
+}
+
+static unsigned long globalmicroseconds(void)
+{
+	return microseconds(globalstart, rdtscll());
+}
+
+/* One-letter commands for code not mean to be ready for humans.
+ * The code was generated by a set of programs/scripts.
+ * M print out a kernel message
+ * R read a register. We do these mainly to ensure that if hardware wanted
+ * the register read, it was read; also, in debug, we can see what was expected
+ * and what was found. This has proven *very* useful to get this debugged.
+ * The udelay, if non-zero, will make sure there is a
+ * udelay() call with the value.
+ * The count is from the kernel and tells us how many times this read was done.
+ * Also useful for debugging and the state
+ * machine uses the info to drive a poll.
+ * W Write a register
+ * V set verbosity. It's a bit mask.
+ *   0 -> nothing
+ *   1 -> print kernel messages
+ *   2 -> print IO ops
+ *   4 -> print the number of times we spin on a register in a poll
+ *   8 -> restore whatever the previous verbosity level was
+ *   		(only one deep stack)
+ *
+ * Again, this is not really meant for human consumption. There is not a poll
+ * operator as such because, sometimes, there is a read/write/read where the
+ * second read is a poll, and this chipset is so touchy I'm reluctant to move
+ * things around and/or delete too many reads.
+ */
+#define M 1
+#define R 2
+#define W 3
+#define V 4
+#define I 8
+
+struct iodef {
+	unsigned char op;
+	unsigned int count;
+	const char *msg;
+	unsigned long addr;
+	unsigned long data;
+	unsigned long udelay;
+} iodefs[] = {
+#include "i915io.c"
+};
+
+static int i915_init_done = 0;
+
+int vbe_mode_info_valid(void);
+int vbe_mode_info_valid(void)
+{
+	return i915_init_done;
+}
+
+void fill_lb_framebuffer(struct lb_framebuffer *framebuffer);
+void fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
+{
+	printk(BIOS_SPEW, "fill_lb_framebuffer: graphics is %p\n", (void *)graphics);
+	framebuffer->physical_address = graphics;
+	framebuffer->x_resolution = 2560;
+	framebuffer->y_resolution = 1700;
+	framebuffer->bytes_per_line = 10240;
+	framebuffer->bits_per_pixel = 32;
+	framebuffer->red_mask_pos = 16;
+	framebuffer->red_mask_size = 8;
+	framebuffer->green_mask_pos = 8;
+	framebuffer->green_mask_size = 8;
+	framebuffer->blue_mask_pos = 0;
+	framebuffer->blue_mask_size = 8;
+	framebuffer->reserved_mask_pos = 0;
+	framebuffer->reserved_mask_size = 0;
+
+}
+
+int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio,
+	unsigned int gfx);
+
+int i915lightup(unsigned int pphysbase,
+	unsigned int piobase,
+	unsigned int pmmio,
+	unsigned int pgfx)
+{
+	int i, prev = 0;
+	struct iodef *id, *lastidread = 0;
+	unsigned long u, t;
+	static unsigned long times[4096];
+	mmio = (void *)pmmio;
+	addrport = piobase;
+	dataport = addrport + 4;
+	physbase = pphysbase;
+	graphics = pgfx;
+	printk(BIOS_SPEW,
+		"i915lightup: graphics %p mmio %p"
+		"addrport %04x physbase %08x\n",
+			(void *)graphics, mmio, addrport, physbase);
+	globalstart = rdtscll();
+
+	/* state machine! */
+	for(i = 0, id = iodefs; i < ARRAY_SIZE(iodefs); i++, id++){
+		switch(id->op){
+		case M:
+			if (verbose & vmsg) printk(BIOS_SPEW, "%ld: %s\n",
+				globalmicroseconds(), id->msg);
+			break;
+		case R:
+			u = READ32(id->addr);
+			if (verbose & vio)printk(BIOS_SPEW, "%s: Got %08lx, expect %08lx\n",
+				regname(id->addr), u, id->data);
+			/* we're looking for something. */
+			if (lastidread->addr == id->addr){
+				/* they're going to be polling.
+				 * just do it 1000 times
+				 */
+				for(t = 0; t < 1000 && id->data != u; t++){
+					u = READ32(id->addr);
+				}
+				if (verbose & vspin) printk(BIOS_SPEW,
+						"%s: # loops %ld got %08lx want %08lx\n",
+						regname(id->addr),
+						t, u, id->data);
+			}
+			lastidread = id;
+			break;
+		case W:
+			if (verbose & vio)printk(BIOS_SPEW, "%s: outl %08lx\n", regname(id->addr),
+									id->data);
+			WRITE32(id->data, id->addr);
+			if (id->addr == PCH_PP_CONTROL){
+				switch(id->data & 0xf){
+					case 8: break;
+					case 7: break;
+					default: udelay(100000);
+				}
+			}
+			break;
+		case V:
+			if (id->count < 8){
+				prev = verbose;
+				verbose = id->count;
+			} else {
+				verbose = prev;
+			}
+			break;
+		case I:
+			break;
+		default:
+			printk(BIOS_SPEW, "BAD TABLE, opcode %d @ %d\n", id->op, i);
+			return -1;
+		}
+		if (id->udelay)
+			udelay(id->udelay);
+		times[i] = globalmicroseconds();
+	}
+	/* optional, we don't even want to take timestamp overhead
+	 * if we can avoid it. */
+	if (0)
+	for(i = 0, id = iodefs; i < ARRAY_SIZE(iodefs); i++, id++){
+		switch(id->op){
+		case R:
+			printk(BIOS_SPEW, "%ld: R %08lx\n", times[i], id->addr);
+			break;
+		case W:
+			printk(BIOS_SPEW, "%ld: W %08lx %08lx\n", times[i],
+				id->addr, id->data);
+			break;
+		}
+	}
+
+	setgtt(0, 4520, physbase, 4096);
+	printk(BIOS_SPEW, "memset %p to 0 for %d bytes\n",
+				(void *)graphics, 4520*4096);
+	memset((void *)graphics, 0, 4520*4096);
+	printk(BIOS_SPEW, "%ld microseconds\n", globalmicroseconds());
+	i915_init_done = 1;
+	oprom_is_loaded = 1;
+	return 0;
+}
diff --git a/src/mainboard/google/stout/i915_reg.h b/src/mainboard/google/stout/i915_reg.h
new file mode 100644
index 0000000000..11c198ae5b
--- /dev/null
+++ b/src/mainboard/google/stout/i915_reg.h
@@ -0,0 +1,3878 @@
+/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _I915_REG_H_
+#define _I915_REG_H_
+
+#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
+
+/*
+ * The Bridge device's PCI config space has information about the
+ * fb aperture size and the amount of pre-reserved memory.
+ * This is all handled in the intel-gtt.ko module. i915.ko only
+ * cares about the vga bit for the vga rbiter.
+ */
+#define INTEL_GMCH_CTRL		0x52
+#define INTEL_GMCH_VGA_DISABLE  (1 << 1)
+
+/* PCI config space */
+
+#define HPLLCC	0xc0 /* 855 only */
+#define   GC_CLOCK_CONTROL_MASK		(0xf << 0)
+#define   GC_CLOCK_133_200		(0 << 0)
+#define   GC_CLOCK_100_200		(1 << 0)
+#define   GC_CLOCK_100_133		(2 << 0)
+#define   GC_CLOCK_166_250		(3 << 0)
+#define GCFGC2	0xda
+#define GCFGC	0xf0 /* 915+ only */
+#define   GC_LOW_FREQUENCY_ENABLE	(1 << 7)
+#define   GC_DISPLAY_CLOCK_190_200_MHZ	(0 << 4)
+#define   GC_DISPLAY_CLOCK_333_MHZ	(4 << 4)
+#define   GC_DISPLAY_CLOCK_MASK		(7 << 4)
+#define   GM45_GC_RENDER_CLOCK_MASK	(0xf << 0)
+#define   GM45_GC_RENDER_CLOCK_266_MHZ	(8 << 0)
+#define   GM45_GC_RENDER_CLOCK_320_MHZ	(9 << 0)
+#define   GM45_GC_RENDER_CLOCK_400_MHZ	(0xb << 0)
+#define   GM45_GC_RENDER_CLOCK_533_MHZ	(0xc << 0)
+#define   I965_GC_RENDER_CLOCK_MASK	(0xf << 0)
+#define   I965_GC_RENDER_CLOCK_267_MHZ	(2 << 0)
+#define   I965_GC_RENDER_CLOCK_333_MHZ	(3 << 0)
+#define   I965_GC_RENDER_CLOCK_444_MHZ	(4 << 0)
+#define   I965_GC_RENDER_CLOCK_533_MHZ	(5 << 0)
+#define   I945_GC_RENDER_CLOCK_MASK	(7 << 0)
+#define   I945_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
+#define   I945_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
+#define   I945_GC_RENDER_CLOCK_250_MHZ	(3 << 0)
+#define   I945_GC_RENDER_CLOCK_400_MHZ	(5 << 0)
+#define   I915_GC_RENDER_CLOCK_MASK	(7 << 0)
+#define   I915_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
+#define   I915_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
+#define   I915_GC_RENDER_CLOCK_333_MHZ	(4 << 0)
+#define LBB	0xf4
+
+/* Graphics reset regs */
+#define I965_GDRST 0xc0 /* PCI config register */
+#define ILK_GDSR 0x2ca4 /* MCHBAR offset */
+#define  GRDOM_FULL	(0<<2)
+#define  GRDOM_RENDER	(1<<2)
+#define  GRDOM_MEDIA	(3<<2)
+
+#define GEN6_MBCUNIT_SNPCR	0x900c /* for LLC config */
+#define   GEN6_MBC_SNPCR_SHIFT	21
+#define   GEN6_MBC_SNPCR_MASK	(3<<21)
+#define   GEN6_MBC_SNPCR_MAX	(0<<21)
+#define   GEN6_MBC_SNPCR_MED	(1<<21)
+#define   GEN6_MBC_SNPCR_LOW	(2<<21)
+#define   GEN6_MBC_SNPCR_MIN	(3<<21) /* only 1/16th of the cache is shared */
+
+#define GEN6_MBCTL		0x0907c
+#define   GEN6_MBCTL_ENABLE_BOOT_FETCH	(1 << 4)
+#define   GEN6_MBCTL_CTX_FETCH_NEEDED	(1 << 3)
+#define   GEN6_MBCTL_BME_UPDATE_ENABLE	(1 << 2)
+#define   GEN6_MBCTL_MAE_UPDATE_ENABLE	(1 << 1)
+#define   GEN6_MBCTL_BOOT_FETCH_MECH	(1 << 0)
+
+#define GEN6_GDRST	0x941c
+#define  GEN6_GRDOM_FULL		(1 << 0)
+#define  GEN6_GRDOM_RENDER		(1 << 1)
+#define  GEN6_GRDOM_MEDIA		(1 << 2)
+#define  GEN6_GRDOM_BLT			(1 << 3)
+
+/* PPGTT stuff */
+#define GEN6_GTT_ADDR_ENCODE(addr)	((addr) | (((addr) >> 28) & 0xff0))
+
+#define GEN6_PDE_VALID			(1 << 0)
+#define GEN6_PDE_LARGE_PAGE		(2 << 0) /* use 32kb pages */
+/* gen6+ has bit 11-4 for physical addr bit 39-32 */
+#define GEN6_PDE_ADDR_ENCODE(addr)	GEN6_GTT_ADDR_ENCODE(addr)
+
+#define GEN6_PTE_VALID			(1 << 0)
+#define GEN6_PTE_UNCACHED		(1 << 1)
+#define GEN6_PTE_CACHE_LLC		(2 << 1)
+#define GEN6_PTE_CACHE_LLC_MLC		(3 << 1)
+#define GEN6_PTE_CACHE_BITS		(3 << 1)
+#define GEN6_PTE_GFDT			(1 << 3)
+#define GEN6_PTE_ADDR_ENCODE(addr)	GEN6_GTT_ADDR_ENCODE(addr)
+
+#define RING_PP_DIR_BASE(ring)		((ring)->mmio_base+0x228)
+#define RING_PP_DIR_BASE_READ(ring)	((ring)->mmio_base+0x518)
+#define RING_PP_DIR_DCLV(ring)		((ring)->mmio_base+0x220)
+#define   PP_DIR_DCLV_2G		0xffffffff
+
+#define GAM_ECOCHK			0x4090
+#define   ECOCHK_SNB_BIT		(1<<10)
+#define   ECOCHK_PPGTT_CACHE64B		(0x3<<3)
+#define   ECOCHK_PPGTT_CACHE4B		(0x0<<3)
+
+/* VGA stuff */
+
+#define VGA_ST01_MDA 0x3ba
+#define VGA_ST01_CGA 0x3da
+
+#define VGA_MSR_WRITE 0x3c2
+#define VGA_MSR_READ 0x3cc
+#define   VGA_MSR_MEM_EN (1<<1)
+#define   VGA_MSR_CGA_MODE (1<<0)
+
+#define VGA_SR_INDEX 0x3c4
+#define VGA_SR_DATA 0x3c5
+
+#define VGA_AR_INDEX 0x3c0
+#define   VGA_AR_VID_EN (1<<5)
+#define VGA_AR_DATA_WRITE 0x3c0
+#define VGA_AR_DATA_READ 0x3c1
+
+#define VGA_GR_INDEX 0x3ce
+#define VGA_GR_DATA 0x3cf
+/* GR05 */
+#define   VGA_GR_MEM_READ_MODE_SHIFT 3
+#define     VGA_GR_MEM_READ_MODE_PLANE 1
+/* GR06 */
+#define   VGA_GR_MEM_MODE_MASK 0xc
+#define   VGA_GR_MEM_MODE_SHIFT 2
+#define   VGA_GR_MEM_A0000_AFFFF 0
+#define   VGA_GR_MEM_A0000_BFFFF 1
+#define   VGA_GR_MEM_B0000_B7FFF 2
+#define   VGA_GR_MEM_B0000_BFFFF 3
+
+#define VGA_DACMASK 0x3c6
+#define VGA_DACRX 0x3c7
+#define VGA_DACWX 0x3c8
+#define VGA_DACDATA 0x3c9
+
+#define VGA_CR_INDEX_MDA 0x3b4
+#define VGA_CR_DATA_MDA 0x3b5
+#define VGA_CR_INDEX_CGA 0x3d4
+#define VGA_CR_DATA_CGA 0x3d5
+
+/*
+ * Memory interface instructions used by the kernel
+ */
+#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
+
+#define MI_NOOP			MI_INSTR(0, 0)
+#define MI_USER_INTERRUPT	MI_INSTR(0x02, 0)
+#define MI_WAIT_FOR_EVENT       MI_INSTR(0x03, 0)
+#define   MI_WAIT_FOR_OVERLAY_FLIP	(1<<16)
+#define   MI_WAIT_FOR_PLANE_B_FLIP      (1<<6)
+#define   MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)
+#define   MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
+#define MI_FLUSH		MI_INSTR(0x04, 0)
+#define   MI_READ_FLUSH		(1 << 0)
+#define   MI_EXE_FLUSH		(1 << 1)
+#define   MI_NO_WRITE_FLUSH	(1 << 2)
+#define   MI_SCENE_COUNT	(1 << 3) /* just increment scene count */
+#define   MI_END_SCENE		(1 << 4) /* flush binner and incr scene count */
+#define   MI_INVALIDATE_ISP	(1 << 5) /* invalidate indirect state pointers */
+#define MI_BATCH_BUFFER_END	MI_INSTR(0x0a, 0)
+#define MI_SUSPEND_FLUSH	MI_INSTR(0x0b, 0)
+#define   MI_SUSPEND_FLUSH_EN	(1<<0)
+#define MI_REPORT_HEAD		MI_INSTR(0x07, 0)
+#define MI_OVERLAY_FLIP		MI_INSTR(0x11, 0)
+#define   MI_OVERLAY_CONTINUE	(0x0<<21)
+#define   MI_OVERLAY_ON		(0x1<<21)
+#define   MI_OVERLAY_OFF	(0x2<<21)
+#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
+#define MI_DISPLAY_FLIP		MI_INSTR(0x14, 2)
+#define MI_DISPLAY_FLIP_I915	MI_INSTR(0x14, 1)
+#define   MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
+#define MI_SET_CONTEXT		MI_INSTR(0x18, 0)
+#define   MI_MM_SPACE_GTT		(1<<8)
+#define   MI_MM_SPACE_PHYSICAL		(0<<8)
+#define   MI_SAVE_EXT_STATE_EN		(1<<3)
+#define   MI_RESTORE_EXT_STATE_EN	(1<<2)
+#define   MI_FORCE_RESTORE		(1<<1)
+#define   MI_RESTORE_INHIBIT		(1<<0)
+#define MI_STORE_DWORD_IMM	MI_INSTR(0x20, 1)
+#define   MI_MEM_VIRTUAL	(1 << 22) /* 965+ only */
+#define MI_STORE_DWORD_INDEX	MI_INSTR(0x21, 1)
+#define   MI_STORE_DWORD_INDEX_SHIFT 2
+/* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
+ * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
+ *   simply ignores the register load under certain conditions.
+ * - One can actually load arbitrary many arbitrary registers: Simply issue x
+ *   address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
+ */
+#define MI_LOAD_REGISTER_IMM(x)	MI_INSTR(0x22, 2*x-1)
+#define MI_FLUSH_DW		MI_INSTR(0x26, 1) /* for GEN6 */
+#define   MI_INVALIDATE_TLB	(1<<18)
+#define   MI_INVALIDATE_BSD	(1<<7)
+#define MI_BATCH_BUFFER		MI_INSTR(0x30, 1)
+#define   MI_BATCH_NON_SECURE	(1)
+#define   MI_BATCH_NON_SECURE_I965 (1<<8)
+#define MI_BATCH_BUFFER_START	MI_INSTR(0x31, 0)
+#define MI_SEMAPHORE_MBOX	MI_INSTR(0x16, 1) /* gen6+ */
+#define  MI_SEMAPHORE_GLOBAL_GTT    (1<<22)
+#define  MI_SEMAPHORE_UPDATE	    (1<<21)
+#define  MI_SEMAPHORE_COMPARE	    (1<<20)
+#define  MI_SEMAPHORE_REGISTER	    (1<<18)
+#define  MI_SEMAPHORE_SYNC_RV	    (2<<16)
+#define  MI_SEMAPHORE_SYNC_RB	    (0<<16)
+#define  MI_SEMAPHORE_SYNC_VR	    (0<<16)
+#define  MI_SEMAPHORE_SYNC_VB	    (2<<16)
+#define  MI_SEMAPHORE_SYNC_BR	    (2<<16)
+#define  MI_SEMAPHORE_SYNC_BV	    (0<<16)
+#define  MI_SEMAPHORE_SYNC_INVALID  (1<<0)
+/*
+ * 3D instructions used by the kernel
+ */
+#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
+
+#define GFX_OP_RASTER_RULES    ((0x3<<29)|(0x7<<24))
+#define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
+#define   SC_UPDATE_SCISSOR       (0x1<<1)
+#define   SC_ENABLE_MASK          (0x1<<0)
+#define   SC_ENABLE               (0x1<<0)
+#define GFX_OP_LOAD_INDIRECT   ((0x3<<29)|(0x1d<<24)|(0x7<<16))
+#define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
+#define   SCI_YMIN_MASK      (0xffff<<16)
+#define   SCI_XMIN_MASK      (0xffff<<0)
+#define   SCI_YMAX_MASK      (0xffff<<16)
+#define   SCI_XMAX_MASK      (0xffff<<0)
+#define GFX_OP_SCISSOR_ENABLE	 ((0x3<<29)|(0x1c<<24)|(0x10<<19))
+#define GFX_OP_SCISSOR_RECT	 ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
+#define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
+#define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
+#define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
+#define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
+#define GFX_OP_DESTBUFFER_INFO	 ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
+#define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
+#define GFX_OP_DRAWRECT_INFO_I965  ((0x7900<<16)|0x2)
+#define SRC_COPY_BLT_CMD                ((2<<29)|(0x43<<22)|4)
+#define XY_SRC_COPY_BLT_CMD		((2<<29)|(0x53<<22)|6)
+#define XY_MONO_SRC_COPY_IMM_BLT	((2<<29)|(0x71<<22)|5)
+#define XY_SRC_COPY_BLT_WRITE_ALPHA	(1<<21)
+#define XY_SRC_COPY_BLT_WRITE_RGB	(1<<20)
+#define   BLT_DEPTH_8			(0<<24)
+#define   BLT_DEPTH_16_565		(1<<24)
+#define   BLT_DEPTH_16_1555		(2<<24)
+#define   BLT_DEPTH_32			(3<<24)
+#define   BLT_ROP_GXCOPY		(0xcc<<16)
+#define XY_SRC_COPY_BLT_SRC_TILED	(1<<15) /* 965+ only */
+#define XY_SRC_COPY_BLT_DST_TILED	(1<<11) /* 965+ only */
+#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
+#define   ASYNC_FLIP                (1<<22)
+#define   DISPLAY_PLANE_A           (0<<20)
+#define   DISPLAY_PLANE_B           (1<<20)
+#define GFX_OP_PIPE_CONTROL(len)	((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
+#define   PIPE_CONTROL_CS_STALL				(1<<20)
+#define   PIPE_CONTROL_QW_WRITE				(1<<14)
+#define   PIPE_CONTROL_DEPTH_STALL			(1<<13)
+#define   PIPE_CONTROL_WRITE_FLUSH			(1<<12)
+#define   PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH	(1<<12) /* gen6+ */
+#define   PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE	(1<<11) /* MBZ on Ironlake */
+#define   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE		(1<<10) /* GM45+ only */
+#define   PIPE_CONTROL_INDIRECT_STATE_DISABLE		(1<<9)
+#define   PIPE_CONTROL_NOTIFY				(1<<8)
+#define   PIPE_CONTROL_VF_CACHE_INVALIDATE		(1<<4)
+#define   PIPE_CONTROL_CONST_CACHE_INVALIDATE		(1<<3)
+#define   PIPE_CONTROL_STATE_CACHE_INVALIDATE		(1<<2)
+#define   PIPE_CONTROL_STALL_AT_SCOREBOARD		(1<<1)
+#define   PIPE_CONTROL_DEPTH_CACHE_FLUSH		(1<<0)
+#define   PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
+
+
+/*
+ * Reset registers
+ */
+#define DEBUG_RESET_I830		0x6070
+#define  DEBUG_RESET_FULL		(1<<7)
+#define  DEBUG_RESET_RENDER		(1<<8)
+#define  DEBUG_RESET_DISPLAY		(1<<9)
+
+
+/*
+ * Fence registers
+ */
+#define FENCE_REG_830_0			0x2000
+#define FENCE_REG_945_8			0x3000
+#define   I830_FENCE_START_MASK		0x07f80000
+#define   I830_FENCE_TILING_Y_SHIFT	12
+#define   I830_FENCE_SIZE_BITS(size)	((ffs((size) >> 19) - 1) << 8)
+#define   I830_FENCE_PITCH_SHIFT	4
+#define   I830_FENCE_REG_VALID		(1<<0)
+#define   I915_FENCE_MAX_PITCH_VAL	4
+#define   I830_FENCE_MAX_PITCH_VAL	6
+#define   I830_FENCE_MAX_SIZE_VAL	(1<<8)
+
+#define   I915_FENCE_START_MASK		0x0ff00000
+#define   I915_FENCE_SIZE_BITS(size)	((ffs((size) >> 20) - 1) << 8)
+
+#define FENCE_REG_965_0			0x03000
+#define   I965_FENCE_PITCH_SHIFT	2
+#define   I965_FENCE_TILING_Y_SHIFT	1
+#define   I965_FENCE_REG_VALID		(1<<0)
+#define   I965_FENCE_MAX_PITCH_VAL	0x0400
+
+#define FENCE_REG_SANDYBRIDGE_0		0x100000
+#define   SANDYBRIDGE_FENCE_PITCH_SHIFT	32
+
+/* control register for cpu gtt access */
+#define TILECTL				0x101000
+#define   TILECTL_SWZCTL			(1 << 0)
+#define   TILECTL_TLB_PREFETCH_DIS	(1 << 2)
+#define   TILECTL_BACKSNOOP_DIS		(1 << 3)
+
+/*
+ * Instruction and interrupt control regs
+ */
+#define PGTBL_ER	0x02024
+#define RENDER_RING_BASE	0x02000
+#define BSD_RING_BASE		0x04000
+#define GEN6_BSD_RING_BASE	0x12000
+#define BLT_RING_BASE		0x22000
+#define RING_TAIL(base)		((base)+0x30)
+#define RING_HEAD(base)		((base)+0x34)
+#define RING_START(base)	((base)+0x38)
+#define RING_CTL(base)		((base)+0x3c)
+#define RING_SYNC_0(base)	((base)+0x40)
+#define RING_SYNC_1(base)	((base)+0x44)
+#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
+#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
+#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
+#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
+#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
+#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
+#define RING_MAX_IDLE(base)	((base)+0x54)
+#define RING_HWS_PGA(base)	((base)+0x80)
+#define RING_HWS_PGA_GEN6(base)	((base)+0x2080)
+#define ARB_MODE		0x04030
+#define   ARB_MODE_SWIZZLE_SNB	(1<<4)
+#define   ARB_MODE_SWIZZLE_IVB	(1<<5)
+#define   ARB_MODE_ENABLE(x)	GFX_MODE_ENABLE(x)
+#define   ARB_MODE_DISABLE(x)	GFX_MODE_DISABLE(x)
+#define RENDER_HWS_PGA_GEN7	(0x04080)
+#define RING_FAULT_REG(ring)	(0x4094 + 0x100*(ring)->id)
+#define DONE_REG		0x40b0
+#define BSD_HWS_PGA_GEN7	(0x04180)
+#define BLT_HWS_PGA_GEN7	(0x04280)
+#define RING_ACTHD(base)	((base)+0x74)
+#define RING_NOPID(base)	((base)+0x94)
+#define RING_IMR(base)		((base)+0xa8)
+#define   TAIL_ADDR		0x001FFFF8
+#define   HEAD_WRAP_COUNT	0xFFE00000
+#define   HEAD_WRAP_ONE		0x00200000
+#define   HEAD_ADDR		0x001FFFFC
+#define   RING_NR_PAGES		0x001FF000
+#define   RING_REPORT_MASK	0x00000006
+#define   RING_REPORT_64K	0x00000002
+#define   RING_REPORT_128K	0x00000004
+#define   RING_NO_REPORT	0x00000000
+#define   RING_VALID_MASK	0x00000001
+#define   RING_VALID		0x00000001
+#define   RING_INVALID		0x00000000
+#define   RING_WAIT_I8XX	(1<<0) /* gen2, PRBx_HEAD */
+#define   RING_WAIT		(1<<11) /* gen3+, PRBx_CTL */
+#define   RING_WAIT_SEMAPHORE	(1<<10) /* gen6+ */
+#define PRB0_TAIL	0x02030
+#define PRB0_HEAD	0x02034
+#define PRB0_START	0x02038
+#define PRB0_CTL	0x0203c
+#if 0
+#define PRB1_TAIL	0x02040 /* 915+ only */
+#define PRB1_HEAD	0x02044 /* 915+ only */
+#define PRB1_START	0x02048 /* 915+ only */
+#define PRB1_CTL	0x0204c /* 915+ only */
+#endif
+#define IPEIR_I965	0x02064
+#define IPEHR_I965	0x02068
+#define INSTDONE_I965	0x0206c
+#define RING_IPEIR(base)	((base)+0x64)
+#define RING_IPEHR(base)	((base)+0x68)
+#define RING_INSTDONE(base)	((base)+0x6c)
+#define RING_INSTPS(base)	((base)+0x70)
+#define RING_DMA_FADD(base)	((base)+0x78)
+#define RING_INSTPM(base)	((base)+0xc0)
+#define INSTPS		0x02070 /* 965+ only */
+#define INSTDONE1	0x0207c /* 965+ only */
+#define ACTHD_I965	0x02074
+#define HWS_PGA		0x02080
+#define HWS_ADDRESS_MASK	0xfffff000
+#define HWS_START_ADDRESS_SHIFT	4
+#define PWRCTXA		0x2088 /* 965GM+ only */
+#define   PWRCTX_EN	(1<<0)
+#define IPEIR		0x02088
+#define IPEHR		0x0208c
+#define INSTDONE	0x02090
+#define NOPID		0x02094
+#define HWSTAM		0x02098
+
+#define ERROR_GEN6	0x040a0
+
+/* GM45+ chicken bits -- debug workaround bits that may be required
+ * for various sorts of correct behavior.  The top 16 bits of each are
+ * the enables for writing to the corresponding low bit.
+ */
+#define _3D_CHICKEN	0x02084
+#define _3D_CHICKEN2	0x0208c
+/* Disables pipelining of read flushes past the SF-WIZ interface.
+ * Required on all Ironlake steppings according to the B-Spec, but the
+ * particular danger of not doing so is not specified.
+ */
+# define _3D_CHICKEN2_WM_READ_PIPELINED			(1 << 14)
+#define _3D_CHICKEN3	0x02090
+
+#define MI_MODE		0x0209c
+# define VS_TIMER_DISPATCH				(1 << 6)
+# define MI_FLUSH_ENABLE				(1 << 12)
+
+#define GFX_MODE	0x02520
+#define GFX_MODE_GEN7	0x0229c
+#define RING_MODE_GEN7(ring)	((ring)->mmio_base+0x29c)
+#define   GFX_RUN_LIST_ENABLE		(1<<15)
+#define   GFX_TLB_INVALIDATE_ALWAYS	(1<<13)
+#define   GFX_SURFACE_FAULT_ENABLE	(1<<12)
+#define   GFX_REPLAY_MODE		(1<<11)
+#define   GFX_PSMI_GRANULARITY		(1<<10)
+#define   GFX_PPGTT_ENABLE		(1<<9)
+
+#define GFX_MODE_ENABLE(bit) (((bit) << 16) | (bit))
+#define GFX_MODE_DISABLE(bit) (((bit) << 16) | (0))
+
+#define SCPD0		0x0209c /* 915+ only */
+#define IER		0x020a0
+#define IIR		0x020a4
+#define IMR		0x020a8
+#define ISR		0x020ac
+#define   I915_PIPE_CONTROL_NOTIFY_INTERRUPT		(1<<18)
+#define   I915_DISPLAY_PORT_INTERRUPT			(1<<17)
+#define   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT	(1<<15)
+#define   I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT	(1<<14) /* p-state */
+#define   I915_HWB_OOM_INTERRUPT			(1<<13)
+#define   I915_SYNC_STATUS_INTERRUPT			(1<<12)
+#define   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT	(1<<11)
+#define   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT	(1<<10)
+#define   I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT	(1<<9)
+#define   I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT	(1<<8)
+#define   I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT		(1<<7)
+#define   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT		(1<<6)
+#define   I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT		(1<<5)
+#define   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT		(1<<4)
+#define   I915_DEBUG_INTERRUPT				(1<<2)
+#define   I915_USER_INTERRUPT				(1<<1)
+#define   I915_ASLE_INTERRUPT				(1<<0)
+#define   I915_BSD_USER_INTERRUPT                      (1<<25)
+#define EIR		0x020b0
+#define EMR		0x020b4
+#define ESR		0x020b8
+#define   GM45_ERROR_PAGE_TABLE				(1<<5)
+#define   GM45_ERROR_MEM_PRIV				(1<<4)
+#define   I915_ERROR_PAGE_TABLE				(1<<4)
+#define   GM45_ERROR_CP_PRIV				(1<<3)
+#define   I915_ERROR_MEMORY_REFRESH			(1<<1)
+#define   I915_ERROR_INSTRUCTION			(1<<0)
+#define INSTPM	        0x020c0
+#define   INSTPM_SELF_EN (1<<12) /* 915GM only */
+#define   INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts
+					will not assert AGPBUSY# and will only
+					be delivered when out of C3. */
+#define   INSTPM_FORCE_ORDERING				(1<<7) /* GEN6+ */
+#define ACTHD	        0x020c8
+#define FW_BLC		0x020d8
+#define FW_BLC2		0x020dc
+#define FW_BLC_SELF	0x020e0 /* 915+ only */
+#define   FW_BLC_SELF_EN_MASK      (1<<31)
+#define   FW_BLC_SELF_FIFO_MASK    (1<<16) /* 945 only */
+#define   FW_BLC_SELF_EN           (1<<15) /* 945 only */
+#define MM_BURST_LENGTH     0x00700000
+#define MM_FIFO_WATERMARK   0x0001F000
+#define LM_BURST_LENGTH     0x00000700
+#define LM_FIFO_WATERMARK   0x0000001F
+#define MI_ARB_STATE	0x020e4 /* 915+ only */
+#define   MI_ARB_MASK_SHIFT	  16	/* shift for enable bits */
+
+/* Make render/texture TLB fetches lower priorty than associated data
+ *   fetches. This is not turned on by default
+ */
+#define   MI_ARB_RENDER_TLB_LOW_PRIORITY	(1 << 15)
+
+/* Isoch request wait on GTT enable (Display A/B/C streams).
+ * Make isoch requests stall on the TLB update. May cause
+ * display underruns (test mode only)
+ */
+#define   MI_ARB_ISOCH_WAIT_GTT			(1 << 14)
+
+/* Block grant count for isoch requests when block count is
+ * set to a finite value.
+ */
+#define   MI_ARB_BLOCK_GRANT_MASK		(3 << 12)
+#define   MI_ARB_BLOCK_GRANT_8			(0 << 12)	/* for 3 display planes */
+#define   MI_ARB_BLOCK_GRANT_4			(1 << 12)	/* for 2 display planes */
+#define   MI_ARB_BLOCK_GRANT_2			(2 << 12)	/* for 1 display plane */
+#define   MI_ARB_BLOCK_GRANT_0			(3 << 12)	/* don't use */
+
+/* Enable render writes to complete in C2/C3/C4 power states.
+ * If this isn't enabled, render writes are prevented in low
+ * power states. That seems bad to me.
+ */
+#define   MI_ARB_C3_LP_WRITE_ENABLE		(1 << 11)
+
+/* This acknowledges an async flip immediately instead
+ * of waiting for 2TLB fetches.
+ */
+#define   MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE	(1 << 10)
+
+/* Enables non-sequential data reads through arbiter
+ */
+#define   MI_ARB_DUAL_DATA_PHASE_DISABLE	(1 << 9)
+
+/* Disable FSB snooping of cacheable write cycles from binner/render
+ * command stream
+ */
+#define   MI_ARB_CACHE_SNOOP_DISABLE		(1 << 8)
+
+/* Arbiter time slice for non-isoch streams */
+#define   MI_ARB_TIME_SLICE_MASK		(7 << 5)
+#define   MI_ARB_TIME_SLICE_1			(0 << 5)
+#define   MI_ARB_TIME_SLICE_2			(1 << 5)
+#define   MI_ARB_TIME_SLICE_4			(2 << 5)
+#define   MI_ARB_TIME_SLICE_6			(3 << 5)
+#define   MI_ARB_TIME_SLICE_8			(4 << 5)
+#define   MI_ARB_TIME_SLICE_10			(5 << 5)
+#define   MI_ARB_TIME_SLICE_14			(6 << 5)
+#define   MI_ARB_TIME_SLICE_16			(7 << 5)
+
+/* Low priority grace period page size */
+#define   MI_ARB_LOW_PRIORITY_GRACE_4KB		(0 << 4)	/* default */
+#define   MI_ARB_LOW_PRIORITY_GRACE_8KB		(1 << 4)
+
+/* Disable display A/B trickle feed */
+#define   MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE	(1 << 2)
+
+/* Set display plane priority */
+#define   MI_ARB_DISPLAY_PRIORITY_A_B		(0 << 0)	/* display A > display B */
+#define   MI_ARB_DISPLAY_PRIORITY_B_A		(1 << 0)	/* display B > display A */
+
+#define CACHE_MODE_0	0x02120 /* 915+ only */
+#define   CM0_MASK_SHIFT          16
+#define   CM0_IZ_OPT_DISABLE      (1<<6)
+#define   CM0_ZR_OPT_DISABLE      (1<<5)
+#define	  CM0_STC_EVICT_DISABLE_LRA_SNB	(1<<5)
+#define   CM0_DEPTH_EVICT_DISABLE (1<<4)
+#define   CM0_COLOR_EVICT_DISABLE (1<<3)
+#define   CM0_DEPTH_WRITE_DISABLE (1<<1)
+#define   CM0_RC_OP_FLUSH_DISABLE (1<<0)
+#define BB_ADDR		0x02140 /* 8 bytes */
+#define GFX_FLSH_CNTL	0x02170 /* 915+ only */
+#define ECOSKPD		0x021d0
+#define   ECO_GATING_CX_ONLY	(1<<3)
+#define   ECO_FLIP_DONE		(1<<0)
+
+/* GEN6 interrupt control */
+#define GEN6_RENDER_HWSTAM	0x2098
+#define GEN6_RENDER_IMR		0x20a8
+#define   GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT		(1 << 8)
+#define   GEN6_RENDER_PPGTT_PAGE_FAULT			(1 << 7)
+#define   GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED		(1 << 6)
+#define   GEN6_RENDER_L3_PARITY_ERROR			(1 << 5)
+#define   GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT	(1 << 4)
+#define   GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR	(1 << 3)
+#define   GEN6_RENDER_SYNC_STATUS			(1 << 2)
+#define   GEN6_RENDER_DEBUG_INTERRUPT			(1 << 1)
+#define   GEN6_RENDER_USER_INTERRUPT			(1 << 0)
+
+#define GEN6_BLITTER_HWSTAM	0x22098
+#define GEN6_BLITTER_IMR	0x220a8
+#define   GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT	(1 << 26)
+#define   GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR	(1 << 25)
+#define   GEN6_BLITTER_SYNC_STATUS			(1 << 24)
+#define   GEN6_BLITTER_USER_INTERRUPT			(1 << 22)
+
+#define GEN6_BLITTER_ECOSKPD	0x221d0
+#define   GEN6_BLITTER_LOCK_SHIFT			16
+#define   GEN6_BLITTER_FBC_NOTIFY			(1<<3)
+
+#define GEN6_BSD_SLEEP_PSMI_CONTROL	0x12050
+#define   GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK	(1 << 16)
+#define   GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE		(1 << 0)
+#define   GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE		0
+#define   GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR			(1 << 3)
+
+#define GEN6_BSD_HWSTAM			0x12098
+#define GEN6_BSD_IMR			0x120a8
+#define   GEN6_BSD_USER_INTERRUPT	(1 << 12)
+
+#define GEN6_BSD_RNCID			0x12198
+
+/*
+ * Framebuffer compression (915+ only)
+ */
+
+#define FBC_CFB_BASE		0x03200 /* 4k page aligned */
+#define FBC_LL_BASE		0x03204 /* 4k page aligned */
+#define FBC_CONTROL		0x03208
+#define   FBC_CTL_EN		(1<<31)
+#define   FBC_CTL_PERIODIC	(1<<30)
+#define   FBC_CTL_INTERVAL_SHIFT (16)
+#define   FBC_CTL_UNCOMPRESSIBLE (1<<14)
+#define   FBC_CTL_C3_IDLE	(1<<13)
+#define   FBC_CTL_STRIDE_SHIFT	(5)
+#define   FBC_CTL_FENCENO	(1<<0)
+#define FBC_COMMAND		0x0320c
+#define   FBC_CMD_COMPRESS	(1<<0)
+#define FBC_STATUS		0x03210
+#define   FBC_STAT_COMPRESSING	(1<<31)
+#define   FBC_STAT_COMPRESSED	(1<<30)
+#define   FBC_STAT_MODIFIED	(1<<29)
+#define   FBC_STAT_CURRENT_LINE	(1<<0)
+#define FBC_CONTROL2		0x03214
+#define   FBC_CTL_FENCE_DBL	(0<<4)
+#define   FBC_CTL_IDLE_IMM	(0<<2)
+#define   FBC_CTL_IDLE_FULL	(1<<2)
+#define   FBC_CTL_IDLE_LINE	(2<<2)
+#define   FBC_CTL_IDLE_DEBUG	(3<<2)
+#define   FBC_CTL_CPU_FENCE	(1<<1)
+#define   FBC_CTL_PLANEA	(0<<0)
+#define   FBC_CTL_PLANEB	(1<<0)
+#define FBC_FENCE_OFF		0x0321b
+#define FBC_TAG			0x03300
+
+#define FBC_LL_SIZE		(1536)
+
+/* Framebuffer compression for GM45+ */
+#define DPFC_CB_BASE		0x3200
+#define DPFC_CONTROL		0x3208
+#define   DPFC_CTL_EN		(1<<31)
+#define   DPFC_CTL_PLANEA	(0<<30)
+#define   DPFC_CTL_PLANEB	(1<<30)
+#define   DPFC_CTL_FENCE_EN	(1<<29)
+#define   DPFC_CTL_PERSISTENT_MODE	(1<<25)
+#define   DPFC_SR_EN		(1<<10)
+#define   DPFC_CTL_LIMIT_1X	(0<<6)
+#define   DPFC_CTL_LIMIT_2X	(1<<6)
+#define   DPFC_CTL_LIMIT_4X	(2<<6)
+#define DPFC_RECOMP_CTL		0x320c
+#define   DPFC_RECOMP_STALL_EN	(1<<27)
+#define   DPFC_RECOMP_STALL_WM_SHIFT (16)
+#define   DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
+#define   DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
+#define   DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
+#define DPFC_STATUS		0x3210
+#define   DPFC_INVAL_SEG_SHIFT  (16)
+#define   DPFC_INVAL_SEG_MASK	(0x07ff0000)
+#define   DPFC_COMP_SEG_SHIFT	(0)
+#define   DPFC_COMP_SEG_MASK	(0x000003ff)
+#define DPFC_STATUS2		0x3214
+#define DPFC_FENCE_YOFF		0x3218
+#define DPFC_CHICKEN		0x3224
+#define   DPFC_HT_MODIFY	(1<<31)
+
+/* Framebuffer compression for Ironlake */
+#define ILK_DPFC_CB_BASE	0x43200
+#define ILK_DPFC_CONTROL	0x43208
+/* The bit 28-8 is reserved */
+#define   DPFC_RESERVED		(0x1FFFFF00)
+#define ILK_DPFC_RECOMP_CTL	0x4320c
+#define ILK_DPFC_STATUS		0x43210
+#define ILK_DPFC_FENCE_YOFF	0x43218
+#define ILK_DPFC_CHICKEN	0x43224
+#define ILK_FBC_RT_BASE		0x2128
+#define   ILK_FBC_RT_VALID	(1<<0)
+
+#define ILK_DISPLAY_CHICKEN1	0x42000
+#define   ILK_FBCQ_DIS		(1<<22)
+#define	  ILK_PABSTRETCH_DIS	(1<<21)
+
+
+/*
+ * Framebuffer compression for Sandybridge
+ *
+ * The following two registers are of type GTTMMADR
+ */
+#define SNB_DPFC_CTL_SA		0x100100
+#define   SNB_CPU_FENCE_ENABLE	(1<<29)
+#define DPFC_CPU_FENCE_OFFSET	0x100104
+
+
+/*
+ * GPIO regs
+ */
+#define GPIOA			0x5010
+#define GPIOB			0x5014
+#define GPIOC			0x5018
+#define GPIOD			0x501c
+#define GPIOE			0x5020
+#define GPIOF			0x5024
+#define GPIOG			0x5028
+#define GPIOH			0x502c
+# define GPIO_CLOCK_DIR_MASK		(1 << 0)
+# define GPIO_CLOCK_DIR_IN		(0 << 1)
+# define GPIO_CLOCK_DIR_OUT		(1 << 1)
+# define GPIO_CLOCK_VAL_MASK		(1 << 2)
+# define GPIO_CLOCK_VAL_OUT		(1 << 3)
+# define GPIO_CLOCK_VAL_IN		(1 << 4)
+# define GPIO_CLOCK_PULLUP_DISABLE	(1 << 5)
+# define GPIO_DATA_DIR_MASK		(1 << 8)
+# define GPIO_DATA_DIR_IN		(0 << 9)
+# define GPIO_DATA_DIR_OUT		(1 << 9)
+# define GPIO_DATA_VAL_MASK		(1 << 10)
+# define GPIO_DATA_VAL_OUT		(1 << 11)
+# define GPIO_DATA_VAL_IN		(1 << 12)
+# define GPIO_DATA_PULLUP_DISABLE	(1 << 13)
+
+#define GMBUS0			0x5100 /* clock/port select */
+#define   GMBUS_RATE_100KHZ	(0<<8)
+#define   GMBUS_RATE_50KHZ	(1<<8)
+#define   GMBUS_RATE_400KHZ	(2<<8) /* reserved on Pineview */
+#define   GMBUS_RATE_1MHZ	(3<<8) /* reserved on Pineview */
+#define   GMBUS_RATE_MASK	(3<<8)
+#define   GMBUS_HOLD_EXT	(1<<7) /* 300ns hold time, rsvd on Pineview */
+#define   GMBUS_PORT_DISABLED	0
+#define   GMBUS_PORT_SSC	1
+#define   GMBUS_PORT_VGADDC	2
+#define   GMBUS_PORT_PANEL	3
+#define   GMBUS_PORT_DPC	4 /* HDMIC */
+#define   GMBUS_PORT_DPB	5 /* SDVO, HDMIB */
+#define   GMBUS_PORT_DPD	6 /* HDMID */
+#define   GMBUS_PORT_RESERVED	7 /* 7 reserved */
+#define   GMBUS_NUM_PORTS	(GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1)
+#define   GMBUS_PORT_MASK	7
+#define GMBUS1			0x5104 /* command/status */
+#define   GMBUS_SW_CLR_INT	(1<<31)
+#define   GMBUS_SW_RDY		(1<<30)
+#define   GMBUS_ENT		(1<<29) /* enable timeout */
+#define   GMBUS_CYCLE_NONE	(0<<25)
+#define   GMBUS_CYCLE_WAIT	(1<<25)
+#define   GMBUS_CYCLE_INDEX	(2<<25)
+#define   GMBUS_CYCLE_STOP	(4<<25)
+#define   GMBUS_BYTE_COUNT_SHIFT 16
+#define   GMBUS_SLAVE_INDEX_SHIFT 8
+#define   GMBUS_SLAVE_ADDR_SHIFT 1
+#define   GMBUS_SLAVE_READ	(1<<0)
+#define   GMBUS_SLAVE_WRITE	(0<<0)
+#define GMBUS2			0x5108 /* status */
+#define   GMBUS_INUSE		(1<<15)
+#define   GMBUS_HW_WAIT_PHASE	(1<<14)
+#define   GMBUS_STALL_TIMEOUT	(1<<13)
+#define   GMBUS_INT		(1<<12)
+#define   GMBUS_HW_RDY		(1<<11)
+#define   GMBUS_SATOER		(1<<10)
+#define   GMBUS_ACTIVE		(1<<9)
+#define GMBUS3			0x510c /* data buffer bytes 3-0 */
+#define GMBUS4			0x5110 /* interrupt mask (Pineview+) */
+#define   GMBUS_SLAVE_TIMEOUT_EN (1<<4)
+#define   GMBUS_NAK_EN		(1<<3)
+#define   GMBUS_IDLE_EN		(1<<2)
+#define   GMBUS_HW_WAIT_EN	(1<<1)
+#define   GMBUS_HW_RDY_EN	(1<<0)
+#define GMBUS5			0x5120 /* byte index */
+#define   GMBUS_2BYTE_INDEX_EN	(1<<31)
+
+/*
+ * Clock control & power management
+ */
+
+#define VGA0	0x6000
+#define VGA1	0x6004
+#define VGA_PD	0x6010
+#define   VGA0_PD_P2_DIV_4	(1 << 7)
+#define   VGA0_PD_P1_DIV_2	(1 << 5)
+#define   VGA0_PD_P1_SHIFT	0
+#define   VGA0_PD_P1_MASK	(0x1f << 0)
+#define   VGA1_PD_P2_DIV_4	(1 << 15)
+#define   VGA1_PD_P1_DIV_2	(1 << 13)
+#define   VGA1_PD_P1_SHIFT	8
+#define   VGA1_PD_P1_MASK	(0x1f << 8)
+#define _DPLL_A	0x06014
+#define _DPLL_B	0x06018
+#define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
+#define   DPLL_VCO_ENABLE		(1 << 31)
+#define   DPLL_DVO_HIGH_SPEED		(1 << 30)
+#define   DPLL_SYNCLOCK_ENABLE		(1 << 29)
+#define   DPLL_VGA_MODE_DIS		(1 << 28)
+#define   DPLLB_MODE_DAC_SERIAL		(1 << 26) /* i915 */
+#define   DPLLB_MODE_LVDS		(2 << 26) /* i915 */
+#define   DPLL_MODE_MASK		(3 << 26)
+#define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
+#define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
+#define   DPLLB_LVDS_P2_CLOCK_DIV_14	(0 << 24) /* i915 */
+#define   DPLLB_LVDS_P2_CLOCK_DIV_7	(1 << 24) /* i915 */
+#define   DPLL_P2_CLOCK_DIV_MASK	0x03000000 /* i915 */
+#define   DPLL_FPA01_P1_POST_DIV_MASK	0x00ff0000 /* i915 */
+#define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW	0x00ff8000 /* Pineview */
+
+#define SRX_INDEX		0x3c4
+#define SRX_DATA		0x3c5
+#define SR01			1
+#define SR01_SCREEN_OFF		(1<<5)
+
+#define PPCR			0x61204
+#define PPCR_ON			(1<<0)
+
+#define DVOB			0x61140
+#define DVOB_ON			(1<<31)
+#define DVOC			0x61160
+#define DVOC_ON			(1<<31)
+#define LVDS			0x61180
+#define LVDS_ON			(1<<31)
+
+/* Scratch pad debug 0 reg:
+ */
+#define   DPLL_FPA01_P1_POST_DIV_MASK_I830	0x001f0000
+/*
+ * The i830 generation, in LVDS mode, defines P1 as the bit number set within
+ * this field (only one bit may be set).
+ */
+#define   DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS	0x003f0000
+#define   DPLL_FPA01_P1_POST_DIV_SHIFT	16
+#define   DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
+/* i830, required in DVO non-gang */
+#define   PLL_P2_DIVIDE_BY_4		(1 << 23)
+#define   PLL_P1_DIVIDE_BY_TWO		(1 << 21) /* i830 */
+#define   PLL_REF_INPUT_DREFCLK		(0 << 13)
+#define   PLL_REF_INPUT_TVCLKINA	(1 << 13) /* i830 */
+#define   PLL_REF_INPUT_TVCLKINBC	(2 << 13) /* SDVO TVCLKIN */
+#define   PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
+#define   PLL_REF_INPUT_MASK		(3 << 13)
+#define   PLL_LOAD_PULSE_PHASE_SHIFT		9
+/* Ironlake */
+# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT     9
+# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK      (7 << 9)
+# define PLL_REF_SDVO_HDMI_MULTIPLIER(x)	(((x)-1) << 9)
+# define DPLL_FPA1_P1_POST_DIV_SHIFT            0
+# define DPLL_FPA1_P1_POST_DIV_MASK             0xff
+
+/*
+ * Parallel to Serial Load Pulse phase selection.
+ * Selects the phase for the 10X DPLL clock for the PCIe
+ * digital display port. The range is 4 to 13; 10 or more
+ * is just a flip delay. The default is 6
+ */
+#define   PLL_LOAD_PULSE_PHASE_MASK		(0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
+#define   DISPLAY_RATE_SELECT_FPA1		(1 << 8)
+/*
+ * SDVO multiplier for 945G/GM. Not used on 965.
+ */
+#define   SDVO_MULTIPLIER_MASK			0x000000ff
+#define   SDVO_MULTIPLIER_SHIFT_HIRES		4
+#define   SDVO_MULTIPLIER_SHIFT_VGA		0
+#define _DPLL_A_MD 0x0601c /* 965+ only */
+/*
+ * UDI pixel divider, controlling how many pixels are stuffed into a packet.
+ *
+ * Value is pixels minus 1.  Must be set to 1 pixel for SDVO.
+ */
+#define   DPLL_MD_UDI_DIVIDER_MASK		0x3f000000
+#define   DPLL_MD_UDI_DIVIDER_SHIFT		24
+/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
+#define   DPLL_MD_VGA_UDI_DIVIDER_MASK		0x003f0000
+#define   DPLL_MD_VGA_UDI_DIVIDER_SHIFT		16
+/*
+ * SDVO/UDI pixel multiplier.
+ *
+ * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
+ * clock rate is 10 times the DPLL clock.  At low resolution/refresh rate
+ * modes, the bus rate would be below the limits, so SDVO allows for stuffing
+ * dummy bytes in the datastream at an increased clock rate, with both sides of
+ * the link knowing how many bytes are fill.
+ *
+ * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
+ * rate to 130Mhz to get a bus rate of 1.30Ghz.  The DPLL clock rate would be
+ * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
+ * through an SDVO command.
+ *
+ * This register field has values of multiplication factor minus 1, with
+ * a maximum multiplier of 5 for SDVO.
+ */
+#define   DPLL_MD_UDI_MULTIPLIER_MASK		0x00003f00
+#define   DPLL_MD_UDI_MULTIPLIER_SHIFT		8
+/*
+ * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
+ * This best be set to the default value (3) or the CRT won't work. No,
+ * I don't entirely understand what this does...
+ */
+#define   DPLL_MD_VGA_UDI_MULTIPLIER_MASK	0x0000003f
+#define   DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT	0
+#define _DPLL_B_MD 0x06020 /* 965+ only */
+#define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
+#define _FPA0	0x06040
+#define _FPA1	0x06044
+#define _FPB0	0x06048
+#define _FPB1	0x0604c
+#define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
+#define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
+#define   FP_N_DIV_MASK		0x003f0000
+#define   FP_N_PINEVIEW_DIV_MASK	0x00ff0000
+#define   FP_N_DIV_SHIFT		16
+#define   FP_M1_DIV_MASK	0x00003f00
+#define   FP_M1_DIV_SHIFT		 8
+#define   FP_M2_DIV_MASK	0x0000003f
+#define   FP_M2_PINEVIEW_DIV_MASK	0x000000ff
+#define   FP_M2_DIV_SHIFT		 0
+#define DPLL_TEST	0x606c
+#define   DPLLB_TEST_SDVO_DIV_1		(0 << 22)
+#define   DPLLB_TEST_SDVO_DIV_2		(1 << 22)
+#define   DPLLB_TEST_SDVO_DIV_4		(2 << 22)
+#define   DPLLB_TEST_SDVO_DIV_MASK	(3 << 22)
+#define   DPLLB_TEST_N_BYPASS		(1 << 19)
+#define   DPLLB_TEST_M_BYPASS		(1 << 18)
+#define   DPLLB_INPUT_BUFFER_ENABLE	(1 << 16)
+#define   DPLLA_TEST_N_BYPASS		(1 << 3)
+#define   DPLLA_TEST_M_BYPASS		(1 << 2)
+#define   DPLLA_INPUT_BUFFER_ENABLE	(1 << 0)
+#define D_STATE		0x6104
+#define  DSTATE_GFX_RESET_I830			(1<<6)
+#define  DSTATE_PLL_D3_OFF			(1<<3)
+#define  DSTATE_GFX_CLOCK_GATING		(1<<1)
+#define  DSTATE_DOT_CLOCK_GATING		(1<<0)
+#define DSPCLK_GATE_D		0x6200
+# define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */
+# define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */
+# define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */
+# define VRDUNIT_CLOCK_GATE_DISABLE		(1 << 27) /* 965 */
+# define AUDUNIT_CLOCK_GATE_DISABLE		(1 << 26) /* 965 */
+# define DPUNIT_A_CLOCK_GATE_DISABLE		(1 << 25) /* 965 */
+# define DPCUNIT_CLOCK_GATE_DISABLE		(1 << 24) /* 965 */
+# define TVRUNIT_CLOCK_GATE_DISABLE		(1 << 23) /* 915-945 */
+# define TVCUNIT_CLOCK_GATE_DISABLE		(1 << 22) /* 915-945 */
+# define TVFUNIT_CLOCK_GATE_DISABLE		(1 << 21) /* 915-945 */
+# define TVEUNIT_CLOCK_GATE_DISABLE		(1 << 20) /* 915-945 */
+# define DVSUNIT_CLOCK_GATE_DISABLE		(1 << 19) /* 915-945 */
+# define DSSUNIT_CLOCK_GATE_DISABLE		(1 << 18) /* 915-945 */
+# define DDBUNIT_CLOCK_GATE_DISABLE		(1 << 17) /* 915-945 */
+# define DPRUNIT_CLOCK_GATE_DISABLE		(1 << 16) /* 915-945 */
+# define DPFUNIT_CLOCK_GATE_DISABLE		(1 << 15) /* 915-945 */
+# define DPBMUNIT_CLOCK_GATE_DISABLE		(1 << 14) /* 915-945 */
+# define DPLSUNIT_CLOCK_GATE_DISABLE		(1 << 13) /* 915-945 */
+# define DPLUNIT_CLOCK_GATE_DISABLE		(1 << 12) /* 915-945 */
+# define DPOUNIT_CLOCK_GATE_DISABLE		(1 << 11)
+# define DPBUNIT_CLOCK_GATE_DISABLE		(1 << 10)
+# define DCUNIT_CLOCK_GATE_DISABLE		(1 << 9)
+# define DPUNIT_CLOCK_GATE_DISABLE		(1 << 8)
+# define VRUNIT_CLOCK_GATE_DISABLE		(1 << 7) /* 915+: reserved */
+# define OVHUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 830-865 */
+# define DPIOUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 915-945 */
+# define OVFUNIT_CLOCK_GATE_DISABLE		(1 << 5)
+# define OVBUNIT_CLOCK_GATE_DISABLE		(1 << 4)
+/**
+ * This bit must be set on the 830 to prevent hangs when turning off the
+ * overlay scaler.
+ */
+# define OVRUNIT_CLOCK_GATE_DISABLE		(1 << 3)
+# define OVCUNIT_CLOCK_GATE_DISABLE		(1 << 2)
+# define OVUUNIT_CLOCK_GATE_DISABLE		(1 << 1)
+# define ZVUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 830 */
+# define OVLUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 845,865 */
+
+#define RENCLK_GATE_D1		0x6204
+# define BLITTER_CLOCK_GATE_DISABLE		(1 << 13) /* 945GM only */
+# define MPEG_CLOCK_GATE_DISABLE		(1 << 12) /* 945GM only */
+# define PC_FE_CLOCK_GATE_DISABLE		(1 << 11)
+# define PC_BE_CLOCK_GATE_DISABLE		(1 << 10)
+# define WINDOWER_CLOCK_GATE_DISABLE		(1 << 9)
+# define INTERPOLATOR_CLOCK_GATE_DISABLE	(1 << 8)
+# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE	(1 << 7)
+# define MOTION_COMP_CLOCK_GATE_DISABLE		(1 << 6)
+# define MAG_CLOCK_GATE_DISABLE			(1 << 5)
+/** This bit must be unset on 855,865 */
+# define MECI_CLOCK_GATE_DISABLE		(1 << 4)
+# define DCMP_CLOCK_GATE_DISABLE		(1 << 3)
+# define MEC_CLOCK_GATE_DISABLE			(1 << 2)
+# define MECO_CLOCK_GATE_DISABLE		(1 << 1)
+/** This bit must be set on 855,865. */
+# define SV_CLOCK_GATE_DISABLE			(1 << 0)
+# define I915_MPEG_CLOCK_GATE_DISABLE		(1 << 16)
+# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE	(1 << 15)
+# define I915_MOTION_COMP_CLOCK_GATE_DISABLE	(1 << 14)
+# define I915_BD_BF_CLOCK_GATE_DISABLE		(1 << 13)
+# define I915_SF_SE_CLOCK_GATE_DISABLE		(1 << 12)
+# define I915_WM_CLOCK_GATE_DISABLE		(1 << 11)
+# define I915_IZ_CLOCK_GATE_DISABLE		(1 << 10)
+# define I915_PI_CLOCK_GATE_DISABLE		(1 << 9)
+# define I915_DI_CLOCK_GATE_DISABLE		(1 << 8)
+# define I915_SH_SV_CLOCK_GATE_DISABLE		(1 << 7)
+# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE	(1 << 6)
+# define I915_SC_CLOCK_GATE_DISABLE		(1 << 5)
+# define I915_FL_CLOCK_GATE_DISABLE		(1 << 4)
+# define I915_DM_CLOCK_GATE_DISABLE		(1 << 3)
+# define I915_PS_CLOCK_GATE_DISABLE		(1 << 2)
+# define I915_CC_CLOCK_GATE_DISABLE		(1 << 1)
+# define I915_BY_CLOCK_GATE_DISABLE		(1 << 0)
+
+# define I965_RCZ_CLOCK_GATE_DISABLE		(1 << 30)
+/** This bit must always be set on 965G/965GM */
+# define I965_RCC_CLOCK_GATE_DISABLE		(1 << 29)
+# define I965_RCPB_CLOCK_GATE_DISABLE		(1 << 28)
+# define I965_DAP_CLOCK_GATE_DISABLE		(1 << 27)
+# define I965_ROC_CLOCK_GATE_DISABLE		(1 << 26)
+# define I965_GW_CLOCK_GATE_DISABLE		(1 << 25)
+# define I965_TD_CLOCK_GATE_DISABLE		(1 << 24)
+/** This bit must always be set on 965G */
+# define I965_ISC_CLOCK_GATE_DISABLE		(1 << 23)
+# define I965_IC_CLOCK_GATE_DISABLE		(1 << 22)
+# define I965_EU_CLOCK_GATE_DISABLE		(1 << 21)
+# define I965_IF_CLOCK_GATE_DISABLE		(1 << 20)
+# define I965_TC_CLOCK_GATE_DISABLE		(1 << 19)
+# define I965_SO_CLOCK_GATE_DISABLE		(1 << 17)
+# define I965_FBC_CLOCK_GATE_DISABLE		(1 << 16)
+# define I965_MARI_CLOCK_GATE_DISABLE		(1 << 15)
+# define I965_MASF_CLOCK_GATE_DISABLE		(1 << 14)
+# define I965_MAWB_CLOCK_GATE_DISABLE		(1 << 13)
+# define I965_EM_CLOCK_GATE_DISABLE		(1 << 12)
+# define I965_UC_CLOCK_GATE_DISABLE		(1 << 11)
+# define I965_SI_CLOCK_GATE_DISABLE		(1 << 6)
+# define I965_MT_CLOCK_GATE_DISABLE		(1 << 5)
+# define I965_PL_CLOCK_GATE_DISABLE		(1 << 4)
+# define I965_DG_CLOCK_GATE_DISABLE		(1 << 3)
+# define I965_QC_CLOCK_GATE_DISABLE		(1 << 2)
+# define I965_FT_CLOCK_GATE_DISABLE		(1 << 1)
+# define I965_DM_CLOCK_GATE_DISABLE		(1 << 0)
+
+#define RENCLK_GATE_D2		0x6208
+#define VF_UNIT_CLOCK_GATE_DISABLE		(1 << 9)
+#define GS_UNIT_CLOCK_GATE_DISABLE		(1 << 7)
+#define CL_UNIT_CLOCK_GATE_DISABLE		(1 << 6)
+#define RAMCLK_GATE_D		0x6210		/* CRL only */
+#define DEUC			0x6214          /* CRL only */
+
+/*
+ * Palette regs
+ */
+
+#define _PALETTE_A		0x0a000
+#define _PALETTE_B		0x0a800
+#define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
+
+/* MCH MMIO space */
+
+/*
+ * MCHBAR mirror.
+ *
+ * This mirrors the MCHBAR MMIO space whose location is determined by
+ * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
+ * every way.  It is not accessible from the CP register read instructions.
+ *
+ */
+#define MCHBAR_MIRROR_BASE	0x10000
+
+#define MCHBAR_MIRROR_BASE_SNB	0x140000
+
+/** 915-945 and GM965 MCH register controlling DRAM channel access */
+#define DCC			0x10200
+#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL		(0 << 0)
+#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC	(1 << 0)
+#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED	(2 << 0)
+#define DCC_ADDRESSING_MODE_MASK			(3 << 0)
+#define DCC_CHANNEL_XOR_DISABLE				(1 << 10)
+#define DCC_CHANNEL_XOR_BIT_17				(1 << 9)
+
+/** Pineview MCH register contains DDR3 setting */
+#define CSHRDDR3CTL            0x101a8
+#define CSHRDDR3CTL_DDR3       (1 << 2)
+
+/** 965 MCH register controlling DRAM channel configuration */
+#define C0DRB3			0x10206
+#define C1DRB3			0x10606
+
+/** snb MCH registers for reading the DRAM channel configuration */
+#define MAD_DIMM_C0			(MCHBAR_MIRROR_BASE_SNB + 0x5004)
+#define MAD_DIMM_C1			(MCHBAR_MIRROR_BASE_SNB + 0x5008)
+#define MAD_DIMM_C2			(MCHBAR_MIRROR_BASE_SNB + 0x500C)
+#define   MAD_DIMM_ECC_MASK		(0x3 << 24)
+#define   MAD_DIMM_ECC_OFF		(0x0 << 24)
+#define   MAD_DIMM_ECC_IO_ON_LOGIC_OFF	(0x1 << 24)
+#define   MAD_DIMM_ECC_IO_OFF_LOGIC_ON	(0x2 << 24)
+#define   MAD_DIMM_ECC_ON		(0x3 << 24)
+#define   MAD_DIMM_ENH_INTERLEAVE	(0x1 << 22)
+#define   MAD_DIMM_RANK_INTERLEAVE	(0x1 << 21)
+#define   MAD_DIMM_B_WIDTH_X16		(0x1 << 20) /* X8 chips if unset */
+#define   MAD_DIMM_A_WIDTH_X16		(0x1 << 19) /* X8 chips if unset */
+#define   MAD_DIMM_B_DUAL_RANK		(0x1 << 18)
+#define   MAD_DIMM_A_DUAL_RANK		(0x1 << 17)
+#define   MAD_DIMM_A_SELECT		(0x1 << 16)
+/* DIMM sizes are in multiples of 256mb. */
+#define   MAD_DIMM_B_SIZE_SHIFT		8
+#define   MAD_DIMM_B_SIZE_MASK		(0xff << MAD_DIMM_B_SIZE_SHIFT)
+#define   MAD_DIMM_A_SIZE_SHIFT		0
+#define   MAD_DIMM_A_SIZE_MASK		(0xff << MAD_DIMM_A_SIZE_SHIFT)
+
+
+/* Clocking configuration register */
+#define CLKCFG			0x10c00
+#define CLKCFG_FSB_400					(5 << 0)	/* hrawclk 100 */
+#define CLKCFG_FSB_533					(1 << 0)	/* hrawclk 133 */
+#define CLKCFG_FSB_667					(3 << 0)	/* hrawclk 166 */
+#define CLKCFG_FSB_800					(2 << 0)	/* hrawclk 200 */
+#define CLKCFG_FSB_1067					(6 << 0)	/* hrawclk 266 */
+#define CLKCFG_FSB_1333					(7 << 0)	/* hrawclk 333 */
+/* Note, below two are guess */
+#define CLKCFG_FSB_1600					(4 << 0)	/* hrawclk 400 */
+#define CLKCFG_FSB_1600_ALT				(0 << 0)	/* hrawclk 400 */
+#define CLKCFG_FSB_MASK					(7 << 0)
+#define CLKCFG_MEM_533					(1 << 4)
+#define CLKCFG_MEM_667					(2 << 4)
+#define CLKCFG_MEM_800					(3 << 4)
+#define CLKCFG_MEM_MASK					(7 << 4)
+
+#define TSC1			0x11001
+#define   TSE			(1<<0)
+#define TR1			0x11006
+#define TSFS			0x11020
+#define   TSFS_SLOPE_MASK	0x0000ff00
+#define   TSFS_SLOPE_SHIFT	8
+#define   TSFS_INTR_MASK	0x000000ff
+
+#define CRSTANDVID		0x11100
+#define PXVFREQ_BASE		0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
+#define   PXVFREQ_PX_MASK	0x7f000000
+#define   PXVFREQ_PX_SHIFT	24
+#define VIDFREQ_BASE		0x11110
+#define VIDFREQ1		0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
+#define VIDFREQ2		0x11114
+#define VIDFREQ3		0x11118
+#define VIDFREQ4		0x1111c
+#define   VIDFREQ_P0_MASK	0x1f000000
+#define   VIDFREQ_P0_SHIFT	24
+#define   VIDFREQ_P0_CSCLK_MASK	0x00f00000
+#define   VIDFREQ_P0_CSCLK_SHIFT 20
+#define   VIDFREQ_P0_CRCLK_MASK	0x000f0000
+#define   VIDFREQ_P0_CRCLK_SHIFT 16
+#define   VIDFREQ_P1_MASK	0x00001f00
+#define   VIDFREQ_P1_SHIFT	8
+#define   VIDFREQ_P1_CSCLK_MASK	0x000000f0
+#define   VIDFREQ_P1_CSCLK_SHIFT 4
+#define   VIDFREQ_P1_CRCLK_MASK	0x0000000f
+#define INTTOEXT_BASE_ILK	0x11300
+#define INTTOEXT_BASE		0x11120 /* INTTOEXT1-8 (0x1113c) */
+#define   INTTOEXT_MAP3_SHIFT	24
+#define   INTTOEXT_MAP3_MASK	(0x1f << INTTOEXT_MAP3_SHIFT)
+#define   INTTOEXT_MAP2_SHIFT	16
+#define   INTTOEXT_MAP2_MASK	(0x1f << INTTOEXT_MAP2_SHIFT)
+#define   INTTOEXT_MAP1_SHIFT	8
+#define   INTTOEXT_MAP1_MASK	(0x1f << INTTOEXT_MAP1_SHIFT)
+#define   INTTOEXT_MAP0_SHIFT	0
+#define   INTTOEXT_MAP0_MASK	(0x1f << INTTOEXT_MAP0_SHIFT)
+#define MEMSWCTL		0x11170 /* Ironlake only */
+#define   MEMCTL_CMD_MASK	0xe000
+#define   MEMCTL_CMD_SHIFT	13
+#define   MEMCTL_CMD_RCLK_OFF	0
+#define   MEMCTL_CMD_RCLK_ON	1
+#define   MEMCTL_CMD_CHFREQ	2
+#define   MEMCTL_CMD_CHVID	3
+#define   MEMCTL_CMD_VMMOFF	4
+#define   MEMCTL_CMD_VMMON	5
+#define   MEMCTL_CMD_STS	(1<<12) /* write 1 triggers command, clears
+					   when command complete */
+#define   MEMCTL_FREQ_MASK	0x0f00 /* jitter, from 0-15 */
+#define   MEMCTL_FREQ_SHIFT	8
+#define   MEMCTL_SFCAVM		(1<<7)
+#define   MEMCTL_TGT_VID_MASK	0x007f
+#define MEMIHYST		0x1117c
+#define MEMINTREN		0x11180 /* 16 bits */
+#define   MEMINT_RSEXIT_EN	(1<<8)
+#define   MEMINT_CX_SUPR_EN	(1<<7)
+#define   MEMINT_CONT_BUSY_EN	(1<<6)
+#define   MEMINT_AVG_BUSY_EN	(1<<5)
+#define   MEMINT_EVAL_CHG_EN	(1<<4)
+#define   MEMINT_MON_IDLE_EN	(1<<3)
+#define   MEMINT_UP_EVAL_EN	(1<<2)
+#define   MEMINT_DOWN_EVAL_EN	(1<<1)
+#define   MEMINT_SW_CMD_EN	(1<<0)
+#define MEMINTRSTR		0x11182 /* 16 bits */
+#define   MEM_RSEXIT_MASK	0xc000
+#define   MEM_RSEXIT_SHIFT	14
+#define   MEM_CONT_BUSY_MASK	0x3000
+#define   MEM_CONT_BUSY_SHIFT	12
+#define   MEM_AVG_BUSY_MASK	0x0c00
+#define   MEM_AVG_BUSY_SHIFT	10
+#define   MEM_EVAL_CHG_MASK	0x0300
+#define   MEM_EVAL_BUSY_SHIFT	8
+#define   MEM_MON_IDLE_MASK	0x00c0
+#define   MEM_MON_IDLE_SHIFT	6
+#define   MEM_UP_EVAL_MASK	0x0030
+#define   MEM_UP_EVAL_SHIFT	4
+#define   MEM_DOWN_EVAL_MASK	0x000c
+#define   MEM_DOWN_EVAL_SHIFT	2
+#define   MEM_SW_CMD_MASK	0x0003
+#define   MEM_INT_STEER_GFX	0
+#define   MEM_INT_STEER_CMR	1
+#define   MEM_INT_STEER_SMI	2
+#define   MEM_INT_STEER_SCI	3
+#define MEMINTRSTS		0x11184
+#define   MEMINT_RSEXIT		(1<<7)
+#define   MEMINT_CONT_BUSY	(1<<6)
+#define   MEMINT_AVG_BUSY	(1<<5)
+#define   MEMINT_EVAL_CHG	(1<<4)
+#define   MEMINT_MON_IDLE	(1<<3)
+#define   MEMINT_UP_EVAL	(1<<2)
+#define   MEMINT_DOWN_EVAL	(1<<1)
+#define   MEMINT_SW_CMD		(1<<0)
+#define MEMMODECTL		0x11190
+#define   MEMMODE_BOOST_EN	(1<<31)
+#define   MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
+#define   MEMMODE_BOOST_FREQ_SHIFT 24
+#define   MEMMODE_IDLE_MODE_MASK 0x00030000
+#define   MEMMODE_IDLE_MODE_SHIFT 16
+#define   MEMMODE_IDLE_MODE_EVAL 0
+#define   MEMMODE_IDLE_MODE_CONT 1
+#define   MEMMODE_HWIDLE_EN	(1<<15)
+#define   MEMMODE_SWMODE_EN	(1<<14)
+#define   MEMMODE_RCLK_GATE	(1<<13)
+#define   MEMMODE_HW_UPDATE	(1<<12)
+#define   MEMMODE_FSTART_MASK	0x00000f00 /* starting jitter, 0-15 */
+#define   MEMMODE_FSTART_SHIFT	8
+#define   MEMMODE_FMAX_MASK	0x000000f0 /* max jitter, 0-15 */
+#define   MEMMODE_FMAX_SHIFT	4
+#define   MEMMODE_FMIN_MASK	0x0000000f /* min jitter, 0-15 */
+#define RCBMAXAVG		0x1119c
+#define MEMSWCTL2		0x1119e /* Cantiga only */
+#define   SWMEMCMD_RENDER_OFF	(0 << 13)
+#define   SWMEMCMD_RENDER_ON	(1 << 13)
+#define   SWMEMCMD_SWFREQ	(2 << 13)
+#define   SWMEMCMD_TARVID	(3 << 13)
+#define   SWMEMCMD_VRM_OFF	(4 << 13)
+#define   SWMEMCMD_VRM_ON	(5 << 13)
+#define   CMDSTS		(1<<12)
+#define   SFCAVM		(1<<11)
+#define   SWFREQ_MASK		0x0380 /* P0-7 */
+#define   SWFREQ_SHIFT		7
+#define   TARVID_MASK		0x001f
+#define MEMSTAT_CTG		0x111a0
+#define RCBMINAVG		0x111a0
+#define RCUPEI			0x111b0
+#define RCDNEI			0x111b4
+#define RSTDBYCTL		0x111b8
+#define   RS1EN			(1<<31)
+#define   RS2EN			(1<<30)
+#define   RS3EN			(1<<29)
+#define   D3RS3EN		(1<<28) /* Display D3 imlies RS3 */
+#define   SWPROMORSX		(1<<27) /* RSx promotion timers ignored */
+#define   RCWAKERW		(1<<26) /* Resetwarn from PCH causes wakeup */
+#define   DPRSLPVREN		(1<<25) /* Fast voltage ramp enable */
+#define   GFXTGHYST		(1<<24) /* Hysteresis to allow trunk gating */
+#define   RCX_SW_EXIT		(1<<23) /* Leave RSx and prevent re-entry */
+#define   RSX_STATUS_MASK	(7<<20)
+#define   RSX_STATUS_ON		(0<<20)
+#define   RSX_STATUS_RC1	(1<<20)
+#define   RSX_STATUS_RC1E	(2<<20)
+#define   RSX_STATUS_RS1	(3<<20)
+#define   RSX_STATUS_RS2	(4<<20) /* aka rc6 */
+#define   RSX_STATUS_RSVD	(5<<20) /* deep rc6 unsupported on ilk */
+#define   RSX_STATUS_RS3	(6<<20) /* rs3 unsupported on ilk */
+#define   RSX_STATUS_RSVD2	(7<<20)
+#define   UWRCRSXE		(1<<19) /* wake counter limit prevents rsx */
+#define   RSCRP			(1<<18) /* rs requests control on rs1/2 reqs */
+#define   JRSC			(1<<17) /* rsx coupled to cpu c-state */
+#define   RS2INC0		(1<<16) /* allow rs2 in cpu c0 */
+#define   RS1CONTSAV_MASK	(3<<14)
+#define   RS1CONTSAV_NO_RS1	(0<<14) /* rs1 doesn't save/restore context */
+#define   RS1CONTSAV_RSVD	(1<<14)
+#define   RS1CONTSAV_SAVE_RS1	(2<<14) /* rs1 saves context */
+#define   RS1CONTSAV_FULL_RS1	(3<<14) /* rs1 saves and restores context */
+#define   NORMSLEXLAT_MASK	(3<<12)
+#define   SLOW_RS123		(0<<12)
+#define   SLOW_RS23		(1<<12)
+#define   SLOW_RS3		(2<<12)
+#define   NORMAL_RS123		(3<<12)
+#define   RCMODE_TIMEOUT	(1<<11) /* 0 is eval interval method */
+#define   IMPROMOEN		(1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
+#define   RCENTSYNC		(1<<9) /* rs coupled to cpu c-state (3/6/7) */
+#define   STATELOCK		(1<<7) /* locked to rs_cstate if 0 */
+#define   RS_CSTATE_MASK	(3<<4)
+#define   RS_CSTATE_C367_RS1	(0<<4)
+#define   RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
+#define   RS_CSTATE_RSVD	(2<<4)
+#define   RS_CSTATE_C367_RS2	(3<<4)
+#define   REDSAVES		(1<<3) /* no context save if was idle during rs0 */
+#define   REDRESTORES		(1<<2) /* no restore if was idle during rs0 */
+#define VIDCTL			0x111c0
+#define VIDSTS			0x111c8
+#define VIDSTART		0x111cc /* 8 bits */
+#define MEMSTAT_ILK			0x111f8
+#define   MEMSTAT_VID_MASK	0x7f00
+#define   MEMSTAT_VID_SHIFT	8
+#define   MEMSTAT_PSTATE_MASK	0x00f8
+#define   MEMSTAT_PSTATE_SHIFT  3
+#define   MEMSTAT_MON_ACTV	(1<<2)
+#define   MEMSTAT_SRC_CTL_MASK	0x0003
+#define   MEMSTAT_SRC_CTL_CORE	0
+#define   MEMSTAT_SRC_CTL_TRB	1
+#define   MEMSTAT_SRC_CTL_THM	2
+#define   MEMSTAT_SRC_CTL_STDBY 3
+#define RCPREVBSYTUPAVG		0x113b8
+#define RCPREVBSYTDNAVG		0x113bc
+#define PMMISC			0x11214
+#define   MCPPCE_EN		(1<<0) /* enable PM_MSG from PCH->MPC */
+#define SDEW			0x1124c
+#define CSIEW0			0x11250
+#define CSIEW1			0x11254
+#define CSIEW2			0x11258
+#define PEW			0x1125c
+#define DEW			0x11270
+#define MCHAFE			0x112c0
+#define CSIEC			0x112e0
+#define DMIEC			0x112e4
+#define DDREC			0x112e8
+#define PEG0EC			0x112ec
+#define PEG1EC			0x112f0
+#define GFXEC			0x112f4
+#define RPPREVBSYTUPAVG		0x113b8
+#define RPPREVBSYTDNAVG		0x113bc
+#define ECR			0x11600
+#define   ECR_GPFE		(1<<31)
+#define   ECR_IMONE		(1<<30)
+#define   ECR_CAP_MASK		0x0000001f /* Event range, 0-31 */
+#define OGW0			0x11608
+#define OGW1			0x1160c
+#define EG0			0x11610
+#define EG1			0x11614
+#define EG2			0x11618
+#define EG3			0x1161c
+#define EG4			0x11620
+#define EG5			0x11624
+#define EG6			0x11628
+#define EG7			0x1162c
+#define PXW			0x11664
+#define PXWL			0x11680
+#define LCFUSE02		0x116c0
+#define   LCFUSE_HIV_MASK	0x000000ff
+#define CSIPLL0			0x12c10
+#define DDRMPLL1		0X12c20
+#define PEG_BAND_GAP_DATA	0x14d68
+
+#define GEN6_GT_THREAD_STATUS_REG 0x13805c
+#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
+
+#define GEN6_GT_PERF_STATUS	0x145948
+#define GEN6_RP_STATE_LIMITS	0x145994
+#define GEN6_RP_STATE_CAP	0x145998
+
+/*
+ * Logical Context regs
+ */
+#define CCID			0x2180
+#define   CCID_EN		(1<<0)
+/*
+ * Overlay regs
+ */
+
+#define OVADD			0x30000
+#define DOVSTA			0x30008
+#define OC_BUF			(0x3<<20)
+#define OGAMC5			0x30010
+#define OGAMC4			0x30014
+#define OGAMC3			0x30018
+#define OGAMC2			0x3001c
+#define OGAMC1			0x30020
+#define OGAMC0			0x30024
+
+/*
+ * Display engine regs
+ */
+
+/* Pipe A timing regs */
+#define _HTOTAL_A	0x60000
+#define _HBLANK_A	0x60004
+#define _HSYNC_A		0x60008
+#define _VTOTAL_A	0x6000c
+#define _VBLANK_A	0x60010
+#define _VSYNC_A		0x60014
+#define _PIPEASRC	0x6001c
+#define _BCLRPAT_A	0x60020
+#define _VSYNCSHIFT_A	0x60028
+
+/* Pipe B timing regs */
+#define _HTOTAL_B	0x61000
+#define _HBLANK_B	0x61004
+#define _HSYNC_B		0x61008
+#define _VTOTAL_B	0x6100c
+#define _VBLANK_B	0x61010
+#define _VSYNC_B		0x61014
+#define _PIPEBSRC	0x6101c
+#define _BCLRPAT_B	0x61020
+#define _VSYNCSHIFT_B	0x61028
+
+
+#define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B)
+#define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B)
+#define HSYNC(pipe) _PIPE(pipe, _HSYNC_A, _HSYNC_B)
+#define VTOTAL(pipe) _PIPE(pipe, _VTOTAL_A, _VTOTAL_B)
+#define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B)
+#define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B)
+#define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
+#define VSYNCSHIFT(pipe) _PIPE(pipe, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
+
+/* VGA port control */
+#define ADPA			0x61100
+#define   ADPA_DAC_ENABLE	(1<<31)
+#define   ADPA_DAC_DISABLE	0
+#define   ADPA_PIPE_SELECT_MASK	(1<<30)
+#define   ADPA_PIPE_A_SELECT	0
+#define   ADPA_PIPE_B_SELECT	(1<<30)
+#define   ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
+#define   ADPA_USE_VGA_HVPOLARITY (1<<15)
+#define   ADPA_SETS_HVPOLARITY	0
+#define   ADPA_VSYNC_CNTL_DISABLE (1<<11)
+#define   ADPA_VSYNC_CNTL_ENABLE 0
+#define   ADPA_HSYNC_CNTL_DISABLE (1<<10)
+#define   ADPA_HSYNC_CNTL_ENABLE 0
+#define   ADPA_VSYNC_ACTIVE_HIGH (1<<4)
+#define   ADPA_VSYNC_ACTIVE_LOW	0
+#define   ADPA_HSYNC_ACTIVE_HIGH (1<<3)
+#define   ADPA_HSYNC_ACTIVE_LOW	0
+#define   ADPA_DPMS_MASK	(~(3<<10))
+#define   ADPA_DPMS_ON		(0<<10)
+#define   ADPA_DPMS_SUSPEND	(1<<10)
+#define   ADPA_DPMS_STANDBY	(2<<10)
+#define   ADPA_DPMS_OFF		(3<<10)
+
+
+/* Hotplug control (945+ only) */
+#define PORT_HOTPLUG_EN		0x61110
+#define   HDMIB_HOTPLUG_INT_EN			(1 << 29)
+#define   DPB_HOTPLUG_INT_EN			(1 << 29)
+#define   HDMIC_HOTPLUG_INT_EN			(1 << 28)
+#define   DPC_HOTPLUG_INT_EN			(1 << 28)
+#define   HDMID_HOTPLUG_INT_EN			(1 << 27)
+#define   DPD_HOTPLUG_INT_EN			(1 << 27)
+#define   SDVOB_HOTPLUG_INT_EN			(1 << 26)
+#define   SDVOC_HOTPLUG_INT_EN			(1 << 25)
+#define   TV_HOTPLUG_INT_EN			(1 << 18)
+#define   CRT_HOTPLUG_INT_EN			(1 << 9)
+#define   CRT_HOTPLUG_FORCE_DETECT		(1 << 3)
+#define CRT_HOTPLUG_ACTIVATION_PERIOD_32	(0 << 8)
+/* must use period 64 on GM45 according to docs */
+#define CRT_HOTPLUG_ACTIVATION_PERIOD_64	(1 << 8)
+#define CRT_HOTPLUG_DAC_ON_TIME_2M		(0 << 7)
+#define CRT_HOTPLUG_DAC_ON_TIME_4M		(1 << 7)
+#define CRT_HOTPLUG_VOLTAGE_COMPARE_40		(0 << 5)
+#define CRT_HOTPLUG_VOLTAGE_COMPARE_50		(1 << 5)
+#define CRT_HOTPLUG_VOLTAGE_COMPARE_60		(2 << 5)
+#define CRT_HOTPLUG_VOLTAGE_COMPARE_70		(3 << 5)
+#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK	(3 << 5)
+#define CRT_HOTPLUG_DETECT_DELAY_1G		(0 << 4)
+#define CRT_HOTPLUG_DETECT_DELAY_2G		(1 << 4)
+#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV	(0 << 2)
+#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV	(1 << 2)
+
+#define PORT_HOTPLUG_STAT	0x61114
+#define   HDMIB_HOTPLUG_INT_STATUS		(1 << 29)
+#define   DPB_HOTPLUG_INT_STATUS		(1 << 29)
+#define   HDMIC_HOTPLUG_INT_STATUS		(1 << 28)
+#define   DPC_HOTPLUG_INT_STATUS		(1 << 28)
+#define   HDMID_HOTPLUG_INT_STATUS		(1 << 27)
+#define   DPD_HOTPLUG_INT_STATUS		(1 << 27)
+#define   CRT_HOTPLUG_INT_STATUS		(1 << 11)
+#define   TV_HOTPLUG_INT_STATUS			(1 << 10)
+#define   CRT_HOTPLUG_MONITOR_MASK		(3 << 8)
+#define   CRT_HOTPLUG_MONITOR_COLOR		(3 << 8)
+#define   CRT_HOTPLUG_MONITOR_MONO		(2 << 8)
+#define   CRT_HOTPLUG_MONITOR_NONE		(0 << 8)
+#define   SDVOC_HOTPLUG_INT_STATUS		(1 << 7)
+#define   SDVOB_HOTPLUG_INT_STATUS		(1 << 6)
+
+/* SDVO port control */
+#define SDVOB			0x61140
+#define SDVOC			0x61160
+#define   SDVO_ENABLE		(1 << 31)
+#define   SDVO_PIPE_B_SELECT	(1 << 30)
+#define   SDVO_STALL_SELECT	(1 << 29)
+#define   SDVO_INTERRUPT_ENABLE	(1 << 26)
+/**
+ * 915G/GM SDVO pixel multiplier.
+ *
+ * Programmed value is multiplier - 1, up to 5x.
+ *
+ * \sa DPLL_MD_UDI_MULTIPLIER_MASK
+ */
+#define   SDVO_PORT_MULTIPLY_MASK	(7 << 23)
+#define   SDVO_PORT_MULTIPLY_SHIFT		23
+#define   SDVO_PHASE_SELECT_MASK	(15 << 19)
+#define   SDVO_PHASE_SELECT_DEFAULT	(6 << 19)
+#define   SDVO_CLOCK_OUTPUT_INVERT	(1 << 18)
+#define   SDVOC_GANG_MODE		(1 << 16)
+#define   SDVO_ENCODING_SDVO		(0x0 << 10)
+#define   SDVO_ENCODING_HDMI		(0x2 << 10)
+/** Requird for HDMI operation */
+#define   SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9)
+#define   SDVO_COLOR_RANGE_16_235	(1 << 8)
+#define   SDVO_BORDER_ENABLE		(1 << 7)
+#define   SDVO_AUDIO_ENABLE		(1 << 6)
+/** New with 965, default is to be set */
+#define   SDVO_VSYNC_ACTIVE_HIGH	(1 << 4)
+/** New with 965, default is to be set */
+#define   SDVO_HSYNC_ACTIVE_HIGH	(1 << 3)
+#define   SDVOB_PCIE_CONCURRENCY	(1 << 3)
+#define   SDVO_DETECTED			(1 << 2)
+/* Bits to be preserved when writing */
+#define   SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))
+#define   SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
+
+/* DVO port control */
+#define DVOA			0x61120
+#define DVOB			0x61140
+#define DVOC			0x61160
+#define   DVO_ENABLE			(1 << 31)
+#define   DVO_PIPE_B_SELECT		(1 << 30)
+#define   DVO_PIPE_STALL_UNUSED		(0 << 28)
+#define   DVO_PIPE_STALL		(1 << 28)
+#define   DVO_PIPE_STALL_TV		(2 << 28)
+#define   DVO_PIPE_STALL_MASK		(3 << 28)
+#define   DVO_USE_VGA_SYNC		(1 << 15)
+#define   DVO_DATA_ORDER_I740		(0 << 14)
+#define   DVO_DATA_ORDER_FP		(1 << 14)
+#define   DVO_VSYNC_DISABLE		(1 << 11)
+#define   DVO_HSYNC_DISABLE		(1 << 10)
+#define   DVO_VSYNC_TRISTATE		(1 << 9)
+#define   DVO_HSYNC_TRISTATE		(1 << 8)
+#define   DVO_BORDER_ENABLE		(1 << 7)
+#define   DVO_DATA_ORDER_GBRG		(1 << 6)
+#define   DVO_DATA_ORDER_RGGB		(0 << 6)
+#define   DVO_DATA_ORDER_GBRG_ERRATA	(0 << 6)
+#define   DVO_DATA_ORDER_RGGB_ERRATA	(1 << 6)
+#define   DVO_VSYNC_ACTIVE_HIGH		(1 << 4)
+#define   DVO_HSYNC_ACTIVE_HIGH		(1 << 3)
+#define   DVO_BLANK_ACTIVE_HIGH		(1 << 2)
+#define   DVO_OUTPUT_CSTATE_PIXELS	(1 << 1)	/* SDG only */
+#define   DVO_OUTPUT_SOURCE_SIZE_PIXELS	(1 << 0)	/* SDG only */
+#define   DVO_PRESERVE_MASK		(0x7<<24)
+#define DVOA_SRCDIM		0x61124
+#define DVOB_SRCDIM		0x61144
+#define DVOC_SRCDIM		0x61164
+#define   DVO_SRCDIM_HORIZONTAL_SHIFT	12
+#define   DVO_SRCDIM_VERTICAL_SHIFT	0
+
+/* LVDS port control */
+#define LVDS			0x61180
+/*
+ * Enables the LVDS port.  This bit must be set before DPLLs are enabled, as
+ * the DPLL semantics change when the LVDS is assigned to that pipe.
+ */
+#define   LVDS_PORT_EN			(1 << 31)
+/* Selects pipe B for LVDS data.  Must be set on pre-965. */
+#define   LVDS_PIPEB_SELECT		(1 << 30)
+#define   LVDS_PIPE_MASK		(1 << 30)
+#define   LVDS_PIPE(pipe)		((pipe) << 30)
+/* LVDS dithering flag on 965/g4x platform */
+#define   LVDS_ENABLE_DITHER		(1 << 25)
+/* LVDS sync polarity flags. Set to invert (i.e. negative) */
+#define   LVDS_VSYNC_POLARITY		(1 << 21)
+#define   LVDS_HSYNC_POLARITY		(1 << 20)
+
+/* Enable border for unscaled (or aspect-scaled) display */
+#define   LVDS_BORDER_ENABLE		(1 << 15)
+/*
+ * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
+ * pixel.
+ */
+#define   LVDS_A0A2_CLKA_POWER_MASK	(3 << 8)
+#define   LVDS_A0A2_CLKA_POWER_DOWN	(0 << 8)
+#define   LVDS_A0A2_CLKA_POWER_UP	(3 << 8)
+/*
+ * Controls the A3 data pair, which contains the additional LSBs for 24 bit
+ * mode.  Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
+ * on.
+ */
+#define   LVDS_A3_POWER_MASK		(3 << 6)
+#define   LVDS_A3_POWER_DOWN		(0 << 6)
+#define   LVDS_A3_POWER_UP		(3 << 6)
+/*
+ * Controls the CLKB pair.  This should only be set when LVDS_B0B3_POWER_UP
+ * is set.
+ */
+#define   LVDS_CLKB_POWER_MASK		(3 << 4)
+#define   LVDS_CLKB_POWER_DOWN		(0 << 4)
+#define   LVDS_CLKB_POWER_UP		(3 << 4)
+/*
+ * Controls the B0-B3 data pairs.  This must be set to match the DPLL p2
+ * setting for whether we are in dual-channel mode.  The B3 pair will
+ * additionally only be powered up when LVDS_A3_POWER_UP is set.
+ */
+#define   LVDS_B0B3_POWER_MASK		(3 << 2)
+#define   LVDS_B0B3_POWER_DOWN		(0 << 2)
+#define   LVDS_B0B3_POWER_UP		(3 << 2)
+
+/* Video Data Island Packet control */
+#define VIDEO_DIP_DATA		0x61178
+#define VIDEO_DIP_CTL		0x61170
+#define   VIDEO_DIP_ENABLE		(1 << 31)
+#define   VIDEO_DIP_PORT_B		(1 << 29)
+#define   VIDEO_DIP_PORT_C		(2 << 29)
+#define   VIDEO_DIP_ENABLE_AVI		(1 << 21)
+#define   VIDEO_DIP_ENABLE_VENDOR	(2 << 21)
+#define   VIDEO_DIP_ENABLE_SPD		(8 << 21)
+#define   VIDEO_DIP_SELECT_AVI		(0 << 19)
+#define   VIDEO_DIP_SELECT_VENDOR	(1 << 19)
+#define   VIDEO_DIP_SELECT_SPD		(3 << 19)
+#define   VIDEO_DIP_SELECT_MASK		(3 << 19)
+#define   VIDEO_DIP_FREQ_ONCE		(0 << 16)
+#define   VIDEO_DIP_FREQ_VSYNC		(1 << 16)
+#define   VIDEO_DIP_FREQ_2VSYNC		(2 << 16)
+
+/* Panel power sequencing */
+#define PP_STATUS	0x61200
+#define   PP_ON		(1 << 31)
+/*
+ * Indicates that all dependencies of the panel are on:
+ *
+ * - PLL enabled
+ * - pipe enabled
+ * - LVDS/DVOB/DVOC on
+ */
+#define   PP_READY		(1 << 30)
+#define   PP_SEQUENCE_NONE	(0 << 28)
+#define   PP_SEQUENCE_POWER_UP	(1 << 28)
+#define   PP_SEQUENCE_POWER_DOWN (2 << 28)
+#define   PP_SEQUENCE_MASK	(3 << 28)
+#define   PP_SEQUENCE_SHIFT	28
+#define   PP_CYCLE_DELAY_ACTIVE	(1 << 27)
+#define   PP_SEQUENCE_STATE_MASK 0x0000000f
+#define   PP_SEQUENCE_STATE_OFF_IDLE	(0x0 << 0)
+#define   PP_SEQUENCE_STATE_OFF_S0_1	(0x1 << 0)
+#define   PP_SEQUENCE_STATE_OFF_S0_2	(0x2 << 0)
+#define   PP_SEQUENCE_STATE_OFF_S0_3	(0x3 << 0)
+#define   PP_SEQUENCE_STATE_ON_IDLE	(0x8 << 0)
+#define   PP_SEQUENCE_STATE_ON_S1_0	(0x9 << 0)
+#define   PP_SEQUENCE_STATE_ON_S1_2	(0xa << 0)
+#define   PP_SEQUENCE_STATE_ON_S1_3	(0xb << 0)
+#define   PP_SEQUENCE_STATE_RESET	(0xf << 0)
+#define PP_CONTROL	0x61204
+#define   POWER_TARGET_ON	(1 << 0)
+#define PP_ON_DELAYS	0x61208
+#define PP_OFF_DELAYS	0x6120c
+#define PP_DIVISOR	0x61210
+
+/* Panel fitting */
+#define PFIT_CONTROL	0x61230
+#define   PFIT_ENABLE		(1 << 31)
+#define   PFIT_PIPE_MASK	(3 << 29)
+#define   PFIT_PIPE_SHIFT	29
+#define   VERT_INTERP_DISABLE	(0 << 10)
+#define   VERT_INTERP_BILINEAR	(1 << 10)
+#define   VERT_INTERP_MASK	(3 << 10)
+#define   VERT_AUTO_SCALE	(1 << 9)
+#define   HORIZ_INTERP_DISABLE	(0 << 6)
+#define   HORIZ_INTERP_BILINEAR	(1 << 6)
+#define   HORIZ_INTERP_MASK	(3 << 6)
+#define   HORIZ_AUTO_SCALE	(1 << 5)
+#define   PANEL_8TO6_DITHER_ENABLE (1 << 3)
+#define   PFIT_FILTER_FUZZY	(0 << 24)
+#define   PFIT_SCALING_AUTO	(0 << 26)
+#define   PFIT_SCALING_PROGRAMMED (1 << 26)
+#define   PFIT_SCALING_PILLAR	(2 << 26)
+#define   PFIT_SCALING_LETTER	(3 << 26)
+#define PFIT_PGM_RATIOS	0x61234
+#define   PFIT_VERT_SCALE_MASK			0xfff00000
+#define   PFIT_HORIZ_SCALE_MASK			0x0000fff0
+/* Pre-965 */
+#define		PFIT_VERT_SCALE_SHIFT		20
+#define		PFIT_VERT_SCALE_MASK		0xfff00000
+#define		PFIT_HORIZ_SCALE_SHIFT		4
+#define		PFIT_HORIZ_SCALE_MASK		0x0000fff0
+/* 965+ */
+#define		PFIT_VERT_SCALE_SHIFT_965	16
+#define		PFIT_VERT_SCALE_MASK_965	0x1fff0000
+#define		PFIT_HORIZ_SCALE_SHIFT_965	0
+#define		PFIT_HORIZ_SCALE_MASK_965	0x00001fff
+
+#define PFIT_AUTO_RATIOS 0x61238
+
+/* Backlight control */
+#define BLC_PWM_CTL		0x61254
+#define   BACKLIGHT_MODULATION_FREQ_SHIFT		(17)
+#define BLC_PWM_CTL2		0x61250 /* 965+ only */
+#define   BLM_COMBINATION_MODE (1 << 30)
+/*
+ * This is the most significant 15 bits of the number of backlight cycles in a
+ * complete cycle of the modulated backlight control.
+ *
+ * The actual value is this field multiplied by two.
+ */
+#define   BACKLIGHT_MODULATION_FREQ_MASK		(0x7fff << 17)
+#define   BLM_LEGACY_MODE				(1 << 16)
+/*
+ * This is the number of cycles out of the backlight modulation cycle for which
+ * the backlight is on.
+ *
+ * This field must be no greater than the number of cycles in the complete
+ * backlight modulation cycle.
+ */
+#define   BACKLIGHT_DUTY_CYCLE_SHIFT		(0)
+#define   BACKLIGHT_DUTY_CYCLE_MASK		(0xffff)
+
+#define BLC_HIST_CTL		0x61260
+
+/* TV port control */
+#define TV_CTL			0x68000
+/** Enables the TV encoder */
+# define TV_ENC_ENABLE			(1 << 31)
+/** Sources the TV encoder input from pipe B instead of A. */
+# define TV_ENC_PIPEB_SELECT		(1 << 30)
+/** Outputs composite video (DAC A only) */
+# define TV_ENC_OUTPUT_COMPOSITE	(0 << 28)
+/** Outputs SVideo video (DAC B/C) */
+# define TV_ENC_OUTPUT_SVIDEO		(1 << 28)
+/** Outputs Component video (DAC A/B/C) */
+# define TV_ENC_OUTPUT_COMPONENT	(2 << 28)
+/** Outputs Composite and SVideo (DAC A/B/C) */
+# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE	(3 << 28)
+# define TV_TRILEVEL_SYNC		(1 << 21)
+/** Enables slow sync generation (945GM only) */
+# define TV_SLOW_SYNC			(1 << 20)
+/** Selects 4x oversampling for 480i and 576p */
+# define TV_OVERSAMPLE_4X		(0 << 18)
+/** Selects 2x oversampling for 720p and 1080i */
+# define TV_OVERSAMPLE_2X		(1 << 18)
+/** Selects no oversampling for 1080p */
+# define TV_OVERSAMPLE_NONE		(2 << 18)
+/** Selects 8x oversampling */
+# define TV_OVERSAMPLE_8X		(3 << 18)
+/** Selects progressive mode rather than interlaced */
+# define TV_PROGRESSIVE			(1 << 17)
+/** Sets the colorburst to PAL mode.  Required for non-M PAL modes. */
+# define TV_PAL_BURST			(1 << 16)
+/** Field for setting delay of Y compared to C */
+# define TV_YC_SKEW_MASK		(7 << 12)
+/** Enables a fix for 480p/576p standard definition modes on the 915GM only */
+# define TV_ENC_SDP_FIX			(1 << 11)
+/**
+ * Enables a fix for the 915GM only.
+ *
+ * Not sure what it does.
+ */
+# define TV_ENC_C0_FIX			(1 << 10)
+/** Bits that must be preserved by software */
+# define TV_CTL_SAVE			((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
+# define TV_FUSE_STATE_MASK		(3 << 4)
+/** Read-only state that reports all features enabled */
+# define TV_FUSE_STATE_ENABLED		(0 << 4)
+/** Read-only state that reports that Macrovision is disabled in hardware*/
+# define TV_FUSE_STATE_NO_MACROVISION	(1 << 4)
+/** Read-only state that reports that TV-out is disabled in hardware. */
+# define TV_FUSE_STATE_DISABLED		(2 << 4)
+/** Normal operation */
+# define TV_TEST_MODE_NORMAL		(0 << 0)
+/** Encoder test pattern 1 - combo pattern */
+# define TV_TEST_MODE_PATTERN_1		(1 << 0)
+/** Encoder test pattern 2 - full screen vertical 75% color bars */
+# define TV_TEST_MODE_PATTERN_2		(2 << 0)
+/** Encoder test pattern 3 - full screen horizontal 75% color bars */
+# define TV_TEST_MODE_PATTERN_3		(3 << 0)
+/** Encoder test pattern 4 - random noise */
+# define TV_TEST_MODE_PATTERN_4		(4 << 0)
+/** Encoder test pattern 5 - linear color ramps */
+# define TV_TEST_MODE_PATTERN_5		(5 << 0)
+/**
+ * This test mode forces the DACs to 50% of full output.
+ *
+ * This is used for load detection in combination with TVDAC_SENSE_MASK
+ */
+# define TV_TEST_MODE_MONITOR_DETECT	(7 << 0)
+# define TV_TEST_MODE_MASK		(7 << 0)
+
+#define TV_DAC			0x68004
+# define TV_DAC_SAVE		0x00ffff00
+/**
+ * Reports that DAC state change logic has reported change (RO).
+ *
+ * This gets cleared when TV_DAC_STATE_EN is cleared
+*/
+# define TVDAC_STATE_CHG		(1 << 31)
+# define TVDAC_SENSE_MASK		(7 << 28)
+/** Reports that DAC A voltage is above the detect threshold */
+# define TVDAC_A_SENSE			(1 << 30)
+/** Reports that DAC B voltage is above the detect threshold */
+# define TVDAC_B_SENSE			(1 << 29)
+/** Reports that DAC C voltage is above the detect threshold */
+# define TVDAC_C_SENSE			(1 << 28)
+/**
+ * Enables DAC state detection logic, for load-based TV detection.
+ *
+ * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
+ * to off, for load detection to work.
+ */
+# define TVDAC_STATE_CHG_EN		(1 << 27)
+/** Sets the DAC A sense value to high */
+# define TVDAC_A_SENSE_CTL		(1 << 26)
+/** Sets the DAC B sense value to high */
+# define TVDAC_B_SENSE_CTL		(1 << 25)
+/** Sets the DAC C sense value to high */
+# define TVDAC_C_SENSE_CTL		(1 << 24)
+/** Overrides the ENC_ENABLE and DAC voltage levels */
+# define DAC_CTL_OVERRIDE		(1 << 7)
+/** Sets the slew rate.  Must be preserved in software */
+# define ENC_TVDAC_SLEW_FAST		(1 << 6)
+# define DAC_A_1_3_V			(0 << 4)
+# define DAC_A_1_1_V			(1 << 4)
+# define DAC_A_0_7_V			(2 << 4)
+# define DAC_A_MASK			(3 << 4)
+# define DAC_B_1_3_V			(0 << 2)
+# define DAC_B_1_1_V			(1 << 2)
+# define DAC_B_0_7_V			(2 << 2)
+# define DAC_B_MASK			(3 << 2)
+# define DAC_C_1_3_V			(0 << 0)
+# define DAC_C_1_1_V			(1 << 0)
+# define DAC_C_0_7_V			(2 << 0)
+# define DAC_C_MASK			(3 << 0)
+
+/**
+ * CSC coefficients are stored in a floating point format with 9 bits of
+ * mantissa and 2 or 3 bits of exponent.  The exponent is represented as 2**-n,
+ * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
+ * -1 (0x3) being the only legal negative value.
+ */
+#define TV_CSC_Y		0x68010
+# define TV_RY_MASK			0x07ff0000
+# define TV_RY_SHIFT			16
+# define TV_GY_MASK			0x00000fff
+# define TV_GY_SHIFT			0
+
+#define TV_CSC_Y2		0x68014
+# define TV_BY_MASK			0x07ff0000
+# define TV_BY_SHIFT			16
+/**
+ * Y attenuation for component video.
+ *
+ * Stored in 1.9 fixed point.
+ */
+# define TV_AY_MASK			0x000003ff
+# define TV_AY_SHIFT			0
+
+#define TV_CSC_U		0x68018
+# define TV_RU_MASK			0x07ff0000
+# define TV_RU_SHIFT			16
+# define TV_GU_MASK			0x000007ff
+# define TV_GU_SHIFT			0
+
+#define TV_CSC_U2		0x6801c
+# define TV_BU_MASK			0x07ff0000
+# define TV_BU_SHIFT			16
+/**
+ * U attenuation for component video.
+ *
+ * Stored in 1.9 fixed point.
+ */
+# define TV_AU_MASK			0x000003ff
+# define TV_AU_SHIFT			0
+
+#define TV_CSC_V		0x68020
+# define TV_RV_MASK			0x0fff0000
+# define TV_RV_SHIFT			16
+# define TV_GV_MASK			0x000007ff
+# define TV_GV_SHIFT			0
+
+#define TV_CSC_V2		0x68024
+# define TV_BV_MASK			0x07ff0000
+# define TV_BV_SHIFT			16
+/**
+ * V attenuation for component video.
+ *
+ * Stored in 1.9 fixed point.
+ */
+# define TV_AV_MASK			0x000007ff
+# define TV_AV_SHIFT			0
+
+#define TV_CLR_KNOBS		0x68028
+/** 2s-complement brightness adjustment */
+# define TV_BRIGHTNESS_MASK		0xff000000
+# define TV_BRIGHTNESS_SHIFT		24
+/** Contrast adjustment, as a 2.6 unsigned floating point number */
+# define TV_CONTRAST_MASK		0x00ff0000
+# define TV_CONTRAST_SHIFT		16
+/** Saturation adjustment, as a 2.6 unsigned floating point number */
+# define TV_SATURATION_MASK		0x0000ff00
+# define TV_SATURATION_SHIFT		8
+/** Hue adjustment, as an integer phase angle in degrees */
+# define TV_HUE_MASK			0x000000ff
+# define TV_HUE_SHIFT			0
+
+#define TV_CLR_LEVEL		0x6802c
+/** Controls the DAC level for black */
+# define TV_BLACK_LEVEL_MASK		0x01ff0000
+# define TV_BLACK_LEVEL_SHIFT		16
+/** Controls the DAC level for blanking */
+# define TV_BLANK_LEVEL_MASK		0x000001ff
+# define TV_BLANK_LEVEL_SHIFT		0
+
+#define TV_H_CTL_1		0x68030
+/** Number of pixels in the hsync. */
+# define TV_HSYNC_END_MASK		0x1fff0000
+# define TV_HSYNC_END_SHIFT		16
+/** Total number of pixels minus one in the line (display and blanking). */
+# define TV_HTOTAL_MASK			0x00001fff
+# define TV_HTOTAL_SHIFT		0
+
+#define TV_H_CTL_2		0x68034
+/** Enables the colorburst (needed for non-component color) */
+# define TV_BURST_ENA			(1 << 31)
+/** Offset of the colorburst from the start of hsync, in pixels minus one. */
+# define TV_HBURST_START_SHIFT		16
+# define TV_HBURST_START_MASK		0x1fff0000
+/** Length of the colorburst */
+# define TV_HBURST_LEN_SHIFT		0
+# define TV_HBURST_LEN_MASK		0x0001fff
+
+#define TV_H_CTL_3		0x68038
+/** End of hblank, measured in pixels minus one from start of hsync */
+# define TV_HBLANK_END_SHIFT		16
+# define TV_HBLANK_END_MASK		0x1fff0000
+/** Start of hblank, measured in pixels minus one from start of hsync */
+# define TV_HBLANK_START_SHIFT		0
+# define TV_HBLANK_START_MASK		0x0001fff
+
+#define TV_V_CTL_1		0x6803c
+/** XXX */
+# define TV_NBR_END_SHIFT		16
+# define TV_NBR_END_MASK		0x07ff0000
+/** XXX */
+# define TV_VI_END_F1_SHIFT		8
+# define TV_VI_END_F1_MASK		0x00003f00
+/** XXX */
+# define TV_VI_END_F2_SHIFT		0
+# define TV_VI_END_F2_MASK		0x0000003f
+
+#define TV_V_CTL_2		0x68040
+/** Length of vsync, in half lines */
+# define TV_VSYNC_LEN_MASK		0x07ff0000
+# define TV_VSYNC_LEN_SHIFT		16
+/** Offset of the start of vsync in field 1, measured in one less than the
+ * number of half lines.
+ */
+# define TV_VSYNC_START_F1_MASK		0x00007f00
+# define TV_VSYNC_START_F1_SHIFT	8
+/**
+ * Offset of the start of vsync in field 2, measured in one less than the
+ * number of half lines.
+ */
+# define TV_VSYNC_START_F2_MASK		0x0000007f
+# define TV_VSYNC_START_F2_SHIFT	0
+
+#define TV_V_CTL_3		0x68044
+/** Enables generation of the equalization signal */
+# define TV_EQUAL_ENA			(1 << 31)
+/** Length of vsync, in half lines */
+# define TV_VEQ_LEN_MASK		0x007f0000
+# define TV_VEQ_LEN_SHIFT		16
+/** Offset of the start of equalization in field 1, measured in one less than
+ * the number of half lines.
+ */
+# define TV_VEQ_START_F1_MASK		0x0007f00
+# define TV_VEQ_START_F1_SHIFT		8
+/**
+ * Offset of the start of equalization in field 2, measured in one less than
+ * the number of half lines.
+ */
+# define TV_VEQ_START_F2_MASK		0x000007f
+# define TV_VEQ_START_F2_SHIFT		0
+
+#define TV_V_CTL_4		0x68048
+/**
+ * Offset to start of vertical colorburst, measured in one less than the
+ * number of lines from vertical start.
+ */
+# define TV_VBURST_START_F1_MASK	0x003f0000
+# define TV_VBURST_START_F1_SHIFT	16
+/**
+ * Offset to the end of vertical colorburst, measured in one less than the
+ * number of lines from the start of NBR.
+ */
+# define TV_VBURST_END_F1_MASK		0x000000ff
+# define TV_VBURST_END_F1_SHIFT		0
+
+#define TV_V_CTL_5		0x6804c
+/**
+ * Offset to start of vertical colorburst, measured in one less than the
+ * number of lines from vertical start.
+ */
+# define TV_VBURST_START_F2_MASK	0x003f0000
+# define TV_VBURST_START_F2_SHIFT	16
+/**
+ * Offset to the end of vertical colorburst, measured in one less than the
+ * number of lines from the start of NBR.
+ */
+# define TV_VBURST_END_F2_MASK		0x000000ff
+# define TV_VBURST_END_F2_SHIFT		0
+
+#define TV_V_CTL_6		0x68050
+/**
+ * Offset to start of vertical colorburst, measured in one less than the
+ * number of lines from vertical start.
+ */
+# define TV_VBURST_START_F3_MASK	0x003f0000
+# define TV_VBURST_START_F3_SHIFT	16
+/**
+ * Offset to the end of vertical colorburst, measured in one less than the
+ * number of lines from the start of NBR.
+ */
+# define TV_VBURST_END_F3_MASK		0x000000ff
+# define TV_VBURST_END_F3_SHIFT		0
+
+#define TV_V_CTL_7		0x68054
+/**
+ * Offset to start of vertical colorburst, measured in one less than the
+ * number of lines from vertical start.
+ */
+# define TV_VBURST_START_F4_MASK	0x003f0000
+# define TV_VBURST_START_F4_SHIFT	16
+/**
+ * Offset to the end of vertical colorburst, measured in one less than the
+ * number of lines from the start of NBR.
+ */
+# define TV_VBURST_END_F4_MASK		0x000000ff
+# define TV_VBURST_END_F4_SHIFT		0
+
+#define TV_SC_CTL_1		0x68060
+/** Turns on the first subcarrier phase generation DDA */
+# define TV_SC_DDA1_EN			(1 << 31)
+/** Turns on the first subcarrier phase generation DDA */
+# define TV_SC_DDA2_EN			(1 << 30)
+/** Turns on the first subcarrier phase generation DDA */
+# define TV_SC_DDA3_EN			(1 << 29)
+/** Sets the subcarrier DDA to reset frequency every other field */
+# define TV_SC_RESET_EVERY_2		(0 << 24)
+/** Sets the subcarrier DDA to reset frequency every fourth field */
+# define TV_SC_RESET_EVERY_4		(1 << 24)
+/** Sets the subcarrier DDA to reset frequency every eighth field */
+# define TV_SC_RESET_EVERY_8		(2 << 24)
+/** Sets the subcarrier DDA to never reset the frequency */
+# define TV_SC_RESET_NEVER		(3 << 24)
+/** Sets the peak amplitude of the colorburst.*/
+# define TV_BURST_LEVEL_MASK		0x00ff0000
+# define TV_BURST_LEVEL_SHIFT		16
+/** Sets the increment of the first subcarrier phase generation DDA */
+# define TV_SCDDA1_INC_MASK		0x00000fff
+# define TV_SCDDA1_INC_SHIFT		0
+
+#define TV_SC_CTL_2		0x68064
+/** Sets the rollover for the second subcarrier phase generation DDA */
+# define TV_SCDDA2_SIZE_MASK		0x7fff0000
+# define TV_SCDDA2_SIZE_SHIFT		16
+/** Sets the increent of the second subcarrier phase generation DDA */
+# define TV_SCDDA2_INC_MASK		0x00007fff
+# define TV_SCDDA2_INC_SHIFT		0
+
+#define TV_SC_CTL_3		0x68068
+/** Sets the rollover for the third subcarrier phase generation DDA */
+# define TV_SCDDA3_SIZE_MASK		0x7fff0000
+# define TV_SCDDA3_SIZE_SHIFT		16
+/** Sets the increent of the third subcarrier phase generation DDA */
+# define TV_SCDDA3_INC_MASK		0x00007fff
+# define TV_SCDDA3_INC_SHIFT		0
+
+#define TV_WIN_POS		0x68070
+/** X coordinate of the display from the start of horizontal active */
+# define TV_XPOS_MASK			0x1fff0000
+# define TV_XPOS_SHIFT			16
+/** Y coordinate of the display from the start of vertical active (NBR) */
+# define TV_YPOS_MASK			0x00000fff
+# define TV_YPOS_SHIFT			0
+
+#define TV_WIN_SIZE		0x68074
+/** Horizontal size of the display window, measured in pixels*/
+# define TV_XSIZE_MASK			0x1fff0000
+# define TV_XSIZE_SHIFT			16
+/**
+ * Vertical size of the display window, measured in pixels.
+ *
+ * Must be even for interlaced modes.
+ */
+# define TV_YSIZE_MASK			0x00000fff
+# define TV_YSIZE_SHIFT			0
+
+#define TV_FILTER_CTL_1		0x68080
+/**
+ * Enables automatic scaling calculation.
+ *
+ * If set, the rest of the registers are ignored, and the calculated values can
+ * be read back from the register.
+ */
+# define TV_AUTO_SCALE			(1 << 31)
+/**
+ * Disables the vertical filter.
+ *
+ * This is required on modes more than 1024 pixels wide */
+# define TV_V_FILTER_BYPASS		(1 << 29)
+/** Enables adaptive vertical filtering */
+# define TV_VADAPT			(1 << 28)
+# define TV_VADAPT_MODE_MASK		(3 << 26)
+/** Selects the least adaptive vertical filtering mode */
+# define TV_VADAPT_MODE_LEAST		(0 << 26)
+/** Selects the moderately adaptive vertical filtering mode */
+# define TV_VADAPT_MODE_MODERATE	(1 << 26)
+/** Selects the most adaptive vertical filtering mode */
+# define TV_VADAPT_MODE_MOST		(3 << 26)
+/**
+ * Sets the horizontal scaling factor.
+ *
+ * This should be the fractional part of the horizontal scaling factor divided
+ * by the oversampling rate.  TV_HSCALE should be less than 1, and set to:
+ *
+ * (src width - 1) / ((oversample * dest width) - 1)
+ */
+# define TV_HSCALE_FRAC_MASK		0x00003fff
+# define TV_HSCALE_FRAC_SHIFT		0
+
+#define TV_FILTER_CTL_2		0x68084
+/**
+ * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
+ *
+ * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
+ */
+# define TV_VSCALE_INT_MASK		0x00038000
+# define TV_VSCALE_INT_SHIFT		15
+/**
+ * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
+ *
+ * \sa TV_VSCALE_INT_MASK
+ */
+# define TV_VSCALE_FRAC_MASK		0x00007fff
+# define TV_VSCALE_FRAC_SHIFT		0
+
+#define TV_FILTER_CTL_3		0x68088
+/**
+ * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
+ *
+ * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
+ *
+ * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
+ */
+# define TV_VSCALE_IP_INT_MASK		0x00038000
+# define TV_VSCALE_IP_INT_SHIFT		15
+/**
+ * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
+ *
+ * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
+ *
+ * \sa TV_VSCALE_IP_INT_MASK
+ */
+# define TV_VSCALE_IP_FRAC_MASK		0x00007fff
+# define TV_VSCALE_IP_FRAC_SHIFT		0
+
+#define TV_CC_CONTROL		0x68090
+# define TV_CC_ENABLE			(1 << 31)
+/**
+ * Specifies which field to send the CC data in.
+ *
+ * CC data is usually sent in field 0.
+ */
+# define TV_CC_FID_MASK			(1 << 27)
+# define TV_CC_FID_SHIFT		27
+/** Sets the horizontal position of the CC data.  Usually 135. */
+# define TV_CC_HOFF_MASK		0x03ff0000
+# define TV_CC_HOFF_SHIFT		16
+/** Sets the vertical position of the CC data.  Usually 21 */
+# define TV_CC_LINE_MASK		0x0000003f
+# define TV_CC_LINE_SHIFT		0
+
+#define TV_CC_DATA		0x68094
+# define TV_CC_RDY			(1 << 31)
+/** Second word of CC data to be transmitted. */
+# define TV_CC_DATA_2_MASK		0x007f0000
+# define TV_CC_DATA_2_SHIFT		16
+/** First word of CC data to be transmitted. */
+# define TV_CC_DATA_1_MASK		0x0000007f
+# define TV_CC_DATA_1_SHIFT		0
+
+#define TV_H_LUMA_0		0x68100
+#define TV_H_LUMA_59		0x681ec
+#define TV_H_CHROMA_0		0x68200
+#define TV_H_CHROMA_59		0x682ec
+#define TV_V_LUMA_0		0x68300
+#define TV_V_LUMA_42		0x683a8
+#define TV_V_CHROMA_0		0x68400
+#define TV_V_CHROMA_42		0x684a8
+
+/* Display Port */
+#define DP_A				0x64000 /* eDP */
+#define DP_B				0x64100
+#define DP_C				0x64200
+#define DP_D				0x64300
+
+#define   DP_PORT_EN			(1 << 31)
+#define   DP_PIPEB_SELECT		(1 << 30)
+#define   DP_PIPE_MASK			(1 << 30)
+
+/* Link training mode - select a suitable mode for each stage */
+#define   DP_LINK_TRAIN_PAT_1		(0 << 28)
+#define   DP_LINK_TRAIN_PAT_2		(1 << 28)
+#define   DP_LINK_TRAIN_PAT_IDLE	(2 << 28)
+#define   DP_LINK_TRAIN_OFF		(3 << 28)
+#define   DP_LINK_TRAIN_MASK		(3 << 28)
+#define   DP_LINK_TRAIN_SHIFT		28
+
+/* CPT Link training mode */
+#define   DP_LINK_TRAIN_PAT_1_CPT	(0 << 8)
+#define   DP_LINK_TRAIN_PAT_2_CPT	(1 << 8)
+#define   DP_LINK_TRAIN_PAT_IDLE_CPT	(2 << 8)
+#define   DP_LINK_TRAIN_OFF_CPT		(3 << 8)
+#define   DP_LINK_TRAIN_MASK_CPT	(7 << 8)
+#define   DP_LINK_TRAIN_SHIFT_CPT	8
+
+/* Signal voltages. These are mostly controlled by the other end */
+#define   DP_VOLTAGE_0_4		(0 << 25)
+#define   DP_VOLTAGE_0_6		(1 << 25)
+#define   DP_VOLTAGE_0_8		(2 << 25)
+#define   DP_VOLTAGE_1_2		(3 << 25)
+#define   DP_VOLTAGE_MASK		(7 << 25)
+#define   DP_VOLTAGE_SHIFT		25
+
+/* Signal pre-emphasis levels, like voltages, the other end tells us what
+ * they want
+ */
+#define   DP_PRE_EMPHASIS_0		(0 << 22)
+#define   DP_PRE_EMPHASIS_3_5		(1 << 22)
+#define   DP_PRE_EMPHASIS_6		(2 << 22)
+#define   DP_PRE_EMPHASIS_9_5		(3 << 22)
+#define   DP_PRE_EMPHASIS_MASK		(7 << 22)
+#define   DP_PRE_EMPHASIS_SHIFT		22
+
+/* How many wires to use. I guess 3 was too hard */
+#define   DP_PORT_WIDTH_1		(0 << 19)
+#define   DP_PORT_WIDTH_2		(1 << 19)
+#define   DP_PORT_WIDTH_4		(3 << 19)
+#define   DP_PORT_WIDTH_MASK		(7 << 19)
+
+/* Mystic DPCD version 1.1 special mode */
+#define   DP_ENHANCED_FRAMING		(1 << 18)
+
+/* eDP */
+#define   DP_PLL_FREQ_270MHZ		(0 << 16)
+#define   DP_PLL_FREQ_160MHZ		(1 << 16)
+#define   DP_PLL_FREQ_MASK		(3 << 16)
+
+/** locked once port is enabled */
+#define   DP_PORT_REVERSAL		(1 << 15)
+
+/* eDP */
+#define   DP_PLL_ENABLE			(1 << 14)
+
+/** sends the clock on lane 15 of the PEG for debug */
+#define   DP_CLOCK_OUTPUT_ENABLE	(1 << 13)
+
+#define   DP_SCRAMBLING_DISABLE		(1 << 12)
+#define   DP_SCRAMBLING_DISABLE_IRONLAKE	(1 << 7)
+
+/** limit RGB values to avoid confusing TVs */
+#define   DP_COLOR_RANGE_16_235		(1 << 8)
+
+/** Turn on the audio link */
+#define   DP_AUDIO_OUTPUT_ENABLE	(1 << 6)
+
+/** vs and hs sync polarity */
+#define   DP_SYNC_VS_HIGH		(1 << 4)
+#define   DP_SYNC_HS_HIGH		(1 << 3)
+
+/** A fantasy */
+#define   DP_DETECTED			(1 << 2)
+
+/** The aux channel provides a way to talk to the
+ * signal sink for DDC etc. Max packet size supported
+ * is 20 bytes in each direction, hence the 5 fixed
+ * data registers
+ */
+#define DPA_AUX_CH_CTL			0x64010
+#define DPA_AUX_CH_DATA1		0x64014
+#define DPA_AUX_CH_DATA2		0x64018
+#define DPA_AUX_CH_DATA3		0x6401c
+#define DPA_AUX_CH_DATA4		0x64020
+#define DPA_AUX_CH_DATA5		0x64024
+
+#define DPB_AUX_CH_CTL			0x64110
+#define DPB_AUX_CH_DATA1		0x64114
+#define DPB_AUX_CH_DATA2		0x64118
+#define DPB_AUX_CH_DATA3		0x6411c
+#define DPB_AUX_CH_DATA4		0x64120
+#define DPB_AUX_CH_DATA5		0x64124
+
+#define DPC_AUX_CH_CTL			0x64210
+#define DPC_AUX_CH_DATA1		0x64214
+#define DPC_AUX_CH_DATA2		0x64218
+#define DPC_AUX_CH_DATA3		0x6421c
+#define DPC_AUX_CH_DATA4		0x64220
+#define DPC_AUX_CH_DATA5		0x64224
+
+#define DPD_AUX_CH_CTL			0x64310
+#define DPD_AUX_CH_DATA1		0x64314
+#define DPD_AUX_CH_DATA2		0x64318
+#define DPD_AUX_CH_DATA3		0x6431c
+#define DPD_AUX_CH_DATA4		0x64320
+#define DPD_AUX_CH_DATA5		0x64324
+
+#define   DP_AUX_CH_CTL_SEND_BUSY	    (1 << 31)
+#define   DP_AUX_CH_CTL_DONE		    (1 << 30)
+#define   DP_AUX_CH_CTL_INTERRUPT	    (1 << 29)
+#define   DP_AUX_CH_CTL_TIME_OUT_ERROR	    (1 << 28)
+#define   DP_AUX_CH_CTL_TIME_OUT_400us	    (0 << 26)
+#define   DP_AUX_CH_CTL_TIME_OUT_600us	    (1 << 26)
+#define   DP_AUX_CH_CTL_TIME_OUT_800us	    (2 << 26)
+#define   DP_AUX_CH_CTL_TIME_OUT_1600us	    (3 << 26)
+#define   DP_AUX_CH_CTL_TIME_OUT_MASK	    (3 << 26)
+#define   DP_AUX_CH_CTL_RECEIVE_ERROR	    (1 << 25)
+#define   DP_AUX_CH_CTL_MESSAGE_SIZE_MASK    (0x1f << 20)
+#define   DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT   20
+#define   DP_AUX_CH_CTL_PRECHARGE_2US_MASK   (0xf << 16)
+#define   DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT  16
+#define   DP_AUX_CH_CTL_AUX_AKSV_SELECT	    (1 << 15)
+#define   DP_AUX_CH_CTL_MANCHESTER_TEST	    (1 << 14)
+#define   DP_AUX_CH_CTL_SYNC_TEST	    (1 << 13)
+#define   DP_AUX_CH_CTL_DEGLITCH_TEST	    (1 << 12)
+#define   DP_AUX_CH_CTL_PRECHARGE_TEST	    (1 << 11)
+#define   DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK    (0x7ff)
+#define   DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT   0
+
+/*
+ * Computing GMCH M and N values for the Display Port link
+ *
+ * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
+ *
+ * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
+ *
+ * The GMCH value is used internally
+ *
+ * bytes_per_pixel is the number of bytes coming out of the plane,
+ * which is after the LUTs, so we want the bytes for our color format.
+ * For our current usage, this is always 3, one byte for R, G and B.
+ */
+#define _PIPEA_GMCH_DATA_M			0x70050
+#define _PIPEB_GMCH_DATA_M			0x71050
+
+/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
+#define   PIPE_GMCH_DATA_M_TU_SIZE_MASK		(0x3f << 25)
+#define   PIPE_GMCH_DATA_M_TU_SIZE_SHIFT	25
+
+#define   PIPE_GMCH_DATA_M_MASK			(0xffffff)
+
+#define _PIPEA_GMCH_DATA_N			0x70054
+#define _PIPEB_GMCH_DATA_N			0x71054
+#define   PIPE_GMCH_DATA_N_MASK			(0xffffff)
+
+/*
+ * Computing Link M and N values for the Display Port link
+ *
+ * Link M / N = pixel_clock / ls_clk
+ *
+ * (the DP spec calls pixel_clock the 'strm_clk')
+ *
+ * The Link value is transmitted in the Main Stream
+ * Attributes and VB-ID.
+ */
+
+#define _PIPEA_DP_LINK_M				0x70060
+#define _PIPEB_DP_LINK_M				0x71060
+#define   PIPEA_DP_LINK_M_MASK			(0xffffff)
+
+#define _PIPEA_DP_LINK_N				0x70064
+#define _PIPEB_DP_LINK_N				0x71064
+#define   PIPEA_DP_LINK_N_MASK			(0xffffff)
+
+#define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M)
+#define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N)
+#define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M)
+#define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N)
+
+/* Display & cursor control */
+
+/* Pipe A */
+#define _PIPEADSL		0x70000
+#define   DSL_LINEMASK		0x00000fff
+#define _PIPEACONF		0x70008
+#define   PIPECONF_ENABLE	(1<<31)
+#define   PIPECONF_DISABLE	0
+#define   PIPECONF_DOUBLE_WIDE	(1<<30)
+#define   I965_PIPECONF_ACTIVE	(1<<30)
+#define   PIPECONF_FRAME_START_DELAY_MASK (3<<27)
+#define   PIPECONF_SINGLE_WIDE	0
+#define   PIPECONF_PIPE_UNLOCKED 0
+#define   PIPECONF_PIPE_LOCKED	(1<<25)
+#define   PIPECONF_PALETTE	0
+#define   PIPECONF_GAMMA		(1<<24)
+#define   PIPECONF_FORCE_BORDER	(1<<25)
+#define   PIPECONF_INTERLACE_MASK	(7 << 21)
+/* Note that pre-gen3 does not support interlaced display directly. Panel
+ * fitting must be disabled on pre-ilk for interlaced. */
+#define   PIPECONF_PROGRESSIVE			(0 << 21)
+#define   PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL	(4 << 21) /* gen4 only */
+#define   PIPECONF_INTERLACE_W_SYNC_SHIFT	(5 << 21) /* gen4 only */
+#define   PIPECONF_INTERLACE_W_FIELD_INDICATION	(6 << 21)
+#define   PIPECONF_INTERLACE_FIELD_0_ONLY	(7 << 21) /* gen3 only */
+/* Ironlake and later have a complete new set of values for interlaced. PFIT
+ * means panel fitter required, PF means progressive fetch, DBL means power
+ * saving pixel doubling. */
+#define   PIPECONF_PFIT_PF_INTERLACED_ILK	(1 << 21)
+#define   PIPECONF_INTERLACED_ILK		(3 << 21)
+#define   PIPECONF_INTERLACED_DBL_ILK		(4 << 21) /* ilk/snb only */
+#define   PIPECONF_PFIT_PF_INTERLACED_DBL_ILK	(5 << 21) /* ilk/snb only */
+#define   PIPECONF_CXSR_DOWNCLOCK	(1<<16)
+#define   PIPECONF_BPP_MASK	(0x000000e0)
+#define   PIPECONF_BPP_8	(0<<5)
+#define   PIPECONF_BPP_10	(1<<5)
+#define   PIPECONF_BPP_6	(2<<5)
+#define   PIPECONF_BPP_12	(3<<5)
+#define   PIPECONF_DITHER_EN	(1<<4)
+#define   PIPECONF_DITHER_TYPE_MASK (0x0000000c)
+#define   PIPECONF_DITHER_TYPE_SP (0<<2)
+#define   PIPECONF_DITHER_TYPE_ST1 (1<<2)
+#define   PIPECONF_DITHER_TYPE_ST2 (2<<2)
+#define   PIPECONF_DITHER_TYPE_TEMP (3<<2)
+#define _PIPEASTAT		0x70024
+#define   PIPE_FIFO_UNDERRUN_STATUS		(1UL<<31)
+#define   PIPE_CRC_ERROR_ENABLE			(1UL<<29)
+#define   PIPE_CRC_DONE_ENABLE			(1UL<<28)
+#define   PIPE_GMBUS_EVENT_ENABLE		(1UL<<27)
+#define   PIPE_HOTPLUG_INTERRUPT_ENABLE		(1UL<<26)
+#define   PIPE_VSYNC_INTERRUPT_ENABLE		(1UL<<25)
+#define   PIPE_DISPLAY_LINE_COMPARE_ENABLE	(1UL<<24)
+#define   PIPE_DPST_EVENT_ENABLE		(1UL<<23)
+#define   PIPE_LEGACY_BLC_EVENT_ENABLE		(1UL<<22)
+#define   PIPE_ODD_FIELD_INTERRUPT_ENABLE	(1UL<<21)
+#define   PIPE_EVEN_FIELD_INTERRUPT_ENABLE	(1UL<<20)
+#define   PIPE_HOTPLUG_TV_INTERRUPT_ENABLE	(1UL<<18) /* pre-965 */
+#define   PIPE_START_VBLANK_INTERRUPT_ENABLE	(1UL<<18) /* 965 or later */
+#define   PIPE_VBLANK_INTERRUPT_ENABLE		(1UL<<17)
+#define   PIPE_OVERLAY_UPDATED_ENABLE		(1UL<<16)
+#define   PIPE_CRC_ERROR_INTERRUPT_STATUS	(1UL<<13)
+#define   PIPE_CRC_DONE_INTERRUPT_STATUS	(1UL<<12)
+#define   PIPE_GMBUS_INTERRUPT_STATUS		(1UL<<11)
+#define   PIPE_HOTPLUG_INTERRUPT_STATUS		(1UL<<10)
+#define   PIPE_VSYNC_INTERRUPT_STATUS		(1UL<<9)
+#define   PIPE_DISPLAY_LINE_COMPARE_STATUS	(1UL<<8)
+#define   PIPE_DPST_EVENT_STATUS		(1UL<<7)
+#define   PIPE_LEGACY_BLC_EVENT_STATUS		(1UL<<6)
+#define   PIPE_ODD_FIELD_INTERRUPT_STATUS	(1UL<<5)
+#define   PIPE_EVEN_FIELD_INTERRUPT_STATUS	(1UL<<4)
+#define   PIPE_HOTPLUG_TV_INTERRUPT_STATUS	(1UL<<2) /* pre-965 */
+#define   PIPE_START_VBLANK_INTERRUPT_STATUS	(1UL<<2) /* 965 or later */
+#define   PIPE_VBLANK_INTERRUPT_STATUS		(1UL<<1)
+#define   PIPE_OVERLAY_UPDATED_STATUS		(1UL<<0)
+#define   PIPE_BPC_MASK				(7 << 5) /* Ironlake */
+#define   PIPE_8BPC				(0 << 5)
+#define   PIPE_10BPC				(1 << 5)
+#define   PIPE_6BPC				(2 << 5)
+#define   PIPE_12BPC				(3 << 5)
+
+#define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)
+#define PIPECONF(pipe) _PIPE(pipe, _PIPEACONF, _PIPEBCONF)
+#define PIPEDSL(pipe)  _PIPE(pipe, _PIPEADSL, _PIPEBDSL)
+#define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH)
+#define PIPEFRAMEPIXEL(pipe)  _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
+#define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
+
+#define DSPARB			0x70030
+#define   DSPARB_CSTART_MASK	(0x7f << 7)
+#define   DSPARB_CSTART_SHIFT	7
+#define   DSPARB_BSTART_MASK	(0x7f)
+#define   DSPARB_BSTART_SHIFT	0
+#define   DSPARB_BEND_SHIFT	9 /* on 855 */
+#define   DSPARB_AEND_SHIFT	0
+
+#define DSPFW1			0x70034
+#define   DSPFW_SR_SHIFT	23
+#define   DSPFW_SR_MASK		(0x1ff<<23)
+#define   DSPFW_CURSORB_SHIFT	16
+#define   DSPFW_CURSORB_MASK	(0x3f<<16)
+#define   DSPFW_PLANEB_SHIFT	8
+#define   DSPFW_PLANEB_MASK	(0x7f<<8)
+#define   DSPFW_PLANEA_MASK	(0x7f)
+#define DSPFW2			0x70038
+#define   DSPFW_CURSORA_MASK	0x00003f00
+#define   DSPFW_CURSORA_SHIFT	8
+#define   DSPFW_PLANEC_MASK	(0x7f)
+#define DSPFW3			0x7003c
+#define   DSPFW_HPLL_SR_EN	(1<<31)
+#define   DSPFW_CURSOR_SR_SHIFT	24
+#define   PINEVIEW_SELF_REFRESH_EN	(1<<30)
+#define   DSPFW_CURSOR_SR_MASK		(0x3f<<24)
+#define   DSPFW_HPLL_CURSOR_SHIFT	16
+#define   DSPFW_HPLL_CURSOR_MASK	(0x3f<<16)
+#define   DSPFW_HPLL_SR_MASK		(0x1ff)
+
+/* FIFO watermark sizes etc */
+#define G4X_FIFO_LINE_SIZE	64
+#define I915_FIFO_LINE_SIZE	64
+#define I830_FIFO_LINE_SIZE	32
+
+#define G4X_FIFO_SIZE		127
+#define I965_FIFO_SIZE		512
+#define I945_FIFO_SIZE		127
+#define I915_FIFO_SIZE		95
+#define I855GM_FIFO_SIZE	127 /* In cachelines */
+#define I830_FIFO_SIZE		95
+
+#define G4X_MAX_WM		0x3f
+#define I915_MAX_WM		0x3f
+
+#define PINEVIEW_DISPLAY_FIFO	512 /* in 64byte unit */
+#define PINEVIEW_FIFO_LINE_SIZE	64
+#define PINEVIEW_MAX_WM		0x1ff
+#define PINEVIEW_DFT_WM		0x3f
+#define PINEVIEW_DFT_HPLLOFF_WM	0
+#define PINEVIEW_GUARD_WM		10
+#define PINEVIEW_CURSOR_FIFO		64
+#define PINEVIEW_CURSOR_MAX_WM	0x3f
+#define PINEVIEW_CURSOR_DFT_WM	0
+#define PINEVIEW_CURSOR_GUARD_WM	5
+
+#define I965_CURSOR_FIFO	64
+#define I965_CURSOR_MAX_WM	32
+#define I965_CURSOR_DFT_WM	8
+
+/* define the Watermark register on Ironlake */
+#define WM0_PIPEA_ILK		0x45100
+#define  WM0_PIPE_PLANE_MASK	(0x7f<<16)
+#define  WM0_PIPE_PLANE_SHIFT	16
+#define  WM0_PIPE_SPRITE_MASK	(0x3f<<8)
+#define  WM0_PIPE_SPRITE_SHIFT	8
+#define  WM0_PIPE_CURSOR_MASK	(0x1f)
+
+#define WM0_PIPEB_ILK		0x45104
+#define WM0_PIPEC_IVB		0x45200
+#define WM1_LP_ILK		0x45108
+#define  WM1_LP_SR_EN		(1<<31)
+#define  WM1_LP_LATENCY_SHIFT	24
+#define  WM1_LP_LATENCY_MASK	(0x7f<<24)
+#define  WM1_LP_FBC_MASK	(0xf<<20)
+#define  WM1_LP_FBC_SHIFT	20
+#define  WM1_LP_SR_MASK		(0x1ff<<8)
+#define  WM1_LP_SR_SHIFT	8
+#define  WM1_LP_CURSOR_MASK	(0x3f)
+#define WM2_LP_ILK		0x4510c
+#define  WM2_LP_EN		(1<<31)
+#define WM3_LP_ILK		0x45110
+#define  WM3_LP_EN		(1<<31)
+#define WM1S_LP_ILK		0x45120
+#define WM2S_LP_IVB		0x45124
+#define WM3S_LP_IVB		0x45128
+#define  WM1S_LP_EN		(1<<31)
+
+/* Memory latency timer register */
+#define MLTR_ILK		0x11222
+#define  MLTR_WM1_SHIFT		0
+#define  MLTR_WM2_SHIFT		8
+/* the unit of memory self-refresh latency time is 0.5us */
+#define  ILK_SRLT_MASK		0x3f
+#define ILK_LATENCY(shift)	(I915_READ(MLTR_ILK) >> (shift) & ILK_SRLT_MASK)
+#define ILK_READ_WM1_LATENCY()	ILK_LATENCY(MLTR_WM1_SHIFT)
+#define ILK_READ_WM2_LATENCY()	ILK_LATENCY(MLTR_WM2_SHIFT)
+
+/* define the fifo size on Ironlake */
+#define ILK_DISPLAY_FIFO	128
+#define ILK_DISPLAY_MAXWM	64
+#define ILK_DISPLAY_DFTWM	8
+#define ILK_CURSOR_FIFO		32
+#define ILK_CURSOR_MAXWM	16
+#define ILK_CURSOR_DFTWM	8
+
+#define ILK_DISPLAY_SR_FIFO	512
+#define ILK_DISPLAY_MAX_SRWM	0x1ff
+#define ILK_DISPLAY_DFT_SRWM	0x3f
+#define ILK_CURSOR_SR_FIFO	64
+#define ILK_CURSOR_MAX_SRWM	0x3f
+#define ILK_CURSOR_DFT_SRWM	8
+
+#define ILK_FIFO_LINE_SIZE	64
+
+/* define the WM info on Sandybridge */
+#define SNB_DISPLAY_FIFO	128
+#define SNB_DISPLAY_MAXWM	0x7f	/* bit 16:22 */
+#define SNB_DISPLAY_DFTWM	8
+#define SNB_CURSOR_FIFO		32
+#define SNB_CURSOR_MAXWM	0x1f	/* bit 4:0 */
+#define SNB_CURSOR_DFTWM	8
+
+#define SNB_DISPLAY_SR_FIFO	512
+#define SNB_DISPLAY_MAX_SRWM	0x1ff	/* bit 16:8 */
+#define SNB_DISPLAY_DFT_SRWM	0x3f
+#define SNB_CURSOR_SR_FIFO	64
+#define SNB_CURSOR_MAX_SRWM	0x3f	/* bit 5:0 */
+#define SNB_CURSOR_DFT_SRWM	8
+
+#define SNB_FBC_MAX_SRWM	0xf	/* bit 23:20 */
+
+#define SNB_FIFO_LINE_SIZE	64
+
+
+/* the address where we get all kinds of latency value */
+#define SSKPD			0x5d10
+#define SSKPD_WM_MASK		0x3f
+#define SSKPD_WM0_SHIFT		0
+#define SSKPD_WM1_SHIFT		8
+#define SSKPD_WM2_SHIFT		16
+#define SSKPD_WM3_SHIFT		24
+
+#define SNB_LATENCY(shift)	(I915_READ(MCHBAR_MIRROR_BASE_SNB + SSKPD) >> (shift) & SSKPD_WM_MASK)
+#define SNB_READ_WM0_LATENCY()		SNB_LATENCY(SSKPD_WM0_SHIFT)
+#define SNB_READ_WM1_LATENCY()		SNB_LATENCY(SSKPD_WM1_SHIFT)
+#define SNB_READ_WM2_LATENCY()		SNB_LATENCY(SSKPD_WM2_SHIFT)
+#define SNB_READ_WM3_LATENCY()		SNB_LATENCY(SSKPD_WM3_SHIFT)
+
+/*
+ * The two pipe frame counter registers are not synchronized, so
+ * reading a stable value is somewhat tricky. The following code
+ * should work:
+ *
+ *  do {
+ *    high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
+ *             PIPE_FRAME_HIGH_SHIFT;
+ *    low1 =  ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
+ *             PIPE_FRAME_LOW_SHIFT);
+ *    high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
+ *             PIPE_FRAME_HIGH_SHIFT);
+ *  } while (high1 != high2);
+ *  frame = (high1 << 8) | low1;
+ */
+#define _PIPEAFRAMEHIGH          0x70040
+#define   PIPE_FRAME_HIGH_MASK    0x0000ffff
+#define   PIPE_FRAME_HIGH_SHIFT   0
+#define _PIPEAFRAMEPIXEL         0x70044
+#define   PIPE_FRAME_LOW_MASK     0xff000000
+#define   PIPE_FRAME_LOW_SHIFT    24
+#define   PIPE_PIXEL_MASK         0x00ffffff
+#define   PIPE_PIXEL_SHIFT        0
+/* GM45+ just has to be different */
+#define _PIPEA_FRMCOUNT_GM45	0x70040
+#define _PIPEA_FLIPCOUNT_GM45	0x70044
+#define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
+
+/* Cursor A & B regs */
+#define _CURACNTR		0x70080
+/* Old style CUR*CNTR flags (desktop 8xx) */
+#define   CURSOR_ENABLE		0x80000000
+#define   CURSOR_GAMMA_ENABLE	0x40000000
+#define   CURSOR_STRIDE_MASK	0x30000000
+#define   CURSOR_FORMAT_SHIFT	24
+#define   CURSOR_FORMAT_MASK	(0x07 << CURSOR_FORMAT_SHIFT)
+#define   CURSOR_FORMAT_2C	(0x00 << CURSOR_FORMAT_SHIFT)
+#define   CURSOR_FORMAT_3C	(0x01 << CURSOR_FORMAT_SHIFT)
+#define   CURSOR_FORMAT_4C	(0x02 << CURSOR_FORMAT_SHIFT)
+#define   CURSOR_FORMAT_ARGB	(0x04 << CURSOR_FORMAT_SHIFT)
+#define   CURSOR_FORMAT_XRGB	(0x05 << CURSOR_FORMAT_SHIFT)
+/* New style CUR*CNTR flags */
+#define   CURSOR_MODE		0x27
+#define   CURSOR_MODE_DISABLE   0x00
+#define   CURSOR_MODE_64_32B_AX 0x07
+#define   CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
+#define   MCURSOR_PIPE_SELECT	(1 << 28)
+#define   MCURSOR_PIPE_A	0x00
+#define   MCURSOR_PIPE_B	(1 << 28)
+#define   MCURSOR_GAMMA_ENABLE  (1 << 26)
+#define _CURABASE		0x70084
+#define _CURAPOS			0x70088
+#define   CURSOR_POS_MASK       0x007FF
+#define   CURSOR_POS_SIGN       0x8000
+#define   CURSOR_X_SHIFT        0
+#define   CURSOR_Y_SHIFT        16
+#define CURSIZE			0x700a0
+#define _CURBCNTR		0x700c0
+#define _CURBBASE		0x700c4
+#define _CURBPOS			0x700c8
+
+#define _CURBCNTR_IVB		0x71080
+#define _CURBBASE_IVB		0x71084
+#define _CURBPOS_IVB		0x71088
+
+#define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR)
+#define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE)
+#define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS)
+
+#define CURCNTR_IVB(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR_IVB)
+#define CURBASE_IVB(pipe) _PIPE(pipe, _CURABASE, _CURBBASE_IVB)
+#define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB)
+
+/* Display A control */
+#define _DSPACNTR                0x70180
+#define   DISPLAY_PLANE_ENABLE			(1<<31)
+#define   DISPLAY_PLANE_DISABLE			0
+#define   DISPPLANE_GAMMA_ENABLE		(1<<30)
+#define   DISPPLANE_GAMMA_DISABLE		0
+#define   DISPPLANE_PIXFORMAT_MASK		(0xf<<26)
+#define   DISPPLANE_8BPP			(0x2<<26)
+#define   DISPPLANE_15_16BPP			(0x4<<26)
+#define   DISPPLANE_16BPP			(0x5<<26)
+#define   DISPPLANE_32BPP_NO_ALPHA		(0x6<<26)
+#define   DISPPLANE_32BPP			(0x7<<26)
+#define   DISPPLANE_32BPP_30BIT_NO_ALPHA	(0xa<<26)
+#define   DISPPLANE_STEREO_ENABLE		(1<<25)
+#define   DISPPLANE_STEREO_DISABLE		0
+#define   DISPPLANE_SEL_PIPE_SHIFT		24
+#define   DISPPLANE_SEL_PIPE_MASK		(3<<DISPPLANE_SEL_PIPE_SHIFT)
+#define   DISPPLANE_SEL_PIPE_A			0
+#define   DISPPLANE_SEL_PIPE_B			(1<<DISPPLANE_SEL_PIPE_SHIFT)
+#define   DISPPLANE_SRC_KEY_ENABLE		(1<<22)
+#define   DISPPLANE_SRC_KEY_DISABLE		0
+#define   DISPPLANE_LINE_DOUBLE			(1<<20)
+#define   DISPPLANE_NO_LINE_DOUBLE		0
+#define   DISPPLANE_STEREO_POLARITY_FIRST	0
+#define   DISPPLANE_STEREO_POLARITY_SECOND	(1<<18)
+#define   DISPPLANE_TRICKLE_FEED_DISABLE	(1<<14) /* Ironlake */
+#define   DISPPLANE_TILED			(1<<10)
+#define _DSPAADDR		0x70184
+#define _DSPASTRIDE		0x70188
+#define _DSPAPOS			0x7018C /* reserved */
+#define _DSPASIZE		0x70190
+#define _DSPASURF		0x7019C /* 965+ only */
+#define _DSPATILEOFF		0x701A4 /* 965+ only */
+
+#define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR)
+#define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR)
+#define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE)
+#define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS)
+#define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE)
+#define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF)
+#define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF)
+
+/* VBIOS flags */
+#define SWF00			0x71410
+#define SWF01			0x71414
+#define SWF02			0x71418
+#define SWF03			0x7141c
+#define SWF04			0x71420
+#define SWF05			0x71424
+#define SWF06			0x71428
+#define SWF10			0x70410
+#define SWF11			0x70414
+#define SWF14			0x71420
+#define SWF30			0x72414
+#define SWF31			0x72418
+#define SWF32			0x7241c
+
+/* Pipe B */
+#define _PIPEBDSL		0x71000
+#define _PIPEBCONF		0x71008
+#define _PIPEBSTAT		0x71024
+#define _PIPEBFRAMEHIGH		0x71040
+#define _PIPEBFRAMEPIXEL		0x71044
+#define _PIPEB_FRMCOUNT_GM45	0x71040
+#define _PIPEB_FLIPCOUNT_GM45	0x71044
+
+
+/* Display B control */
+#define _DSPBCNTR		0x71180
+#define   DISPPLANE_ALPHA_TRANS_ENABLE		(1<<15)
+#define   DISPPLANE_ALPHA_TRANS_DISABLE		0
+#define   DISPPLANE_SPRITE_ABOVE_DISPLAY	0
+#define   DISPPLANE_SPRITE_ABOVE_OVERLAY	(1)
+#define _DSPBADDR		0x71184
+#define _DSPBSTRIDE		0x71188
+#define _DSPBPOS			0x7118C
+#define _DSPBSIZE		0x71190
+#define _DSPBSURF		0x7119C
+#define _DSPBTILEOFF		0x711A4
+
+/* Sprite A control */
+#define _DVSACNTR		0x72180
+#define   DVS_ENABLE		(1<<31)
+#define   DVS_GAMMA_ENABLE	(1<<30)
+#define   DVS_PIXFORMAT_MASK	(3<<25)
+#define   DVS_FORMAT_YUV422	(0<<25)
+#define   DVS_FORMAT_RGBX101010	(1<<25)
+#define   DVS_FORMAT_RGBX888	(2<<25)
+#define   DVS_FORMAT_RGBX161616	(3<<25)
+#define   DVS_SOURCE_KEY	(1<<22)
+#define   DVS_RGB_ORDER_XBGR	(1<<20)
+#define   DVS_YUV_BYTE_ORDER_MASK (3<<16)
+#define   DVS_YUV_ORDER_YUYV	(0<<16)
+#define   DVS_YUV_ORDER_UYVY	(1<<16)
+#define   DVS_YUV_ORDER_YVYU	(2<<16)
+#define   DVS_YUV_ORDER_VYUY	(3<<16)
+#define   DVS_DEST_KEY		(1<<2)
+#define   DVS_TRICKLE_FEED_DISABLE (1<<14)
+#define   DVS_TILED		(1<<10)
+#define _DVSALINOFF		0x72184
+#define _DVSASTRIDE		0x72188
+#define _DVSAPOS		0x7218c
+#define _DVSASIZE		0x72190
+#define _DVSAKEYVAL		0x72194
+#define _DVSAKEYMSK		0x72198
+#define _DVSASURF		0x7219c
+#define _DVSAKEYMAXVAL		0x721a0
+#define _DVSATILEOFF		0x721a4
+#define _DVSASURFLIVE		0x721ac
+#define _DVSASCALE		0x72204
+#define   DVS_SCALE_ENABLE	(1<<31)
+#define   DVS_FILTER_MASK	(3<<29)
+#define   DVS_FILTER_MEDIUM	(0<<29)
+#define   DVS_FILTER_ENHANCING	(1<<29)
+#define   DVS_FILTER_SOFTENING	(2<<29)
+#define   DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
+#define   DVS_VERTICAL_OFFSET_ENABLE (1<<27)
+#define _DVSAGAMC		0x72300
+
+#define _DVSBCNTR		0x73180
+#define _DVSBLINOFF		0x73184
+#define _DVSBSTRIDE		0x73188
+#define _DVSBPOS		0x7318c
+#define _DVSBSIZE		0x73190
+#define _DVSBKEYVAL		0x73194
+#define _DVSBKEYMSK		0x73198
+#define _DVSBSURF		0x7319c
+#define _DVSBKEYMAXVAL		0x731a0
+#define _DVSBTILEOFF		0x731a4
+#define _DVSBSURFLIVE		0x731ac
+#define _DVSBSCALE		0x73204
+#define _DVSBGAMC		0x73300
+
+#define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR)
+#define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
+#define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
+#define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS)
+#define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF)
+#define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
+#define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE)
+#define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE)
+#define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
+#define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
+#define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
+
+#define _SPRA_CTL		0x70280
+#define   SPRITE_ENABLE			(1<<31)
+#define   SPRITE_GAMMA_ENABLE		(1<<30)
+#define   SPRITE_PIXFORMAT_MASK		(7<<25)
+#define   SPRITE_FORMAT_YUV422		(0<<25)
+#define   SPRITE_FORMAT_RGBX101010	(1<<25)
+#define   SPRITE_FORMAT_RGBX888		(2<<25)
+#define   SPRITE_FORMAT_RGBX161616	(3<<25)
+#define   SPRITE_FORMAT_YUV444		(4<<25)
+#define   SPRITE_FORMAT_XR_BGR101010	(5<<25) /* Extended range */
+#define   SPRITE_CSC_ENABLE		(1<<24)
+#define   SPRITE_SOURCE_KEY		(1<<22)
+#define   SPRITE_RGB_ORDER_RGBX		(1<<20) /* only for 888 and 161616 */
+#define   SPRITE_YUV_TO_RGB_CSC_DISABLE	(1<<19)
+#define   SPRITE_YUV_CSC_FORMAT_BT709	(1<<18) /* 0 is BT601 */
+#define   SPRITE_YUV_BYTE_ORDER_MASK	(3<<16)
+#define   SPRITE_YUV_ORDER_YUYV		(0<<16)
+#define   SPRITE_YUV_ORDER_UYVY		(1<<16)
+#define   SPRITE_YUV_ORDER_YVYU		(2<<16)
+#define   SPRITE_YUV_ORDER_VYUY		(3<<16)
+#define   SPRITE_TRICKLE_FEED_DISABLE	(1<<14)
+#define   SPRITE_INT_GAMMA_ENABLE	(1<<13)
+#define   SPRITE_TILED			(1<<10)
+#define   SPRITE_DEST_KEY		(1<<2)
+#define _SPRA_LINOFF		0x70284
+#define _SPRA_STRIDE		0x70288
+#define _SPRA_POS		0x7028c
+#define _SPRA_SIZE		0x70290
+#define _SPRA_KEYVAL		0x70294
+#define _SPRA_KEYMSK		0x70298
+#define _SPRA_SURF		0x7029c
+#define _SPRA_KEYMAX		0x702a0
+#define _SPRA_TILEOFF		0x702a4
+#define _SPRA_SCALE		0x70304
+#define   SPRITE_SCALE_ENABLE	(1<<31)
+#define   SPRITE_FILTER_MASK	(3<<29)
+#define   SPRITE_FILTER_MEDIUM	(0<<29)
+#define   SPRITE_FILTER_ENHANCING	(1<<29)
+#define   SPRITE_FILTER_SOFTENING	(2<<29)
+#define   SPRITE_VERTICAL_OFFSET_HALF	(1<<28) /* must be enabled below */
+#define   SPRITE_VERTICAL_OFFSET_ENABLE	(1<<27)
+#define _SPRA_GAMC		0x70400
+
+#define _SPRB_CTL		0x71280
+#define _SPRB_LINOFF		0x71284
+#define _SPRB_STRIDE		0x71288
+#define _SPRB_POS		0x7128c
+#define _SPRB_SIZE		0x71290
+#define _SPRB_KEYVAL		0x71294
+#define _SPRB_KEYMSK		0x71298
+#define _SPRB_SURF		0x7129c
+#define _SPRB_KEYMAX		0x712a0
+#define _SPRB_TILEOFF		0x712a4
+#define _SPRB_SCALE		0x71304
+#define _SPRB_GAMC		0x71400
+
+#define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
+#define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
+#define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
+#define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS)
+#define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
+#define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
+#define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
+#define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
+#define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
+#define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
+#define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
+#define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
+
+/* VBIOS regs */
+#define VGACNTRL		0x71400
+# define VGA_DISP_DISABLE			(1 << 31)
+# define VGA_2X_MODE				(1 << 30)
+# define VGA_PIPE_B_SELECT			(1 << 29)
+
+/* Ironlake */
+
+#define CPU_VGACNTRL	0x41000
+
+#define DIGITAL_PORT_HOTPLUG_CNTRL      0x44030
+#define  DIGITAL_PORTA_HOTPLUG_ENABLE           (1 << 4)
+#define  DIGITAL_PORTA_SHORT_PULSE_2MS          (0 << 2)
+#define  DIGITAL_PORTA_SHORT_PULSE_4_5MS        (1 << 2)
+#define  DIGITAL_PORTA_SHORT_PULSE_6MS          (2 << 2)
+#define  DIGITAL_PORTA_SHORT_PULSE_100MS        (3 << 2)
+#define  DIGITAL_PORTA_NO_DETECT                (0 << 0)
+#define  DIGITAL_PORTA_LONG_PULSE_DETECT_MASK   (1 << 1)
+#define  DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK  (1 << 0)
+
+/* refresh rate hardware control */
+#define RR_HW_CTL       0x45300
+#define  RR_HW_LOW_POWER_FRAMES_MASK    0xff
+#define  RR_HW_HIGH_POWER_FRAMES_MASK   0xff00
+
+#define FDI_PLL_BIOS_0  0x46000
+#define  FDI_PLL_FB_CLOCK_MASK  0xff
+#define FDI_PLL_BIOS_1  0x46004
+#define FDI_PLL_BIOS_2  0x46008
+#define DISPLAY_PORT_PLL_BIOS_0         0x4600c
+#define DISPLAY_PORT_PLL_BIOS_1         0x46010
+#define DISPLAY_PORT_PLL_BIOS_2         0x46014
+
+#define PCH_DSPCLK_GATE_D	0x42020
+# define DPFCUNIT_CLOCK_GATE_DISABLE		(1 << 9)
+# define DPFCRUNIT_CLOCK_GATE_DISABLE		(1 << 8)
+# define DPFDUNIT_CLOCK_GATE_DISABLE		(1 << 7)
+# define DPARBUNIT_CLOCK_GATE_DISABLE		(1 << 5)
+
+#define PCH_3DCGDIS0		0x46020
+# define MARIUNIT_CLOCK_GATE_DISABLE		(1 << 18)
+# define SVSMUNIT_CLOCK_GATE_DISABLE		(1 << 1)
+
+#define PCH_3DCGDIS1		0x46024
+# define VFMUNIT_CLOCK_GATE_DISABLE		(1 << 11)
+
+#define FDI_PLL_FREQ_CTL        0x46030
+#define  FDI_PLL_FREQ_CHANGE_REQUEST    (1<<24)
+#define  FDI_PLL_FREQ_LOCK_LIMIT_MASK   0xfff00
+#define  FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK  0xff
+
+
+#define _PIPEA_DATA_M1           0x60030
+#define  TU_SIZE(x)             (((x)-1) << 25) /* default size 64 */
+#define  TU_SIZE_MASK           0x7e000000
+#define  PIPE_DATA_M1_OFFSET    0
+#define _PIPEA_DATA_N1           0x60034
+#define  PIPE_DATA_N1_OFFSET    0
+
+#define _PIPEA_DATA_M2           0x60038
+#define  PIPE_DATA_M2_OFFSET    0
+#define _PIPEA_DATA_N2           0x6003c
+#define  PIPE_DATA_N2_OFFSET    0
+
+#define _PIPEA_LINK_M1           0x60040
+#define  PIPE_LINK_M1_OFFSET    0
+#define _PIPEA_LINK_N1           0x60044
+#define  PIPE_LINK_N1_OFFSET    0
+
+#define _PIPEA_LINK_M2           0x60048
+#define  PIPE_LINK_M2_OFFSET    0
+#define _PIPEA_LINK_N2           0x6004c
+#define  PIPE_LINK_N2_OFFSET    0
+
+/* PIPEB timing regs are same start from 0x61000 */
+
+#define _PIPEB_DATA_M1           0x61030
+#define _PIPEB_DATA_N1           0x61034
+
+#define _PIPEB_DATA_M2           0x61038
+#define _PIPEB_DATA_N2           0x6103c
+
+#define _PIPEB_LINK_M1           0x61040
+#define _PIPEB_LINK_N1           0x61044
+
+#define _PIPEB_LINK_M2           0x61048
+#define _PIPEB_LINK_N2           0x6104c
+
+#define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
+#define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
+#define PIPE_DATA_M2(pipe) _PIPE(pipe, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
+#define PIPE_DATA_N2(pipe) _PIPE(pipe, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
+#define PIPE_LINK_M1(pipe) _PIPE(pipe, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
+#define PIPE_LINK_N1(pipe) _PIPE(pipe, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
+#define PIPE_LINK_M2(pipe) _PIPE(pipe, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
+#define PIPE_LINK_N2(pipe) _PIPE(pipe, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
+
+/* CPU panel fitter */
+/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
+#define _PFA_CTL_1               0x68080
+#define _PFB_CTL_1               0x68880
+#define  PF_ENABLE              (1<<31)
+#define  PF_FILTER_MASK		(3<<23)
+#define  PF_FILTER_PROGRAMMED	(0<<23)
+#define  PF_FILTER_MED_3x3	(1<<23)
+#define  PF_FILTER_EDGE_ENHANCE	(2<<23)
+#define  PF_FILTER_EDGE_SOFTEN	(3<<23)
+#define _PFA_WIN_SZ		0x68074
+#define _PFB_WIN_SZ		0x68874
+#define _PFA_WIN_POS		0x68070
+#define _PFB_WIN_POS		0x68870
+#define _PFA_VSCALE		0x68084
+#define _PFB_VSCALE		0x68884
+#define _PFA_HSCALE		0x68090
+#define _PFB_HSCALE		0x68890
+
+#define PF_CTL(pipe)		_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
+#define PF_WIN_SZ(pipe)		_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
+#define PF_WIN_POS(pipe)	_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
+#define PF_VSCALE(pipe)		_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
+#define PF_HSCALE(pipe)		_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
+
+/* legacy palette */
+#define _LGC_PALETTE_A           0x4a000
+#define _LGC_PALETTE_B           0x4a800
+#define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
+
+/* interrupts */
+#define DE_MASTER_IRQ_CONTROL   (1 << 31)
+#define DE_SPRITEB_FLIP_DONE    (1 << 29)
+#define DE_SPRITEA_FLIP_DONE    (1 << 28)
+#define DE_PLANEB_FLIP_DONE     (1 << 27)
+#define DE_PLANEA_FLIP_DONE     (1 << 26)
+#define DE_PCU_EVENT            (1 << 25)
+#define DE_GTT_FAULT            (1 << 24)
+#define DE_POISON               (1 << 23)
+#define DE_PERFORM_COUNTER      (1 << 22)
+#define DE_PCH_EVENT            (1 << 21)
+#define DE_AUX_CHANNEL_A        (1 << 20)
+#define DE_DP_A_HOTPLUG         (1 << 19)
+#define DE_GSE                  (1 << 18)
+#define DE_PIPEB_VBLANK         (1 << 15)
+#define DE_PIPEB_EVEN_FIELD     (1 << 14)
+#define DE_PIPEB_ODD_FIELD      (1 << 13)
+#define DE_PIPEB_LINE_COMPARE   (1 << 12)
+#define DE_PIPEB_VSYNC          (1 << 11)
+#define DE_PIPEB_FIFO_UNDERRUN  (1 << 8)
+#define DE_PIPEA_VBLANK         (1 << 7)
+#define DE_PIPEA_EVEN_FIELD     (1 << 6)
+#define DE_PIPEA_ODD_FIELD      (1 << 5)
+#define DE_PIPEA_LINE_COMPARE   (1 << 4)
+#define DE_PIPEA_VSYNC          (1 << 3)
+#define DE_PIPEA_FIFO_UNDERRUN  (1 << 0)
+
+/* More Ivybridge lolz */
+#define DE_ERR_DEBUG_IVB		(1<<30)
+#define DE_GSE_IVB			(1<<29)
+#define DE_PCH_EVENT_IVB		(1<<28)
+#define DE_DP_A_HOTPLUG_IVB		(1<<27)
+#define DE_AUX_CHANNEL_A_IVB		(1<<26)
+#define DE_SPRITEB_FLIP_DONE_IVB	(1<<9)
+#define DE_SPRITEA_FLIP_DONE_IVB	(1<<4)
+#define DE_PLANEB_FLIP_DONE_IVB		(1<<8)
+#define DE_PLANEA_FLIP_DONE_IVB		(1<<3)
+#define DE_PIPEB_VBLANK_IVB		(1<<5)
+#define DE_PIPEA_VBLANK_IVB		(1<<0)
+
+#define DEISR   0x44000
+#define DEIMR   0x44004
+#define DEIIR   0x44008
+#define DEIER   0x4400c
+
+/* GT interrupt */
+#define GT_PIPE_NOTIFY		(1 << 4)
+#define GT_SYNC_STATUS          (1 << 2)
+#define GT_USER_INTERRUPT       (1 << 0)
+#define GT_BSD_USER_INTERRUPT   (1 << 5)
+#define GT_GEN6_BSD_USER_INTERRUPT	(1 << 12)
+#define GT_BLT_USER_INTERRUPT	(1 << 22)
+
+#define GTISR   0x44010
+#define GTIMR   0x44014
+#define GTIIR   0x44018
+#define GTIER   0x4401c
+
+#define ILK_DISPLAY_CHICKEN2	0x42004
+/* Required on all Ironlake and Sandybridge according to the B-Spec. */
+#define  ILK_ELPIN_409_SELECT	(1 << 25)
+#define  ILK_DPARB_GATE	(1<<22)
+#define  ILK_VSDPFD_FULL	(1<<21)
+#define ILK_DISPLAY_CHICKEN_FUSES	0x42014
+#define  ILK_INTERNAL_GRAPHICS_DISABLE	(1<<31)
+#define  ILK_INTERNAL_DISPLAY_DISABLE	(1<<30)
+#define  ILK_DISPLAY_DEBUG_DISABLE	(1<<29)
+#define  ILK_HDCP_DISABLE		(1<<25)
+#define  ILK_eDP_A_DISABLE		(1<<24)
+#define  ILK_DESKTOP			(1<<23)
+#define ILK_DSPCLK_GATE		0x42020
+#define  IVB_VRHUNIT_CLK_GATE	(1<<28)
+#define  ILK_DPARB_CLK_GATE	(1<<5)
+#define  ILK_DPFD_CLK_GATE	(1<<7)
+
+/* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */
+#define   ILK_CLK_FBC		(1<<7)
+#define   ILK_DPFC_DIS1		(1<<8)
+#define   ILK_DPFC_DIS2		(1<<9)
+
+#define IVB_CHICKEN3	0x4200c
+# define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE	(1 << 5)
+# define CHICKEN3_DGMG_DONE_FIX_DISABLE		(1 << 2)
+
+#define DISP_ARB_CTL	0x45000
+#define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)
+#define  DISP_FBC_WM_DIS		(1<<15)
+
+/* GEN7 chicken */
+#define GEN7_COMMON_SLICE_CHICKEN1		0x7010
+# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	((1<<10) | (1<<26))
+
+#define GEN7_L3CNTLREG1				0xB01C
+#define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C4FFF8C
+
+#define GEN7_L3_CHICKEN_MODE_REGISTER		0xB030
+#define  GEN7_WA_L3_CHICKEN_MODE				0x20000000
+
+/* WaCatErrorRejectionIssue */
+#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
+#define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
+
+/* PCH */
+
+/* south display engine interrupt */
+#define SDE_AUDIO_POWER_D	(1 << 27)
+#define SDE_AUDIO_POWER_C	(1 << 26)
+#define SDE_AUDIO_POWER_B	(1 << 25)
+#define SDE_AUDIO_POWER_SHIFT	(25)
+#define SDE_AUDIO_POWER_MASK	(7 << SDE_AUDIO_POWER_SHIFT)
+#define SDE_GMBUS		(1 << 24)
+#define SDE_AUDIO_HDCP_TRANSB	(1 << 23)
+#define SDE_AUDIO_HDCP_TRANSA	(1 << 22)
+#define SDE_AUDIO_HDCP_MASK	(3 << 22)
+#define SDE_AUDIO_TRANSB	(1 << 21)
+#define SDE_AUDIO_TRANSA	(1 << 20)
+#define SDE_AUDIO_TRANS_MASK	(3 << 20)
+#define SDE_POISON		(1 << 19)
+/* 18 reserved */
+#define SDE_FDI_RXB		(1 << 17)
+#define SDE_FDI_RXA		(1 << 16)
+#define SDE_FDI_MASK		(3 << 16)
+#define SDE_AUXD		(1 << 15)
+#define SDE_AUXC		(1 << 14)
+#define SDE_AUXB		(1 << 13)
+#define SDE_AUX_MASK		(7 << 13)
+/* 12 reserved */
+#define SDE_CRT_HOTPLUG         (1 << 11)
+#define SDE_PORTD_HOTPLUG       (1 << 10)
+#define SDE_PORTC_HOTPLUG       (1 << 9)
+#define SDE_PORTB_HOTPLUG       (1 << 8)
+#define SDE_SDVOB_HOTPLUG       (1 << 6)
+#define SDE_HOTPLUG_MASK	(0xf << 8)
+#define SDE_TRANSB_CRC_DONE	(1 << 5)
+#define SDE_TRANSB_CRC_ERR	(1 << 4)
+#define SDE_TRANSB_FIFO_UNDER	(1 << 3)
+#define SDE_TRANSA_CRC_DONE	(1 << 2)
+#define SDE_TRANSA_CRC_ERR	(1 << 1)
+#define SDE_TRANSA_FIFO_UNDER	(1 << 0)
+#define SDE_TRANS_MASK		(0x3f)
+/* CPT */
+#define SDE_CRT_HOTPLUG_CPT	(1 << 19)
+#define SDE_PORTD_HOTPLUG_CPT	(1 << 23)
+#define SDE_PORTC_HOTPLUG_CPT	(1 << 22)
+#define SDE_PORTB_HOTPLUG_CPT	(1 << 21)
+#define SDE_HOTPLUG_MASK_CPT	(SDE_CRT_HOTPLUG_CPT |		\
+				 SDE_PORTD_HOTPLUG_CPT |	\
+				 SDE_PORTC_HOTPLUG_CPT |	\
+				 SDE_PORTB_HOTPLUG_CPT)
+
+#define SDEISR  0xc4000
+#define SDEIMR  0xc4004
+#define SDEIIR  0xc4008
+#define SDEIER  0xc400c
+
+/* digital port hotplug */
+#define PCH_PORT_HOTPLUG        0xc4030		/* SHOTPLUG_CTL */
+#define PORTD_HOTPLUG_ENABLE            (1 << 20)
+#define PORTD_PULSE_DURATION_2ms        (0)
+#define PORTD_PULSE_DURATION_4_5ms      (1 << 18)
+#define PORTD_PULSE_DURATION_6ms        (2 << 18)
+#define PORTD_PULSE_DURATION_100ms      (3 << 18)
+#define PORTD_PULSE_DURATION_MASK	(3 << 18)
+#define PORTD_HOTPLUG_NO_DETECT         (0)
+#define PORTD_HOTPLUG_SHORT_DETECT      (1 << 16)
+#define PORTD_HOTPLUG_LONG_DETECT       (1 << 17)
+#define PORTC_HOTPLUG_ENABLE            (1 << 12)
+#define PORTC_PULSE_DURATION_2ms        (0)
+#define PORTC_PULSE_DURATION_4_5ms      (1 << 10)
+#define PORTC_PULSE_DURATION_6ms        (2 << 10)
+#define PORTC_PULSE_DURATION_100ms      (3 << 10)
+#define PORTC_PULSE_DURATION_MASK	(3 << 10)
+#define PORTC_HOTPLUG_NO_DETECT         (0)
+#define PORTC_HOTPLUG_SHORT_DETECT      (1 << 8)
+#define PORTC_HOTPLUG_LONG_DETECT       (1 << 9)
+#define PORTB_HOTPLUG_ENABLE            (1 << 4)
+#define PORTB_PULSE_DURATION_2ms        (0)
+#define PORTB_PULSE_DURATION_4_5ms      (1 << 2)
+#define PORTB_PULSE_DURATION_6ms        (2 << 2)
+#define PORTB_PULSE_DURATION_100ms      (3 << 2)
+#define PORTB_PULSE_DURATION_MASK	(3 << 2)
+#define PORTB_HOTPLUG_NO_DETECT         (0)
+#define PORTB_HOTPLUG_SHORT_DETECT      (1 << 0)
+#define PORTB_HOTPLUG_LONG_DETECT       (1 << 1)
+
+#define PCH_GPIOA               0xc5010
+#define PCH_GPIOB               0xc5014
+#define PCH_GPIOC               0xc5018
+#define PCH_GPIOD               0xc501c
+#define PCH_GPIOE               0xc5020
+#define PCH_GPIOF               0xc5024
+
+#define PCH_GMBUS0		0xc5100
+#define PCH_GMBUS1		0xc5104
+#define PCH_GMBUS2		0xc5108
+#define PCH_GMBUS3		0xc510c
+#define PCH_GMBUS4		0xc5110
+#define PCH_GMBUS5		0xc5120
+
+#define _PCH_DPLL_A              0xc6014
+#define _PCH_DPLL_B              0xc6018
+#define PCH_DPLL(pipe) (pipe == 0 ?  _PCH_DPLL_A : _PCH_DPLL_B)
+
+#define _PCH_FPA0                0xc6040
+#define  FP_CB_TUNE		(0x3<<22)
+#define _PCH_FPA1                0xc6044
+#define _PCH_FPB0                0xc6048
+#define _PCH_FPB1                0xc604c
+#define PCH_FP0(pipe) (pipe == 0 ? _PCH_FPA0 : _PCH_FPB0)
+#define PCH_FP1(pipe) (pipe == 0 ? _PCH_FPA1 : _PCH_FPB1)
+
+#define PCH_DPLL_TEST           0xc606c
+
+#define PCH_DREF_CONTROL        0xC6200
+#define  DREF_CONTROL_MASK      0x7fc3
+#define  DREF_CPU_SOURCE_OUTPUT_DISABLE         (0<<13)
+#define  DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD      (2<<13)
+#define  DREF_CPU_SOURCE_OUTPUT_NONSPREAD       (3<<13)
+#define  DREF_CPU_SOURCE_OUTPUT_MASK		(3<<13)
+#define  DREF_SSC_SOURCE_DISABLE                (0<<11)
+#define  DREF_SSC_SOURCE_ENABLE                 (2<<11)
+#define  DREF_SSC_SOURCE_MASK			(3<<11)
+#define  DREF_NONSPREAD_SOURCE_DISABLE          (0<<9)
+#define  DREF_NONSPREAD_CK505_ENABLE		(1<<9)
+#define  DREF_NONSPREAD_SOURCE_ENABLE           (2<<9)
+#define  DREF_NONSPREAD_SOURCE_MASK		(3<<9)
+#define  DREF_SUPERSPREAD_SOURCE_DISABLE        (0<<7)
+#define  DREF_SUPERSPREAD_SOURCE_ENABLE         (2<<7)
+#define  DREF_SUPERSPREAD_SOURCE_MASK		(3<<7)
+#define  DREF_SSC4_DOWNSPREAD                   (0<<6)
+#define  DREF_SSC4_CENTERSPREAD                 (1<<6)
+#define  DREF_SSC1_DISABLE                      (0<<1)
+#define  DREF_SSC1_ENABLE                       (1<<1)
+#define  DREF_SSC4_DISABLE                      (0)
+#define  DREF_SSC4_ENABLE                       (1)
+
+#define PCH_RAWCLK_FREQ         0xc6204
+#define  FDL_TP1_TIMER_SHIFT    12
+#define  FDL_TP1_TIMER_MASK     (3<<12)
+#define  FDL_TP2_TIMER_SHIFT    10
+#define  FDL_TP2_TIMER_MASK     (3<<10)
+#define  RAWCLK_FREQ_MASK       0x3ff
+
+#define PCH_DPLL_TMR_CFG        0xc6208
+
+#define PCH_SSC4_PARMS          0xc6210
+#define PCH_SSC4_AUX_PARMS      0xc6214
+
+#define PCH_DPLL_SEL		0xc7000
+#define  TRANSA_DPLL_ENABLE	(1<<3)
+#define	 TRANSA_DPLLB_SEL	(1<<0)
+#define	 TRANSA_DPLLA_SEL	0
+#define  TRANSB_DPLL_ENABLE	(1<<7)
+#define	 TRANSB_DPLLB_SEL	(1<<4)
+#define	 TRANSB_DPLLA_SEL	(0)
+#define  TRANSC_DPLL_ENABLE	(1<<11)
+#define	 TRANSC_DPLLB_SEL	(1<<8)
+#define	 TRANSC_DPLLA_SEL	(0)
+
+/* transcoder */
+
+#define _TRANS_HTOTAL_A          0xe0000
+#define  TRANS_HTOTAL_SHIFT     16
+#define  TRANS_HACTIVE_SHIFT    0
+#define _TRANS_HBLANK_A          0xe0004
+#define  TRANS_HBLANK_END_SHIFT 16
+#define  TRANS_HBLANK_START_SHIFT 0
+#define _TRANS_HSYNC_A           0xe0008
+#define  TRANS_HSYNC_END_SHIFT  16
+#define  TRANS_HSYNC_START_SHIFT 0
+#define _TRANS_VTOTAL_A          0xe000c
+#define  TRANS_VTOTAL_SHIFT     16
+#define  TRANS_VACTIVE_SHIFT    0
+#define _TRANS_VBLANK_A          0xe0010
+#define  TRANS_VBLANK_END_SHIFT 16
+#define  TRANS_VBLANK_START_SHIFT 0
+#define _TRANS_VSYNC_A           0xe0014
+#define  TRANS_VSYNC_END_SHIFT  16
+#define  TRANS_VSYNC_START_SHIFT 0
+#define _TRANS_VSYNCSHIFT_A	0xe0028
+
+#define _TRANSA_DATA_M1          0xe0030
+#define _TRANSA_DATA_N1          0xe0034
+#define _TRANSA_DATA_M2          0xe0038
+#define _TRANSA_DATA_N2          0xe003c
+#define _TRANSA_DP_LINK_M1       0xe0040
+#define _TRANSA_DP_LINK_N1       0xe0044
+#define _TRANSA_DP_LINK_M2       0xe0048
+#define _TRANSA_DP_LINK_N2       0xe004c
+
+/* Per-transcoder DIP controls */
+
+#define _VIDEO_DIP_CTL_A         0xe0200
+#define _VIDEO_DIP_DATA_A        0xe0208
+#define _VIDEO_DIP_GCP_A         0xe0210
+
+#define _VIDEO_DIP_CTL_B         0xe1200
+#define _VIDEO_DIP_DATA_B        0xe1208
+#define _VIDEO_DIP_GCP_B         0xe1210
+
+#define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
+#define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
+#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
+
+#define _TRANS_HTOTAL_B          0xe1000
+#define _TRANS_HBLANK_B          0xe1004
+#define _TRANS_HSYNC_B           0xe1008
+#define _TRANS_VTOTAL_B          0xe100c
+#define _TRANS_VBLANK_B          0xe1010
+#define _TRANS_VSYNC_B           0xe1014
+#define _TRANS_VSYNCSHIFT_B	 0xe1028
+
+#define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B)
+#define TRANS_HBLANK(pipe) _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B)
+#define TRANS_HSYNC(pipe) _PIPE(pipe, _TRANS_HSYNC_A, _TRANS_HSYNC_B)
+#define TRANS_VTOTAL(pipe) _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B)
+#define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B)
+#define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B)
+#define TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _TRANS_VSYNCSHIFT_A, \
+				     _TRANS_VSYNCSHIFT_B)
+
+#define _TRANSB_DATA_M1          0xe1030
+#define _TRANSB_DATA_N1          0xe1034
+#define _TRANSB_DATA_M2          0xe1038
+#define _TRANSB_DATA_N2          0xe103c
+#define _TRANSB_DP_LINK_M1       0xe1040
+#define _TRANSB_DP_LINK_N1       0xe1044
+#define _TRANSB_DP_LINK_M2       0xe1048
+#define _TRANSB_DP_LINK_N2       0xe104c
+
+#define TRANSDATA_M1(pipe) _PIPE(pipe, _TRANSA_DATA_M1, _TRANSB_DATA_M1)
+#define TRANSDATA_N1(pipe) _PIPE(pipe, _TRANSA_DATA_N1, _TRANSB_DATA_N1)
+#define TRANSDATA_M2(pipe) _PIPE(pipe, _TRANSA_DATA_M2, _TRANSB_DATA_M2)
+#define TRANSDATA_N2(pipe) _PIPE(pipe, _TRANSA_DATA_N2, _TRANSB_DATA_N2)
+#define TRANSDPLINK_M1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M1, _TRANSB_DP_LINK_M1)
+#define TRANSDPLINK_N1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N1, _TRANSB_DP_LINK_N1)
+#define TRANSDPLINK_M2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M2, _TRANSB_DP_LINK_M2)
+#define TRANSDPLINK_N2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N2, _TRANSB_DP_LINK_N2)
+
+#define _TRANSACONF              0xf0008
+#define _TRANSBCONF              0xf1008
+#define TRANSCONF(plane) _PIPE(plane, _TRANSACONF, _TRANSBCONF)
+#define  TRANS_DISABLE          (0<<31)
+#define  TRANS_ENABLE           (1<<31)
+#define  TRANS_STATE_MASK       (1<<30)
+#define  TRANS_STATE_DISABLE    (0<<30)
+#define  TRANS_STATE_ENABLE     (1<<30)
+#define  TRANS_FSYNC_DELAY_HB1  (0<<27)
+#define  TRANS_FSYNC_DELAY_HB2  (1<<27)
+#define  TRANS_FSYNC_DELAY_HB3  (2<<27)
+#define  TRANS_FSYNC_DELAY_HB4  (3<<27)
+#define  TRANS_DP_AUDIO_ONLY    (1<<26)
+#define  TRANS_DP_VIDEO_AUDIO   (0<<26)
+#define  TRANS_INTERLACE_MASK   (7<<21)
+#define  TRANS_PROGRESSIVE      (0<<21)
+#define  TRANS_INTERLACED       (3<<21)
+#define  TRANS_LEGACY_INTERLACED_ILK (2<<21)
+#define  TRANS_8BPC             (0<<5)
+#define  TRANS_10BPC            (1<<5)
+#define  TRANS_6BPC             (2<<5)
+#define  TRANS_12BPC            (3<<5)
+
+#define _TRANSA_CHICKEN2	 0xf0064
+#define _TRANSB_CHICKEN2	 0xf1064
+#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
+#define   TRANS_AUTOTRAIN_GEN_STALL_DIS	(1<<31)
+
+#define SOUTH_CHICKEN1		0xc2000
+#define  FDIA_PHASE_SYNC_SHIFT_OVR	19
+#define  FDIA_PHASE_SYNC_SHIFT_EN	18
+#define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
+#define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
+#define SOUTH_CHICKEN2		0xc2004
+#define  DPLS_EDP_PPS_FIX_DIS	(1<<0)
+
+#define _FDI_RXA_CHICKEN         0xc200c
+#define _FDI_RXB_CHICKEN         0xc2010
+#define  FDI_RX_PHASE_SYNC_POINTER_OVR	(1<<1)
+#define  FDI_RX_PHASE_SYNC_POINTER_EN	(1<<0)
+#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
+
+#define SOUTH_DSPCLK_GATE_D	0xc2020
+#define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
+
+/* CPU: FDI_TX */
+#define _FDI_TXA_CTL             0x60100
+#define _FDI_TXB_CTL             0x61100
+#define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
+#define  FDI_TX_DISABLE         (0<<31)
+#define  FDI_TX_ENABLE          (1<<31)
+#define  FDI_LINK_TRAIN_PATTERN_1       (0<<28)
+#define  FDI_LINK_TRAIN_PATTERN_2       (1<<28)
+#define  FDI_LINK_TRAIN_PATTERN_IDLE    (2<<28)
+#define  FDI_LINK_TRAIN_NONE            (3<<28)
+#define  FDI_LINK_TRAIN_VOLTAGE_0_4V    (0<<25)
+#define  FDI_LINK_TRAIN_VOLTAGE_0_6V    (1<<25)
+#define  FDI_LINK_TRAIN_VOLTAGE_0_8V    (2<<25)
+#define  FDI_LINK_TRAIN_VOLTAGE_1_2V    (3<<25)
+#define  FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
+#define  FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
+#define  FDI_LINK_TRAIN_PRE_EMPHASIS_2X   (2<<22)
+#define  FDI_LINK_TRAIN_PRE_EMPHASIS_3X   (3<<22)
+/* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
+   SNB has different settings. */
+/* SNB A-stepping */
+#define  FDI_LINK_TRAIN_400MV_0DB_SNB_A		(0x38<<22)
+#define  FDI_LINK_TRAIN_400MV_6DB_SNB_A		(0x02<<22)
+#define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_A	(0x01<<22)
+#define  FDI_LINK_TRAIN_800MV_0DB_SNB_A		(0x0<<22)
+/* SNB B-stepping */
+#define  FDI_LINK_TRAIN_400MV_0DB_SNB_B		(0x0<<22)
+#define  FDI_LINK_TRAIN_400MV_6DB_SNB_B		(0x3a<<22)
+#define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_B	(0x39<<22)
+#define  FDI_LINK_TRAIN_800MV_0DB_SNB_B		(0x38<<22)
+#define  FDI_LINK_TRAIN_VOL_EMP_MASK		(0x3f<<22)
+#define  FDI_DP_PORT_WIDTH_X1           (0<<19)
+#define  FDI_DP_PORT_WIDTH_X2           (1<<19)
+#define  FDI_DP_PORT_WIDTH_X3           (2<<19)
+#define  FDI_DP_PORT_WIDTH_X4           (3<<19)
+#define  FDI_TX_ENHANCE_FRAME_ENABLE    (1<<18)
+/* Ironlake: hardwired to 1 */
+#define  FDI_TX_PLL_ENABLE              (1<<14)
+
+/* Ivybridge has different bits for lolz */
+#define  FDI_LINK_TRAIN_PATTERN_1_IVB       (0<<8)
+#define  FDI_LINK_TRAIN_PATTERN_2_IVB       (1<<8)
+#define  FDI_LINK_TRAIN_PATTERN_IDLE_IVB    (2<<8)
+#define  FDI_LINK_TRAIN_NONE_IVB            (3<<8)
+
+/* both Tx and Rx */
+#define  FDI_COMPOSITE_SYNC		(1<<11)
+#define  FDI_LINK_TRAIN_AUTO		(1<<10)
+#define  FDI_SCRAMBLING_ENABLE          (0<<7)
+#define  FDI_SCRAMBLING_DISABLE         (1<<7)
+
+/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
+#define _FDI_RXA_CTL             0xf000c
+#define _FDI_RXB_CTL             0xf100c
+#define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
+#define  FDI_RX_ENABLE          (1<<31)
+/* train, dp width same as FDI_TX */
+#define  FDI_FS_ERRC_ENABLE		(1<<27)
+#define  FDI_FE_ERRC_ENABLE		(1<<26)
+#define  FDI_DP_PORT_WIDTH_X8           (7<<19)
+#define  FDI_8BPC                       (0<<16)
+#define  FDI_10BPC                      (1<<16)
+#define  FDI_6BPC                       (2<<16)
+#define  FDI_12BPC                      (3<<16)
+#define  FDI_LINK_REVERSE_OVERWRITE     (1<<15)
+#define  FDI_DMI_LINK_REVERSE_MASK      (1<<14)
+#define  FDI_RX_PLL_ENABLE              (1<<13)
+#define  FDI_FS_ERR_CORRECT_ENABLE      (1<<11)
+#define  FDI_FE_ERR_CORRECT_ENABLE      (1<<10)
+#define  FDI_FS_ERR_REPORT_ENABLE       (1<<9)
+#define  FDI_FE_ERR_REPORT_ENABLE       (1<<8)
+#define  FDI_RX_ENHANCE_FRAME_ENABLE    (1<<6)
+#define  FDI_PCDCLK	                (1<<4)
+/* CPT */
+#define  FDI_AUTO_TRAINING			(1<<10)
+#define  FDI_LINK_TRAIN_PATTERN_1_CPT		(0<<8)
+#define  FDI_LINK_TRAIN_PATTERN_2_CPT		(1<<8)
+#define  FDI_LINK_TRAIN_PATTERN_IDLE_CPT	(2<<8)
+#define  FDI_LINK_TRAIN_NORMAL_CPT		(3<<8)
+#define  FDI_LINK_TRAIN_PATTERN_MASK_CPT	(3<<8)
+
+#define _FDI_RXA_MISC            0xf0010
+#define _FDI_RXB_MISC            0xf1010
+#define _FDI_RXA_TUSIZE1         0xf0030
+#define _FDI_RXA_TUSIZE2         0xf0038
+#define _FDI_RXB_TUSIZE1         0xf1030
+#define _FDI_RXB_TUSIZE2         0xf1038
+#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
+#define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
+#define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
+
+/* FDI_RX interrupt register format */
+#define FDI_RX_INTER_LANE_ALIGN         (1<<10)
+#define FDI_RX_SYMBOL_LOCK              (1<<9) /* train 2 */
+#define FDI_RX_BIT_LOCK                 (1<<8) /* train 1 */
+#define FDI_RX_TRAIN_PATTERN_2_FAIL     (1<<7)
+#define FDI_RX_FS_CODE_ERR              (1<<6)
+#define FDI_RX_FE_CODE_ERR              (1<<5)
+#define FDI_RX_SYMBOL_ERR_RATE_ABOVE    (1<<4)
+#define FDI_RX_HDCP_LINK_FAIL           (1<<3)
+#define FDI_RX_PIXEL_FIFO_OVERFLOW      (1<<2)
+#define FDI_RX_CROSS_CLOCK_OVERFLOW     (1<<1)
+#define FDI_RX_SYMBOL_QUEUE_OVERFLOW    (1<<0)
+
+#define _FDI_RXA_IIR             0xf0014
+#define _FDI_RXA_IMR             0xf0018
+#define _FDI_RXB_IIR             0xf1014
+#define _FDI_RXB_IMR             0xf1018
+#define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
+#define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
+
+#define FDI_PLL_CTL_1           0xfe000
+#define FDI_PLL_CTL_2           0xfe004
+
+/* CRT */
+#define PCH_ADPA                0xe1100
+#define  ADPA_TRANS_SELECT_MASK (1<<30)
+#define  ADPA_TRANS_A_SELECT    0
+#define  ADPA_TRANS_B_SELECT    (1<<30)
+#define  ADPA_CRT_HOTPLUG_MASK  0x03ff0000 /* bit 25-16 */
+#define  ADPA_CRT_HOTPLUG_MONITOR_NONE  (0<<24)
+#define  ADPA_CRT_HOTPLUG_MONITOR_MASK  (3<<24)
+#define  ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
+#define  ADPA_CRT_HOTPLUG_MONITOR_MONO  (2<<24)
+#define  ADPA_CRT_HOTPLUG_ENABLE        (1<<23)
+#define  ADPA_CRT_HOTPLUG_PERIOD_64     (0<<22)
+#define  ADPA_CRT_HOTPLUG_PERIOD_128    (1<<22)
+#define  ADPA_CRT_HOTPLUG_WARMUP_5MS    (0<<21)
+#define  ADPA_CRT_HOTPLUG_WARMUP_10MS   (1<<21)
+#define  ADPA_CRT_HOTPLUG_SAMPLE_2S     (0<<20)
+#define  ADPA_CRT_HOTPLUG_SAMPLE_4S     (1<<20)
+#define  ADPA_CRT_HOTPLUG_VOLTAGE_40    (0<<18)
+#define  ADPA_CRT_HOTPLUG_VOLTAGE_50    (1<<18)
+#define  ADPA_CRT_HOTPLUG_VOLTAGE_60    (2<<18)
+#define  ADPA_CRT_HOTPLUG_VOLTAGE_70    (3<<18)
+#define  ADPA_CRT_HOTPLUG_VOLREF_325MV  (0<<17)
+#define  ADPA_CRT_HOTPLUG_VOLREF_475MV  (1<<17)
+#define  ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
+
+/* or SDVOB */
+#define HDMIB   0xe1140
+#define  PORT_ENABLE    (1 << 31)
+#define  TRANSCODER(pipe)       ((pipe) << 30)
+#define  TRANSCODER_CPT(pipe)   ((pipe) << 29)
+#define  TRANSCODER_MASK        (1 << 30)
+#define  TRANSCODER_MASK_CPT    (3 << 29)
+#define  COLOR_FORMAT_8bpc      (0)
+#define  COLOR_FORMAT_12bpc     (3 << 26)
+#define  SDVOB_HOTPLUG_ENABLE   (1 << 23)
+#define  SDVO_ENCODING          (0)
+#define  TMDS_ENCODING          (2 << 10)
+#define  NULL_PACKET_VSYNC_ENABLE       (1 << 9)
+/* CPT */
+#define  HDMI_MODE_SELECT	(1 << 9)
+#define  DVI_MODE_SELECT	(0)
+#define  SDVOB_BORDER_ENABLE    (1 << 7)
+#define  AUDIO_ENABLE           (1 << 6)
+#define  VSYNC_ACTIVE_HIGH      (1 << 4)
+#define  HSYNC_ACTIVE_HIGH      (1 << 3)
+#define  PORT_DETECTED          (1 << 2)
+
+/* PCH SDVOB multiplex with HDMIB */
+#define PCH_SDVOB	HDMIB
+
+#define HDMIC   0xe1150
+#define HDMID   0xe1160
+
+#define PCH_LVDS	0xe1180
+#define  LVDS_DETECTED	(1 << 1)
+
+#define BLC_PWM_CPU_CTL2	0x48250
+#define  PWM_ENABLE		(1 << 31)
+#define  PWM_PIPE_A		(0 << 29)
+#define  PWM_PIPE_B		(1 << 29)
+#define BLC_PWM_CPU_CTL		0x48254
+
+#define BLC_PWM_PCH_CTL1	0xc8250
+#define  PWM_PCH_ENABLE		(1 << 31)
+#define  PWM_POLARITY_ACTIVE_LOW	(1 << 29)
+#define  PWM_POLARITY_ACTIVE_HIGH	(0 << 29)
+#define  PWM_POLARITY_ACTIVE_LOW2	(1 << 28)
+#define  PWM_POLARITY_ACTIVE_HIGH2	(0 << 28)
+
+#define BLC_PWM_PCH_CTL2	0xc8254
+
+#define PCH_PP_STATUS		0xc7200
+#define PCH_PP_CONTROL		0xc7204
+#define  PANEL_UNLOCK_REGS	(0xabcd << 16)
+#define  PANEL_UNLOCK_MASK	(0xffff << 16)
+#define  EDP_FORCE_VDD		(1 << 3)
+#define  EDP_BLC_ENABLE		(1 << 2)
+#define  PANEL_POWER_RESET	(1 << 1)
+#define  PANEL_POWER_OFF	(0 << 0)
+#define  PANEL_POWER_ON		(1 << 0)
+#define PCH_PP_ON_DELAYS	0xc7208
+#define  PANEL_PORT_SELECT_MASK	(3 << 30)
+#define  PANEL_PORT_SELECT_LVDS	(0 << 30)
+#define  PANEL_PORT_SELECT_DPA	(1 << 30)
+#define  EDP_PANEL		(1 << 30)
+#define  PANEL_PORT_SELECT_DPC	(2 << 30)
+#define  PANEL_PORT_SELECT_DPD	(3 << 30)
+#define  PANEL_POWER_UP_DELAY_MASK	(0x1fff0000)
+#define  PANEL_POWER_UP_DELAY_SHIFT	16
+#define  PANEL_LIGHT_ON_DELAY_MASK	(0x1fff)
+#define  PANEL_LIGHT_ON_DELAY_SHIFT	0
+
+#define PCH_PP_OFF_DELAYS	0xc720c
+#define  PANEL_POWER_DOWN_DELAY_MASK	(0x1fff0000)
+#define  PANEL_POWER_DOWN_DELAY_SHIFT	16
+#define  PANEL_LIGHT_OFF_DELAY_MASK	(0x1fff)
+#define  PANEL_LIGHT_OFF_DELAY_SHIFT	0
+
+#define PCH_PP_DIVISOR		0xc7210
+#define  PP_REFERENCE_DIVIDER_MASK	(0xffffff00)
+#define  PP_REFERENCE_DIVIDER_SHIFT	8
+#define  PANEL_POWER_CYCLE_DELAY_MASK	(0x1f)
+#define  PANEL_POWER_CYCLE_DELAY_SHIFT	0
+
+#define PCH_DP_B		0xe4100
+#define PCH_DPB_AUX_CH_CTL	0xe4110
+#define PCH_DPB_AUX_CH_DATA1	0xe4114
+#define PCH_DPB_AUX_CH_DATA2	0xe4118
+#define PCH_DPB_AUX_CH_DATA3	0xe411c
+#define PCH_DPB_AUX_CH_DATA4	0xe4120
+#define PCH_DPB_AUX_CH_DATA5	0xe4124
+
+#define PCH_DP_C		0xe4200
+#define PCH_DPC_AUX_CH_CTL	0xe4210
+#define PCH_DPC_AUX_CH_DATA1	0xe4214
+#define PCH_DPC_AUX_CH_DATA2	0xe4218
+#define PCH_DPC_AUX_CH_DATA3	0xe421c
+#define PCH_DPC_AUX_CH_DATA4	0xe4220
+#define PCH_DPC_AUX_CH_DATA5	0xe4224
+
+#define PCH_DP_D		0xe4300
+#define PCH_DPD_AUX_CH_CTL	0xe4310
+#define PCH_DPD_AUX_CH_DATA1	0xe4314
+#define PCH_DPD_AUX_CH_DATA2	0xe4318
+#define PCH_DPD_AUX_CH_DATA3	0xe431c
+#define PCH_DPD_AUX_CH_DATA4	0xe4320
+#define PCH_DPD_AUX_CH_DATA5	0xe4324
+
+/* CPT */
+#define  PORT_TRANS_A_SEL_CPT	0
+#define  PORT_TRANS_B_SEL_CPT	(1<<29)
+#define  PORT_TRANS_C_SEL_CPT	(2<<29)
+#define  PORT_TRANS_SEL_MASK	(3<<29)
+#define  PORT_TRANS_SEL_CPT(pipe)	((pipe) << 29)
+
+#define TRANS_DP_CTL_A		0xe0300
+#define TRANS_DP_CTL_B		0xe1300
+#define TRANS_DP_CTL_C		0xe2300
+#define TRANS_DP_CTL(pipe)	(TRANS_DP_CTL_A + (pipe) * 0x01000)
+#define  TRANS_DP_OUTPUT_ENABLE	(1<<31)
+#define  TRANS_DP_PORT_SEL_B	(0<<29)
+#define  TRANS_DP_PORT_SEL_C	(1<<29)
+#define  TRANS_DP_PORT_SEL_D	(2<<29)
+#define  TRANS_DP_PORT_SEL_NONE	(3<<29)
+#define  TRANS_DP_PORT_SEL_MASK	(3<<29)
+#define  TRANS_DP_AUDIO_ONLY	(1<<26)
+#define  TRANS_DP_ENH_FRAMING	(1<<18)
+#define  TRANS_DP_8BPC		(0<<9)
+#define  TRANS_DP_10BPC		(1<<9)
+#define  TRANS_DP_6BPC		(2<<9)
+#define  TRANS_DP_12BPC		(3<<9)
+#define  TRANS_DP_BPC_MASK	(3<<9)
+#define  TRANS_DP_VSYNC_ACTIVE_HIGH	(1<<4)
+#define  TRANS_DP_VSYNC_ACTIVE_LOW	0
+#define  TRANS_DP_HSYNC_ACTIVE_HIGH	(1<<3)
+#define  TRANS_DP_HSYNC_ACTIVE_LOW	0
+#define  TRANS_DP_SYNC_MASK	(3<<3)
+
+/* SNB eDP training params */
+/* SNB A-stepping */
+#define  EDP_LINK_TRAIN_400MV_0DB_SNB_A		(0x38<<22)
+#define  EDP_LINK_TRAIN_400MV_6DB_SNB_A		(0x02<<22)
+#define  EDP_LINK_TRAIN_600MV_3_5DB_SNB_A	(0x01<<22)
+#define  EDP_LINK_TRAIN_800MV_0DB_SNB_A		(0x0<<22)
+/* SNB B-stepping */
+#define  EDP_LINK_TRAIN_400_600MV_0DB_SNB_B	(0x0<<22)
+#define  EDP_LINK_TRAIN_400MV_3_5DB_SNB_B	(0x1<<22)
+#define  EDP_LINK_TRAIN_400_600MV_6DB_SNB_B	(0x3a<<22)
+#define  EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B	(0x39<<22)
+#define  EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B	(0x38<<22)
+#define  EDP_LINK_TRAIN_VOL_EMP_MASK_SNB	(0x3f<<22)
+
+/* IVB */
+#define EDP_LINK_TRAIN_400MV_0DB_IVB		(0x24 <<22)
+#define EDP_LINK_TRAIN_400MV_3_5DB_IVB		(0x2a <<22)
+#define EDP_LINK_TRAIN_400MV_6DB_IVB		(0x2f <<22)
+#define EDP_LINK_TRAIN_600MV_0DB_IVB		(0x30 <<22)
+#define EDP_LINK_TRAIN_600MV_3_5DB_IVB		(0x36 <<22)
+#define EDP_LINK_TRAIN_800MV_0DB_IVB		(0x38 <<22)
+#define EDP_LINK_TRAIN_800MV_3_5DB_IVB		(0x33 <<22)
+
+/* legacy values */
+#define EDP_LINK_TRAIN_500MV_0DB_IVB		(0x00 <<22)
+#define EDP_LINK_TRAIN_1000MV_0DB_IVB		(0x20 <<22)
+#define EDP_LINK_TRAIN_500MV_3_5DB_IVB		(0x02 <<22)
+#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB		(0x22 <<22)
+#define EDP_LINK_TRAIN_1000MV_6DB_IVB		(0x23 <<22)
+
+#define  EDP_LINK_TRAIN_VOL_EMP_MASK_IVB	(0x3f<<22)
+
+#define  FORCEWAKE				0xA18C
+#define  FORCEWAKE_ACK				0x130090
+#define  FORCEWAKE_MT				0xa188 /* multi-threaded */
+#define  FORCEWAKE_MT_ACK			0x130040
+#define  ECOBUS					0xa180
+#define    FORCEWAKE_MT_ENABLE			(1<<5)
+
+#define  GTFIFODBG				0x120000
+#define    GT_FIFO_CPU_ERROR_MASK		7
+#define    GT_FIFO_OVFERR			(1<<2)
+#define    GT_FIFO_IAWRERR			(1<<1)
+#define    GT_FIFO_IARDERR			(1<<0)
+
+#define  GT_FIFO_FREE_ENTRIES			0x120008
+#define    GT_FIFO_NUM_RESERVED_ENTRIES		20
+
+#define GEN6_UCGCTL1				0x9400
+# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE		(1 << 5)
+
+#define GEN6_UCGCTL2				0x9404
+# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE		(1 << 13)
+# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE		(1 << 12)
+# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE		(1 << 11)
+
+#define GEN6_RPNSWREQ				0xA008
+#define   GEN6_TURBO_DISABLE			(1<<31)
+#define   GEN6_FREQUENCY(x)			((x)<<25)
+#define   GEN6_OFFSET(x)			((x)<<19)
+#define   GEN6_AGGRESSIVE_TURBO			(0<<15)
+#define GEN6_RC_VIDEO_FREQ			0xA00C
+#define GEN6_RC_CONTROL				0xA090
+#define   GEN6_RC_CTL_RC6pp_ENABLE		(1<<16)
+#define   GEN6_RC_CTL_RC6p_ENABLE		(1<<17)
+#define   GEN6_RC_CTL_RC6_ENABLE		(1<<18)
+#define   GEN6_RC_CTL_RC1e_ENABLE		(1<<20)
+#define   GEN6_RC_CTL_RC7_ENABLE		(1<<22)
+#define   GEN6_RC_CTL_EI_MODE(x)		((x)<<27)
+#define   GEN6_RC_CTL_HW_ENABLE			(1<<31)
+#define GEN6_RP_DOWN_TIMEOUT			0xA010
+#define GEN6_RP_INTERRUPT_LIMITS		0xA014
+#define GEN6_RPSTAT1				0xA01C
+#define   GEN6_CAGF_SHIFT			8
+#define   GEN6_CAGF_MASK			(0x7f << GEN6_CAGF_SHIFT)
+#define GEN6_RP_CONTROL				0xA024
+#define   GEN6_RP_MEDIA_TURBO			(1<<11)
+#define   GEN6_RP_MEDIA_MODE_MASK		(3<<9)
+#define   GEN6_RP_MEDIA_HW_TURBO_MODE		(3<<9)
+#define   GEN6_RP_MEDIA_HW_NORMAL_MODE		(2<<9)
+#define   GEN6_RP_MEDIA_HW_MODE			(1<<9)
+#define   GEN6_RP_MEDIA_SW_MODE			(0<<9)
+#define   GEN6_RP_MEDIA_IS_GFX			(1<<8)
+#define   GEN6_RP_ENABLE			(1<<7)
+#define   GEN6_RP_UP_IDLE_MIN			(0x1<<3)
+#define   GEN6_RP_UP_BUSY_AVG			(0x2<<3)
+#define   GEN6_RP_UP_BUSY_CONT			(0x4<<3)
+#define   GEN6_RP_DOWN_IDLE_CONT		(0x1<<0)
+#define GEN6_RP_UP_THRESHOLD			0xA02C
+#define GEN6_RP_DOWN_THRESHOLD			0xA030
+#define GEN6_RP_CUR_UP_EI			0xA050
+#define   GEN6_CURICONT_MASK			0xffffff
+#define GEN6_RP_CUR_UP				0xA054
+#define   GEN6_CURBSYTAVG_MASK			0xffffff
+#define GEN6_RP_PREV_UP				0xA058
+#define GEN6_RP_CUR_DOWN_EI			0xA05C
+#define   GEN6_CURIAVG_MASK			0xffffff
+#define GEN6_RP_CUR_DOWN			0xA060
+#define GEN6_RP_PREV_DOWN			0xA064
+#define GEN6_RP_UP_EI				0xA068
+#define GEN6_RP_DOWN_EI				0xA06C
+#define GEN6_RP_IDLE_HYSTERSIS			0xA070
+#define GEN6_RC_STATE				0xA094
+#define GEN6_RC1_WAKE_RATE_LIMIT		0xA098
+#define GEN6_RC6_WAKE_RATE_LIMIT		0xA09C
+#define GEN6_RC6pp_WAKE_RATE_LIMIT		0xA0A0
+#define GEN6_RC_EVALUATION_INTERVAL		0xA0A8
+#define GEN6_RC_IDLE_HYSTERSIS			0xA0AC
+#define GEN6_RC_SLEEP				0xA0B0
+#define GEN6_RC1e_THRESHOLD			0xA0B4
+#define GEN6_RC6_THRESHOLD			0xA0B8
+#define GEN6_RC6p_THRESHOLD			0xA0BC
+#define GEN6_RC6pp_THRESHOLD			0xA0C0
+#define GEN6_PMINTRMSK				0xA168
+
+#define GEN6_PMISR				0x44020
+#define GEN6_PMIMR				0x44024 /* rps_lock */
+#define GEN6_PMIIR				0x44028
+#define GEN6_PMIER				0x4402C
+#define  GEN6_PM_MBOX_EVENT			(1<<25)
+#define  GEN6_PM_THERMAL_EVENT			(1<<24)
+#define  GEN6_PM_RP_DOWN_TIMEOUT		(1<<6)
+#define  GEN6_PM_RP_UP_THRESHOLD		(1<<5)
+#define  GEN6_PM_RP_DOWN_THRESHOLD		(1<<4)
+#define  GEN6_PM_RP_UP_EI_EXPIRED		(1<<2)
+#define  GEN6_PM_RP_DOWN_EI_EXPIRED		(1<<1)
+#define  GEN6_PM_DEFERRED_EVENTS		(GEN6_PM_RP_UP_THRESHOLD | \
+						 GEN6_PM_RP_DOWN_THRESHOLD | \
+						 GEN6_PM_RP_DOWN_TIMEOUT)
+
+#define GEN6_PCODE_MAILBOX			0x138124
+#define   GEN6_PCODE_READY			(1<<31)
+#define   GEN6_READ_OC_PARAMS			0xc
+#define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE	0x8
+#define   GEN6_PCODE_READ_MIN_FREQ_TABLE	0x9
+#define GEN6_PCODE_DATA				0x138128
+#define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
+
+#define GEN6_GT_CORE_STATUS		0x138060
+#define   GEN6_CORE_CPD_STATE_MASK	(7<<4)
+#define   GEN6_RCn_MASK			7
+#define   GEN6_RC0			0
+#define   GEN6_RC3			2
+#define   GEN6_RC6			3
+#define   GEN6_RC7			4
+
+#define G4X_AUD_VID_DID			0x62020
+#define INTEL_AUDIO_DEVCL		0x808629FB
+#define INTEL_AUDIO_DEVBLC		0x80862801
+#define INTEL_AUDIO_DEVCTG		0x80862802
+
+#define G4X_AUD_CNTL_ST			0x620B4
+#define G4X_ELDV_DEVCL_DEVBLC		(1 << 13)
+#define G4X_ELDV_DEVCTG			(1 << 14)
+#define G4X_ELD_ADDR			(0xf << 5)
+#define G4X_ELD_ACK			(1 << 4)
+#define G4X_HDMIW_HDMIEDID		0x6210C
+
+#define IBX_HDMIW_HDMIEDID_A		0xE2050
+#define IBX_AUD_CNTL_ST_A		0xE20B4
+#define IBX_ELD_BUFFER_SIZE		(0x1f << 10)
+#define IBX_ELD_ADDRESS			(0x1f << 5)
+#define IBX_ELD_ACK			(1 << 4)
+#define IBX_AUD_CNTL_ST2		0xE20C0
+#define IBX_ELD_VALIDB			(1 << 0)
+#define IBX_CP_READYB			(1 << 1)
+
+#define CPT_HDMIW_HDMIEDID_A		0xE5050
+#define CPT_AUD_CNTL_ST_A		0xE50B4
+#define CPT_AUD_CNTRL_ST2		0xE50C0
+
+/* These are the 4 32-bit write offset registers for each stream
+ * output buffer.  It determines the offset from the
+ * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
+ */
+#define GEN7_SO_WRITE_OFFSET(n)		(0x5280 + (n) * 4)
+
+#define IBX_AUD_CONFIG_A			0xe2000
+#define CPT_AUD_CONFIG_A			0xe5000
+#define   AUD_CONFIG_N_VALUE_INDEX		(1 << 29)
+#define   AUD_CONFIG_N_PROG_ENABLE		(1 << 28)
+#define   AUD_CONFIG_UPPER_N_SHIFT		20
+#define   AUD_CONFIG_UPPER_N_VALUE		(0xff << 20)
+#define   AUD_CONFIG_LOWER_N_SHIFT		4
+#define   AUD_CONFIG_LOWER_N_VALUE		(0xfff << 4)
+#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT	16
+#define   AUD_CONFIG_PIXEL_CLOCK_HDMI		(0xf << 16)
+#define   AUD_CONFIG_DISABLE_NCTS		(1 << 3)
+
+#endif /* _I915_REG_H_ */
diff --git a/src/mainboard/google/stout/i915io.c b/src/mainboard/google/stout/i915io.c
new file mode 100644
index 0000000000..ba03c386d9
--- /dev/null
+++ b/src/mainboard/google/stout/i915io.c
@@ -0,0 +1,3143 @@
+{V, 7},
+{M, 1, "[drm] Initialized drm 1.1.0 20060810", },
+{M, 1, "i915 0000 00 02.0 setting latency timer to 64", },
+{W, 1, "", PCH_GMBUS0, 0x0, 0},
+{R, 1, "", PP_ON_DELAYS, 0x0, 0},
+{R, 1, "", PP_OFF_DELAYS, 0x0, 0},
+{W, 1, "", PP_ON_DELAYS, 0x19007d0, 0},
+{W, 1, "", PP_OFF_DELAYS, 0x15e07d0, 0},
+{W, 1, "", 0x100000, 0x0, 0},
+{W, 1, "", 0x100008, 0x0, 0},
+{W, 1, "", 0x100010, 0x0, 0},
+{W, 1, "", 0x100018, 0x0, 0},
+{W, 1, "", 0x100020, 0x0, 0},
+{W, 1, "", 0x100028, 0x0, 0},
+{W, 1, "", 0x100030, 0x0, 0},
+{W, 1, "", 0x100038, 0x0, 0},
+{W, 1, "", 0x100040, 0x0, 0},
+{W, 1, "", 0x100048, 0x0, 0},
+{W, 1, "", 0x100050, 0x0, 0},
+{W, 1, "", 0x100058, 0x0, 0},
+{W, 1, "", 0x100060, 0x0, 0},
+{W, 1, "", 0x100068, 0x0, 0},
+{W, 1, "", 0x100070, 0x0, 0},
+{W, 1, "", 0x100078, 0x0, 0},
+{R, 1, "", 0x145004, 0x600008, 0},
+{R, 1, "", 0x145008, 0x600008, 0},
+{M, 1, "i915 0000 00 02.0 irq 44 for MSI/MSI-X", },
+{M, 1, "[drm] Supports vblank timestamp caching Rev 1 (10.10.2010).", },
+{M, 1, "[drm] Driver supports precise vblank timestamp query.", },
+{R, 1, "", 0x145d10, 0x16040307, 0},
+{R, 1, "", _PIPEACONF, 0xd8000050, 0},
+{W, 1, "", _PIPEACONF, 0xc0000050, 0},
+{R, 1, "", _PIPEBCONF, 0x0, 0},
+{W, 1, "", _PIPEBCONF, 0x0, 0},
+{R, 1, "", _PIPEACONF, 0xc0000050, 0},
+{W, 1, "", _PIPEACONF, 0xc0000050, 0},
+{R, 1, "", _PIPEBCONF, 0x0, 0},
+{W, 1, "", _PIPEBCONF, 0x0, 300},
+{W, 1, "", CPU_VGACNTRL, 0x80000000, 0},
+{R, 1, "", CPU_VGACNTRL, 0x80000000, 0},
+{R, 1, "", PCH_LVDS, 0x80300302, 0},
+{W, 1, "", PCH_GMBUS0, 0x3, 0},
+{W, 1, "", PCH_GMBUS1, 0x460100a1, 0},
+{R, 1, "", PCH_GMBUS2, 0x200, 0},
+{R, 3, "", PCH_GMBUS2, 0x8200, 0},
+{R, 1, "", PCH_GMBUS2, 0xca00, 0},
+{R, 1, "", PCH_GMBUS3, 0xe1003200, 0},
+{R, 1, "", PCH_GMBUS2, 0xc200, 0},
+{W, 1, "", PCH_GMBUS1, 0x48000000, 0},
+{R, 1, "", PCH_GMBUS2, 0x8200, 0},
+{R, 1, "", PCH_GMBUS2, 0x8800, 0},
+{W, 1, "", PCH_GMBUS0, 0x0, 0},
+{W, 1, "", PCH_GMBUS0, 0x3, 0},
+{W, 1, "", PCH_GMBUS1, 0x468000a1, 0},
+{R, 4, "", PCH_GMBUS2, 0x8200, 0},
+{R, 1, "", PCH_GMBUS2, 0x8201, 0},
+{R, 1, "", PCH_GMBUS2, 0x8203, 0},
+{R, 1, "", PCH_GMBUS2, 0x8a04, 0},
+{R, 1, "", PCH_GMBUS3, 0xffffff00, 0},
+{R, 1, "", PCH_GMBUS2, 0x8204, 0},
+{R, 1, "", PCH_GMBUS2, 0x8206, 0},
+{R, 1, "", PCH_GMBUS2, 0x8207, 0},
+{R, 1, "", PCH_GMBUS2, 0x8a08, 0},
+{R, 1, "", PCH_GMBUS3, 0xffffff, 0},
+{R, 1, "", PCH_GMBUS2, 0x8209, 0},
+{R, 1, "", PCH_GMBUS2, 0x820a, 0},
+{R, 1, "", PCH_GMBUS2, 0x820b, 0},
+{R, 1, "", PCH_GMBUS2, 0x8a0d, 0},
+{R, 1, "", PCH_GMBUS3, 0x3143a34c, 0},
+{R, 1, "", PCH_GMBUS2, 0x820d, 0},
+{R, 1, "", PCH_GMBUS2, 0x820e, 0},
+{R, 1, "", PCH_GMBUS2, 0x820f, 0},
+{R, 1, "", PCH_GMBUS2, 0x8a11, 0},
+{R, 1, "", PCH_GMBUS3, 0x0, 0},
+{R, 1, "", PCH_GMBUS2, 0x8211, 0},
+{R, 1, "", PCH_GMBUS2, 0x8212, 0},
+{R, 1, "", PCH_GMBUS2, 0x8a14, 0},
+{R, 1, "", PCH_GMBUS3, 0x3011500, 0},
+{R, 1, "", PCH_GMBUS2, 0x8214, 0},
+{R, 1, "", PCH_GMBUS2, 0x8215, 0},
+{R, 1, "", PCH_GMBUS2, 0x8217, 0},
+{R, 1, "", PCH_GMBUS2, 0x8a18, 0},
+{R, 1, "", PCH_GMBUS3, 0x780e1a80, 0},
+{R, 1, "", PCH_GMBUS2, 0x8218, 0},
+{R, 1, "", PCH_GMBUS2, 0x8219, 0},
+{R, 1, "", PCH_GMBUS2, 0x821b, 0},
+{R, 1, "", PCH_GMBUS2, 0x8a1c, 0},
+{R, 1, "", PCH_GMBUS3, 0x91851dea, 0},
+{R, 1, "", PCH_GMBUS2, 0x821c, 0},
+{R, 1, "", PCH_GMBUS2, 0x821e, 0},
+{R, 1, "", PCH_GMBUS2, 0x821f, 0},
+{R, 1, "", PCH_GMBUS2, 0x8a20, 0},
+{R, 1, "", PCH_GMBUS3, 0x268f5956, 0},
+{R, 1, "", PCH_GMBUS2, 0x8220, 0},
+{R, 1, "", PCH_GMBUS2, 0x8222, 0},
+{R, 1, "", PCH_GMBUS2, 0x8223, 0},
+{R, 1, "", PCH_GMBUS2, 0x8a24, 0},
+{R, 1, "", PCH_GMBUS3, 0x545018, 0},
+{R, 1, "", PCH_GMBUS2, 0x8225, 0},
+{R, 1, "", PCH_GMBUS2, 0x8226, 0},
+{R, 1, "", PCH_GMBUS2, 0x8227, 0},
+{R, 1, "", PCH_GMBUS2, 0x8a29, 0},
+{R, 1, "", PCH_GMBUS3, 0x1010000, 0},
+{R, 1, "", PCH_GMBUS2, 0x8229, 0},
+{R, 1, "", PCH_GMBUS2, 0x822a, 0},
+{R, 1, "", PCH_GMBUS2, 0x822b, 0},
+{R, 1, "", PCH_GMBUS2, 0x8a2d, 0},
+{R, 1, "", PCH_GMBUS3, 0x1010101, 0},
+{R, 1, "", PCH_GMBUS2, 0x822d, 0},
+{R, 1, "", PCH_GMBUS2, 0x822e, 0},
+{R, 1, "", PCH_GMBUS2, 0x8a30, 0},
+{R, 1, "", PCH_GMBUS3, 0x1010101, 0},
+{R, 1, "", PCH_GMBUS2, 0x8230, 0},
+{R, 1, "", PCH_GMBUS2, 0x8231, 0},
+{R, 1, "", PCH_GMBUS2, 0x8233, 0},
+{R, 1, "", PCH_GMBUS2, 0x8a34, 0},
+{R, 1, "", PCH_GMBUS3, 0x1010101, 0},
+{R, 1, "", PCH_GMBUS2, 0x8234, 0},
+{R, 1, "", PCH_GMBUS2, 0x8235, 0},
+{R, 1, "", PCH_GMBUS2, 0x8237, 0},
+{R, 1, "", PCH_GMBUS2, 0x8a38, 0},
+{R, 1, "", PCH_GMBUS3, 0x1db90101, 0},
+{R, 1, "", PCH_GMBUS2, 0x8238, 0},
+{R, 1, "", PCH_GMBUS2, 0x823a, 0},
+{R, 1, "", PCH_GMBUS2, 0x823b, 0},
+{R, 1, "", PCH_GMBUS2, 0x8a3c, 0},
+{R, 1, "", PCH_GMBUS3, 0x50f056, 0},
+{R, 1, "", PCH_GMBUS2, 0x823d, 0},
+{R, 1, "", PCH_GMBUS2, 0x823e, 0},
+{R, 1, "", PCH_GMBUS2, 0x823f, 0},
+{R, 1, "", PCH_GMBUS2, 0x8a40, 0},
+{R, 1, "", PCH_GMBUS3, 0x20303016, 0},
+{R, 1, "", PCH_GMBUS2, 0x8241, 0},
+{R, 1, "", PCH_GMBUS2, 0x8242, 0},
+{R, 1, "", PCH_GMBUS2, 0x8243, 0},
+{R, 1, "", PCH_GMBUS2, 0x8a45, 0},
+{R, 1, "", PCH_GMBUS3, 0x90000025, 0},
+{R, 1, "", PCH_GMBUS2, 0x8245, 0},
+{R, 1, "", PCH_GMBUS2, 0x8246, 0},
+{R, 1, "", PCH_GMBUS2, 0x8a48, 0},
+{R, 1, "", PCH_GMBUS3, 0x19000010, 0},
+{R, 1, "", PCH_GMBUS2, 0x8248, 0},
+{R, 1, "", PCH_GMBUS2, 0x8249, 0},
+{R, 1, "", PCH_GMBUS2, 0x824a, 0},
+{R, 1, "", PCH_GMBUS2, 0x8a4c, 0},
+{R, 1, "", PCH_GMBUS3, 0xf000000, 0},
+{R, 1, "", PCH_GMBUS2, 0x824c, 0},
+{R, 1, "", PCH_GMBUS2, 0x824d, 0},
+{R, 1, "", PCH_GMBUS2, 0x824f, 0},
+{R, 1, "", PCH_GMBUS2, 0x8a50, 0},
+{R, 1, "", PCH_GMBUS3, 0x0, 0},
+{R, 1, "", PCH_GMBUS2, 0x8250, 0},
+{R, 1, "", PCH_GMBUS2, 0x8251, 0},
+{R, 1, "", PCH_GMBUS2, 0x8253, 0},
+{R, 1, "", PCH_GMBUS2, 0x8a54, 0},
+{R, 1, "", PCH_GMBUS3, 0x0, 0},
+{R, 1, "", PCH_GMBUS2, 0x8254, 0},
+{R, 1, "", PCH_GMBUS2, 0x8256, 0},
+{R, 1, "", PCH_GMBUS2, 0x8257, 0},
+{R, 1, "", PCH_GMBUS2, 0x8a58, 0},
+{R, 1, "", PCH_GMBUS3, 0x6d92500, 0},
+{R, 1, "", PCH_GMBUS2, 0x8258, 0},
+{R, 1, "", PCH_GMBUS2, 0x825a, 0},
+{R, 1, "", PCH_GMBUS2, 0x825b, 0},
+{R, 1, "", PCH_GMBUS2, 0x8a5d, 0},
+{R, 1, "", PCH_GMBUS3, 0x6a, 0},
+{R, 1, "", PCH_GMBUS2, 0x825d, 0},
+{R, 1, "", PCH_GMBUS2, 0x825e, 0},
+{R, 1, "", PCH_GMBUS2, 0x825f, 0},
+{R, 1, "", PCH_GMBUS2, 0x8a61, 0},
+{R, 1, "", PCH_GMBUS3, 0x5300fe00, 0},
+{R, 1, "", PCH_GMBUS2, 0x8261, 0},
+{R, 1, "", PCH_GMBUS2, 0x8262, 0},
+{R, 1, "", PCH_GMBUS2, 0x8a64, 0},
+{R, 1, "", PCH_GMBUS3, 0x55534d41, 0},
+{R, 1, "", PCH_GMBUS2, 0x8264, 0},
+{R, 1, "", PCH_GMBUS2, 0x8265, 0},
+{R, 1, "", PCH_GMBUS2, 0x8266, 0},
+{R, 1, "", PCH_GMBUS2, 0x8a68, 0},
+{R, 1, "", PCH_GMBUS3, 0x200a474e, 0},
+{R, 1, "", PCH_GMBUS2, 0x8268, 0},
+{R, 1, "", PCH_GMBUS2, 0x8269, 0},
+{R, 1, "", PCH_GMBUS2, 0x826b, 0},
+{R, 1, "", PCH_GMBUS2, 0x8a6c, 0},
+{R, 1, "", PCH_GMBUS3, 0x5441a34c, 0},
+{R, 1, "", PCH_GMBUS2, 0x826c, 0},
+{R, 1, "", PCH_GMBUS2, 0x826d, 0},
+{R, 1, "", PCH_GMBUS2, 0x826f, 0},
+{R, 1, "", PCH_GMBUS2, 0x8a70, 0},
+{R, 1, "", PCH_GMBUS3, 0xfe000000, 0},
+{R, 1, "", PCH_GMBUS2, 0x8270, 0},
+{R, 1, "", PCH_GMBUS2, 0x8272, 0},
+{R, 1, "", PCH_GMBUS2, 0x8273, 0},
+{R, 1, "", PCH_GMBUS2, 0x8a74, 0},
+{R, 1, "", PCH_GMBUS3, 0x4e544c00, 0},
+{R, 1, "", PCH_GMBUS2, 0x8275, 0},
+{R, 1, "", PCH_GMBUS2, 0x8276, 0},
+{R, 1, "", PCH_GMBUS2, 0x8277, 0},
+{R, 1, "", PCH_GMBUS2, 0x8a78, 0},
+{R, 1, "", PCH_GMBUS3, 0x41363131, 0},
+{R, 1, "", PCH_GMBUS2, 0x8279, 0},
+{R, 1, "", PCH_GMBUS2, 0x827a, 0},
+{R, 1, "", PCH_GMBUS2, 0x827b, 0},
+{R, 1, "", PCH_GMBUS2, 0x8a7d, 0},
+{R, 1, "", PCH_GMBUS3, 0x34363054, 0},
+{R, 1, "", PCH_GMBUS2, 0x827d, 0},
+{R, 1, "", PCH_GMBUS2, 0x827e, 0},
+{R, 1, "", PCH_GMBUS2, 0xca80, 0},
+{R, 1, "", PCH_GMBUS3, 0xe1003230, 0},
+{R, 1, "", PCH_GMBUS2, 0xc200, 0},
+{W, 1, "", PCH_GMBUS1, 0x48000000, 0},
+{R, 1, "", PCH_GMBUS2, 0x8200, 0},
+{R, 1, "", PCH_GMBUS2, 0x8800, 0},
+{W, 1, "", PCH_GMBUS0, 0x0, 0},
+{R, 1, "", PCH_LVDS, 0x80300302, 0},
+{R, 1, "", BLC_PWM_CPU_CTL2, 0x80000000, 0},
+{W, 1, "", BLC_PWM_CPU_CTL2, 0x80000000, 0},
+{R, 1, "", BLC_PWM_PCH_CTL1, 0x80000000, 0},
+{W, 1, "", BLC_PWM_PCH_CTL1, 0x80000000, 0},
+{R, 1, "", PCH_PP_CONTROL, 0x3, 0},
+{W, 1, "", PCH_PP_CONTROL, 0xabcd0003, 0},
+{R, 1, "", BLC_PWM_CPU_CTL, 0x1312, 0},
+{R, 1, "", BLC_PWM_PCH_CTL2, 0x13121312, 0},
+{R, 1, "", BLC_PWM_CPU_CTL, 0x1312, 0},
+{R, 1, "", 0x64000, 0x18, 0},
+{R, 1, "", PCH_ADPA, 0x40000, 0},
+{W, 1, "", PCH_ADPA, 0xf40000, 0},
+{R, 1, "", PCH_ADPA, 0xf40000, 0},
+{R, 1, "", HDMIB, 0x1c, 0},
+{W, 1, "", PCH_GMBUS0, 0x0, 0},
+{R, 1, "", PCH_GPIOE, 0x1810, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{R, 2, "", PCH_GPIOE, 0x1810, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x1810, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 1, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", _VIDEO_DIP_CTL_A, 0x0, 0},
+{W, 1, "", _VIDEO_DIP_CTL_B, 0x0, 0},
+{R, 1, "", PCH_DP_B, 0x4, 0},
+{R, 1, "", PCH_DPB_AUX_CH_CTL, 0x144003e, 0},
+{W, 1, "", PCH_DPB_AUX_CH_DATA1, 0x40000000, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0xd235003f, 0},
+{R, 5, "", PCH_DPB_AUX_CH_CTL, 0x8145003f, 100},
+{R, 1, "", PCH_DPB_AUX_CH_CTL, 0x5145003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0x5345003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_DATA1, 0x40000000, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0xd235003f, 0},
+{R, 5, "", PCH_DPB_AUX_CH_CTL, 0x8145003f, 100},
+{R, 1, "", PCH_DPB_AUX_CH_CTL, 0x5145003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0x5345003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_DATA1, 0x40000000, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0xd235003f, 0},
+{R, 5, "", PCH_DPB_AUX_CH_CTL, 0x8145003f, 100},
+{R, 1, "", PCH_DPB_AUX_CH_CTL, 0x5145003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0x5345003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_DATA1, 0x40000000, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0xd235003f, 0},
+{R, 5, "", PCH_DPB_AUX_CH_CTL, 0x8145003f, 100},
+{R, 1, "", PCH_DPB_AUX_CH_CTL, 0x5145003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0x5345003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_DATA1, 0x40000000, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0xd235003f, 0},
+{R, 5, "", PCH_DPB_AUX_CH_CTL, 0x8145003f, 100},
+{R, 1, "", PCH_DPB_AUX_CH_CTL, 0x5145003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0x5345003f, 0},
+{R, 1, "", PCH_DPB_AUX_CH_CTL, 0x145003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_DATA1, 0x0, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0xd235003f, 0},
+{R, 5, "", PCH_DPB_AUX_CH_CTL, 0x8145003f, 100},
+{R, 1, "", PCH_DPB_AUX_CH_CTL, 0x5145003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0x5345003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_DATA1, 0x0, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0xd235003f, 0},
+{R, 5, "", PCH_DPB_AUX_CH_CTL, 0x8145003f, 100},
+{R, 1, "", PCH_DPB_AUX_CH_CTL, 0x5145003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0x5345003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_DATA1, 0x0, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0xd235003f, 0},
+{R, 5, "", PCH_DPB_AUX_CH_CTL, 0x8145003f, 100},
+{R, 1, "", PCH_DPB_AUX_CH_CTL, 0x5145003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0x5345003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_DATA1, 0x0, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0xd235003f, 0},
+{R, 5, "", PCH_DPB_AUX_CH_CTL, 0x8145003f, 100},
+{R, 1, "", PCH_DPB_AUX_CH_CTL, 0x5145003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0x5345003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_DATA1, 0x0, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0xd235003f, 0},
+{R, 5, "", PCH_DPB_AUX_CH_CTL, 0x8145003f, 100},
+{R, 1, "", PCH_DPB_AUX_CH_CTL, 0x5145003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0x5345003f, 0},
+{R, 1, "", HDMIC, 0x18, 0},
+{R, 1, "", HDMID, 0x18, 0},
+{R, 1, "", PCH_DP_C, 0x0, 0},
+{R, 1, "", PCH_DP_D, 0x0, 0},
+{R, 1, "", BLC_PWM_CPU_CTL, 0x1312, 0},
+{W, 1, "", BLC_PWM_CPU_CTL, 0x0, 0},
+{R, 1, "", PCH_PP_CONTROL, 0xabcd0003, 0},
+{W, 1, "", PCH_PP_CONTROL, 0xabcd0002, 0},
+{R, 1, "", PCH_PP_STATUS, 0xc0000008, 0},
+{R, 1625, "", PCH_PP_STATUS, 0xe0000003, 0},
+{R, 406, "", PCH_PP_STATUS, 0xe0000002, 0},
+{R, 1, "", PCH_PP_STATUS, 0x48000001, 0},
+{R, 1, "", PCH_LVDS, 0x80300302, 0},
+{W, 1, "", PCH_LVDS, 0x300302, 0},
+{R, 1, "", PCH_LVDS, 0x300302, 0},
+{R, 1, "", PCH_ADPA, 0xf40000, 0},
+{W, 1, "", PCH_ADPA, 0xf40c00, 0},
+{R, 1, "", HDMIB, 0x1c, 0},
+{W, 1, "", HDMIB, 0x1c, 0},
+{R, 1, "", HDMIB, 0x1c, 0},
+{W, 1, "", HDMIB, 0x1c, 0},
+{R, 1, "", HDMIB, 0x1c, 0},
+{W, 1, "", HDMIB, 0x1c, 0},
+{R, 1, "", HDMIB, 0x1c, 0},
+{R, 2, "", PCH_DP_B, 0x4, 0},
+{W, 1, "", DEIMR, 0x80, 0},
+{R, 1, "", DEIMR, 0x80, 0},
+{R, 1, "", _PIPEACONF, 0xc0000050, 0},
+{R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x306, 0},
+{R, 1, "", _PIPEACONF, 0xc0000050, 0},
+{R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x306, 0},
+{R, 1, "", _DSPACNTR, 0x94000000, 0},
+{W, 1, "", _DSPACNTR, 0x14000000, 0},
+{R, 1, "", _DSPAADDR, 0x0, 0},
+{W, 1, "", _DSPAADDR, 0x0, 0},
+{R, 1, "", _DSPASIZE+0xc, 0x0, 0},
+{W, 1, "", _DSPASIZE+0xc, 0x0, 0},
+{R, 1, "", _PIPEASTAT, 0x0, 0},
+{W, 1, "", _PIPEASTAT, 0x2, 0},
+{R, 416, "", _PIPEASTAT, 0x0, 0},
+{R, 1, "", ILK_DPFC_CONTROL, 0x0, 0},
+{R, 1, "", _DSPACNTR, 0x14000000, 0},
+{R, 1, "", _PIPEACONF, 0xc0000050, 0},
+{W, 1, "", _PIPEACONF, 0x40000050, 0},
+{R, 117, "", _PIPEACONF, 0x40000050, 0},
+{R, 1, "", _PIPEACONF, 0x50, 0},
+{W, 1, "", _PFA_CTL_1, 0x0, 0},
+{W, 1, "", _PFA_WIN_SZ, 0x0, 0},
+{R, 1, "", _FDI_TXA_CTL, 0xb0044000, 0},
+{W, 1, "", _FDI_TXA_CTL, 0x30044000, 0},
+{R, 1, "", _FDI_TXA_CTL, 0x30044000, 0},
+{R, 1, "", _FDI_RXA_CTL, 0x80022350, 0},
+{R, 1, "", _PIPEACONF, 0x50, 0},
+{W, 1, "", _FDI_RXA_CTL, 0x22350, 0},
+{R, 1, "", _FDI_RXA_CTL, 0x22350, 100},
+{R, 1, "", SOUTH_CHICKEN1, 0x0, 0},
+{W, 2, "", SOUTH_CHICKEN1, 0x0, 0},
+{R, 1, "", SOUTH_CHICKEN1, 0x0, 0},
+{R, 1, "", _FDI_TXA_CTL, 0x30044000, 0},
+{W, 1, "", _FDI_TXA_CTL, 0x44000, 0},
+{R, 1, "", _FDI_RXA_CTL, 0x22350, 0},
+{R, 1, "", _PIPEACONF, 0x50, 0},
+{W, 1, "", _FDI_RXA_CTL, 0x22050, 0},
+{R, 1, "", _FDI_RXA_CTL, 0x22050, 100},
+{R, 1, "", PCH_PP_CONTROL, 0xabcd0002, 0},
+{W, 1, "", PCH_PP_CONTROL, 0xabcd0002, 0},
+{R, 1, "", PCH_DP_B, 0x4, 0},
+{R, 1, "", PCH_DP_C, 0x0, 0},
+{R, 1, "", PCH_DP_D, 0x0, 0},
+{R, 1, "", PCH_ADPA, 0xf40000, 0},
+{R, 1, "", PCH_LVDS, 0x300302, 0},
+{R, 1, "", HDMIB, 0x1c, 0},
+{R, 1, "", HDMIC, 0x18, 0},
+{R, 1, "", HDMID, 0x18, 0},
+{R, 1, "", _FDI_TXA_CTL, 0x44000, 0},
+{R, 1, "", _FDI_RXA_CTL, 0x22050, 0},
+{R, 1, "", PCH_DP_B, 0x4, 0},
+{R, 1, "", PCH_DP_C, 0x0, 0},
+{R, 1, "", PCH_DP_D, 0x0, 0},
+{R, 1, "", PCH_ADPA, 0xf40000, 0},
+{R, 1, "", PCH_LVDS, 0x300302, 0},
+{R, 1, "", HDMIB, 0x1c, 0},
+{R, 1, "", HDMIC, 0x18, 0},
+{R, 1, "", HDMID, 0x18, 0},
+{R, 1, "", _TRANSACONF, 0xc0000000, 0},
+{W, 1, "", _TRANSACONF, 0x40000000, 0},
+{R, 131, "", _TRANSACONF, 0x40000000, 0},
+{R, 1, "", _TRANSACONF, 0x0, 0},
+{R, 1, "", TRANS_DP_CTL_A, 0x60000418, 0},
+{W, 1, "", TRANS_DP_CTL_A, 0x60000418, 0},
+{R, 1, "", PCH_DPLL_SEL, 0x8, 0},
+{W, 1, "", PCH_DPLL_SEL, 0x0, 0},
+{R, 1, "", _TRANSACONF, 0x0, 0},
+{R, 1, "", PCH_DPLL_SEL, 0x0, 0},
+{R, 1, "", _PCH_DPLL_A, 0x88040004, 0},
+{W, 1, "", _PCH_DPLL_A, 0x8040004, 0},
+{R, 1, "", _PCH_DPLL_A, 0x8040004, 200},
+{R, 1, "", _FDI_RXA_CTL, 0x22050, 0},
+{W, 1, "", _FDI_RXA_CTL, 0x22040, 0},
+{R, 1, "", _FDI_TXA_CTL, 0x44000, 0},
+{W, 1, "", _FDI_TXA_CTL, 0x40000, 0},
+{R, 1, "", _FDI_TXA_CTL, 0x40000, 100},
+{R, 1, "", _FDI_RXA_CTL, 0x22040, 0},
+{W, 1, "", _FDI_RXA_CTL, 0x20040, 0},
+{R, 1, "", _FDI_RXA_CTL, 0x20040, 100},
+{R, 1, "", 0x145d10, 0x16040307, 0},
+{W, 1, "", WM3_LP_ILK, 0x0, 0},
+{W, 1, "", WM2_LP_ILK, 0x0, 0},
+{W, 1, "", WM1_LP_ILK, 0x0, 0},
+{R, 1, "", ILK_DPFC_CONTROL, 0x0, 0},
+{R, 1, "", 0x130090, 0x0, 0},
+{W, 1, "", 0xa18c, 0x1, 0},
+{R, 1, "", 0xa18c, 0x0, 0},
+{R, 12, "", 0x130090, 0x0, 0},
+{R, 1, "", 0x130090, 0x1, 0},
+{R, 1, "", 0x13805c, 0x40000000, 0},
+{W, 1, "", 0xa18c, 0x0, 0},
+{R, 1, "", 0x120000, 0x0, 0},
+{R, 1, "", 0x3c, 0x0, 0},
+{R, 1, "", _DSPACNTR, 0x14000000, 0},
+{R, 1, "", _PIPEACONF, 0x50, 0},
+{W, 1, "", DEIMR, 0x8080, 0},
+{R, 1, "", DEIMR, 0x8080, 0},
+{R, 2, "", _PIPEBCONF, 0x0, 0},
+{R, 2, "", _DSPBCNTR, 0x0, 0},
+{R, 1, "", _PIPEBCONF, 0x0, 0},
+{W, 1, "", _PFB_CTL_1, 0x0, 0},
+{W, 1, "", _PFB_WIN_SZ, 0x0, 0},
+{R, 1, "", _FDI_TXB_CTL, 0x40000, 0},
+{W, 1, "", _FDI_TXB_CTL, 0x40000, 0},
+{R, 1, "", _FDI_TXB_CTL, 0x40000, 0},
+{R, 1, "", _FDI_RXB_CTL, 0x40, 0},
+{R, 1, "", _PIPEBCONF, 0x0, 0},
+{W, 1, "", _FDI_RXB_CTL, 0x40, 0},
+{R, 1, "", _FDI_RXB_CTL, 0x40, 100},
+{R, 1, "", SOUTH_CHICKEN1, 0x0, 0},
+{W, 2, "", SOUTH_CHICKEN1, 0x0, 0},
+{R, 1, "", SOUTH_CHICKEN1, 0x0, 0},
+{R, 1, "", _FDI_TXB_CTL, 0x40000, 0},
+{W, 1, "", _FDI_TXB_CTL, 0x40000, 0},
+{R, 1, "", _FDI_RXB_CTL, 0x40, 0},
+{R, 1, "", _PIPEBCONF, 0x0, 0},
+{W, 1, "", _FDI_RXB_CTL, 0x40, 0},
+{R, 1, "", _FDI_RXB_CTL, 0x40, 100},
+{R, 1, "", PCH_PP_CONTROL, 0xabcd0002, 0},
+{W, 1, "", PCH_PP_CONTROL, 0xabcd0002, 0},
+{R, 1, "", PCH_DP_B, 0x4, 0},
+{R, 1, "", PCH_DP_C, 0x0, 0},
+{R, 1, "", PCH_DP_D, 0x0, 0},
+{R, 1, "", PCH_ADPA, 0xf40000, 0},
+{R, 1, "", PCH_LVDS, 0x300302, 0},
+{R, 1, "", HDMIB, 0x1c, 0},
+{R, 1, "", HDMIC, 0x18, 0},
+{R, 1, "", HDMID, 0x18, 0},
+{R, 1, "", _FDI_TXB_CTL, 0x40000, 0},
+{R, 1, "", _FDI_RXB_CTL, 0x40, 0},
+{R, 1, "", PCH_DP_B, 0x4, 0},
+{R, 1, "", PCH_DP_C, 0x0, 0},
+{R, 1, "", PCH_DP_D, 0x0, 0},
+{R, 1, "", PCH_ADPA, 0xf40000, 0},
+{R, 1, "", PCH_LVDS, 0x300302, 0},
+{R, 1, "", HDMIB, 0x1c, 0},
+{R, 1, "", HDMIC, 0x18, 0},
+{R, 1, "", HDMID, 0x18, 0},
+{R, 1, "", _TRANSBCONF, 0x0, 0},
+{W, 1, "", _TRANSBCONF, 0x0, 0},
+{R, 1, "", _TRANSBCONF, 0x0, 0},
+{R, 1, "", TRANS_DP_CTL_B, 0x60000018, 0},
+{W, 1, "", TRANS_DP_CTL_B, 0x60000018, 0},
+{R, 1, "", PCH_DPLL_SEL, 0x0, 0},
+{W, 1, "", PCH_DPLL_SEL, 0x0, 0},
+{R, 1, "", _TRANSBCONF, 0x0, 0},
+{R, 1, "", PCH_DPLL_SEL, 0x0, 0},
+{R, 1, "", _PCH_DPLL_B, 0x4800080, 0},
+{W, 1, "", _PCH_DPLL_B, 0x4800080, 0},
+{R, 1, "", _PCH_DPLL_B, 0x4800080, 200},
+{R, 1, "", _FDI_RXB_CTL, 0x40, 0},
+{W, 1, "", _FDI_RXB_CTL, 0x40, 0},
+{R, 1, "", _FDI_TXB_CTL, 0x40000, 0},
+{W, 1, "", _FDI_TXB_CTL, 0x40000, 0},
+{R, 1, "", _FDI_TXB_CTL, 0x40000, 100},
+{R, 1, "", _FDI_RXB_CTL, 0x40, 0},
+{W, 1, "", _FDI_RXB_CTL, 0x40, 0},
+{R, 1, "", _FDI_RXB_CTL, 0x40, 100},
+{R, 1, "", 0x145d10, 0x16040307, 0},
+{W, 1, "", WM3_LP_ILK, 0x0, 0},
+{W, 1, "", WM2_LP_ILK, 0x0, 0},
+{W, 1, "", WM1_LP_ILK, 0x0, 0},
+{R, 1, "", ILK_DPFC_CONTROL, 0x0, 0},
+{R, 1, "", 0x130090, 0x0, 0},
+{W, 1, "", 0xa18c, 0x1, 0},
+{R, 1, "", 0xa18c, 0x0, 0},
+{R, 10, "", 0x130090, 0x0, 0},
+{R, 1, "", 0x130090, 0x1, 0},
+{R, 1, "", 0x13805c, 0x40000000, 0},
+{W, 1, "", 0xa18c, 0x0, 0},
+{R, 1, "", 0x120000, 0x0, 0},
+{R, 1, "", 0x3c, 0x0, 0},
+{R, 1, "", _DSPBCNTR, 0x0, 0},
+{R, 1, "", _PIPEBCONF, 0x0, 0},
+{R, 1, "", PCH_DREF_CONTROL, 0x400, 0},
+{W, 1, "", PCH_DREF_CONTROL, 0x1400, 0},
+{R, 1, "", PCH_DREF_CONTROL, 0x1400, 200},
+{W, 1, "", PCH_DREF_CONTROL, 0x1400, 0},
+{R, 1, "", PCH_DREF_CONTROL, 0x1400, 200},
+{W, 1, "", ILK_DSPCLK_GATE, 0x10000000, 0},
+{R, 1, "", ILK_DISPLAY_CHICKEN2, 0x200c000, 0},
+{W, 1, "", ILK_DISPLAY_CHICKEN2, 0x200c000, 0},
+{W, 1, "", WM3_LP_ILK, 0x0, 0},
+{W, 1, "", WM2_LP_ILK, 0x0, 0},
+{W, 1, "", WM1_LP_ILK, 0x0, 0},
+{R, 1, "", 0x130090, 0x0, 0},
+{W, 1, "", 0xa18c, 0x1, 0},
+{R, 1, "", 0xa18c, 0x0, 0},
+{R, 8, "", 0x130090, 0x0, 0},
+{R, 1, "", 0x130090, 0x1, 0},
+{R, 1, "", 0x13805c, 0x40000000, 0},
+{W, 1, "", 0xa18c, 0x0, 0},
+{R, 1, "", 0x120000, 0x0, 0},
+{R, 1, "", 0x9400, 0x2f00080, 0},
+{R, 1, "", 0x120008, 0x3f, 0},
+{W, 1, "", 0x9400, 0x2f000a0, 0},
+{W, 1, "", 0x9404, 0x1800, 0},
+{R, 1, "", ILK_DISPLAY_CHICKEN1, 0x0, 0},
+{W, 1, "", ILK_DISPLAY_CHICKEN1, 0x600000, 0},
+{R, 1, "", ILK_DISPLAY_CHICKEN2, 0x200c000, 0},
+{W, 1, "", ILK_DISPLAY_CHICKEN2, 0x260c000, 0},
+{R, 1, "", ILK_DSPCLK_GATE, 0x10000000, 0},
+{W, 1, "", ILK_DSPCLK_GATE, 0x100000a0, 0},
+{R, 1, "", _DSPACNTR, 0x14000000, 0},
+{W, 1, "", _DSPACNTR, 0x14004000, 0},
+{R, 1, "", _DSPAADDR, 0x0, 0},
+{W, 1, "", _DSPAADDR, 0x0, 0},
+{R, 1, "", _DSPASIZE+0xc, 0x0, 0},
+{W, 1, "", _DSPASIZE+0xc, 0x0, 0},
+{R, 1, "", _DSPBCNTR, 0x0, 0},
+{W, 1, "", _DSPBCNTR, 0x4000, 0},
+{R, 1, "", _DSPBADDR, 0x0, 0},
+{W, 1, "", _DSPBADDR, 0x0, 0},
+{R, 1, "", _DSPBSURF, 0x0, 0},
+{W, 1, "", _DSPBSURF, 0x0, 0},
+{W, 1, "", SOUTH_DSPCLK_GATE_D, 0x20000000, 0},
+{R, 1, "", SOUTH_CHICKEN2, 0x4, 0},
+{W, 1, "", SOUTH_CHICKEN2, 0x5, 0},
+{W, 1, "", _TRANSA_CHICKEN2, 0x80000000, 0},
+{W, 1, "", _TRANSB_CHICKEN2, 0x80000000, 0},
+{R, 1, "", 0x145998, 0x70714, 0},
+{R, 1, "", 0x145948, 0x729, 0},
+{W, 1, "", 0xa094, 0x0, 0},
+{R, 1, "", 0x120000, 0x0, 0},
+{R, 1, "", 0x130090, 0x0, 0},
+{W, 1, "", 0xa18c, 0x1, 0},
+{R, 1, "", 0xa18c, 0x0, 0},
+{R, 4, "", 0x130090, 0x0, 0},
+{R, 1, "", 0x130090, 0x1, 0},
+{R, 1, "", 0x13805c, 0x40000000, 0},
+{W, 1, "", 0xa090, 0x0, 0},
+{W, 1, "", 0xa098, 0x3e80000, 0},
+{W, 1, "", 0xa09c, 0x28001e, 0},
+{W, 1, "", 0xa0a0, 0x1e, 0},
+{W, 1, "", 0xa0a8, 0x1e848, 0},
+{W, 1, "", 0xa0ac, 0x19, 0},
+{W, 3, "", 0x54, 0xa, 0},
+{W, 1, "", 0xa0b0, 0x0, 0},
+{W, 1, "", 0xa0b4, 0x3e8, 0},
+{W, 1, "", 0xa0b8, 0xc350, 0},
+{W, 1, "", 0xa0bc, 0x186a0, 0},
+{W, 1, "", 0xa0c0, 0xfa00, 0},
+{M, 1, "[drm] Enabling RC6 states RC6 on, RC6p off, RC6pp off", },
+{W, 1, "", 0xa090, 0x88040000, 0},
+{W, 1, "", _PALETTE_A+0x8, 0x14000000, 0},
+{W, 1, "", _PALETTE_A+0xc, 0x18000000, 0},
+{W, 1, "", _PALETTE_A+0x10, 0x2710, 0},
+{W, 1, "", _PALETTE_A+0x14, 0x12060000, 0},
+{W, 1, "", _PALETTE_A+0x2c, 0x4000, 0},
+{W, 1, "", _PALETTE_A+0x30, 0x4000, 0},
+{W, 1, "", _PALETTE_A+0x68, 0x186a0, 0},
+{W, 1, "", _PALETTE_A+0x6c, 0x4c4b40, 0},
+{W, 1, "", _PALETTE_A+0x70, 0xa, 0},
+{W, 1, "", _PALETTE_A+0x24, 0xb91, 0},
+{R, 1, "", 0x138124, 0x0, 0},
+{W, 1, "", 0x138128, 0x0, 0},
+{W, 1, "", 0x138124, 0x80000008, 0},
+{R, 2, "", 0x138124, 0x10, 0},
+{W, 1, "", 0x138124, 0xc, 0},
+{R, 1, "", 0x138128, 0x0, 0},
+{R, 1, "", 0x138124, 0xc, 0},
+{W, 1, "", GEN6_PMIER, 0x3000076, 0},
+{W, 1, "", GEN6_PMISR+0x4, 0x0, 0},
+{W, 1, "", 0xa168, 0x0, 0},
+{W, 1, "", 0xa18c, 0x0, 0},
+{R, 1, "", 0x120000, 0x0, 0},
+{W, 1, "", 0x138128, 0xe14, 0},
+{W, 1, "", 0x138124, 0x80000008, 0},
+{R, 1, "", 0x138124, 0x0, 0},
+{W, 1, "", 0x138128, 0xd13, 0},
+{W, 1, "", 0x138124, 0x80000008, 0},
+{R, 1, "", 0x138124, 0x0, 0},
+{W, 1, "", 0x138128, 0xc12, 0},
+{W, 1, "", 0x138124, 0x80000008, 0},
+{R, 1, "", 0x138124, 0x0, 0},
+{W, 1, "", 0x138128, 0xb11, 0},
+{W, 1, "", 0x138124, 0x80000008, 0},
+{R, 1, "", 0x138124, 0x0, 0},
+{W, 1, "", 0x138128, 0xa10, 0},
+{W, 1, "", 0x138124, 0x80000008, 0},
+{R, 1, "", 0x138124, 0x0, 0},
+{W, 1, "", 0x138128, 0x90f, 0},
+{W, 1, "", 0x138124, 0x80000008, 0},
+{R, 1, "", 0x138124, 0x0, 0},
+{W, 1, "", 0x138128, 0x80e, 0},
+{W, 1, "", 0x138124, 0x80000008, 0},
+{R, 1, "", 0x138124, 0x0, 0},
+{W, 1, "", 0x138128, 0x80d, 0},
+{W, 1, "", 0x138124, 0x80000008, 0},
+{R, 1, "", 0x138124, 0x0, 0},
+{W, 1, "", 0x138128, 0x80c, 0},
+{W, 1, "", 0x138124, 0x80000008, 0},
+{R, 1, "", 0x138124, 0x0, 0},
+{W, 1, "", 0x138128, 0x80b, 0},
+{W, 1, "", 0x138124, 0x80000008, 0},
+{R, 1, "", 0x138124, 0x0, 0},
+{W, 1, "", 0x138128, 0x80a, 0},
+{W, 1, "", 0x138124, 0x80000008, 0},
+{R, 1, "", 0x138124, 0x0, 0},
+{W, 1, "", 0x138128, 0x809, 0},
+{W, 1, "", 0x138124, 0x80000008, 0},
+{R, 1, "", 0x138124, 0x0, 0},
+{W, 1, "", 0x138128, 0x808, 0},
+{W, 1, "", 0x138124, 0x80000008, 0},
+{R, 1, "", 0x138124, 0x0, 0},
+{W, 1, "", 0x138128, 0x807, 0},
+{W, 1, "", 0x138124, 0x80000008, 0},
+{R, 1, "", 0x138124, 0x0, 0},
+{R, 1, "", DISP_ARB_CTL, 0xc2240622, 0},
+{W, 1, "", DISP_ARB_CTL, 0xc2242622, 0},
+{R, 1, "", 0x101000, 0x0, 0},
+{W, 1, "", 0x101000, 0x1, 0},
+{W, 1, "", ARB_MODE, 0x100010, 0},
+{W, 1, "", 0x4080, 0x0, 0},
+{R, 1, "", 0x4080, 0x0, 0},
+{W, 1, "", PRB0_CTL, 0x0, 0},
+{W, 1, "", PRB0_HEAD, 0x0, 0},
+{W, 1, "", PRB0_TAIL, 0x0, 0},
+{W, 1, "", PRB0_START, 0x1000, 0},
+{R, 1, "", 0x130090, 0x0, 0},
+{W, 1, "", 0xa18c, 0x1, 0},
+{R, 1, "", 0xa18c, 0x0, 0},
+{R, 1, "", 0x130090, 0x0, 0},
+{R, 1, "", 0x130090, 0x1, 0},
+{R, 1, "", 0x13805c, 0x40000000, 0},
+{W, 1, "", 0xa18c, 0x0, 0},
+{R, 1, "", 0x120000, 0x0, 0},
+{R, 1, "", PRB0_HEAD, 0x0, 0},
+{W, 1, "", PRB0_CTL, 0x1f001, 0},
+{R, 1, "", 0x130090, 0x0, 0},
+{W, 1, "", 0xa18c, 0x1, 0},
+{R, 1, "", 0xa18c, 0x1, 0},
+{R, 1, "", 0x130090, 0x1, 0},
+{R, 1, "", 0x13805c, 0x40000000, 0},
+{W, 1, "", 0xa18c, 0x0, 0},
+{R, 1, "", 0x120000, 0x0, 0},
+{R, 1, "", PRB0_CTL, 0x1f001, 0},
+{R, 1, "", 0x130090, 0x0, 0},
+{W, 1, "", 0xa18c, 0x1, 0},
+{R, 1, "", 0xa18c, 0x1, 0},
+{R, 1, "", 0x130090, 0x1, 0},
+{R, 1, "", 0x13805c, 0x40000000, 0},
+{W, 1, "", 0xa18c, 0x0, 0},
+{R, 1, "", 0x120000, 0x0, 0},
+{R, 1, "", PRB0_START, 0x1000, 0},
+{R, 1, "", 0x130090, 0x0, 0},
+{W, 1, "", 0xa18c, 0x1, 0},
+{R, 1, "", 0xa18c, 0x0, 0},
+{R, 3, "", 0x130090, 0x0, 0},
+{R, 1, "", 0x130090, 0x1, 0},
+{R, 1, "", 0x13805c, 0x40000000, 0},
+{W, 1, "", 0xa18c, 0x0, 0},
+{R, 1, "", 0x120000, 0x0, 0},
+{R, 1, "", PRB0_HEAD, 0x0, 0},
+{R, 1, "", 0x130090, 0x0, 0},
+{W, 1, "", 0xa18c, 0x1, 0},
+{R, 1, "", 0xa18c, 0x1, 0},
+{R, 1, "", 0x130090, 0x1, 0},
+{R, 1, "", 0x13805c, 0x40000000, 0},
+{W, 1, "", 0xa18c, 0x0, 0},
+{R, 1, "", 0x120000, 0x0, 0},
+{R, 1, "", PRB0_HEAD, 0x0, 0},
+{R, 1, "", 0x130090, 0x0, 0},
+{W, 1, "", 0xa18c, 0x1, 0},
+{R, 1, "", 0xa18c, 0x0, 0},
+{R, 4, "", 0x130090, 0x0, 0},
+{R, 1, "", 0x130090, 0x1, 0},
+{R, 1, "", 0x13805c, 0x40000000, 0},
+{W, 1, "", 0xa18c, 0x0, 0},
+{R, 1, "", 0x120000, 0x0, 0},
+{R, 1, "", PRB0_TAIL, 0x0, 0},
+{W, 1, "", MI_MODE, 0x400040, 0},
+{W, 1, "", 0x2120, 0x200000, 0},
+{W, 1, "", INSTPM, 0x800080, 0},
+{W, 1, "", 0x14080, 0x22000, 0},
+{R, 1, "", 0x14080, 0x0, 0},
+{W, 1, "", GEN6_BSD_RING_BASE+0x3c, 0x0, 0},
+{W, 1, "", GEN6_BSD_RING_BASE+0x34, 0x0, 0},
+{W, 1, "", GEN6_BSD_SLEEP_PSMI_CONTROL, 0x10001, 0},
+{W, 1, "", GEN6_BSD_RNCID, 0x0, 0},
+{R, 1, "", 0x130090, 0x0, 0},
+{W, 1, "", 0xa18c, 0x1, 0},
+{R, 1, "", 0xa18c, 0x0, 0},
+{R, 3, "", 0x130090, 0x0, 0},
+{R, 1, "", 0x130090, 0x1, 0},
+{R, 1, "", 0x13805c, 0x40000000, 0},
+{W, 1, "", 0xa18c, 0x0, 0},
+{R, 1, "", 0x120000, 0x0, 0},
+{R, 1, "", GEN6_BSD_SLEEP_PSMI_CONTROL, 0x11, 0},
+{R, 1, "", 0x120008, 0x3f, 0},
+{W, 1, "", GEN6_BSD_RING_BASE+0x30, 0x0, 0},
+{W, 1, "", GEN6_BSD_SLEEP_PSMI_CONTROL, 0x10000, 0},
+{W, 1, "", GEN6_BSD_RING_BASE+0x38, 0x23000, 0},
+{R, 1, "", 0x130090, 0x0, 0},
+{W, 1, "", 0xa18c, 0x1, 0},
+{R, 1, "", 0xa18c, 0x1, 0},
+{R, 1, "", 0x130090, 0x1, 0},
+{R, 1, "", 0x13805c, 0x40000000, 0},
+{W, 1, "", 0xa18c, 0x0, 0},
+{R, 1, "", 0x120000, 0x0, 0},
+{R, 1, "", GEN6_BSD_RING_BASE+0x34, 0x0, 0},
+{W, 1, "", GEN6_BSD_RING_BASE+0x3c, 0x1f001, 0},
+{R, 1, "", 0x130090, 0x0, 0},
+{W, 1, "", 0xa18c, 0x1, 0},
+{R, 1, "", 0xa18c, 0x0, 0},
+{R, 4, "", 0x130090, 0x0, 0},
+{R, 1, "", 0x130090, 0x1, 0},
+{R, 1, "", 0x13805c, 0x40000000, 0},
+{W, 1, "", 0xa18c, 0x0, 0},
+{R, 1, "", 0x120000, 0x0, 0},
+{R, 1, "", GEN6_BSD_RING_BASE+0x3c, 0x1f001, 0},
+{R, 1, "", 0x130090, 0x0, 0},
+{W, 1, "", 0xa18c, 0x1, 0},
+{R, 1, "", 0xa18c, 0x1, 0},
+{R, 1, "", 0x130090, 0x1, 0},
+{R, 1, "", 0x13805c, 0x40000000, 0},
+{W, 1, "", 0xa18c, 0x0, 0},
+{R, 1, "", 0x120000, 0x0, 0},
+{R, 1, "", GEN6_BSD_RING_BASE+0x38, 0x23000, 0},
+{R, 1, "", 0x130090, 0x0, 0},
+{W, 1, "", 0xa18c, 0x1, 0},
+{R, 1, "", 0xa18c, 0x0, 0},
+{R, 3, "", 0x130090, 0x0, 0},
+{R, 1, "", 0x130090, 0x1, 0},
+{R, 1, "", 0x13805c, 0x40000000, 0},
+{W, 1, "", 0xa18c, 0x0, 0},
+{R, 1, "", 0x120000, 0x0, 0},
+{R, 1, "", GEN6_BSD_RING_BASE+0x34, 0x0, 0},
+{R, 1, "", 0x130090, 0x0, 0},
+{W, 1, "", 0xa18c, 0x1, 0},
+{R, 1, "", 0xa18c, 0x1, 0},
+{R, 1, "", 0x130090, 0x1, 0},
+{R, 1, "", 0x13805c, 0x40000000, 0},
+{W, 1, "", 0xa18c, 0x0, 0},
+{R, 1, "", 0x120000, 0x0, 0},
+{R, 1, "", GEN6_BSD_RING_BASE+0x34, 0x0, 0},
+{R, 1, "", 0x130090, 0x0, 0},
+{W, 1, "", 0xa18c, 0x1, 0},
+{R, 1, "", 0xa18c, 0x0, 0},
+{R, 4, "", 0x130090, 0x0, 0},
+{R, 1, "", 0x130090, 0x1, 0},
+{R, 1, "", 0x13805c, 0x40000000, 0},
+{W, 1, "", 0xa18c, 0x0, 0},
+{R, 1, "", 0x120000, 0x0, 0},
+{R, 1, "", GEN6_BSD_RING_BASE+0x30, 0x0, 0},
+{W, 1, "", 0x24080, 0x43000, 0},
+{R, 1, "", 0x24080, 0x43000, 0},
+{W, 1, "", BLT_RING_BASE+0x3c, 0x0, 0},
+{W, 1, "", BLT_RING_BASE+0x34, 0x0, 0},
+{W, 1, "", BLT_RING_BASE+0x30, 0x0, 0},
+{W, 1, "", BLT_RING_BASE+0x38, 0x44000, 0},
+{R, 1, "", 0x130090, 0x0, 0},
+{W, 1, "", 0xa18c, 0x1, 0},
+{R, 1, "", 0xa18c, 0x0, 0},
+{R, 3, "", 0x130090, 0x0, 0},
+{R, 1, "", 0x130090, 0x1, 0},
+{R, 1, "", 0x13805c, 0x40000000, 0},
+{W, 1, "", 0xa18c, 0x0, 0},
+{R, 1, "", 0x120000, 0x0, 0},
+{R, 1, "", BLT_RING_BASE+0x34, 0x0, 0},
+{W, 1, "", BLT_RING_BASE+0x3c, 0x1f001, 0},
+{R, 1, "", 0x130090, 0x0, 0},
+{W, 1, "", 0xa18c, 0x1, 0},
+{R, 1, "", 0xa18c, 0x1, 0},
+{R, 1, "", 0x130090, 0x1, 0},
+{R, 1, "", 0x13805c, 0x40000000, 0},
+{W, 1, "", 0xa18c, 0x0, 0},
+{R, 1, "", 0x120000, 0x0, 0},
+{R, 1, "", BLT_RING_BASE+0x3c, 0x1f001, 0},
+{R, 1, "", 0x130090, 0x0, 0},
+{W, 1, "", 0xa18c, 0x1, 0},
+{R, 1, "", 0xa18c, 0x0, 0},
+{R, 3, "", 0x130090, 0x0, 0},
+{R, 1, "", 0x130090, 0x1, 0},
+{R, 1, "", 0x13805c, 0x40000000, 0},
+{W, 1, "", 0xa18c, 0x0, 0},
+{R, 1, "", 0x120000, 0x0, 0},
+{R, 1, "", BLT_RING_BASE+0x38, 0x44000, 0},
+{R, 1, "", 0x130090, 0x0, 0},
+{W, 1, "", 0xa18c, 0x1, 0},
+{R, 1, "", 0xa18c, 0x1, 0},
+{R, 1, "", 0x130090, 0x1, 0},
+{R, 1, "", 0x13805c, 0x40000000, 0},
+{W, 1, "", 0xa18c, 0x0, 0},
+{R, 1, "", 0x120000, 0x0, 0},
+{R, 1, "", BLT_RING_BASE+0x34, 0x0, 0},
+{R, 1, "", 0x130090, 0x0, 0},
+{W, 1, "", 0xa18c, 0x1, 0},
+{R, 1, "", 0xa18c, 0x0, 0},
+{R, 3, "", 0x130090, 0x0, 0},
+{R, 1, "", 0x130090, 0x1, 0},
+{R, 1, "", 0x13805c, 0x40000000, 0},
+{W, 1, "", 0xa18c, 0x0, 0},
+{R, 1, "", 0x120000, 0x0, 0},
+{R, 1, "", BLT_RING_BASE+0x34, 0x0, 0},
+{R, 1, "", 0x130090, 0x0, 0},
+{W, 1, "", 0xa18c, 0x1, 0},
+{R, 1, "", 0xa18c, 0x1, 0},
+{R, 1, "", 0x130090, 0x1, 0},
+{R, 1, "", 0x13805c, 0x40000000, 0},
+{W, 1, "", 0xa18c, 0x0, 0},
+{R, 1, "", 0x120000, 0x0, 0},
+{R, 1, "", BLT_RING_BASE+0x30, 0x0, 0},
+{R, 1, "", 0x130090, 0x0, 0},
+{W, 1, "", 0xa18c, 0x1, 0},
+{R, 1, "", 0xa18c, 0x0, 0},
+{R, 4, "", 0x130090, 0x0, 0},
+{R, 1, "", 0x130090, 0x1, 0},
+{R, 1, "", 0x13805c, 0x40000000, 0},
+{W, 1, "", 0xa18c, 0x0, 0},
+{R, 1, "", 0x120000, 0x0, 0},
+{R, 1, "", 0x4090, 0x140, 0},
+{W, 1, "", 0x4090, 0x558, 0},
+{W, 1, "", GFX_MODE, 0x2000200, 0},
+{W, 1, "", 0x2220, 0xffffffff, 0},
+{W, 1, "", 0x2228, 0x7fe00000, 0},
+{W, 1, "", 0x12220, 0xffffffff, 0},
+{W, 1, "", 0x12228, 0x7fe00000, 0},
+{W, 1, "", 0x22220, 0xffffffff, 0},
+{W, 1, "", 0x22228, 0x7fe00000, 0},
+{R, 1, "", ILK_DPFC_CONTROL, 0x0, 0},
+{W, 1, "", ILK_DPFC_CB_BASE, 0x0, 0},
+{W, 1, "", HWSTAM, 0xeffe, 0},
+{W, 1, "", DEIMR, 0xffffffff, 0},
+{W, 1, "", DEIER, 0x0, 0},
+{R, 1, "", DEIER, 0x0, 0},
+{W, 1, "", GTIMR, 0xffffffff, 0},
+{W, 1, "", GTIER, 0x0, 0},
+{R, 1, "", GTIER, 0x0, 0},
+{W, 1, "", SDEIMR, 0xffffffff, 0},
+{W, 1, "", SDEIER, 0x0, 0},
+{R, 1, "", SDEIER, 0x0, 0},
+{R, 1, "", DEIIR, 0x4000008, 0},
+{W, 1, "", DEIIR, 0x4000008, 0},
+{W, 1, "", DEIMR, 0x73dbffff, 0},
+{W, 1, "", DEIER, 0x8c248080, 0},
+{R, 1, "", DEIER, 0x8c248080, 0},
+{W, 1, "", DEIER, 0xc248080, 0},
+{R, 1, "", DEIER, 0xc248080, 0},
+{R, 1, "", DEIIR, 0x8, 0},
+{R, 1, "", GTIIR, 0x0, 0},
+{R, 1, "", SDEIIR, 0x0, 0},
+{R, 1, "", GEN6_PMIIR, 0x40, 0},
+{W, 1, "", GEN6_PMISR+0x4, 0x40, 0},
+{R, 1, "", GEN6_PMISR+0x4, 0x40, 0},
+{W, 1, "", SDEIIR, 0x0, 0},
+{W, 1, "", GTIIR, 0x0, 0},
+{R, 1, "", GEN6_PMISR+0x4, 0x40, 0},
+{W, 1, "", DEIIR, 0x8, 0},
+{W, 1, "", GEN6_PMIIR, 0x40, 0},
+{W, 1, "", GEN6_PMISR+0x4, 0x0, 0},
+{R, 1, "", 0x130090, 0x0, 0},
+{W, 1, "", 0xa18c, 0x1, 0},
+{W, 1, "", DEIER, 0x8c248080, 0},
+{R, 2, "", DEIER, 0x8c248080, 0},
+{R, 1, "", GTIIR, 0x0, 0},
+{W, 1, "", GTIIR, 0x0, 0},
+{R, 1, "", 0xa18c, 0x0, 0},
+{R, 2, "", 0x130090, 0x0, 0},
+{W, 1, "", GTIMR, 0xffffffff, 0},
+{W, 1, "", GTIER, 0x401001, 0},
+{R, 1, "", GTIER, 0x401001, 0},
+{R, 1, "", SDEIIR, 0x0, 0},
+{R, 1, "", 0x130090, 0x0, 0},
+{W, 1, "", SDEIIR, 0x0, 0},
+{W, 1, "", SDEIMR, 0xff17ffff, 0},
+{W, 1, "", SDEIER, 0xe80000, 0},
+{R, 1, "", 0x130090, 0x0, 0},
+{R, 1, "", SDEIER, 0xe80000, 0},
+{R, 1, "", 0x130090, 0x1, 0},
+{R, 1, "", 0x13805c, 0x40000000, 0},
+{R, 1, "", SDEISR+0x30, 0x10, 0},
+{W, 1, "", SDEISR+0x30, 0x101010, 0},
+{R, 1, "", _PALETTE_A+0x14, 0x12060000, 0},
+{W, 1, "", _PALETTE_A+0x14, 0x12000000, 0},
+{W, 1, "", 0xa18c, 0x0, 0},
+{R, 1, "", 0x120000, 0x0, 0},
+{R, 1, "", BLC_PWM_CPU_CTL, 0x0, 0},
+{W, 1, "", BLC_PWM_CPU_CTL, 0x0, 0},
+{W, 1, "", _PALETTE_A+0x8, 0xe000000, 0},
+{R, 1, "", PCH_PP_CONTROL, 0xabcd0002, 0},
+{W, 1, "", PCH_PP_CONTROL, 0xabcd0002, 0},
+{R, 1, "", PCH_PP_STATUS, 0x8000001, 0},
+{R, 1, "", PCH_LVDS, 0x300302, 0},
+{W, 1, "", PCH_LVDS, 0x300302, 0},
+{R, 1, "", PCH_LVDS, 0x300302, 0},
+{R, 1, "", PCH_ADPA, 0xf40000, 0},
+{W, 1, "", PCH_ADPA, 0xf40c00, 0},
+{R, 1, "", HDMIB, 0x1c, 0},
+{W, 1, "", HDMIB, 0x1c, 0},
+{R, 1, "", HDMIB, 0x1c, 0},
+{W, 1, "", HDMIB, 0x1c, 0},
+{R, 1, "", HDMIB, 0x1c, 0},
+{W, 1, "", HDMIB, 0x1c, 0},
+{R, 1, "", HDMIB, 0x1c, 0},
+{R, 2, "", PCH_DP_B, 0x4, 0},
+{R, 1, "", _DSPACNTR, 0x14004000, 0},
+{R, 1, "", _PIPEACONF, 0x50, 0},
+{R, 1, "", _DSPBCNTR, 0x4000, 0},
+{R, 1, "", _PIPEBCONF, 0x0, 0},
+{R, 1, "", PCH_ADPA, 0xf40000, 0},
+{W, 1, "", PCH_ADPA, 0xf50000, 0},
+{R, 69, "", PCH_ADPA, 0xf50000, 0},
+{R, 1, "", PCH_ADPA, 0xf40000, 0},
+{W, 1, "", PCH_ADPA, 0xf40000, 0},
+{R, 2, "", PCH_ADPA, 0xf40000, 0},
+{W, 1, "", PCH_GMBUS0, 0x0, 0},
+{R, 1, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 1, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GMBUS0, 0x0, 0},
+{R, 1, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 1, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GMBUS0, 0x0, 0},
+{R, 1, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 1, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GMBUS0, 0x0, 0},
+{R, 1, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 1, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GMBUS0, 0x0, 0},
+{R, 1, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x7, 0},
+{R, 2, "", PCH_GPIOE, 0x1002, 0},
+{W, 1, "", PCH_GPIOE, 0x700, 0},
+{R, 2, "", PCH_GPIOE, 0x202, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{W, 1, "", PCH_GPIOE, 0x0, 0},
+{R, 2, "", PCH_GPIOE, 0x210, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x100, 0},
+{R, 2, "", PCH_GPIOE, 0x1010, 0},
+{W, 1, "", PCH_GPIOE, 0x1, 0},
+{R, 1, "", PCH_GPIOE, 0x1010, 0},
+{R, 1, "", PCH_DPB_AUX_CH_CTL, 0x145003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_DATA1, 0x9000000e, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0xd245003f, 0},
+{R, 5, "", PCH_DPB_AUX_CH_CTL, 0x8145003f, 100},
+{R, 1, "", PCH_DPB_AUX_CH_CTL, 0x5145003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0x5345003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_DATA1, 0x9000000e, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0xd245003f, 0},
+{R, 5, "", PCH_DPB_AUX_CH_CTL, 0x8145003f, 100},
+{R, 1, "", PCH_DPB_AUX_CH_CTL, 0x5145003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0x5345003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_DATA1, 0x9000000e, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0xd245003f, 0},
+{R, 5, "", PCH_DPB_AUX_CH_CTL, 0x8145003f, 100},
+{R, 1, "", PCH_DPB_AUX_CH_CTL, 0x5145003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0x5345003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_DATA1, 0x9000000e, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0xd245003f, 0},
+{R, 5, "", PCH_DPB_AUX_CH_CTL, 0x8145003f, 100},
+{R, 1, "", PCH_DPB_AUX_CH_CTL, 0x5145003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0x5345003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_DATA1, 0x9000000e, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0xd245003f, 0},
+{R, 5, "", PCH_DPB_AUX_CH_CTL, 0x8145003f, 100},
+{R, 1, "", PCH_DPB_AUX_CH_CTL, 0x5145003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0x5345003f, 0},
+{R, 1, "", PCH_DPB_AUX_CH_CTL, 0x145003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_DATA1, 0x9000000e, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0xd245003f, 0},
+{R, 5, "", PCH_DPB_AUX_CH_CTL, 0x8145003f, 100},
+{R, 1, "", PCH_DPB_AUX_CH_CTL, 0x5145003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0x5345003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_DATA1, 0x9000000e, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0xd245003f, 0},
+{R, 5, "", PCH_DPB_AUX_CH_CTL, 0x8145003f, 100},
+{R, 1, "", PCH_DPB_AUX_CH_CTL, 0x5145003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0x5345003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_DATA1, 0x9000000e, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0xd245003f, 0},
+{R, 5, "", PCH_DPB_AUX_CH_CTL, 0x8145003f, 100},
+{R, 1, "", PCH_DPB_AUX_CH_CTL, 0x5145003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0x5345003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_DATA1, 0x9000000e, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0xd245003f, 0},
+{R, 5, "", PCH_DPB_AUX_CH_CTL, 0x8145003f, 100},
+{R, 1, "", PCH_DPB_AUX_CH_CTL, 0x5145003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0x5345003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_DATA1, 0x9000000e, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0xd245003f, 0},
+{R, 5, "", PCH_DPB_AUX_CH_CTL, 0x8145003f, 100},
+{R, 1, "", PCH_DPB_AUX_CH_CTL, 0x5145003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0x5345003f, 0},
+{R, 1, "", PCH_DPB_AUX_CH_CTL, 0x145003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_DATA1, 0x9000000e, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0xd245003f, 0},
+{R, 5, "", PCH_DPB_AUX_CH_CTL, 0x8145003f, 100},
+{R, 1, "", PCH_DPB_AUX_CH_CTL, 0x5145003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0x5345003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_DATA1, 0x9000000e, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0xd245003f, 0},
+{R, 5, "", PCH_DPB_AUX_CH_CTL, 0x8145003f, 100},
+{R, 1, "", PCH_DPB_AUX_CH_CTL, 0x5145003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0x5345003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_DATA1, 0x9000000e, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0xd245003f, 0},
+{R, 5, "", PCH_DPB_AUX_CH_CTL, 0x8145003f, 100},
+{R, 1, "", PCH_DPB_AUX_CH_CTL, 0x5145003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0x5345003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_DATA1, 0x9000000e, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0xd245003f, 0},
+{R, 5, "", PCH_DPB_AUX_CH_CTL, 0x8145003f, 100},
+{R, 1, "", PCH_DPB_AUX_CH_CTL, 0x5145003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0x5345003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_DATA1, 0x9000000e, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0xd245003f, 0},
+{R, 5, "", PCH_DPB_AUX_CH_CTL, 0x8145003f, 100},
+{R, 1, "", PCH_DPB_AUX_CH_CTL, 0x5145003f, 0},
+{W, 1, "", PCH_DPB_AUX_CH_CTL, 0x5345003f, 0},
+{M, 1, "fbcon inteldrmfb (fb0) is primary device", },
+{R, 1, "", PCH_ADPA, 0xf40000, 0},
+{W, 1, "", PCH_ADPA, 0xf40c00, 0},
+{R, 1, "", HDMIB, 0x1c, 0},
+{W, 1, "", HDMIB, 0x1c, 0},
+{R, 1, "", HDMIB, 0x1c, 0},
+{W, 1, "", HDMIB, 0x1c, 0},
+{R, 1, "", HDMIB, 0x1c, 0},
+{W, 1, "", HDMIB, 0x1c, 0},
+{R, 1, "", HDMIB, 0x1c, 0},
+{R, 2, "", PCH_DP_B, 0x4, 0},
+{R, 1, "", _PIPEACONF, 0x50, 0},
+{R, 2, "", PCH_LVDS, 0x300302, 0},
+{R, 1, "", _PIPEACONF, 0x50, 0},
+{R, 1, "", PCH_LVDS, 0x300302, 0},
+{W, 1, "", _PIPEACONF, 0x50, 0},
+{R, 1, "", PCH_LVDS, 0x300302, 0},
+{R, 1, "", _PIPEACONF, 0x50, 0},
+{W, 1, "", _PCH_FPA0, 0x10c08, 0},
+{W, 1, "", _PCH_DPLL_A, 0x8040004, 0},
+{R, 1, "", _PCH_DPLL_A, 0x8040004, 150},
+{R, 1, "", PCH_LVDS, 0x300302, 0},
+{W, 1, "", PCH_LVDS, 0x80300302, 0},
+{W, 1, "", _TRANSA_DATA_M1, 0x0, 0},
+{W, 1, "", _TRANSA_DATA_N1, 0x0, 0},
+{W, 1, "", _TRANSA_DP_LINK_M1, 0x0, 0},
+{W, 1, "", _TRANSA_DP_LINK_N1, 0x0, 0},
+{W, 1, "", _PCH_DPLL_A, 0x8040004, 0},
+{R, 1, "", _PCH_DPLL_A, 0x8040004, 150},
+{W, 1, "", _PCH_DPLL_A, 0x8040004, 0},
+{W, 1, "", _PCH_FPA1, 0x10c08, 0},
+{W, 1, "", _VSYNCSHIFT_A, 0x0, 0},
+{W, 1, "", _HTOTAL_A, 0x6450555, 0},
+{W, 1, "", _HBLANK_A, 0x6450555, 0},
+{W, 1, "", _HSYNC_A, 0x5a50585, 0},
+{W, 1, "", _VTOTAL_A, 0x31502ff, 0},
+{W, 1, "", _VBLANK_A, 0x31502ff, 0},
+{W, 1, "", _VSYNC_A, 0x3060301, 0},
+{W, 1, "", _PIPEASRC, 0x55502ff, 0},
+{W, 1, "", _PIPEA_DATA_M1, 0x7e14e614, 0},
+{W, 1, "", _PIPEA_DATA_N1, 0x20f580, 0},
+{W, 1, "", _PIPEA_LINK_M1, 0x1293a, 0},
+{W, 1, "", _PIPEA_LINK_N1, 0x41eb0, 0},
+{W, 1, "", _PIPEACONF, 0x50, 0},
+{R, 1, "", _PIPEACONF, 0x50, 0},
+{R, 1, "", _PIPEASTAT, 0x0, 0},
+{W, 1, "", _PIPEASTAT, 0x2, 0},
+{R, 440, "", _PIPEASTAT, 0x0, 0},
+{W, 1, "", _DSPACNTR, 0x40000000, 0},
+{R, 2, "", _DSPACNTR, 0x40000000, 0},
+{W, 1, "", _DSPACNTR, 0x58004000, 0},
+{W, 1, "", _DSPASTRIDE, 0x1580, 0},
+{W, 1, "", _DSPASIZE+0xc, 0x64000, 0},
+{W, 1, "", _DSPACNTR+0x24, 0x0, 0},
+{W, 1, "", _DSPAADDR, 0x0, 0},
+{R, 1, "", _DSPACNTR, 0x58004000, 0},
+{R, 1, "", ILK_DPFC_CONTROL, 0x0, 0},
+{R, 1, "", 0x145d10, 0x16040307, 0},
+{R, 1, "", WM0_PIPEA_ILK, 0x783818, 0},
+{W, 1, "", WM0_PIPEA_ILK, 0x63806, 0},
+{W, 1, "", WM3_LP_ILK, 0x0, 0},
+{W, 1, "", WM2_LP_ILK, 0x0, 0},
+{W, 1, "", WM1_LP_ILK, 0x0, 0},
+{R, 2, "", 0x145d10, 0x16040307, 0},
+{W, 1, "", WM1_LP_ILK, 0x83300a06, 0},
+{R, 2, "", 0x145d10, 0x16040307, 0},
+{W, 1, "", WM2_LP_ILK, 0x84300c06, 0},
+{R, 2, "", 0x145d10, 0x16040307, 0},
+{W, 1, "", WM3_LP_ILK, 0x96303706, 0},
+{R, 1, "", 0x145d10, 0x16040307, 0},
+{R, 1, "", WM0_PIPEA_ILK, 0x63806, 0},
+{W, 1, "", WM0_PIPEA_ILK, 0x63806, 0},
+{W, 1, "", WM3_LP_ILK, 0x0, 0},
+{W, 1, "", WM2_LP_ILK, 0x0, 0},
+{W, 1, "", WM1_LP_ILK, 0x0, 0},
+{R, 2, "", 0x145d10, 0x16040307, 0},
+{W, 1, "", WM1_LP_ILK, 0x83300a06, 0},
+{R, 2, "", 0x145d10, 0x16040307, 0},
+{W, 1, "", WM2_LP_ILK, 0x84300c06, 0},
+{R, 2, "", 0x145d10, 0x16040307, 0},
+{W, 1, "", WM3_LP_ILK, 0x96303706, 0},
+{R, 1, "", PCH_LVDS, 0x80300302, 0},
+{R, 1, "", _PIPEA_DATA_M1, 0x7e14e614, 0},
+{W, 1, "", _FDI_RXA_TUSIZE1, 0x7e000000, 0},
+{R, 1, "", _FDI_RXA_CTL, 0x20040, 0},
+{R, 1, "", _PIPEACONF, 0x50, 0},
+{W, 1, "", _FDI_RXA_CTL, 0x22040, 0},
+{R, 1, "", _FDI_RXA_CTL, 0x22040, 200},
+{R, 1, "", _FDI_RXA_CTL, 0x22040, 0},
+{W, 1, "", _FDI_RXA_CTL, 0x22050, 0},
+{R, 1, "", _FDI_RXA_CTL, 0x22050, 200},
+{R, 1, "", _FDI_TXA_CTL, 0x40000, 0},
+{W, 1, "", _FDI_TXA_CTL, 0x44000, 0},
+{R, 1, "", _FDI_TXA_CTL, 0x44000, 100},
+{W, 1, "", _LGC_PALETTE_A, 0x0, 0},
+{W, 1, "", _LGC_PALETTE_A+0x4, 0x10101, 0},
+{W, 1, "", _LGC_PALETTE_A+0x8, 0x20202, 0},
+{W, 1, "", _LGC_PALETTE_A+0xc, 0x30303, 0},
+{W, 1, "", _LGC_PALETTE_A+0x10, 0x40404, 0},
+{W, 1, "", _LGC_PALETTE_A+0x14, 0x50505, 0},
+{W, 1, "", _LGC_PALETTE_A+0x18, 0x60606, 0},
+{W, 1, "", _LGC_PALETTE_A+0x1c, 0x70707, 0},
+{W, 1, "", _LGC_PALETTE_A+0x20, 0x80808, 0},
+{W, 1, "", _LGC_PALETTE_A+0x24, 0x90909, 0},
+{W, 1, "", _LGC_PALETTE_A+0x28, 0xa0a0a, 0},
+{W, 1, "", _LGC_PALETTE_A+0x2c, 0xb0b0b, 0},
+{W, 1, "", _LGC_PALETTE_A+0x30, 0xc0c0c, 0},
+{W, 1, "", _LGC_PALETTE_A+0x34, 0xd0d0d, 0},
+{W, 1, "", _LGC_PALETTE_A+0x38, 0xe0e0e, 0},
+{W, 1, "", _LGC_PALETTE_A+0x3c, 0xf0f0f, 0},
+{W, 1, "", _LGC_PALETTE_A+0x40, 0x101010, 0},
+{W, 1, "", _LGC_PALETTE_A+0x44, 0x111111, 0},
+{W, 1, "", _LGC_PALETTE_A+0x48, 0x121212, 0},
+{W, 1, "", _LGC_PALETTE_A+0x4c, 0x131313, 0},
+{W, 1, "", _LGC_PALETTE_A+0x50, 0x141414, 0},
+{W, 1, "", _LGC_PALETTE_A+0x54, 0x151515, 0},
+{W, 1, "", _LGC_PALETTE_A+0x58, 0x161616, 0},
+{W, 1, "", _LGC_PALETTE_A+0x5c, 0x171717, 0},
+{W, 1, "", _LGC_PALETTE_A+0x60, 0x181818, 0},
+{W, 1, "", _LGC_PALETTE_A+0x64, 0x191919, 0},
+{W, 1, "", _LGC_PALETTE_A+0x68, 0x1a1a1a, 0},
+{W, 1, "", _LGC_PALETTE_A+0x6c, 0x1b1b1b, 0},
+{W, 1, "", _LGC_PALETTE_A+0x70, 0x1c1c1c, 0},
+{W, 1, "", _LGC_PALETTE_A+0x74, 0x1d1d1d, 0},
+{W, 1, "", _LGC_PALETTE_A+0x78, 0x1e1e1e, 0},
+{W, 1, "", _LGC_PALETTE_A+0x7c, 0x1f1f1f, 0},
+{W, 1, "", 0x4a080, 0x202020, 0},
+{W, 1, "", 0x4a084, 0x212121, 0},
+{W, 1, "", 0x4a088, 0x222222, 0},
+{W, 1, "", 0x4a08c, 0x232323, 0},
+{W, 1, "", 0x4a090, 0x242424, 0},
+{W, 1, "", 0x4a094, 0x252525, 0},
+{W, 1, "", 0x4a098, 0x262626, 0},
+{W, 1, "", 0x4a09c, 0x272727, 0},
+{W, 1, "", 0x4a0a0, 0x282828, 0},
+{W, 1, "", 0x4a0a4, 0x292929, 0},
+{W, 1, "", 0x4a0a8, 0x2a2a2a, 0},
+{W, 1, "", 0x4a0ac, 0x2b2b2b, 0},
+{W, 1, "", 0x4a0b0, 0x2c2c2c, 0},
+{W, 1, "", 0x4a0b4, 0x2d2d2d, 0},
+{W, 1, "", 0x4a0b8, 0x2e2e2e, 0},
+{W, 1, "", 0x4a0bc, 0x2f2f2f, 0},
+{W, 1, "", 0x4a0c0, 0x303030, 0},
+{W, 1, "", 0x4a0c4, 0x313131, 0},
+{W, 1, "", 0x4a0c8, 0x323232, 0},
+{W, 1, "", 0x4a0cc, 0x333333, 0},
+{W, 1, "", 0x4a0d0, 0x343434, 0},
+{W, 1, "", 0x4a0d4, 0x353535, 0},
+{W, 1, "", 0x4a0d8, 0x363636, 0},
+{W, 1, "", 0x4a0dc, 0x373737, 0},
+{W, 1, "", 0x4a0e0, 0x383838, 0},
+{W, 1, "", 0x4a0e4, 0x393939, 0},
+{W, 1, "", 0x4a0e8, 0x3a3a3a, 0},
+{W, 1, "", 0x4a0ec, 0x3b3b3b, 0},
+{W, 1, "", 0x4a0f0, 0x3c3c3c, 0},
+{W, 1, "", 0x4a0f4, 0x3d3d3d, 0},
+{W, 1, "", 0x4a0f8, 0x3e3e3e, 0},
+{W, 1, "", 0x4a0fc, 0x3f3f3f, 0},
+{W, 1, "", 0x4a100, 0x404040, 0},
+{W, 1, "", 0x4a104, 0x414141, 0},
+{W, 1, "", 0x4a108, 0x424242, 0},
+{W, 1, "", 0x4a10c, 0x434343, 0},
+{W, 1, "", 0x4a110, 0x444444, 0},
+{W, 1, "", 0x4a114, 0x454545, 0},
+{W, 1, "", 0x4a118, 0x464646, 0},
+{W, 1, "", 0x4a11c, 0x474747, 0},
+{W, 1, "", 0x4a120, 0x484848, 0},
+{W, 1, "", 0x4a124, 0x494949, 0},
+{W, 1, "", 0x4a128, 0x4a4a4a, 0},
+{W, 1, "", 0x4a12c, 0x4b4b4b, 0},
+{W, 1, "", 0x4a130, 0x4c4c4c, 0},
+{W, 1, "", 0x4a134, 0x4d4d4d, 0},
+{W, 1, "", 0x4a138, 0x4e4e4e, 0},
+{W, 1, "", 0x4a13c, 0x4f4f4f, 0},
+{W, 1, "", 0x4a140, 0x505050, 0},
+{W, 1, "", 0x4a144, 0x515151, 0},
+{W, 1, "", 0x4a148, 0x525252, 0},
+{W, 1, "", 0x4a14c, 0x535353, 0},
+{W, 1, "", 0x4a150, 0x545454, 0},
+{W, 1, "", 0x4a154, 0x555555, 0},
+{W, 1, "", 0x4a158, 0x565656, 0},
+{W, 1, "", 0x4a15c, 0x575757, 0},
+{W, 1, "", 0x4a160, 0x585858, 0},
+{W, 1, "", 0x4a164, 0x595959, 0},
+{W, 1, "", 0x4a168, 0x5a5a5a, 0},
+{W, 1, "", 0x4a16c, 0x5b5b5b, 0},
+{W, 1, "", 0x4a170, 0x5c5c5c, 0},
+{W, 1, "", 0x4a174, 0x5d5d5d, 0},
+{W, 1, "", 0x4a178, 0x5e5e5e, 0},
+{W, 1, "", 0x4a17c, 0x5f5f5f, 0},
+{W, 1, "", 0x4a180, 0x606060, 0},
+{W, 1, "", 0x4a184, 0x616161, 0},
+{W, 1, "", 0x4a188, 0x626262, 0},
+{W, 1, "", 0x4a18c, 0x636363, 0},
+{W, 1, "", 0x4a190, 0x646464, 0},
+{W, 1, "", 0x4a194, 0x656565, 0},
+{W, 1, "", 0x4a198, 0x666666, 0},
+{W, 1, "", 0x4a19c, 0x676767, 0},
+{W, 1, "", 0x4a1a0, 0x686868, 0},
+{W, 1, "", 0x4a1a4, 0x696969, 0},
+{W, 1, "", 0x4a1a8, 0x6a6a6a, 0},
+{W, 1, "", 0x4a1ac, 0x6b6b6b, 0},
+{W, 1, "", 0x4a1b0, 0x6c6c6c, 0},
+{W, 1, "", 0x4a1b4, 0x6d6d6d, 0},
+{W, 1, "", 0x4a1b8, 0x6e6e6e, 0},
+{W, 1, "", 0x4a1bc, 0x6f6f6f, 0},
+{W, 1, "", 0x4a1c0, 0x707070, 0},
+{W, 1, "", 0x4a1c4, 0x717171, 0},
+{W, 1, "", 0x4a1c8, 0x727272, 0},
+{W, 1, "", 0x4a1cc, 0x737373, 0},
+{W, 1, "", 0x4a1d0, 0x747474, 0},
+{W, 1, "", 0x4a1d4, 0x757575, 0},
+{W, 1, "", 0x4a1d8, 0x767676, 0},
+{W, 1, "", 0x4a1dc, 0x777777, 0},
+{W, 1, "", 0x4a1e0, 0x787878, 0},
+{W, 1, "", 0x4a1e4, 0x797979, 0},
+{W, 1, "", 0x4a1e8, 0x7a7a7a, 0},
+{W, 1, "", 0x4a1ec, 0x7b7b7b, 0},
+{W, 1, "", 0x4a1f0, 0x7c7c7c, 0},
+{W, 1, "", 0x4a1f4, 0x7d7d7d, 0},
+{W, 1, "", 0x4a1f8, 0x7e7e7e, 0},
+{W, 1, "", 0x4a1fc, 0x7f7f7f, 0},
+{W, 1, "", 0x4a200, 0x808080, 0},
+{W, 1, "", 0x4a204, 0x818181, 0},
+{W, 1, "", 0x4a208, 0x828282, 0},
+{W, 1, "", 0x4a20c, 0x838383, 0},
+{W, 1, "", 0x4a210, 0x848484, 0},
+{W, 1, "", 0x4a214, 0x858585, 0},
+{W, 1, "", 0x4a218, 0x868686, 0},
+{W, 1, "", 0x4a21c, 0x878787, 0},
+{W, 1, "", 0x4a220, 0x888888, 0},
+{W, 1, "", 0x4a224, 0x898989, 0},
+{W, 1, "", 0x4a228, 0x8a8a8a, 0},
+{W, 1, "", 0x4a22c, 0x8b8b8b, 0},
+{W, 1, "", 0x4a230, 0x8c8c8c, 0},
+{W, 1, "", 0x4a234, 0x8d8d8d, 0},
+{W, 1, "", 0x4a238, 0x8e8e8e, 0},
+{W, 1, "", 0x4a23c, 0x8f8f8f, 0},
+{W, 1, "", 0x4a240, 0x909090, 0},
+{W, 1, "", 0x4a244, 0x919191, 0},
+{W, 1, "", 0x4a248, 0x929292, 0},
+{W, 1, "", 0x4a24c, 0x939393, 0},
+{W, 1, "", 0x4a250, 0x949494, 0},
+{W, 1, "", 0x4a254, 0x959595, 0},
+{W, 1, "", 0x4a258, 0x969696, 0},
+{W, 1, "", 0x4a25c, 0x979797, 0},
+{W, 1, "", 0x4a260, 0x989898, 0},
+{W, 1, "", 0x4a264, 0x999999, 0},
+{W, 1, "", 0x4a268, 0x9a9a9a, 0},
+{W, 1, "", 0x4a26c, 0x9b9b9b, 0},
+{W, 1, "", 0x4a270, 0x9c9c9c, 0},
+{W, 1, "", 0x4a274, 0x9d9d9d, 0},
+{W, 1, "", 0x4a278, 0x9e9e9e, 0},
+{W, 1, "", 0x4a27c, 0x9f9f9f, 0},
+{W, 1, "", 0x4a280, 0xa0a0a0, 0},
+{W, 1, "", 0x4a284, 0xa1a1a1, 0},
+{W, 1, "", 0x4a288, 0xa2a2a2, 0},
+{W, 1, "", 0x4a28c, 0xa3a3a3, 0},
+{W, 1, "", 0x4a290, 0xa4a4a4, 0},
+{W, 1, "", 0x4a294, 0xa5a5a5, 0},
+{W, 1, "", 0x4a298, 0xa6a6a6, 0},
+{W, 1, "", 0x4a29c, 0xa7a7a7, 0},
+{W, 1, "", 0x4a2a0, 0xa8a8a8, 0},
+{W, 1, "", 0x4a2a4, 0xa9a9a9, 0},
+{W, 1, "", 0x4a2a8, 0xaaaaaa, 0},
+{W, 1, "", 0x4a2ac, 0xababab, 0},
+{W, 1, "", 0x4a2b0, 0xacacac, 0},
+{W, 1, "", 0x4a2b4, 0xadadad, 0},
+{W, 1, "", 0x4a2b8, 0xaeaeae, 0},
+{W, 1, "", 0x4a2bc, 0xafafaf, 0},
+{W, 1, "", 0x4a2c0, 0xb0b0b0, 0},
+{W, 1, "", 0x4a2c4, 0xb1b1b1, 0},
+{W, 1, "", 0x4a2c8, 0xb2b2b2, 0},
+{W, 1, "", 0x4a2cc, 0xb3b3b3, 0},
+{W, 1, "", 0x4a2d0, 0xb4b4b4, 0},
+{W, 1, "", 0x4a2d4, 0xb5b5b5, 0},
+{W, 1, "", 0x4a2d8, 0xb6b6b6, 0},
+{W, 1, "", 0x4a2dc, 0xb7b7b7, 0},
+{W, 1, "", 0x4a2e0, 0xb8b8b8, 0},
+{W, 1, "", 0x4a2e4, 0xb9b9b9, 0},
+{W, 1, "", 0x4a2e8, 0xbababa, 0},
+{W, 1, "", 0x4a2ec, 0xbbbbbb, 0},
+{W, 1, "", 0x4a2f0, 0xbcbcbc, 0},
+{W, 1, "", 0x4a2f4, 0xbdbdbd, 0},
+{W, 1, "", 0x4a2f8, 0xbebebe, 0},
+{W, 1, "", 0x4a2fc, 0xbfbfbf, 0},
+{W, 1, "", 0x4a300, 0xc0c0c0, 0},
+{W, 1, "", 0x4a304, 0xc1c1c1, 0},
+{W, 1, "", 0x4a308, 0xc2c2c2, 0},
+{W, 1, "", 0x4a30c, 0xc3c3c3, 0},
+{W, 1, "", 0x4a310, 0xc4c4c4, 0},
+{W, 1, "", 0x4a314, 0xc5c5c5, 0},
+{W, 1, "", 0x4a318, 0xc6c6c6, 0},
+{W, 1, "", 0x4a31c, 0xc7c7c7, 0},
+{W, 1, "", 0x4a320, 0xc8c8c8, 0},
+{W, 1, "", 0x4a324, 0xc9c9c9, 0},
+{W, 1, "", 0x4a328, 0xcacaca, 0},
+{W, 1, "", 0x4a32c, 0xcbcbcb, 0},
+{W, 1, "", 0x4a330, 0xcccccc, 0},
+{W, 1, "", 0x4a334, 0xcdcdcd, 0},
+{W, 1, "", 0x4a338, 0xcecece, 0},
+{W, 1, "", 0x4a33c, 0xcfcfcf, 0},
+{W, 1, "", 0x4a340, 0xd0d0d0, 0},
+{W, 1, "", 0x4a344, 0xd1d1d1, 0},
+{W, 1, "", 0x4a348, 0xd2d2d2, 0},
+{W, 1, "", 0x4a34c, 0xd3d3d3, 0},
+{W, 1, "", 0x4a350, 0xd4d4d4, 0},
+{W, 1, "", 0x4a354, 0xd5d5d5, 0},
+{W, 1, "", 0x4a358, 0xd6d6d6, 0},
+{W, 1, "", 0x4a35c, 0xd7d7d7, 0},
+{W, 1, "", 0x4a360, 0xd8d8d8, 0},
+{W, 1, "", 0x4a364, 0xd9d9d9, 0},
+{W, 1, "", 0x4a368, 0xdadada, 0},
+{W, 1, "", 0x4a36c, 0xdbdbdb, 0},
+{W, 1, "", 0x4a370, 0xdcdcdc, 0},
+{W, 1, "", 0x4a374, 0xdddddd, 0},
+{W, 1, "", 0x4a378, 0xdedede, 0},
+{W, 1, "", 0x4a37c, 0xdfdfdf, 0},
+{W, 1, "", 0x4a380, 0xe0e0e0, 0},
+{W, 1, "", 0x4a384, 0xe1e1e1, 0},
+{W, 1, "", 0x4a388, 0xe2e2e2, 0},
+{W, 1, "", 0x4a38c, 0xe3e3e3, 0},
+{W, 1, "", 0x4a390, 0xe4e4e4, 0},
+{W, 1, "", 0x4a394, 0xe5e5e5, 0},
+{W, 1, "", 0x4a398, 0xe6e6e6, 0},
+{W, 1, "", 0x4a39c, 0xe7e7e7, 0},
+{W, 1, "", 0x4a3a0, 0xe8e8e8, 0},
+{W, 1, "", 0x4a3a4, 0xe9e9e9, 0},
+{W, 1, "", 0x4a3a8, 0xeaeaea, 0},
+{W, 1, "", 0x4a3ac, 0xebebeb, 0},
+{W, 1, "", 0x4a3b0, 0xececec, 0},
+{W, 1, "", 0x4a3b4, 0xededed, 0},
+{W, 1, "", 0x4a3b8, 0xeeeeee, 0},
+{W, 1, "", 0x4a3bc, 0xefefef, 0},
+{W, 1, "", 0x4a3c0, 0xf0f0f0, 0},
+{W, 1, "", 0x4a3c4, 0xf1f1f1, 0},
+{W, 1, "", 0x4a3c8, 0xf2f2f2, 0},
+{W, 1, "", 0x4a3cc, 0xf3f3f3, 0},
+{W, 1, "", 0x4a3d0, 0xf4f4f4, 0},
+{W, 1, "", 0x4a3d4, 0xf5f5f5, 0},
+{W, 1, "", 0x4a3d8, 0xf6f6f6, 0},
+{W, 1, "", 0x4a3dc, 0xf7f7f7, 0},
+{W, 1, "", 0x4a3e0, 0xf8f8f8, 0},
+{W, 1, "", 0x4a3e4, 0xf9f9f9, 0},
+{W, 1, "", 0x4a3e8, 0xfafafa, 0},
+{W, 1, "", 0x4a3ec, 0xfbfbfb, 0},
+{W, 1, "", 0x4a3f0, 0xfcfcfc, 0},
+{W, 1, "", 0x4a3f4, 0xfdfdfd, 0},
+{W, 1, "", 0x4a3f8, 0xfefefe, 0},
+{W, 1, "", 0x4a3fc, 0xffffff, 0},
+{R, 1, "", _FDI_RXA_CTL, 0x22050, 0},
+{R, 1, "", _FDI_TXA_CTL, 0x44000, 0},
+{R, 1, "", _PIPEACONF, 0x50, 0},
+{W, 1, "", _PIPEACONF, 0x80000050, 0},
+{R, 1, "", _PIPEASTAT, 0x0, 0},
+{W, 1, "", _PIPEASTAT, 0x2, 0},
+{R, 441, "", _PIPEASTAT, 0x0, 0},
+{R, 1, "", _PIPEACONF, 0x80000050, 0},
+{R, 1, "", _DSPACNTR, 0x58004000, 0},
+{W, 1, "", _DSPACNTR, 0xd8004000, 0},
+{R, 1, "", _DSPAADDR, 0x0, 0},
+{W, 1, "", _DSPAADDR, 0x0, 0},
+{R, 1, "", _DSPASIZE+0xc, 0x64000, 0},
+{W, 1, "", _DSPASIZE+0xc, 0x64000, 0},
+{R, 1, "", _PIPEASTAT, 0x0, 0},
+{W, 1, "", _PIPEASTAT, 0x2, 0},
+{R, 441, "", _PIPEASTAT, 0x0, 0},
+{R, 1, "", _FDI_RXA_IMR, 0x8ff, 0},
+{W, 1, "", _FDI_RXA_IMR, 0x8ff, 0},
+{R, 1, "", _FDI_RXA_IMR, 0x8ff, 150},
+{R, 1, "", _FDI_TXA_CTL, 0x44000, 0},
+{W, 1, "", _FDI_TXA_CTL, 0x80044000, 0},
+{R, 1, "", _FDI_RXA_CTL, 0x22050, 0},
+{W, 1, "", _FDI_RXA_CTL, 0x80022050, 0},
+{R, 1, "", _FDI_RXA_CTL, 0x80022050, 150},
+{R, 1, "", SOUTH_CHICKEN1, 0x0, 0},
+{W, 1, "", SOUTH_CHICKEN1, 0x80000, 0},
+{W, 1, "", SOUTH_CHICKEN1, 0xc0000, 0},
+{R, 1, "", SOUTH_CHICKEN1, 0xc0000, 0},
+{R, 1, "", _FDI_TXA_CTL, 0x80044000, 0},
+{W, 1, "", _FDI_TXA_CTL, 0x80044000, 0},
+{R, 1, "", _FDI_TXA_CTL, 0x80044000, 500},
+{R, 1, "", _FDI_RXA_IIR, 0x700, 0},
+{W, 1, "", _FDI_RXA_IIR, 0x700, 0},
+{R, 1, "", _FDI_TXA_CTL, 0x80044000, 0},
+{W, 1, "", _FDI_TXA_CTL, 0x90044000, 0},
+{R, 1, "", _FDI_RXA_CTL, 0x80022050, 0},
+{W, 1, "", _FDI_RXA_CTL, 0x80022150, 0},
+{R, 1, "", _FDI_RXA_CTL, 0x80022150, 150},
+{R, 1, "", _FDI_TXA_CTL, 0x90044000, 0},
+{W, 1, "", _FDI_TXA_CTL, 0x90044000, 0},
+{R, 1, "", _FDI_TXA_CTL, 0x90044000, 500},
+{R, 1, "", _FDI_RXA_IIR, 0x600, 0},
+{W, 1, "", _FDI_RXA_IIR, 0x600, 0},
+{R, 1, "", PCH_DREF_CONTROL, 0x1400, 0},
+{R, 1, "", _PCH_DPLL_A, 0x8040004, 0},
+{W, 1, "", _PCH_DPLL_A, 0x88040004, 0},
+{R, 1, "", _PCH_DPLL_A, 0x88040004, 200},
+{R, 1, "", PCH_DPLL_SEL, 0x0, 0},
+{W, 1, "", PCH_DPLL_SEL, 0x8, 0},
+{R, 1, "", PCH_PP_CONTROL, 0xabcd0002, 0},
+{R, 1, "", PCH_LVDS, 0x80300302, 0},
+{R, 1, "", _HTOTAL_A, 0x6450555, 0},
+{W, 1, "", _TRANS_HTOTAL_A, 0x6450555, 0},
+{R, 1, "", _HBLANK_A, 0x6450555, 0},
+{W, 1, "", _TRANS_HBLANK_A, 0x6450555, 0},
+{R, 1, "", _HSYNC_A, 0x5a50585, 0},
+{W, 1, "", _TRANS_HSYNC_A, 0x5a50585, 0},
+{R, 1, "", _VTOTAL_A, 0x31502ff, 0},
+{W, 1, "", _TRANS_VTOTAL_A, 0x31502ff, 0},
+{R, 1, "", _VBLANK_A, 0x31502ff, 0},
+{W, 1, "", _TRANS_VBLANK_A, 0x31502ff, 0},
+{R, 1, "", _VSYNC_A, 0x3060301, 0},
+{W, 1, "", _TRANS_VSYNC_A, 0x3060301, 0},
+{R, 1, "", _VSYNCSHIFT_A, 0x0, 0},
+{W, 1, "", _TRANS_VSYNCSHIFT_A, 0x0, 0},
+{R, 1, "", _FDI_TXA_CTL, 0x90044000, 0},
+{W, 1, "", _FDI_TXA_CTL, 0xb0044000, 0},
+{R, 1, "", _FDI_RXA_CTL, 0x80022150, 0},
+{W, 1, "", _FDI_RXA_CTL, 0x80022350, 0},
+{R, 1, "", _FDI_RXA_CTL, 0x80022350, 0},
+{M, 1, "1000", },
+{R, 1, "", PCH_DPLL_SEL, 0x8, 0},
+{R, 1, "", _PCH_DPLL_A, 0x88040004, 0},
+{R, 1, "", _FDI_TXA_CTL, 0xb0044000, 0},
+{R, 1, "", _FDI_RXA_CTL, 0x80022350, 0},
+{R, 1, "", _TRANSACONF, 0x0, 0},
+{R, 1, "", _PIPEACONF, 0xc0000050, 0},
+{W, 1, "", _TRANSACONF, 0x80000000, 0},
+{R, 1, "", _TRANSACONF, 0xc0000000, 0},
+{R, 1, "", ILK_DPFC_CONTROL, 0x0, 0},
+{R, 1, "", PCH_LVDS, 0x80300302, 0},
+{W, 1, "", PCH_LVDS, 0x80300302, 0},
+{R, 1, "", PCH_PP_CONTROL, 0xabcd0002, 0},
+{W, 1, "", PCH_PP_CONTROL, 0xabcd0003, 0},
+{R, 1, "", PCH_LVDS, 0x80300302, 0},
+{R, 142, "", PCH_PP_STATUS, 0x4800000b, 0},
+{R, 1, "", DEIER, 0x8c248080, 0},
+{W, 1, "", DEIER, 0xc248080, 0},
+{R, 1, "", DEIER, 0xc248080, 0},
+{R, 1, "", DEIIR, 0x4000000, 0},
+{R, 1, "", GTIIR, 0x0, 0},
+{R, 1, "", SDEIIR, 0x0, 0},
+{R, 1, "", GEN6_PMIIR, 0x0, 0},
+{W, 1, "", SDEIIR, 0x0, 0},
+{W, 1, "", GTIIR, 0x0, 0},
+{W, 1, "", DEIIR, 0x4000000, 0},
+{W, 1, "", GEN6_PMIIR, 0x0, 0},
+{W, 1, "", DEIER, 0x8c248080, 0},
+{R, 1, "", DEIER, 0x8c248080, 0},
+{R, 1322, "", PCH_PP_STATUS, 0x4800000b, 0},
+{R, 1, "", PCH_PP_STATUS, 0x4000000a, 0},
+{R, 1, "", PCH_PP_STATUS, 0xd000000a, 0},
+{R, 1, "", BLC_PWM_CPU_CTL, 0x0, 0},
+{W, 1, "", BLC_PWM_CPU_CTL, 0x1312, 0},
+{R, 1, "", PCH_ADPA, 0xf40000, 0},
+{W, 1, "", PCH_ADPA, 0xf40c00, 0},
+{R, 1, "", HDMIB, 0x1c, 0},
+{W, 1, "", HDMIB, 0x1c, 0},
+{R, 1, "", HDMIB, 0x1c, 0},
+{W, 1, "", HDMIB, 0x1c, 0},
+{R, 1, "", HDMIB, 0x1c, 0},
+{W, 1, "", HDMIB, 0x1c, 0},
+{R, 1, "", HDMIB, 0x1c, 0},
+{R, 2, "", PCH_DP_B, 0x4, 0},
+{R, 1, "", _DSPBCNTR, 0x4000, 0},
+{R, 1, "", _PIPEBCONF, 0x0, 0},
+{R, 1, "", PCH_ADPA, 0xf40000, 0},
+{W, 1, "", PCH_ADPA, 0xf40c00, 0},
+{R, 1, "", HDMIB, 0x1c, 0},
+{W, 1, "", HDMIB, 0x1c, 0},
+{R, 1, "", HDMIB, 0x1c, 0},
+{W, 1, "", HDMIB, 0x1c, 0},
+{R, 1, "", HDMIB, 0x1c, 0},
+{W, 1, "", HDMIB, 0x1c, 0},
+{R, 1, "", HDMIB, 0x1c, 0},
+{R, 2, "", PCH_DP_B, 0x4, 0},
+{R, 1, "", _DSPBCNTR, 0x4000, 0},
+{R, 1, "", _PIPEBCONF, 0x0, 0},
+{W, 1, "", _LGC_PALETTE_A, 0x0, 0},
+{W, 1, "", _LGC_PALETTE_A+0x4, 0x10101, 0},
+{W, 1, "", _LGC_PALETTE_A+0x8, 0x20202, 0},
+{W, 1, "", _LGC_PALETTE_A+0xc, 0x30303, 0},
+{W, 1, "", _LGC_PALETTE_A+0x10, 0x40404, 0},
+{W, 1, "", _LGC_PALETTE_A+0x14, 0x50505, 0},
+{W, 1, "", _LGC_PALETTE_A+0x18, 0x60606, 0},
+{W, 1, "", _LGC_PALETTE_A+0x1c, 0x70707, 0},
+{W, 1, "", _LGC_PALETTE_A+0x20, 0x80808, 0},
+{W, 1, "", _LGC_PALETTE_A+0x24, 0x90909, 0},
+{W, 1, "", _LGC_PALETTE_A+0x28, 0xa0a0a, 0},
+{W, 1, "", _LGC_PALETTE_A+0x2c, 0xb0b0b, 0},
+{W, 1, "", _LGC_PALETTE_A+0x30, 0xc0c0c, 0},
+{W, 1, "", _LGC_PALETTE_A+0x34, 0xd0d0d, 0},
+{W, 1, "", _LGC_PALETTE_A+0x38, 0xe0e0e, 0},
+{W, 1, "", _LGC_PALETTE_A+0x3c, 0xf0f0f, 0},
+{W, 1, "", _LGC_PALETTE_A+0x40, 0x101010, 0},
+{W, 1, "", _LGC_PALETTE_A+0x44, 0x111111, 0},
+{W, 1, "", _LGC_PALETTE_A+0x48, 0x121212, 0},
+{W, 1, "", _LGC_PALETTE_A+0x4c, 0x131313, 0},
+{W, 1, "", _LGC_PALETTE_A+0x50, 0x141414, 0},
+{W, 1, "", _LGC_PALETTE_A+0x54, 0x151515, 0},
+{W, 1, "", _LGC_PALETTE_A+0x58, 0x161616, 0},
+{W, 1, "", _LGC_PALETTE_A+0x5c, 0x171717, 0},
+{W, 1, "", _LGC_PALETTE_A+0x60, 0x181818, 0},
+{W, 1, "", _LGC_PALETTE_A+0x64, 0x191919, 0},
+{W, 1, "", _LGC_PALETTE_A+0x68, 0x1a1a1a, 0},
+{W, 1, "", _LGC_PALETTE_A+0x6c, 0x1b1b1b, 0},
+{W, 1, "", _LGC_PALETTE_A+0x70, 0x1c1c1c, 0},
+{W, 1, "", _LGC_PALETTE_A+0x74, 0x1d1d1d, 0},
+{W, 1, "", _LGC_PALETTE_A+0x78, 0x1e1e1e, 0},
+{W, 1, "", _LGC_PALETTE_A+0x7c, 0x1f1f1f, 0},
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+{W, 1, "", 0x4a358, 0xd6d6d6, 0},
+{W, 1, "", 0x4a35c, 0xd7d7d7, 0},
+{W, 1, "", 0x4a360, 0xd8d8d8, 0},
+{W, 1, "", 0x4a364, 0xd9d9d9, 0},
+{W, 1, "", 0x4a368, 0xdadada, 0},
+{W, 1, "", 0x4a36c, 0xdbdbdb, 0},
+{W, 1, "", 0x4a370, 0xdcdcdc, 0},
+{W, 1, "", 0x4a374, 0xdddddd, 0},
+{W, 1, "", 0x4a378, 0xdedede, 0},
+{W, 1, "", 0x4a37c, 0xdfdfdf, 0},
+{W, 1, "", 0x4a380, 0xe0e0e0, 0},
+{W, 1, "", 0x4a384, 0xe1e1e1, 0},
+{W, 1, "", 0x4a388, 0xe2e2e2, 0},
+{W, 1, "", 0x4a38c, 0xe3e3e3, 0},
+{W, 1, "", 0x4a390, 0xe4e4e4, 0},
+{W, 1, "", 0x4a394, 0xe5e5e5, 0},
+{W, 1, "", 0x4a398, 0xe6e6e6, 0},
+{W, 1, "", 0x4a39c, 0xe7e7e7, 0},
+{W, 1, "", 0x4a3a0, 0xe8e8e8, 0},
+{W, 1, "", 0x4a3a4, 0xe9e9e9, 0},
+{W, 1, "", 0x4a3a8, 0xeaeaea, 0},
+{W, 1, "", 0x4a3ac, 0xebebeb, 0},
+{W, 1, "", 0x4a3b0, 0xececec, 0},
+{W, 1, "", 0x4a3b4, 0xededed, 0},
+{W, 1, "", 0x4a3b8, 0xeeeeee, 0},
+{W, 1, "", 0x4a3bc, 0xefefef, 0},
+{W, 1, "", 0x4a3c0, 0xf0f0f0, 0},
+{W, 1, "", 0x4a3c4, 0xf1f1f1, 0},
+{W, 1, "", 0x4a3c8, 0xf2f2f2, 0},
+{W, 1, "", 0x4a3cc, 0xf3f3f3, 0},
+{W, 1, "", 0x4a3d0, 0xf4f4f4, 0},
+{W, 1, "", 0x4a3d4, 0xf5f5f5, 0},
+{W, 1, "", 0x4a3d8, 0xf6f6f6, 0},
+{W, 1, "", 0x4a3dc, 0xf7f7f7, 0},
+{W, 1, "", 0x4a3e0, 0xf8f8f8, 0},
+{W, 1, "", 0x4a3e4, 0xf9f9f9, 0},
+{W, 1, "", 0x4a3e8, 0xfafafa, 0},
+{W, 1, "", 0x4a3ec, 0xfbfbfb, 0},
+{W, 1, "", 0x4a3f0, 0xfcfcfc, 0},
+{W, 1, "", 0x4a3f4, 0xfdfdfd, 0},
+{W, 1, "", 0x4a3f8, 0xfefefe, 0},
+{W, 1, "", 0x4a3fc, 0xffffff, 0},
+{M, 1, "fb0 inteldrmfb frame buffer device", },
+{M, 1, "drm registered panic notifier", },
+{M, 1, "[drm] Initialized i915 1.6.0 20080730 for 0000 00 02.0 on minor 0", },
diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c
new file mode 100644
index 0000000000..f28c920fc1
--- /dev/null
+++ b/src/mainboard/google/stout/mainboard.c
@@ -0,0 +1,292 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
+#include <x86emu/x86emu.h>
+#endif
+#include <pc80/mc146818rtc.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <arch/coreboot_tables.h>
+#include "hda_verb.h"
+#include "onboard.h"
+#include "ec.h"
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <smbios.h>
+#include <device/pci.h>
+#include <ec/quanta/it8518/ec.h>
+
+void mainboard_suspend_resume(void)
+{
+	/* Call SMM finalize() handlers before resume */
+	outb(0xcb, 0xb2);
+
+	/* Stout EC needs to be put back in ACPI mode */
+	ec_write_cmd(EC_CMD_NOTIFY_ACPI_ENTER);
+}
+
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+static int int15_handler(struct eregs *regs)
+{
+	int res=-1;
+
+	printk(BIOS_DEBUG, "%s: INT15 function %04x!\n",
+			__func__, regs->eax & 0xffff);
+
+	switch(regs->eax & 0xffff) {
+	case 0x5f34:
+		/*
+		 * Set Panel Fitting Hook:
+		 *  bit 2 = Graphics Stretching
+		 *  bit 1 = Text Stretching
+		 *  bit 0 = Centering (do not set with bit1 or bit2)
+		 *  0     = video bios default
+		 */
+		regs->eax &= 0xffff0000;
+		regs->eax |= 0x005f;
+		regs->ecx &= 0xffffff00;
+		regs->ecx |= 0x00; /* Use video bios default */
+		res = 0;
+		break;
+	case 0x5f35:
+		/*
+		 * Boot Display Device Hook:
+		 *  bit 0 = CRT
+		 *  bit 1 = TV (eDP)
+		 *  bit 2 = EFP
+		 *  bit 3 = LFP
+		 *  bit 4 = CRT2
+		 *  bit 5 = TV2 (eDP)
+		 *  bit 6 = EFP2
+		 *  bit 7 = LFP2
+		 */
+		regs->eax &= 0xffff0000;
+		regs->eax |= 0x005f;
+		regs->ecx &= 0xffff0000;
+		regs->ecx |= 0x0000; /* Use video bios default */
+		res = 0;
+		break;
+	case 0x5f51:
+		/*
+		 * Hook to select active LFP configuration:
+		 *  00h = No LVDS, VBIOS does not enable LVDS
+		 *  01h = Int-LVDS, LFP driven by integrated LVDS decoder
+		 *  02h = SVDO-LVDS, LFP driven by SVDO decoder
+		 *  03h = eDP, LFP Driven by Int-DisplayPort encoder
+		 */
+		regs->eax &= 0xffff0000;
+		regs->eax |= 0x005f;
+		regs->ecx &= 0xffff0000;
+		regs->ecx |= 0x0001;
+		res = 0;
+		break;
+	case 0x5f70:
+		switch ((regs->ecx >> 8) & 0xff) {
+		case 0:
+			/* Get Mux */
+			regs->eax &= 0xffff0000;
+			regs->eax |= 0x005f;
+			regs->ecx &= 0xffff0000;
+			regs->ecx |= 0x0000;
+			res = 0;
+			break;
+		case 1:
+			/* Set Mux */
+			regs->eax &= 0xffff0000;
+			regs->eax |= 0x005f;
+			regs->ecx &= 0xffff0000;
+			regs->ecx |= 0x0000;
+			res = 0;
+			break;
+		case 2:
+			/* Get SG/Non-SG mode */
+			regs->eax &= 0xffff0000;
+			regs->eax |= 0x005f;
+			regs->ecx &= 0xffff0000;
+			regs->ecx |= 0x0000;
+			res = 0;
+			break;
+		default:
+			/* Interrupt was not handled */
+			printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n",
+				((regs->ecx >> 8) & 0xff));
+			return 0;
+		}
+		break;
+
+        default:
+		printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
+				regs->eax & 0xffff);
+		break;
+	}
+	return res;
+}
+#endif
+
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
+static int int15_handler(void)
+{
+	printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
+			  __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
+
+	switch (M.x86.R_AX) {
+	case 0x5f34:
+		/*
+		 * Set Panel Fitting Hook:
+		 *  bit 2 = Graphics Stretching
+		 *  bit 1 = Text Stretching
+		 *  bit 0 = Centering (do not set with bit1 or bit2)
+		 */
+		M.x86.R_AX = 0x005f;
+		M.x86.R_CL = 0x00;
+		break;
+	case 0x5f35:
+		/*
+		 * Boot Display Device Hook:
+		 *  bit 0 = CRT
+		 *  bit 1 = TV (eDP)
+		 *  bit 2 = EFP
+		 *  bit 3 = LFP
+		 *  bit 4 = CRT2
+		 *  bit 5 = TV2 (eDP)
+		 *  bit 6 = EFP2
+		 *  bit 7 = LFP2
+		 */
+		M.x86.R_AX = 0x005f;
+		M.x86.R_CX = 0x0000; /* Use video bios default */
+		break;
+	case 0x5f51:
+		/*
+		 * Hook to select active LFP configuration:
+		 *  00h = No LVDS, VBIOS does not enable LVDS
+		 *  01h = Int-LVDS, LFP driven by integrated LVDS decoder
+		 *  02h = SVDO-LVDS, LFP driven by SVDO decoder
+		 *  03h = eDP, LFP Driven by Int-DisplayPort encoder
+		 */
+		M.x86.R_AX = 0x005f;
+		M.x86.R_CX = 1;
+		break;
+	case 0x5f70:
+		switch (M.x86.R_CH) {
+		case 0:
+			/* Get Mux */
+			M.x86.R_AX = 0x005f;
+			M.x86.R_CL = 0;
+			break;
+		case 1:
+			/* Set Mux */
+			M.x86.R_AX = 0x005f;
+			M.x86.R_CX = 0;
+			break;
+		case 2:
+			/* Get SG/Non-SG mode */
+			M.x86.R_AX = 0x005f;
+			M.x86.R_CX = 0;
+			break;
+		default:
+			/* Interrupt was not handled */
+			printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n",
+				M.x86.R_CH);
+			return 0;
+		}
+		break;
+	default:
+		/* Interrupt was not handled */
+		printk(BIOS_DEBUG, "Unknown INT15 function: 0x%04x\n",
+			M.x86.R_AX);
+		return 0;
+	}
+
+	/* Interrupt handled */
+	return 1;
+}
+#endif
+
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+static void int15_install(void)
+{
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
+	typedef int (* yabel_handleIntFunc)(void);
+	extern yabel_handleIntFunc yabel_intFuncArray[256];
+	yabel_intFuncArray[0x15] = int15_handler;
+#endif
+#ifdef CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+	mainboard_interrupt_handlers(0x15, &int15_handler);
+#endif
+}
+#endif
+
+/* Audio Setup */
+
+extern const u32 * cim_verb_data;
+extern u32 cim_verb_data_size;
+extern const u32 * pc_beep_verbs;
+extern u32 pc_beep_verbs_size;
+
+static void verb_setup(void)
+{
+	cim_verb_data = mainboard_cim_verb_data;
+	cim_verb_data_size = sizeof(mainboard_cim_verb_data);
+	pc_beep_verbs = mainboard_pc_beep_verbs;
+	pc_beep_verbs_size = mainboard_pc_beep_verbs_size;
+}
+
+static void mainboard_init(device_t dev)
+{
+	struct device *ethernet_dev = NULL;
+
+	/* Initialize the Embedded Controller */
+	stout_ec_init();
+
+	/*
+	 * Battery life time - LAN PCIe should enter ASPM L1 to save
+	 * power when LAN connection is idle.
+	 * enable CLKREQ: LAN pci config space 0x81h=01
+	 */
+	ethernet_dev = dev_find_device(STOUT_NIC_VENDOR_ID,
+				       STOUT_NIC_DEVICE_ID, dev);
+
+	if (ethernet_dev != NULL)
+		pci_write_config8(ethernet_dev, 0x81, 0x01);
+}
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+
+static void mainboard_enable(device_t dev)
+{
+	dev->ops->init = mainboard_init;
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+	/* Install custom int15 handler for VGA OPROM */
+	int15_install();
+#endif
+	verb_setup();
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/google/stout/mainboard_smi.c b/src/mainboard/google/stout/mainboard_smi.c
new file mode 100644
index 0000000000..f6663de6f6
--- /dev/null
+++ b/src/mainboard/google/stout/mainboard_smi.c
@@ -0,0 +1,155 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <southbridge/intel/bd82x6x/nvs.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/me.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <northbridge/intel/sandybridge/pcie_config.c>
+#include <cpu/intel/model_206ax/model_206ax.h>
+
+/* Include romstage serial for SIO helper functions */
+#include <superio/ite/it8772f/early_serial.c>
+
+/* Include EC functions */
+#include <ec/quanta/it8518/ec.h>
+#include "ec.h"
+
+int mainboard_io_trap_handler(int smif)
+{
+	switch (smif) {
+	case 0x99:
+		printk(BIOS_DEBUG, "Sample\n");
+		smm_get_gnvs()->smif = 0;
+		break;
+	default:
+		return 0;
+	}
+
+	/* On success, the IO Trap Handler returns 0
+	 * On failure, the IO Trap Handler returns a value != 0
+	 *
+	 * For now, we force the return value to 0 and log all traps to
+	 * see what's going on.
+	 */
+	//gnvs->smif = 0;
+	return 1;
+}
+
+static u8 mainboard_smi_ec(void)
+{
+	u8 cmd = ec_it8518_get_event();
+	u32 pm1_cnt;
+
+	switch (cmd) {
+	case EC_SMI_LID_CLOSED:
+		printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
+		/* Go to S5 */
+		pm1_cnt = inl(smm_get_pmbase() + PM1_CNT);
+		pm1_cnt |= (0xf << 10);
+		outl(pm1_cnt, smm_get_pmbase() + PM1_CNT);
+		break;
+	}
+
+	return cmd;
+}
+
+void mainboard_smi_gpi(u16 gpi_sts)
+{
+	if (gpi_sts & (1 << EC_SMI_GPI)) {
+		/* Process all pending events */
+		while (mainboard_smi_ec() != 0);
+	}
+}
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+	/*
+	 * Tell the EC to Enable USB power for S3 if requested.
+	 * Bit0 of 0x0D/Bit0 of 0x26
+	 * 0/0 All USB port off
+	 * 1/0 USB on, all USB port didn’t support wake up
+	 * 0/1 USB on, yellow port support wake up charge, but may not support
+	 *             charge smart phone.
+	 * 1/1 USB on, yellow port in AUTO mode and didn’t support wake up system.
+	 */
+	if (smm_get_gnvs()->s3u0 != 0 || smm_get_gnvs()->s3u1 != 0) {
+		ec_write(EC_PERIPH_CNTL_3, ec_read(EC_PERIPH_CNTL_3) | 0x00);
+		ec_write(EC_USB_S3_EN, ec_read(EC_USB_S3_EN) | 0x01);
+		printk(BIOS_DEBUG, "USB wake from S3 enabled.\n");
+	} else {
+		/*
+		 * If USB charging in suspend is disabled then also disable
+		 * the XHCI PME to prevent wake when the port power is cut
+		 * after the transition into suspend.
+		 */
+		if (smm_get_gnvs()->xhci) {
+			u32 reg32 = pcie_read_config32(PCH_XHCI_DEV, 0x74);
+			reg32 &= ~(1 << 8); /* disable PME */
+			reg32 |= (1 << 15); /* clear PME status */
+			pcie_write_config32(PCH_XHCI_DEV, 0x74, reg32);
+		}
+	}
+
+	ec_kbc_write_cmd(EC_KBD_CMD_MUTE);
+	ec_it8518_enable_wake_events();
+}
+
+#define APMC_FINALIZE 0xcb
+#define APMC_ACPI_EN  0xe1
+#define APMC_ACPI_DIS 0x1e
+
+static int mainboard_finalized = 0;
+
+int mainboard_smi_apmc(u8 apmc)
+{
+	switch (apmc) {
+	case APMC_FINALIZE:
+		if (mainboard_finalized) {
+			printk(BIOS_DEBUG, "SMI#: Already finalized\n");
+			return 0;
+		}
+	printk(BIOS_DEBUG, "SMI#: finalize\n");
+		intel_me_finalize_smm();
+		intel_pch_finalize_smm();
+		intel_sandybridge_finalize_smm();
+		intel_model_206ax_finalize_smm();
+		stout_ec_finalize_smm();
+
+		mainboard_finalized = 1;
+		break;
+	case APMC_ACPI_EN:
+		/*
+		 * TODO(kimarie) Clear all pending events and enable SCI.
+		 */
+		ec_write_cmd(EC_CMD_NOTIFY_ACPI_ENTER);
+		break;
+	case APMC_ACPI_DIS:
+		/*
+		 * TODO(kimarie) Clear all pending events and enable SMI.
+		 */
+		ec_write_cmd(EC_CMD_NOTIFY_ACPI_EXIT);
+		break;
+	}
+	return 0;
+}
diff --git a/src/mainboard/google/stout/onboard.h b/src/mainboard/google/stout/onboard.h
new file mode 100644
index 0000000000..18dce32ae9
--- /dev/null
+++ b/src/mainboard/google/stout/onboard.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011-2012 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef STOUT_ONBOARD_H
+#define STOUT_ONBOARD_H
+
+#include <arch/smp/mpspec.h>
+
+#define STOUT_NIC_VENDOR_ID		0x10EC
+#define STOUT_NIC_DEVICE_ID		0x8168
+
+#define XHCI_MODE     2  // Auto
+#define XHCI_PORTS    3  // Port 0 & 1
+#define XHCI_PREBOOT  0  // No PreOS boot support
+#define XHCI_STREAMS  1  // Sure, lets have streams
+
+#endif
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
new file mode 100644
index 0000000000..2f4e1a7a76
--- /dev/null
+++ b/src/mainboard/google/stout/romstage.c
@@ -0,0 +1,360 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <lib.h>
+#include <timestamp.h>
+#include <arch/byteorder.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <pc80/mc146818rtc.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include "northbridge/intel/sandybridge/sandybridge.h"
+#include "northbridge/intel/sandybridge/raminit.h"
+#include "southbridge/intel/bd82x6x/pch.h"
+#include "southbridge/intel/bd82x6x/gpio.h"
+#include <arch/cpu.h>
+#include <cpu/x86/bist.h>
+#include <cpu/x86/msr.h>
+#include "gpio.h"
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/chromeos.h>
+#endif
+#include <cbfs.h>
+#include <ec/quanta/it8518/ec.h>
+#include "ec.h"
+#include "onboard.h"
+
+static void pch_enable_lpc(void)
+{
+	/*
+	 * Enable:
+	 *  EC Decode Range Port62/66
+	 *  SuperIO Port2E/2F
+	 *  PS/2 Keyboard/Mouse Port60/64
+	 *  FDD Port3F0h-3F5h and Port3F7h
+	 */
+	pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
+			CNF1_LPC_EN | FDD_LPC_EN);
+
+	/* Stout EC Decode Range Port68/6C */
+	pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 | 0x40001));
+}
+
+static void rcba_config(void)
+{
+	u32 reg32;
+
+	/*
+	 *             GFX         INTA -> PIRQA (MSI)
+	 * D20IP_XHCI  XHCI        INTA -> PIRQD (MSI)
+	 * D26IP_E2P   EHCI #2     INTA -> PIRQF
+	 * D27IP_ZIP   HDA         INTA -> PIRQA (MSI)
+	 * D28IP_P2IP  WLAN        INTA -> PIRQD
+	 * D28IP_P3IP  Card Reader INTB -> PIRQE
+	 * D28IP_P6IP  LAN         INTC -> PIRQB
+	 * D29IP_E1P   EHCI #1     INTA -> PIRQD
+	 * D31IP_SIP   SATA        INTA -> PIRQB (MSI)
+	 * D31IP_SMIP  SMBUS       INTB -> PIRQH
+	 */
+
+	/* Device interrupt pin register (board specific) */
+	RCBA32(D31IP) = (NOINT << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
+		(INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
+	RCBA32(D30IP) = (NOINT << D30IP_PIP);
+	RCBA32(D29IP) = (INTA << D29IP_E1P);
+	RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) |
+		(INTB << D28IP_P3IP) | (NOINT << D28IP_P4IP) |
+		(NOINT << D28IP_P5IP) | (INTC << D28IP_P6IP) |
+		(NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP);
+	RCBA32(D27IP) = (INTA << D27IP_ZIP);
+	RCBA32(D26IP) = (INTA << D26IP_E2P);
+	RCBA32(D25IP) = (NOINT << D25IP_LIP);
+	RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
+	RCBA32(D20IP) = (INTA << D20IP_XHCIIP);
+
+	/* Device interrupt route registers */
+	DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
+	DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
+	DIR_ROUTE(D28IR, PIRQD, PIRQE, PIRQB, PIRQC);
+	DIR_ROUTE(D27IR, PIRQA, PIRQB, PIRQC, PIRQD);
+	DIR_ROUTE(D26IR, PIRQF, PIRQB, PIRQC, PIRQD);
+	DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
+	DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
+	DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG);
+
+	/* Enable IOAPIC (generic) */
+	RCBA16(OIC) = 0x0100;
+	/* PCH BWG says to read back the IOAPIC enable register */
+	(void) RCBA16(OIC);
+
+	/* Disable unused devices (board specific) */
+	reg32 = RCBA32(FD);
+	reg32 |= PCH_DISABLE_ALWAYS;
+	/* Disable PCI bridge so MRC does not probe this bus */
+	reg32 |= PCH_DISABLE_P2P;
+	RCBA32(FD) = reg32;
+}
+
+// FIXME, this function is generic code that should go to sb/... or
+// nb/../early_init.c
+static void early_pch_init(void)
+{
+	// Nothing to do for stout
+}
+
+	/*
+	 * The Stout EC needs to be reset to RW mode. It is important that
+	 * the RTC_PWR_STS is not set until ramstage EC init.
+	 */
+static void early_ec_init(void)
+{
+	u8 ec_status = ec_read(EC_STATUS_REG);
+	int rec_mode = get_recovery_mode_switch();
+
+	if (((ec_status & 0x3) == EC_IN_RO_MODE) ||
+	    ((ec_status & 0x3) == EC_IN_RECOVERY_MODE)) {
+
+		printk(BIOS_DEBUG, "EC Cold Boot Detected\n");
+		if (!rec_mode) {
+			/*
+			 * Tell EC to exit RO mode
+			 */
+			printk(BIOS_DEBUG, "EC will exit RO mode and boot normally\n");
+			ec_write_cmd(EC_CMD_EXIT_BOOT_BLOCK);
+			die("wait for ec to reset");
+		}
+	} else {
+		printk(BIOS_DEBUG, "EC Warm Boot Detected\n");
+		ec_write_cmd(EC_CMD_WARM_RESET);
+	}
+}
+
+void main(unsigned long bist)
+{
+	int boot_mode = 0;
+	int cbmem_was_initted;
+	u32 pm1_cnt;
+	u16 pm1_sts;
+
+#if CONFIG_COLLECT_TIMESTAMPS
+	tsc_t start_romstage_time;
+	tsc_t before_dram_time;
+	tsc_t after_dram_time;
+	tsc_t base_time = {
+		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
+		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
+	};
+#endif
+	struct pei_data pei_data = {
+		pei_version: PEI_VERSION,
+		mchbar: DEFAULT_MCHBAR,
+		dmibar: DEFAULT_DMIBAR,
+		epbar: DEFAULT_EPBAR,
+		pciexbar: CONFIG_MMCONF_BASE_ADDRESS,
+		smbusbar: SMBUS_IO_BASE,
+		wdbbar: 0x4000000,
+		wdbsize: 0x1000,
+		hpet_address: CONFIG_HPET_ADDRESS,
+		rcba: DEFAULT_RCBABASE,
+		pmbase: DEFAULT_PMBASE,
+		gpiobase: DEFAULT_GPIOBASE,
+		thermalbase: 0xfed08000,
+		system_type: 0, // 0 Mobile, 1 Desktop/Server
+		tseg_size: CONFIG_SMM_TSEG_SIZE,
+		spd_addresses: { 0xA0, 0x00,0xA4,0x00 },
+		ts_addresses: { 0x00, 0x00, 0x00, 0x00 },
+		ec_present: 1,
+		// 0 = leave channel enabled
+		// 1 = disable dimm 0 on channel
+		// 2 = disable dimm 1 on channel
+		// 3 = disable dimm 0+1 on channel
+		dimm_channel0_disabled: 2,
+		dimm_channel1_disabled: 2,
+		max_ddr3_freq: 1600,
+		usb_port_config: {
+			/* enabled   usb oc pin    length */
+			{ 1, 0, 0x0040 }, /* P0: USB 3.0 1  (OC0) */
+			{ 1, 0, 0x0040 }, /* P1: USB 3.0 2  (OC0) */
+			{ 0, 1, 0x0000 }, /* P2: Empty */
+			{ 1, 1, 0x0040 }, /* P3: Camera (no OC) */
+			{ 1, 1, 0x0040 }, /* P4: WLAN   (no OC) */
+			{ 1, 1, 0x0040 }, /* P5: WWAN   (no OC) */
+			{ 0, 1, 0x0000 }, /* P6: Empty */
+			{ 0, 1, 0x0000 }, /* P7: Empty */
+			{ 0, 5, 0x0000 }, /* P8: Empty */
+			{ 1, 4, 0x0040 }, /* P9: USB 2.0 (AUO4) (OC4) */
+			{ 0, 5, 0x0000 }, /* P10: Empty */
+			{ 0, 5, 0x0000 }, /* P11: Empty */
+			{ 0, 5, 0x0000 }, /* P12: Empty */
+			{ 1, 5, 0x0040 }, /* P13: Bluetooth (no OC) */
+		},
+		usb3: {
+			mode: XHCI_MODE,
+			hs_port_switch_mask: XHCI_PORTS,
+			preboot_support: XHCI_PREBOOT,
+			xhci_streams: XHCI_STREAMS,
+		},
+	};
+
+#if CONFIG_COLLECT_TIMESTAMPS
+	start_romstage_time = rdtsc();
+#endif
+
+	if (bist == 0)
+		enable_lapic();
+
+	pch_enable_lpc();
+
+	/* Enable GPIOs */
+	pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
+	pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
+	setup_pch_gpios(&stout_gpio_map);
+
+	/* Initialize console device(s) */
+	console_init();
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+	if (MCHBAR16(SSKPD) == 0xCAFE) {
+		printk(BIOS_DEBUG, "soft reset detected\n");
+		boot_mode = 1;
+
+		/* System is not happy after keyboard reset... */
+		printk(BIOS_DEBUG, "Issuing CF9 warm reset\n");
+		outb(0x6, 0xcf9);
+		hlt();
+	}
+
+
+	/* Perform some early chipset initialization required
+	 * before RAM initialization can work
+	 */
+	sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
+	printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
+
+	/* Check PM1_STS[15] to see if we are waking from Sx */
+	pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
+
+	/* Read PM1_CNT[12:10] to determine which Sx state */
+	pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
+
+	if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
+#if CONFIG_HAVE_ACPI_RESUME
+		printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+		boot_mode = 2;
+		/* Clear SLP_TYPE. This will break stage2 but
+		 * we care for that when we get there.
+		 */
+		outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
+#else
+		printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+#endif
+	}
+
+	/* Do ec reset as early as possible, but skip it on S3 resume */
+	if (boot_mode < 2)
+		early_ec_init();
+
+	post_code(0x38);
+	/* Enable SPD ROMs and DDR-III DRAM */
+	enable_smbus();
+
+	/* Prepare USB controller early in S3 resume */
+	if (boot_mode == 2)
+		enable_usb_bar();
+
+	post_code(0x39);
+
+	post_code(0x3a);
+	pei_data.boot_mode = boot_mode;
+#if CONFIG_COLLECT_TIMESTAMPS
+	before_dram_time = rdtsc();
+#endif
+	sdram_initialize(&pei_data);
+
+#if CONFIG_COLLECT_TIMESTAMPS
+	after_dram_time = rdtsc();
+#endif
+	post_code(0x3b);
+	/* Perform some initialization that must run before stage2 */
+	early_pch_init();
+	post_code(0x3c);
+
+	rcba_config();
+	post_code(0x3d);
+
+	quick_ram_check();
+	post_code(0x3e);
+
+	MCHBAR16(SSKPD) = 0xCAFE;
+#if CONFIG_EARLY_CBMEM_INIT
+	cbmem_was_initted = !cbmem_initialize();
+#else
+	cbmem_was_initted = cbmem_reinit((uint64_t) (get_top_of_ram()
+						     - HIGH_MEMORY_SIZE));
+#endif
+
+#if CONFIG_HAVE_ACPI_RESUME
+	/* If there is no high memory area, we didn't boot before, so
+	 * this is not a resume. In that case we just create the cbmem toc.
+	 */
+
+	*(u32 *)CBMEM_BOOT_MODE = 0;
+	*(u32 *)CBMEM_RESUME_BACKUP = 0;
+
+	if ((boot_mode == 2) && cbmem_was_initted) {
+		void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
+		if (resume_backup_memory) {
+			*(u32 *)CBMEM_BOOT_MODE = boot_mode;
+			*(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory;
+		}
+		/* Magic for S3 resume */
+		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
+	} else if (boot_mode == 2) {
+		/* Failed S3 resume, reset to come up cleanly */
+		outb(0x6, 0xcf9);
+		hlt();
+	} else {
+		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
+	}
+#endif
+	post_code(0x3f);
+#if CONFIG_CHROMEOS
+	init_chromeos(boot_mode);
+#endif
+#if CONFIG_COLLECT_TIMESTAMPS
+	timestamp_init(base_time);
+	timestamp_add(TS_START_ROMSTAGE, start_romstage_time );
+	timestamp_add(TS_BEFORE_INITRAM, before_dram_time );
+	timestamp_add(TS_AFTER_INITRAM, after_dram_time );
+	timestamp_add_now(TS_END_ROMSTAGE);
+#endif
+#if CONFIG_CONSOLE_CBMEM
+	/* Keep this the last thing this function does. */
+	cbmemc_reinit();
+#endif
+}
diff --git a/src/mainboard/google/stout/thermal.h b/src/mainboard/google/stout/thermal.h
new file mode 100644
index 0000000000..d93fbef42a
--- /dev/null
+++ b/src/mainboard/google/stout/thermal.h
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef STOUT_THERMAL_H
+#define STOUT_THERMAL_H
+
+/* Active Thermal and fans are controlled by the EC. */
+
+/* Temperature which OS will shutdown at */
+#define CRITICAL_TEMPERATURE    99
+
+/* Temperature which OS will throttle CPU */
+#define PASSIVE_TEMPERATURE     90
+
+/* Tj_max value for calculating PECI CPU temperature */
+#define MAX_TEMPERATURE        100
+
+#endif /* STOUT_THERMAL_H */