diff options
| author | Edward O'Callaghan <quasisec@chromium.org> | 2019-10-23 00:28:39 +1100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-06 10:15:10 +0000 |
| commit | b4741616ea3dc1f0b281376f9c5e0ffe75a1b15b (patch) | |
| tree | 74f462a669397f8456d118f5b3535da5a479ca0e /src | |
| parent | fb2a9d5ed86d9d5e5d7a8b20e71df0deba3bc5c0 (diff) | |
mainboard/google: Rework Hatch so that SPD in CBFS is optional
All Hatch variants so far embed static SPD data encoded within the
firmware image. However we wish the flexibility for romstage
implementations that allow for reading the SPD data dynamically over
SMBus.
BRANCH=none
BUG=b:143134702
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: Ie1637d08cdd85bc8d7c3b6f2d6f386d0e0c6589b
Signed-off-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/hatch/Kconfig | 4 | ||||
| -rw-r--r-- | src/mainboard/google/hatch/Makefile.inc | 4 | ||||
| -rw-r--r-- | src/mainboard/google/hatch/romstage_spd_cbfs.c (renamed from src/mainboard/google/hatch/romstage.c) | 0 |
3 files changed, 6 insertions, 2 deletions
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 004cc28633..219be2265a 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -58,6 +58,10 @@ config DIMM_SPD_SIZE int default 512 +config ROMSTAGE_SPD_CBFS + bool + default y + config DRIVER_TPM_SPI_BUS default 0x1 diff --git a/src/mainboard/google/hatch/Makefile.inc b/src/mainboard/google/hatch/Makefile.inc index 01a1eb85dd..a226bd623c 100644 --- a/src/mainboard/google/hatch/Makefile.inc +++ b/src/mainboard/google/hatch/Makefile.inc @@ -20,7 +20,7 @@ ramstage-y += ramstage.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c -romstage-y += romstage.c +romstage-$(CONFIG_ROMSTAGE_SPD_CBFS) += romstage_spd_cbfs.c romstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_CHROMEOS) += chromeos.c @@ -33,4 +33,4 @@ VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR)) subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include -subdirs-y += spd +subdirs-$(CONFIG_ROMSTAGE_SPD_CBFS) += spd diff --git a/src/mainboard/google/hatch/romstage.c b/src/mainboard/google/hatch/romstage_spd_cbfs.c index a94fab5df9..a94fab5df9 100644 --- a/src/mainboard/google/hatch/romstage.c +++ b/src/mainboard/google/hatch/romstage_spd_cbfs.c |