diff options
| author | Maxim Polyakov <max.senia.poliak@gmail.com> | 2019-09-11 19:18:02 +0300 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2019-09-14 05:47:18 +0000 |
| commit | afd7ce680be5a3efd170cc4ce4e4be7f5d27d61e (patch) | |
| tree | 9821982e41716124b2bdd1f74f2327b617df2325 /src | |
| parent | 7d549f8908c754e2a396cf1e91a3d14274793e5e (diff) | |
mb/asrock/h110m: enable ACPI LDN in SuperIO
Change-Id: Icbfec4dc82a1fbbfeb49c3dbd047509f5873d235
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/asrock/h110m/devicetree.cb | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index eed67b762e..9552b10f0a 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -365,7 +365,13 @@ chip soc/intel/skylake device pnp 2e.109 off end # GPIO3 device pnp 2e.209 off end # GPIO4 device pnp 2e.309 off end # GPIO5 - device pnp 2e.a off end # ACPI + device pnp 2e.a on + # Power RAM in S3 and let the PCH + # handle power failure actions + irq 0xe4 = 0x70 + # Set HWM reset source to LRESET# + irq 0xe7 = 0x01 + end # ACPI device pnp 2e.b on # HWM, LED io 0x60 = 0x0290 io 0x62 = 0 |