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authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-07-16 19:02:20 +1000
committerEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-07-17 02:19:30 +0200
commita47ab1be121004a88a8c680f218ad0f04a374901 (patch)
treed9a49325d99f49b0b20749404efb02d3cb4a2b15 /src
parentff9e45e0b2a6bff85911e64572df3c9d1047feff (diff)
soc,Makefile.inc: Trivial - drop trailing blank lines at EOF
Change-Id: I6db4eada5be5f9a4340d9edb942924e2fd18b5ca Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6284 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/fsp_baytrail/Makefile.inc1
-rw-r--r--src/soc/intel/fsp_baytrail/fsp/Makefile.inc1
2 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc
index e0f1e1dfc0..598deb4b33 100644
--- a/src/soc/intel/fsp_baytrail/Makefile.inc
+++ b/src/soc/intel/fsp_baytrail/Makefile.inc
@@ -87,4 +87,3 @@ endif
endif
endif
-
diff --git a/src/soc/intel/fsp_baytrail/fsp/Makefile.inc b/src/soc/intel/fsp_baytrail/fsp/Makefile.inc
index ebdc80a721..05620aedcc 100644
--- a/src/soc/intel/fsp_baytrail/fsp/Makefile.inc
+++ b/src/soc/intel/fsp_baytrail/fsp/Makefile.inc
@@ -19,4 +19,3 @@
ramstage-y += chipset_fsp_util.c
romstage-y += chipset_fsp_util.c
-