nb/intel/haswell/gma: Use common init_igd_opregion method

Use common init_igd_opregion method and remove duplicated code in
acpi.c.

Change-Id: I811e8bd2be68813321dc4581af02e1c21b0da076
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>

4 files changed, 19 insertions, 130 deletions

diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index d5dec53041..90f877499b 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -17,6 +17,7 @@ config NORTHBRIDGE_INTEL_HASWELL
 	bool
 	select CPU_INTEL_HASWELL
 	select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE
+	select NORTHBRIDGE_INTEL_COMMON_GMA_OPREGION
 	select INTEL_DDI
 	select INTEL_GMA_ACPI
 	select RELOCATABLE_RAMSTAGE
diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c
index cb430f927a..8afef00baa 100644
--- a/src/northbridge/intel/haswell/acpi.c
+++ b/src/northbridge/intel/haswell/acpi.c
@@ -16,18 +16,12 @@
  */
 
 #include <types.h>
-#include <string.h>
 #include <console/console.h>
-#include <arch/io.h>
 #include <arch/acpi.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include "haswell.h"
-#include <cbmem.h>
-#include <arch/acpigen.h>
-#include <cpu/cpu.h>
-#include <drivers/intel/gma/intel_bios.h>
 
 unsigned long acpi_fill_mcfg(unsigned long current)
 {
@@ -71,121 +65,3 @@ unsigned long acpi_fill_mcfg(unsigned long current)
 
 	return current;
 }
-
-static void *get_intel_vbios(void)
-{
-	/* This should probably be looking at CBFS or we should always
-	 * deploy the VBIOS on Intel systems, even if we don't run it
-	 * in coreboot (e.g. SeaBIOS only scenarios).
-	 */
-	u8 *vbios = (u8 *)0xc0000;
-
-	optionrom_header_t *oprom = (optionrom_header_t *)vbios;
-	optionrom_pcir_t *pcir = (optionrom_pcir_t *)(vbios +
-						oprom->pcir_offset);
-
-
-	printk(BIOS_DEBUG, "GET_VBIOS: %x %x %x %x %x\n",
-		oprom->signature, pcir->vendor, pcir->classcode[0],
-		pcir->classcode[1], pcir->classcode[2]);
-
-
-	if ((oprom->signature == OPROM_SIGNATURE) &&
-		(pcir->vendor == PCI_VENDOR_ID_INTEL) &&
-		(pcir->classcode[0] == 0x00) &&
-		(pcir->classcode[1] == 0x00) &&
-		(pcir->classcode[2] == 0x03))
-		return (void *)vbios;
-
-	return NULL;
-}
-
-static int init_opregion_vbt(igd_opregion_t *opregion)
-{
-	void *vbios;
-	vbios = get_intel_vbios();
-	if (!vbios) {
-		printk(BIOS_DEBUG, "VBIOS not found.\n");
-		return 1;
-	}
-
-	printk(BIOS_DEBUG, " ... VBIOS found at %p\n", vbios);
-	optionrom_header_t *oprom = (optionrom_header_t *)vbios;
-	optionrom_vbt_t *vbt = (optionrom_vbt_t *)(vbios +
-						oprom->vbt_offset);
-
-	if (read32(vbt->hdr_signature) != VBT_SIGNATURE) {
-		printk(BIOS_DEBUG, "VBT not found!\n");
-		return 1;
-	}
-
-	memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, 4);
-	memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size < 7168 ?
-						vbt->hdr_vbt_size : 7168);
-
-	return 0;
-}
-
-
-/* Initialize IGD OpRegion, called from ACPI code */
-int init_igd_opregion(igd_opregion_t *opregion)
-{
-	device_t igd;
-	u16 reg16;
-
-	memset((void *)opregion, 0, sizeof(igd_opregion_t));
-
-	// FIXME if IGD is disabled, we should exit here.
-
-	memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
-		sizeof(opregion->header.signature));
-
-	/* 8kb */
-	opregion->header.size = sizeof(igd_opregion_t) / 1024;
-	opregion->header.version = IGD_OPREGION_VERSION;
-
-	// FIXME We just assume we're mobile for now
-	opregion->header.mailboxes = MAILBOXES_MOBILE;
-
-	// TODO Initialize Mailbox 1
-
-	// TODO Initialize Mailbox 3
-	opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;
-	opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;
-	opregion->mailbox3.pcft = 0; // should be (IMON << 1) & 0x3e
-	opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS;
-	opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000;
-	opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19;
-	opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433;
-	opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c;
-	opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866;
-	opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f;
-	opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99;
-	opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2;
-	opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc;
-	opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;
-	opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;
-
-	init_opregion_vbt(opregion);
-
-	/* TODO This needs to happen in S3 resume, too.
-	 * Maybe it should move to the finalize handler
-	 */
-	igd = dev_find_slot(0, PCI_DEVFN(0x2, 0));
-
-	pci_write_config32(igd, ASLS, (u32)opregion);
-	reg16 = pci_read_config16(igd, SWSCI);
-	reg16 &= ~(1 << 0);
-	reg16 |= (1 << 15);
-	pci_write_config16(igd, SWSCI, reg16);
-
-	/* clear dmisci status */
-	reg16 = inw(get_pmbase() + TCO1_STS);
-	reg16 |= DMISCI_STS; // reference code does an &=
-	outw(get_pmbase() + TCO1_STS, reg16);
-
-	/* clear and enable ACPI TCO SCI */
-	enable_tco_sci();
-
-	return 0;
-}
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 172aa7ed0d..fa4dec91e2 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -23,6 +23,7 @@
 #include <drivers/intel/gma/i915_reg.h>
 #include <drivers/intel/gma/i915.h>
 #include <cpu/intel/haswell/haswell.h>
+#include <northbridge/intel/common/gma_opregion.h>
 #include <stdlib.h>
 #include <string.h>
 
@@ -493,6 +494,20 @@ static void gma_ssdt(device_t device)
 	drivers_intel_gma_displays_ssdt_generate(gfx);
 }
 
+/* Enable SCI to ACPI _GPE._L06 */
+static void gma_enable_swsci(void)
+{
+	u16 reg16;
+
+	/* clear DMISCI status */
+	reg16 = inw(get_pmbase() + TCO1_STS);
+	reg16 &= DMISCI_STS;
+	outw(get_pmbase() + TCO1_STS, reg16);
+
+	/* clear and enable ACPI TCO SCI */
+	enable_tco_sci();
+}
+
 static unsigned long
 gma_write_acpi_tables(struct device *const dev,
 		      unsigned long current,
@@ -500,11 +515,13 @@ gma_write_acpi_tables(struct device *const dev,
 {
 	igd_opregion_t *opregion = (igd_opregion_t *)current;
 
-	if (init_igd_opregion(opregion))
+	if (init_igd_opregion(opregion) != CB_SUCCESS)
 		return current;
 
 	current += sizeof(igd_opregion_t);
 
+	gma_enable_swsci();
+
 	current = acpi_align_current(current);
 	return current;
 }
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index f0fe07d91d..00616afb49 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -213,11 +213,6 @@ void dump_mem(unsigned start, unsigned end);
 void report_platform_info(void);
 #endif /* !__SMM__ */
 
-#if !defined(__PRE_RAM__)
-#include <drivers/intel/gma/opregion.h>
-int init_igd_opregion(igd_opregion_t *igd_opregion);
-#endif
-
 #endif
 #endif
 #endif /* __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ */