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authorMarshall Dawson <marshalldawson3rd@gmail.com>2017-07-10 18:26:28 -0600
committerMartin Roth <martinroth@google.com>2017-07-31 17:31:22 +0000
commit8040fbf9fbd8f26ed4b53a54f92e5dcce20d4a1d (patch)
tree36f2a34fff1cdc564b170724f98f054abe22b9ba /src
parent5ebc8652cc50932286ce6752135e30a53ce69cee (diff)
soc/amd/stoneyridge: Fix GPIO bank1 control definition
Change-Id: Ia6c7357ba0c581dc46d173f462efce181847a4e1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20526 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/amd/stoneyridge/include/soc/gpio.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h
index a66701ac56..06933681c6 100644
--- a/src/soc/amd/stoneyridge/include/soc/gpio.h
+++ b/src/soc/amd/stoneyridge/include/soc/gpio.h
@@ -58,7 +58,7 @@
#define GPIO_42 (GPIO_BANK0_CONTROL + 0xa8)
/* GPIO_64 - GPIO_127 */
-#define GPIO_BANK1 (CONTROL AMD_SB_ACPI_MMIO_ADDR + 0x1600)
+#define GPIO_BANK1_CONTROL (AMD_SB_ACPI_MMIO_ADDR + 0x1600)
#define GPIO_64 (GPIO_BANK1_CONTROL + 0x00)
#define GPIO_65 (GPIO_BANK1_CONTROL + 0x04)
#define GPIO_66 (GPIO_BANK1_CONTROL + 0x08)