diff options
| author | David Wu <david_wu@quanta.corp-partner.google.com> | 2020-10-27 16:13:17 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-02 06:25:31 +0000 |
| commit | 77a23d10bfbc928812bbe6ba5426ca461a64ff26 (patch) | |
| tree | 783e503eec84736300bbd3ea2a65d9f6282ca978 /src | |
| parent | bc2c12c72834a5b24fadd13d24df93298199dda1 (diff) | |
mb/google/volteer/var/terrador: Enable SaGv support
Enable SaGv for terrador.
BUG=b:171763116
BRANCH=volteer
TEST="emerge-volteer coreboot" compiles successfully.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ie00166a619424a67f70f870e55822ae2cc6d023d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/volteer/variants/terrador/overridetree.cb | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index fbf724f601..d2e2d0b323 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -14,8 +14,6 @@ chip soc/intel/tigerlake register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A / Type-C Port 0 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A / Type-C Port 1 - register "SaGv" = "SaGv_Disabled" - # Disable SRCCLKREQ1# register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" |