* Adds support for PC Engines Alix.2D(1)3 board to Coreboot.

* DRAM initialization done message is now printed in debug-mode only, rather than everytime.

Signed-off-by: Aurelien Guillaume <aurelien@iwi.me>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5739 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

9 files changed, 549 insertions, 1 deletions

diff --git a/src/mainboard/pcengines/Kconfig b/src/mainboard/pcengines/Kconfig
index c1b0168505..db6426d099 100644
--- a/src/mainboard/pcengines/Kconfig
+++ b/src/mainboard/pcengines/Kconfig
@@ -3,6 +3,7 @@ choice
 	depends on VENDOR_PC_ENGINES
 
 source "src/mainboard/pcengines/alix1c/Kconfig"
+source "src/mainboard/pcengines/alix2d3/Kconfig"
 
 endchoice
 
diff --git a/src/mainboard/pcengines/alix2d3/Kconfig b/src/mainboard/pcengines/alix2d3/Kconfig
new file mode 100644
index 0000000000..ab6bcdad68
--- /dev/null
+++ b/src/mainboard/pcengines/alix2d3/Kconfig
@@ -0,0 +1,31 @@
+config BOARD_PCENGINES_ALIX2D3
+	bool "ALIX.2D3"
+	select ARCH_X86
+	select CPU_AMD_LX
+	select NORTHBRIDGE_AMD_LX
+	select SOUTHBRIDGE_AMD_CS5536
+	select HAVE_PIRQ_TABLE
+	select PIRQ_ROUTE
+	select UDELAY_TSC
+	select USE_DCACHE_RAM
+	select BOARD_ROMSIZE_KB_512
+
+config MAINBOARD_DIR
+	string
+	default pcengines/alix2d3
+	depends on BOARD_PCENGINES_ALIX2D3
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "ALIX.2D3"
+	depends on BOARD_PCENGINES_ALIX2D3
+
+config IRQ_SLOT_COUNT
+	int
+	default 6
+	depends on BOARD_PCENGINES_ALIX2D3
+
+config RAMBASE
+	hex
+	default 0x4000
+	depends on BOARD_PCENGINES_ALIX2D3
diff --git a/src/mainboard/pcengines/alix2d3/chip.h b/src/mainboard/pcengines/alix2d3/chip.h
new file mode 100644
index 0000000000..4dba37680a
--- /dev/null
+++ b/src/mainboard/pcengines/alix2d3/chip.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config {
+	int nothing;
+};
diff --git a/src/mainboard/pcengines/alix2d3/cmos.layout b/src/mainboard/pcengines/alix2d3/cmos.layout
new file mode 100644
index 0000000000..c1354a2866
--- /dev/null
+++ b/src/mainboard/pcengines/alix2d3/cmos.layout
@@ -0,0 +1,74 @@
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+#96         288       r       0        temporary_filler
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432          8       h       0        boot_countdown
+1008         16      h       0        check_sum
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+#7     3     ROM
+
+checksums
+
+checksum 392 1007 1008
+
+
diff --git a/src/mainboard/pcengines/alix2d3/devicetree.cb b/src/mainboard/pcengines/alix2d3/devicetree.cb
new file mode 100644
index 0000000000..edcbc06623
--- /dev/null
+++ b/src/mainboard/pcengines/alix2d3/devicetree.cb
@@ -0,0 +1,46 @@
+chip northbridge/amd/lx
+  	device pci_domain 0 on
+    		device pci 1.0 on end
+		device pci 1.1 on end
+      		chip southbridge/amd/cs5536
+			# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
+			# SIRQ Mode = Active(Quiet) mode. Save power....
+			# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
+			# How to get these? Boot linux and do this:
+			# rdmsr 0x51400025
+			register "lpc_serirq_enable" = "0x00001002"
+			# rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits
+			register "lpc_serirq_polarity" = "0x0000EFFD"
+			# mode is high 10 bits (determined from code)
+			register "lpc_serirq_mode" = "1"
+			# Don't yet know how to find this.
+			register "enable_gpio_int_route" = "0x0D0C0700"
+			register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
+			register "enable_USBP4_device" = "0"	#0: host, 1:device
+			register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+			register "com1_enable" = "1"
+			register "com1_address" = "0x3F8"
+			register "com1_irq" = "4"
+			register "com2_enable" = "1"                # Wired on Alix.2D13 only
+			register "com2_address" = "0x2F8"
+			register "com2_irq" = "3"
+			register "unwanted_vpci[0]" = "0x80000900"	# Disable VGA controller (not wired)
+			register "unwanted_vpci[1]" = "0x80007B00"	# Disable AC97 controller (not wired)
+			register "unwanted_vpci[2]" = "0"	        # End of list has a zero
+			device pci f.0 on end	# ISA Bridge
+			device pci f.1 on end	# Flash controller
+			device pci f.2 on end	# IDE controller
+			device pci f.4 on end	# OHCI
+			device pci f.5 on end	# EHCI
+      		end
+	end
+
+	# APIC cluster is late CPU init.
+	device lapic_cluster 0 on
+		chip cpu/amd/model_lx
+			device lapic 0 on end
+		end
+	end
+
+end
+
diff --git a/src/mainboard/pcengines/alix2d3/irq_tables.c b/src/mainboard/pcengines/alix2d3/irq_tables.c
new file mode 100644
index 0000000000..0dffcb6586
--- /dev/null
+++ b/src/mainboard/pcengines/alix2d3/irq_tables.c
@@ -0,0 +1,114 @@
+/*
+* This file is part of the coreboot project.
+*
+* Copyright (C) 2007 Advanced Micro Devices, Inc.
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+*/
+
+#include <arch/pirq_routing.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include "../../../southbridge/amd/cs5536/cs5536.h"
+
+/* Platform IRQs */
+#define PIRQA 11
+#define PIRQB 10
+#define PIRQC 11
+#define PIRQD 9
+
+/* Map */
+#define M_PIRQA (1 << PIRQA)	/* Bitmap of supported IRQs */
+#define M_PIRQB (1 << PIRQB)	/* Bitmap of supported IRQs */
+#define M_PIRQC (1 << PIRQC)	/* Bitmap of supported IRQs */
+#define M_PIRQD (1 << PIRQD)	/* Bitmap of supported IRQs */
+
+/* Link */
+#define L_PIRQA 1		/* Means Slot INTx# Connects To Chipset INTA# */
+#define L_PIRQB 2		/* Means Slot INTx# Connects To Chipset INTB# */
+#define L_PIRQC 3		/* Means Slot INTx# Connects To Chipset INTC# */
+#define L_PIRQD 4		/* Means Slot INTx# Connects To Chipset INTD# */
+
+/*
+ * ALIX.2D3 interrupt wiring.
+ *
+ * Devices are:
+ * 00:01.0 Host bridge [0600]: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge [1022:2080] (rev 33)
+ * 00:01.2 Entertainment encryption device [1010]: Advanced Micro Devices [AMD] Geode LX AES Security Block [1022:2082]
+ * 00:09.0 Ethernet controller [0200]: VIA Technologies, Inc. VT6105M [Rhine-III] [1106:3053] (rev 96)
+ * 00:0a.0 Ethernet controller [0200]: VIA Technologies, Inc. VT6105M [Rhine-III] [1106:3053] (rev 96)
+ * 00:0b.0 Ethernet controller [0200]: VIA Technologies, Inc. VT6105M [Rhine-III] [1106:3053] (rev 96)
+ * 00:0f.0 ISA bridge [0601]: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA [1022:2090] (rev 03)
+ * 00:0f.2 IDE interface [0101]: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE [1022:209a] (rev 01)
+ * 00:0f.4 USB Controller [0c03]: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC [1022:2094] (rev 02)
+ * 00:0f.5 USB Controller [0c03]: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC [1022:2095] (rev 02)
+
+  * The only devices that interrupt are:
+ *
+ * What         Device  IRQ     PIN     PIN WIRED TO
+ * -------------------------------------------------
+ * AES          00:01.2 0a      01      A       A
+ * eth0         00:09.0 0b      01      A       B
+ * eth1         00:0a.0 0b      01      A       C
+ * eth2         00:0b.0 0b      01      A       D
+ * mpci         00:0c.0 0a      01      A       A
+ * mpci         00:0c.0 0b      02      B       B
+ * usb          00:0f.4 0b      04      D       D
+ * usb          00:0f.5 0b      04      D       D
+ *
+ * The only swizzled interrupts are the ethernet controllers, where INTA is wired to
+ * interrupt controller lines B, C and D.
+ */
+
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,
+	PIRQ_VERSION,
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+	0x00,			/* Where the interrupt router lies (bus) */
+	(0x0F << 3) | 0x0,      /* Where the interrupt router lies (dev) */
+	0x00,			/* IRQs devoted exclusively to PCI usage */
+	0x100B,			/* Vendor */
+	0x002B,			/* Device */
+	0,			/* Crap (miniport) */
+	{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},	/* u8 rfu[11] */
+	0x00,			/* Checksum */
+	{
+		/* If you change the number of entries, change CONFIG_IRQ_SLOT_COUNT above! */
+
+		/* bus, dev|fn,           {link, bitmap},      {link, bitmap},     {link, bitmap},     {link, bitmap},     slot, rfu */
+
+		/* CPU */
+		{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
+
+		/* On-board ethernet (Left) */
+		{0x00, (0x09 << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
+
+		/* On-board ethernet (Middle) */
+		{0x00, (0x0A << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
+
+		/* On-board ethernet (Right) */
+		{0x00, (0x0B << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
+
+		/* Mini PCI (slot 1) */
+		{0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
+
+		/* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D. */
+		{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},
+	}
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	return copy_pirq_routing_table(addr);
+}
diff --git a/src/mainboard/pcengines/alix2d3/mainboard.c b/src/mainboard/pcengines/alix2d3/mainboard.c
new file mode 100644
index 0000000000..416e3b1264
--- /dev/null
+++ b/src/mainboard/pcengines/alix2d3/mainboard.c
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include "chip.h"
+
+static void init(struct device *dev)
+{
+	printk(BIOS_DEBUG, "ALIX.2D3 ENTER %s\n", __func__);
+	printk(BIOS_DEBUG, "ALIX.2D3 EXIT %s\n", __func__);
+}
+
+static void enable_dev(struct device *dev)
+{
+	dev->ops->init = init;
+}
+
+struct chip_operations mainboard_ops = {
+	CHIP_NAME("PC Engines ALIX.2D3 Mainboard")
+	.enable_dev = enable_dev,
+};
+
diff --git a/src/mainboard/pcengines/alix2d3/romstage.c b/src/mainboard/pcengines/alix2d3/romstage.c
new file mode 100644
index 0000000000..3c2480abd2
--- /dev/null
+++ b/src/mainboard/pcengines/alix2d3/romstage.c
@@ -0,0 +1,219 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <spd.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <arch/hlt.h>
+#include <console/console.h>
+#include "lib/ramtest.c"
+#include "cpu/x86/bist.h"
+#include "cpu/x86/msr.h"
+#include <cpu/amd/lxdef.h>
+#include <cpu/amd/geode_post_code.h>
+#include "southbridge/amd/cs5536/cs5536.h"
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
+/* The ALIX.2D3 has no SMBus; the setup is hard-wired. */
+static void cs5536_enable_smbus(void)
+{
+}
+
+#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+
+/* The part is a Hynix hy5du121622ctp-d43.
+ *
+ * HY 5D U 12 16 2 2 C <blank> T <blank> P D43
+ * Hynix
+ * DDR SDRAM (5D)
+ * VDD 2.5 VDDQ 2.5 (U)
+ * 512M 8K REFRESH (12)
+ * x16 (16)
+ * 4banks (2)
+ * SSTL_2 (2)
+ * 4th GEN die (C)
+ * Normal Power Consumption (<blank> )
+ * TSOP (T)
+ * Single Die (<blank>)
+ * Lead Free (P)
+ * DDR400 3-3-3 (D43)
+ */
+/* SPD array */
+static const u8 spdbytes[] = {
+	[SPD_ACCEPTABLE_CAS_LATENCIES] = 0x10,
+	[SPD_BANK_DENSITY] = 0x40,
+	[SPD_DEVICE_ATTRIBUTES_GENERAL] = 0xff,
+	[SPD_MEMORY_TYPE] = 7,
+	[SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 10, /* A guess for the tRAC value */
+	[SPD_MODULE_ATTRIBUTES] = 0xff, /* FIXME later when we figure out. */
+	[SPD_NUM_BANKS_PER_SDRAM] = 4,
+	[SPD_PRIMARY_SDRAM_WIDTH] = 8,
+	[SPD_NUM_DIMM_BANKS] = 1, /* ALIX1.C is 1 bank. */
+	[SPD_NUM_COLUMNS] = 0xa,
+	[SPD_NUM_ROWS] = 3,
+	[SPD_REFRESH] = 0x3a,
+	[SPD_SDRAM_CYCLE_TIME_2ND] = 60,
+	[SPD_SDRAM_CYCLE_TIME_3RD] = 75,
+	[SPD_tRAS] = 40,
+	[SPD_tRCD] = 15,
+	[SPD_tRFC] = 70,
+	[SPD_tRP] = 15,
+	[SPD_tRRD] = 10,
+};
+
+static u8 spd_read_byte(u8 device, u8 address)
+{
+	print_debug("spd_read_byte dev ");
+	print_debug_hex8(device);
+
+	if (device != (0x50 << 1)) {
+		print_debug(" returns 0xff\n");
+		return 0xff;
+	}
+
+	print_debug(" addr ");
+	print_debug_hex8(address);
+	print_debug(" returns ");
+	print_debug_hex8(spdbytes[address]);
+	print_debug("\n");
+
+	return spdbytes[address];
+}
+
+#define ManualConf	0		/* Do automatic strapped PLL config */
+#define PLLMSRhi	0x00001490	/* Manual settings for the PLL */
+#define PLLMSRlo	0x02000030
+
+#define DIMM0		0xa0
+#define DIMM1		0xa2
+
+#include "northbridge/amd/lx/raminit.h"
+#include "northbridge/amd/lx/pll_reset.c"
+#include "northbridge/amd/lx/raminit.c"
+#include "lib/generic_sdram.c"
+#include "cpu/amd/model_lx/cpureginit.c"
+#include "cpu/amd/model_lx/syspreinit.c"
+#include "cpu/amd/model_lx/msrinit.c"
+
+/** Early mainboard specific GPIO setup. */
+static void mb_gpio_init(void)
+{
+	/*
+	 * Disable power button, since it is hardwired to ground on this board,
+	 * and the power would be cut off atfer a 4-second delay otherwise.
+	 */
+	outl(0x00020000, PMS_IO_BASE + 0x40);
+
+	/*
+	 * Enable LEDs GPIO outputs to light up the leds
+	 * This is how the original tinyBIOS sets them after boot.
+	 * Info: GPIO_IO_BASE, 0x6100, is only valid before PCI init, so it
+	 *       may be used here, but not after PCI Init.
+	 * Note: Prior to a certain release, Linux used a hardwired 0x6100 in the
+	 *       leds-alix2.c driver. Coreboot dynamically assigns this space,
+	 *       so the driver does not work anymore.
+	 *       Good workaround: use the newer driver
+	 *       Ugly workaround: $ wrmsr 0x5140000C 0xf00100006100
+	 *         This resets the GPIO I/O space to 0x6100.
+	 *         This may break other things, though.
+     */
+	outl(1 << 6, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);
+	outl(1 << 9, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
+	outl(1 << 11, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
+
+	/* outl(1 << 6, GPIO_IO_BASE + GPIOL_OUTPUT_VALUE); */  /* Led 1 enabled  */
+    outl(1 << 9, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE);        /* Led 2 disabled */
+	outl(1 << 11, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE);       /* Led 3 disabled */
+
+
+}
+
+void main(unsigned long bist)
+{
+	static const struct mem_controller memctrl[] = {
+		{.channel0 = {0x50}},
+	};
+
+	post_code(0x01);
+
+	SystemPreInit();
+	msr_init();
+
+	cs5536_early_setup();
+
+	/* NOTE: Must do this AFTER cs5536_early_setup()!
+	 * It is counting on some early MSR setup for the CS5536.
+	 */
+	cs5536_setup_onchipuart(1);
+	mb_gpio_init();
+	uart_init();
+	console_init();
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+	pll_reset(ManualConf);
+
+	cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
+
+	sdram_initialize(1, memctrl);
+
+	/* Check memory */
+	/* Enable this only if you are having questions. */
+	/* ram_check(0, 640 * 1024); */
+
+	/* Switch from Cache as RAM to real RAM.
+	 *
+	 * There are two ways we could think about this.
+	 *
+	 * 1. If we are using the romstage.inc ROMCC way, the stack is
+	 * going to be re-setup in the code following this code.  Just
+	 * wbinvd the stack to clear the cache tags.  We don't care
+	 * where the stack used to be.
+	 *
+	 * 2. This file is built as a normal .c -> .o and linked in
+	 * etc.  The stack might be used to return etc.  That means we
+	 * care about what is in the stack.  If we are smart we set
+	 * the CAR stack to the same location as the rest of
+	 * coreboot. If that is the case we can just do a wbinvd.
+	 * The stack will be written into real RAM that is now setup
+	 * and we continue like nothing happened.  If the stack is
+	 * located somewhere other than where LB would like it, you
+	 * need to write some code to do a copy from cache to RAM
+	 *
+	 * We use method 1 on Norwich and on this board too.
+	 */
+	post_code(0x02);
+	print_err("POST 02\n");
+	__asm__("wbinvd\n");
+	print_err("Past wbinvd\n");
+
+	/* We are finding the return does not work on this board. Explicitly
+	 * call the label that is after the call to us. This is gross, but
+	 * sometimes at this level it is the only way out.
+	 */
+	void done_cache_as_ram_main(void);
+	done_cache_as_ram_main();
+}
+
diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c
index d2197a7583..7240898695 100644
--- a/src/northbridge/amd/lx/raminit.c
+++ b/src/northbridge/amd/lx/raminit.c
@@ -739,7 +739,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	msr.lo |= (209 << 8);	/* bits[15:8] = 209 */
 	wrmsr(msrnum, msr);
 
-	print_emerg("DRAM controller init done.\n");
+	banner("DRAM controller init done.\n");
 	post_code(POST_MEM_SETUP_GOOD);	//0x7E
 
 	/* make sure there is nothing stale in the cache */