diff options
| author | Marc Jones <marcj303@gmail.com> | 2018-07-26 17:07:13 -0600 |
|---|---|---|
| committer | Marc Jones <marc@marcjonesconsulting.com> | 2018-07-27 20:12:58 +0000 |
| commit | 6dcb6c2fa400495df97aa2e95a1897cd4b05a1a8 (patch) | |
| tree | ce00988a9e4bca776db6fc440ff424f41a370ef6 /src | |
| parent | bd21f2844bdb3580a7107e0eb46333a3105e25a3 (diff) | |
soc/amd/stoneyridge: Add IGFX device ACPI ASL entry
Add internal graphics device 00.01.00 to the ACPI tables so that the
ACPI PCI option ROM save functions have a proper scope to save the
ROM to.
BUG=b:111697181
TEST=Check coreboot log doesn't have "PCI: 00:01.0: Missing ACPI scope"
and check _ROM method is added in the SSDT1.
Change-Id: I2c9ef8d9dff76805b1fcde2ccceef958a5b53b4f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/27653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/amd/stoneyridge/acpi/northbridge.asl | 5 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/chip.c | 2 |
2 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/acpi/northbridge.asl b/src/soc/amd/stoneyridge/acpi/northbridge.asl index 4df6567e2c..fe78534403 100644 --- a/src/soc/amd/stoneyridge/acpi/northbridge.asl +++ b/src/soc/amd/stoneyridge/acpi/northbridge.asl @@ -46,6 +46,11 @@ Device(AMRT) { Name(_ADR, 0x00000000) } /* end AMRT */ +/* Internal Graphics */ +Device(IGFX) { + Name(_ADR, 0x00010000) +} + /* Gpp 0 */ Device(PBR4) { Name(_ADR, 0x00020001) diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 9ca2db7e85..33c17308c8 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -82,6 +82,8 @@ const char *soc_acpi_name(const struct device *dev) return NULL; switch (dev->path.pci.devfn) { + case GFX_DEVFN: + return "IGFX"; case PCIE0_DEVFN: return "PBR4"; case PCIE1_DEVFN: |