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authorMarshall Dawson <marshalldawson3rd@gmail.com>2016-10-08 09:53:58 -0600
committerMartin Roth <martinroth@google.com>2016-12-16 23:02:08 +0100
commit4bbea904170196b4cc59031a8ada7901def934fb (patch)
tree3c70cbf4e6fe848b5c7f62680cdb2211ac404664 /src
parent91135fef22262b1789abeb1a23efc43460cffa3d (diff)
amd/gardenia: Correct SPD AGESA callout
Gardenia makes no special considerations for a board_id regarding SPD access and addressing. Remove this from the source and use the standard AGESA call. Make SPD address changes to devicetree.cb. Note that Gardenia is designed to be a two channel, single DIMM/channel system (some SKUs with two DIMMs on the second channel). However, this port is for the Stoney processor which is a single channel. As a result, the second DIMM slot is not usable. A future improvement could involve a port using a different processor, with unique devicetree files for each. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 77511f98f819dfe08c3ed16ebc11e1b328bdca15) Change-Id: Id00c2be83340ceeec043ec86e96779e6bf46ae7b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17219 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/amd/gardenia/BiosCallOuts.c46
-rw-r--r--src/mainboard/amd/gardenia/devicetree.cb7
2 files changed, 5 insertions, 48 deletions
diff --git a/src/mainboard/amd/gardenia/BiosCallOuts.c b/src/mainboard/amd/gardenia/BiosCallOuts.c
index 380c3f41de..44644ce069 100644
--- a/src/mainboard/amd/gardenia/BiosCallOuts.c
+++ b/src/mainboard/amd/gardenia/BiosCallOuts.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
+ * Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -35,14 +35,13 @@
#include <boardid.h>
static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr);
-static AGESA_STATUS board_ReadSpd(UINT32 Func, UINTN Data, VOID *ConfigPtr);
const BIOS_CALLOUT_STRUCT BiosCallouts[] =
{
{AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer },
{AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer },
{AGESA_LOCATE_BUFFER, agesa_LocateBuffer },
- {AGESA_READ_SPD, board_ReadSpd },
+ {AGESA_READ_SPD, agesa_ReadSpd },
{AGESA_DO_RESET, agesa_Reset },
{AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
{AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
@@ -104,43 +103,6 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
return AGESA_SUCCESS;
}
-static AGESA_STATUS board_ReadSpd(UINT32 Func, UINTN Data, VOID *ConfigPtr)
-{
-#ifdef __PRE_RAM__
- int spdAddress;
- AGESA_READ_SPD_PARAMS *info = ConfigPtr;
-
- ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
- ROMSTAGE_CONST struct northbridge_amd_pi_00670F00_config *config = dev->chip_info;
- UINT8 spdAddrLookup_rev_F [2][2][4]= {
- { {0xA0, 0xA2}, {0xA4, 0xAC}, }, /* socket 0 - Channel 0 & 1 - 8-bit SPD addresses */
- { {0x00, 0x00}, {0x00, 0x00}, }, /* socket 1 - Channel 0 & 1 - 8-bit SPD addresses */
- };
-
- if ((dev == 0) || (config == 0))
- return AGESA_ERROR;
- if (info->SocketId >= ARRAY_SIZE(config->spdAddrLookup))
- return AGESA_ERROR;
- if (info->MemChannelId >= ARRAY_SIZE(config->spdAddrLookup[0]))
- return AGESA_ERROR;
- if (info->DimmId >= ARRAY_SIZE(config->spdAddrLookup[0][0]))
- return AGESA_ERROR;
- if (board_id() == 'F')
- spdAddress = spdAddrLookup_rev_F
- [info->SocketId] [info->MemChannelId] [info->DimmId];
- else
- spdAddress = config->spdAddrLookup
- [info->SocketId] [info->MemChannelId] [info->DimmId];
-
- if (spdAddress == 0)
- return AGESA_ERROR;
- int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 128);
- if (err)
- return AGESA_ERROR;
-#endif
- return AGESA_SUCCESS;
-}
-
#ifdef __PRE_RAM__
const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
@@ -157,8 +119,6 @@ const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
void OemPostParams(AMD_POST_PARAMS *PostParams)
{
- if (board_id() == 'F') {
- PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR4PlatformMemoryConfiguration;
- }
+ PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR4PlatformMemoryConfiguration;
}
#endif
diff --git a/src/mainboard/amd/gardenia/devicetree.cb b/src/mainboard/amd/gardenia/devicetree.cb
index 946aae99e3..a7573b1b1a 100644
--- a/src/mainboard/amd/gardenia/devicetree.cb
+++ b/src/mainboard/amd/gardenia/devicetree.cb
@@ -1,7 +1,7 @@
#
# This file is part of the coreboot project.
#
-# Copyright (C) 2015 Advanced Micro Devices, Inc.
+# Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
@@ -42,10 +42,7 @@ chip northbridge/amd/pi/00670F00/root_complex
device pci 11.0 on end # SATA
device pci 12.0 on end # EHCI
device pci 14.0 on # SM
- chip drivers/generic/generic #dimm 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic #dimm 0-0-1
+ chip drivers/generic/generic # dimm 0-0-0
device i2c 51 on end
end
end # SM