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authorEric Biederman <ebiederm@xmission.com>2003-07-17 03:26:03 +0000
committerEric Biederman <ebiederm@xmission.com>2003-07-17 03:26:03 +0000
commit4086d16ba216955d6124d99c9aae7ceeb2457a71 (patch)
treef31ec9105e99df6cc78064ac6218ba3e96146cce /src
parent5fb929e6e399ecf41aec9c6053a0340671534a63 (diff)
- Implement an enable method for pci devices.
- Add initial support for the amd8131 - Update the mptable to something possible - hdama/Config add the amd8131 southbridge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@968 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r--src/devices/pci_device.c36
-rw-r--r--src/include/device/device.h4
-rw-r--r--src/mainboard/arima/hdama/mptable.c36
-rw-r--r--src/southbridge/amd/amd8131/amd8131_bridge.c54
4 files changed, 93 insertions, 37 deletions
diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c
index 25c39f8f9a..d9ce9c5eb1 100644
--- a/src/devices/pci_device.c
+++ b/src/devices/pci_device.c
@@ -572,23 +572,18 @@ unsigned int pci_scan_bus(struct device *bus, unsigned int max)
continue;
}
memset(dev, 0, sizeof(*dev));
+ dev->bus = bus;
+ dev->devfn = devfn;
+ dev->vendor = id & 0xffff;
+ dev->device = (id >> 16) & 0xffff;
+ dev->hdr_type = hdr_type;
+ /* class code, the upper 3 bytes of PCI_CLASS_REVISION */
+ dev->class = class >> 8;
+
+ /* If we don't have prior information about this device enable it */
+ dev->enable = 1;
}
- dev->bus = bus;
- dev->devfn = devfn;
- dev->vendor = id & 0xffff;
- dev->device = (id >> 16) & 0xffff;
- dev->hdr_type = hdr_type;
- /* class code, the upper 3 bytes of PCI_CLASS_REVISION */
- dev->class = class >> 8;
-
- /* non-destructively determine if device can be a master: */
- cmd = pci_read_config8(dev, PCI_COMMAND);
- pci_write_config8(dev, PCI_COMMAND, cmd | PCI_COMMAND_MASTER);
- tmp = pci_read_config8(dev, PCI_COMMAND);
-
- dev->master = ((tmp & PCI_COMMAND_MASTER) != 0);
- pci_write_config8(dev, PCI_COMMAND, cmd);
/* Look at the vendor and device id, or at least the
* header type and class and figure out which set of configuration
@@ -600,9 +595,16 @@ unsigned int pci_scan_bus(struct device *bus, unsigned int max)
free(dev);
continue;
}
- printk_debug("PCI: %02x:%02x.%01x [%04x/%04x]\n",
+
+ /* Now run the magic enable/disable sequence for the device */
+ if (dev->ops && dev->ops->enable) {
+ dev->ops->enable(dev);
+ }
+
+ printk_debug("PCI: %02x:%02x.%01x [%04x/%04x] %s\n",
bus->secondary, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
- dev->vendor, dev->device);
+ dev->vendor, dev->device,
+ dev->enable?"enabled": "disabled");
/* Put it into the global device chain. */
append_device(dev);
diff --git a/src/include/device/device.h b/src/include/device/device.h
index def9f539ab..4ad776ffc9 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -11,6 +11,7 @@ struct device_operations {
void (*set_resources)(device_t dev);
void (*init)(device_t dev);
unsigned int (*scan_bus)(device_t bus, unsigned int max);
+ void (*enable)(device_t dev);
};
@@ -31,7 +32,7 @@ struct device {
unsigned short device;
unsigned int class; /* 3 bytes: (base,sub,prog-if) */
unsigned int hdr_type; /* PCI header type */
- unsigned int master : 1; /* set if device is master capable */
+ unsigned int enable : 1; /* set if we should enable the device */
unsigned char secondary; /* secondary bus number */
unsigned char subordinate; /* max subordinate bus number */
@@ -56,7 +57,6 @@ struct device {
unsigned int resources;
unsigned long rom_address;
struct device_operations *ops;
-
};
extern struct device dev_root; /* root bus */
diff --git a/src/mainboard/arima/hdama/mptable.c b/src/mainboard/arima/hdama/mptable.c
index faf0711b17..ef1037993f 100644
--- a/src/mainboard/arima/hdama/mptable.c
+++ b/src/mainboard/arima/hdama/mptable.c
@@ -150,43 +150,43 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
/* PCI Slot 1 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (1<<2)|0, 0x04, 0x11);
+ bus_8131_2, (1<<2)|0, 0x04, 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (1<<2)|1, 0x04, 0x12);
+ bus_8131_2, (1<<2)|1, 0x04, 0x2);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (1<<2)|2, 0x04, 0x13);
+ bus_8131_2, (1<<2)|2, 0x04, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (1<<2)|3, 0x04, 0x10);
+ bus_8131_2, (1<<2)|3, 0x04, 0x0);
/* PCI Slot 2 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (2<<2)|0, 0x04, 0x12);
+ bus_8131_2, (2<<2)|0, 0x04, 0x2);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (2<<2)|1, 0x04, 0x13);
+ bus_8131_2, (2<<2)|1, 0x04, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (2<<2)|2, 0x04, 0x10);
+ bus_8131_2, (2<<2)|2, 0x04, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (2<<2)|3, 0x04, 0x11);
+ bus_8131_2, (2<<2)|3, 0x04, 0x1);
/* PCI Slot 3 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (1<<2)|0, 0x03, 0x11);
+ bus_8131_1, (1<<2)|0, 0x03, 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (1<<2)|1, 0x03, 0x12);
+ bus_8131_1, (1<<2)|1, 0x03, 0x2);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (1<<2)|2, 0x03, 0x13);
+ bus_8131_1, (1<<2)|2, 0x03, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (1<<2)|3, 0x03, 0x10);
+ bus_8131_1, (1<<2)|3, 0x03, 0x0);
/* PCI Slot 4 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (2<<2)|0, 0x03, 0x12);
+ bus_8131_1, (2<<2)|0, 0x03, 0x2);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (2<<2)|1, 0x03, 0x13);
+ bus_8131_1, (2<<2)|1, 0x03, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (2<<2)|2, 0x03, 0x10);
+ bus_8131_1, (2<<2)|2, 0x03, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (2<<2)|3, 0x03, 0x11);
+ bus_8131_1, (2<<2)|3, 0x03, 0x1);
/* PCI Slot 5 */
#warning "FIXME get the irqs right, it's just hacked to work for now"
@@ -212,9 +212,9 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
/* On board nics */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (3<<2)|0, 0x03, 0x13);
+ bus_8131_1, (3<<2)|0, 0x03, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (4<<2)|0, 0x03, 0x10);
+ bus_8131_1, (4<<2)|0, 0x03, 0x0);
/* There is no extension information... */
diff --git a/src/southbridge/amd/amd8131/amd8131_bridge.c b/src/southbridge/amd/amd8131/amd8131_bridge.c
new file mode 100644
index 0000000000..9ef83da50d
--- /dev/null
+++ b/src/southbridge/amd/amd8131/amd8131_bridge.c
@@ -0,0 +1,54 @@
+/*
+ * (C) 2003 Linux Networx
+ */
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+
+static void pcix_init(device_t dev)
+{
+ return;
+}
+
+static struct device_operations pcix_ops = {
+ .read_resources = pci_bus_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .init = pcix_init,
+ .scan_bus = pci_scan_bridge,
+};
+
+static struct pci_driver pcix_driver __pci_driver = {
+ .ops = &pcix_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = 0x7450,
+};
+
+
+static void ioapic_enable(device_t dev)
+{
+ uint32_t value;
+ value = pci_read_config32(dev, 0x44);
+ if (dev->enable) {
+ value |= ((1 << 1) | (1 << 0));
+ } else {
+ value &= ~((1 << 1) | (1 << 0));
+ }
+ pci_write_config32(dev, 0x44, value);
+}
+
+static struct device_operations ioapic_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .init = 0,
+ .scan_bus = 0,
+ .enable = ioapic_enable,
+};
+
+static struct pci_driver ioapic_driver __pci_driver = {
+ .ops = &ioapic_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = 0x7451,
+
+};