gizmosphere/gizmo2: Switch away from ROMCC_BOOTBLOCK

Warning: Not tested on hardware.

Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: Iad86755952204bb1a56ef341e626b0627a958467
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38868
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

5 files changed, 35 insertions, 40 deletions

diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig b/src/mainboard/gizmosphere/gizmo2/Kconfig
index 685e27190a..47a39b694b 100644
--- a/src/mainboard/gizmosphere/gizmo2/Kconfig
+++ b/src/mainboard/gizmosphere/gizmo2/Kconfig
@@ -14,14 +14,10 @@
 # GNU General Public License for more details.
 #
 
-config BOARD_GIZMOSPHERE_GIZMO2
-	def_bool n
-
 if BOARD_GIZMOSPHERE_GIZMO2
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	#select ROMCC_BOOTBLOCK
 	select CPU_AMD_AGESA_FAMILY16_KB
 	select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
 	select SOUTHBRIDGE_AMD_AGESA_YANGTZE
diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig.name b/src/mainboard/gizmosphere/gizmo2/Kconfig.name
index 29688e2a34..a3bae57b28 100644
--- a/src/mainboard/gizmosphere/gizmo2/Kconfig.name
+++ b/src/mainboard/gizmosphere/gizmo2/Kconfig.name
@@ -1,2 +1,2 @@
-#config BOARD_GIZMOSPHERE_GIZMO2
-#	bool"Gizmo2"
+config BOARD_GIZMOSPHERE_GIZMO2
+	bool "Gizmo2"
diff --git a/src/mainboard/gizmosphere/gizmo2/Makefile.inc b/src/mainboard/gizmosphere/gizmo2/Makefile.inc
index 8a24bea452..2a7d26bd6b 100644
--- a/src/mainboard/gizmosphere/gizmo2/Makefile.inc
+++ b/src/mainboard/gizmosphere/gizmo2/Makefile.inc
@@ -14,6 +14,8 @@
 # GNU General Public License for more details.
 #
 
+bootblock-y += bootblock.c
+
 romstage-y += buildOpts.c
 romstage-y += BiosCallOuts.c
 romstage-y += OemCustomize.c
diff --git a/src/mainboard/gizmosphere/gizmo2/bootblock.c b/src/mainboard/gizmosphere/gizmo2/bootblock.c
new file mode 100644
index 0000000000..312b5cc0a6
--- /dev/null
+++ b/src/mainboard/gizmosphere/gizmo2/bootblock.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <amdblocks/acpimmio.h>
+#include <bootblock_common.h>
+
+void bootblock_mainboard_early_init(void)
+{
+#if 0
+	volatile u32 i, val;
+
+	/* LPC clock? Should happen before enable_serial. */
+
+	/*
+	* On Larne, after LpcClkDrvSth is set, it needs some time to be stable,
+	* because of the buffer ICS551M
+	*/
+	for (i = 0; i < 200000; i++)
+		val = inb(0xcd6);
+#endif
+}
diff --git a/src/mainboard/gizmosphere/gizmo2/romstage.c b/src/mainboard/gizmosphere/gizmo2/romstage.c
deleted file mode 100644
index 6312270712..0000000000
--- a/src/mainboard/gizmosphere/gizmo2/romstage.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <amdblocks/acpimmio.h>
-#include <arch/io.h>
-#include <device/pci_ops.h>
-#include <northbridge/amd/agesa/state_machine.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
-
-void board_BeforeAgesa(struct sysinfo *cb)
-{
-	/* For serial port option, plug-in card on LPC. */
-	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
-	pci_write_config32(dev, 0x44, 0xff03ffd5);
-
-	/* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
-	 *  LpcClk[1:0]".  To be consistent with Parmer, setting to 4mA
-	 *  even though the register is not documented in the Kabini BKDG.
-	 *  Otherwise the serial output is bad code.
-	 */
-	pm_io_write8(0xd2, 0);
-}