diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-08-10 13:02:20 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-08-12 10:54:06 +0000 |
| commit | 0b3512b495528adfe29fe7d9267a59361a6f01cd (patch) | |
| tree | da2eab9c29252746a0bd7b7089a03480fbf75d62 /src | |
| parent | 1d68d6d14d4c9f6e414845335bb6a8493a6d5d62 (diff) | |
sb/intel: Remove inexistent references to IDE controller
This device doesn't exist on these southbridges.
Change-Id: Ie17427ba044c465adf95300ff7f5610c25ae3373
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 3 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/pch.h | 3 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pch.h | 3 |
3 files changed, 3 insertions, 6 deletions
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index b7842c085f..75529065f8 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -155,8 +155,7 @@ void early_usb_init(const struct southbridge_usb_port *portmap); #define LGMR 0x98 /* LPC Generic Memory Range */ #define BIOS_DEC_EN1 0xd8 /* BIOS Decode Enable */ -/* PCI Configuration Space (D31:F1): IDE */ -#define PCH_IDE_DEV PCI_DEV(0, 0x1f, 1) +/* PCI Configuration Space (D31:F2): SATA */ #define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2) #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 7c2e2a9f7d..76d0ad6efb 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -148,8 +148,7 @@ void pch_enable(struct device *dev); #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ -/* PCI Configuration Space (D31:F1): IDE */ -#define PCH_IDE_DEV PCI_DEV(0, 0x1f, 1) +/* PCI Configuration Space (D31:F2): SATA */ #define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2) #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) #define INTR_LN 0x3c diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 99469448d7..893bfde457 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -212,8 +212,7 @@ void mainboard_config_rcba(void); #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ #define LGMR 0x98 /* LPC Generic Memory Range */ -/* PCI Configuration Space (D31:F1): IDE */ -#define PCH_IDE_DEV PCI_DEV(0, 0x1f, 1) +/* PCI Configuration Space (D31:F2): SATA */ #define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2) #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) #define INTR_LN 0x3c |