mainboard/google/poppy/variants/atlas: config ISH in mainboard side

To enable ISH device on atlas board, change "device pci 13.0 off end" to
"device pci 13.0 on end" in file
mainboard/google/poppy/variants/atlas/devicetree.cb. "IshEnable" is
not needed.

Config atlas board specific ISH setting in devicetree.cb.
Dynamically load gpio setting for ISH enabled/disabled cases.

BUG=b:79244403
BRANCH=none
TEST=Verified on Atlas board with ISH rework. ISH log showed on console.

Change-Id: I8269a85cd2ab7917bfc0e7d63d988e0e678d0bf2
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://review.coreboot.org/26486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

2 files changed, 50 insertions, 9 deletions

diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
index 34bc4d45b7..f58ba8feee 100644
--- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
@@ -45,7 +45,6 @@ chip soc/intel/skylake
 	register "ScsEmmcEnabled" = "1"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "ScsSdCardEnabled" = "0"
-	register "IshEnable" = "0"		# FIXME: enable once ISH is ready
 	register "PttSwitch" = "0"
 	register "InternalGfx" = "1"
 	register "SkipExtGfxScan" = "1"
@@ -255,6 +254,7 @@ chip soc/intel/skylake
 	device domain 0 on
 		device pci 00.0 on  end # Host Bridge
 		device pci 02.0 on  end # Integrated Graphics Device
+		device pci 13.0 off end # Integrated Sensor Hub
 		device pci 14.0 on  end # USB xHCI
 		device pci 14.1 on  end # USB xDCI (OTG)
 		device pci 14.2 on  end # Thermal Subsystem
diff --git a/src/mainboard/google/poppy/variants/atlas/gpio.c b/src/mainboard/google/poppy/variants/atlas/gpio.c
index d99a0e4d82..51dbf69f54 100644
--- a/src/mainboard/google/poppy/variants/atlas/gpio.c
+++ b/src/mainboard/google/poppy/variants/atlas/gpio.c
@@ -16,6 +16,8 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
+#include <device/device.h>
+#include <soc/pci_devs.h>
 
 /* Pad configuration in ramstage */
 /* Leave eSPI pins untouched from default settings */
@@ -51,10 +53,6 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NC(GPP_A17),
 	/* A18 : ISH_GP0 ==> ISH_GP0 */
 	PAD_CFG_NC(GPP_A18),
-	/* A19 : ISH_GP1 ==> TRACKPAD_INT_L */
-	PAD_CFG_GPI_APIC(GPP_A19, NONE, PLTRST),
-	/* A20 : ISH_GP2 ==> ISH_UART0_RXD */
-	PAD_CFG_NC(GPP_A20),
 	/* A21 : ISH_GP3 */
 	PAD_CFG_NC(GPP_A21),
 	/* A22 : ISH_GP4 */
@@ -186,10 +184,6 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF_1V8(GPP_D11, NONE, DEEP, NF1),
 	/* D12 : ISH_SPI_MOSI ==> ISH_SPI_MOSI */
 	PAD_CFG_NF_1V8(GPP_D12, NONE, DEEP, NF1),
-	/* D13 : ISH_UART0_RXD ==> ISH_UART0_RXD */
-	PAD_CFG_NF_1V8(GPP_D13, NONE, DEEP, NF1),
-	/* D14 : ISH_UART0_TXD ==> ISH_UART0_TXD */
-	PAD_CFG_NF_1V8(GPP_D14, NONE, DEEP, NF1),
 	/* D15 : ISH_UART0_RTS# ==> NC */
 	PAD_CFG_NC(GPP_D15),
 	/* D16 : ISH_UART0_CTS# ==> NC */
@@ -388,3 +382,50 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
 	*num = ARRAY_SIZE(early_gpio_table);
 	return early_gpio_table;
 }
+
+static const struct pad_config ish_enabled_gpio_table[] = {
+	/* A19 : ISH_GP1 ==> TRACKPAD_INT_L
+	 * trackpad interrupt to ISH
+	 */
+	PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
+	/* A20 : ISH_GP2 ==> ISH_UART0_RXD
+	 * ISH_UART0_RXD signal goes to this ISH GPIO pin.
+	 * It is used as wake up source in ISH firmware.
+	 * Implementation is in ISH firmware also.
+	 */
+	PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
+
+	/* D13 : ISH_UART0_RXD ==> ISH_UART0_RXD */
+	PAD_CFG_NF_1V8(GPP_D13, NONE, DEEP, NF1),
+	/* D14 : ISH_UART0_TXD ==> ISH_UART0_TXD */
+	PAD_CFG_NF_1V8(GPP_D14, NONE, DEEP, NF1),
+};
+
+
+static const struct pad_config ish_disabled_gpio_table[] = {
+	/* A19 : GPP_A19 ==> TRACKPAD_INT_L
+	 * trackpad interrupt to PCH
+	 */
+	PAD_CFG_GPI_APIC(GPP_A19, NONE, PLTRST),
+	/* A20 : ISH_GP2 ==> NC */
+	PAD_CFG_NC(GPP_A20),
+
+	/* D13 : ISH_UART0_RXD ==> NC */
+	PAD_CFG_NC(GPP_D13),
+	/* D14 : ISH_UART0_TXD ==> NC */
+	PAD_CFG_NC(GPP_D14),
+};
+
+const struct pad_config *variant_sku_gpio_table(size_t *num)
+{
+	const struct pad_config *board_gpio_tables;
+	const struct device *dev = dev_find_slot(0, PCH_DEVFN_ISH);
+	if (dev && dev->enabled) {
+		*num = ARRAY_SIZE(ish_enabled_gpio_table);
+		board_gpio_tables = ish_enabled_gpio_table;
+	} else {
+		*num = ARRAY_SIZE(ish_disabled_gpio_table);
+		board_gpio_tables = ish_disabled_gpio_table;
+	}
+	return board_gpio_tables;
+}