diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2015-08-17 16:27:09 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-08-27 14:19:22 +0000 |
| commit | 028bcaae32e8ca779d216dc61a9b3dd468ff4be2 (patch) | |
| tree | eea7f801d503d02709ac741e3f14e070268a4b3f /src | |
| parent | 56260850e8274d6088cbddca2e06a8735aa22995 (diff) | |
skylake: make PAD_CFG_GPI default to GPIO ownership
The prior implementation of PAD_CFG_GPI kept the pad
ownership as ACPI. The gpio driver in the kernel then
wouldn't allow one to export those GPIOs through sysfs
in /sys/class/gpio. Fix this by setting the ownership
to GPIO.
BUG=chrome-os-partner:44147
BRANCH=None
TEST=Built and boot glados. PCH_WP gpio is properly exported
by crossystem.
Original-Change-Id: I9fc7ab141a3fd74e0ff8b3ff5009b007b8a0d69b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294081
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Ifbb61c5d64bb6a04f140685c70f4681e2babecef
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11283
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/gpio.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h index 488a2b5653..4871c8c024 100644 --- a/src/soc/intel/skylake/include/soc/gpio.h +++ b/src/soc/intel/skylake/include/soc/gpio.h @@ -121,8 +121,9 @@ void gpio_configure_pads(const struct pad_config *cfgs, size_t num); /* General purpose input with no special IRQ routing. */ #define PAD_CFG_GPI(pad_, term_, rst_) \ - _PAD_CFG(pad_, term_, \ - _DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, GPIO, NO, YES)) + _PAD_CFG_ATTRS(pad_, term_, \ + _DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, GPIO, NO, YES),\ + PAD_FIELD(HOSTSW, GPIO)) /* General purpose input passed through to IOxAPIC. Assume APIC logic can * handle polarity/edge/level constraints. */ |