This is the final patch to enable the msm800sev to build. This patch

adds a symbol to the model_lx/cache_as_ram.inc, and modifies some
files in the mainboard directory. This patch has been tested but there
is a remaining problem which I am tracking down. Expect one more patch
to "get it all working".

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2638 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

5 files changed, 346 insertions, 118 deletions

diff --git a/src/cpu/amd/model_lx/cache_as_ram.inc b/src/cpu/amd/model_lx/cache_as_ram.inc
index fa90c5bf7f..5be87681be 100644
--- a/src/cpu/amd/model_lx/cache_as_ram.inc
+++ b/src/cpu/amd/model_lx/cache_as_ram.inc
@@ -177,6 +177,7 @@ DCacheSetupGood:
 
 	/* Go do early init and memory setup */
 	call	cache_as_ram_main
+done_cache_as_ram_main:
 
 	/* If you wanted to maintain the stack in memory you would need to set the tags as dirty
 	  so the wbinvd would push out the old stack contents to memory */
diff --git a/src/mainboard/digitallogic/msm800sev/Config.lb b/src/mainboard/digitallogic/msm800sev/Config.lb
index 3817dc5b52..6294701e4c 100644
--- a/src/mainboard/digitallogic/msm800sev/Config.lb
+++ b/src/mainboard/digitallogic/msm800sev/Config.lb
@@ -44,30 +44,21 @@ arch i386 end
 
 driver mainboard.o
 
-if HAVE_PIRQ_TABLE object irq_tables.o end
-#object reset.o
-
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ./romcc" 
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+if HAVE_PIRQ_TABLE
+	object irq_tables.o
 end
 
-makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ./romcc"
-	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+if USE_DCACHE_RAM
+	#compile cache_as_ram.c to auto.inc
+	makerule ./cache_as_ram_auto.inc
+			depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+			action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
+			action "perl -e 's/.rodata/.rom.data/g' -pi $@"
+			action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+	end
 end
 
-makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
-	action	"./romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	action	"./romcc    -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
+
 
 ##
 ## Build our 16 bit and 32 bit linuxBIOS entry code
@@ -104,7 +95,7 @@ ldscript /arch/i386/lib/id.lds
 ###
 if USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
+#	mainboardinit ./failover.inc
 end
 
 ###
@@ -115,7 +106,11 @@ end
 ## Setup RAM
 ##
 mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit ./auto.inc
+
+if USE_DCACHE_RAM
+	mainboardinit cpu/amd/model_lx/cache_as_ram.inc
+	mainboardinit ./cache_as_ram_auto.inc
+end
 
 ##
 ## Include the secondary Configuration files 
@@ -124,57 +119,88 @@ dir /pc80
 config chip.h
 
 chip northbridge/amd/lx
-	# they keep changing this. 0:f.0 5c.w to see where it is
-	register "irqmap" = "0xbaba"
-	register "setupflash" = "0"
-	device apic_cluster 0 on
-		chip cpu/amd/model_lx
-			device apic 0 on end
-		end
-	end
   	device pci_domain 0 on 
     		device pci 1.0 on end
 		device pci 1.1 on end
-      		chip southbridge/amd/cs5536_lx
-			register "isa_irq" = "0"
-			#register "flash_irq" = "14"
-
-			## IDE IRQ
-			register "enable_ide_irq" = "0"
-
-			register "audio_irq" = "5"
-			register "usb_irq" = "7"
-			
-			register "uart0_irq" = "0"
-			register "uart1_irq" = "4"
-
-			## PCI INTA ... INTD and their GPIO pins
-			##   int==0: disable 
-			register "pci_int[0]" = "0"
-			register "pci_int[1]" = "10"
-			register "pci_int[2]" = "0"
-			register "pci_int[3]" = "0"
-			register "pci_int_pin[0]" = "0"
-			register "pci_int_pin[1]" = "7"
-			register "pci_int_pin[2]" = "0"
-			register "pci_int_pin[3]" = "0"			
-
-
-			# Keyboard Emulation Logic IRQs
-			# Enable keyboard IRQ2
-			register "enable_kel_keyb_irq" = "0"
-			# Enable mouse IRQ12
-			register "enable_kel_mouse_irq" = "0"
-			# Configure KEL Emulation IRQ, 0 to disable
-			register "kel_emul_irq" = "0"
-
-        		device pci f.0 on end	# ISA Bridge
+      		chip southbridge/amd/cs5536
+			# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
+			# SIRQ Mode = Active(Quiet) mode. Save power....
+			# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
+			# How to get these? Boot linux and do this:
+			# rdmsr 0x51400025
+			register "lpc_serirq_enable" = "0x000010da"
+			# rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits
+			register "lpc_serirq_polarity" = "0x0000EF25"
+			# mode is high 10 bits (determined from code)
+			register "lpc_serirq_mode" = "1"
+			# Don't yet know how to find this.
+			register "enable_gpio_int_route" = "0x0D0C0700"
+			register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
+			register "enable_USBP4_device" = "0"	#0: host, 1:device
+			register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+			register "com1_enable" = "0"
+			register "com1_address" = "0x3F8"
+			register "com1_irq" = "4"
+			register "com2_enable" = "0"
+			register "com2_address" = "0x2F8"
+			register "com2_irq" = "3"
+			register "unwanted_vpci[0]" = "0"	# End of list has a zero
+        			device pci f.0 on	# ISA Bridge
+				chip superio/winbond/w83627hf
+					device pnp 2e.0 off #  Floppy
+						io 0x60 = 0x3f0
+						irq 0x70 = 6
+						drq 0x74 = 2
+					end
+					device pnp 2e.1 off #  Parallel Port
+						io 0x60 = 0x378
+						irq 0x70 = 7
+					end
+					device pnp 2e.2 on #  Com1
+						io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.3 on #  Com2
+						io 0x60 = 0x2f8
+						irq 0x70 = 3
+					end
+					device pnp 2e.5 on #  Keyboard
+						io 0x60 = 0x60
+						io 0x62 = 0x64
+						irq 0x70 = 1
+						irq 0x72 = 12
+					end
+					device pnp 2e.6 off #  CIR
+						io 0x60 = 0x100
+					end
+					device pnp 2e.7 off #  GAME_MIDI_GIPO1
+						io 0x60 = 0x220
+						io 0x62 = 0x300
+						irq 0x70 = 9
+					end						
+					device pnp 2e.8 off end #  GPIO2
+					device pnp 2e.9 off end #  GPIO3
+					device pnp 2e.a off end #  ACPI
+					device pnp 2e.b on #  HW Monitor
+						io 0x60 = 0x290
+						irq 0x70 = 5
+					end
+				end
+			end
 			device pci f.1 on end	# Flash controller
-			device pci f.2 off end	# IDE controller
-        		device pci f.3 on end 	# Audio
-        		device pci f.4 on end	# OHCI
+			device pci f.2 on end	# IDE controller
+        			device pci f.3 on end 	# Audio
+        			device pci f.4 on end	# OHCI
 			device pci f.5 on end	# EHCI
       		end
-    	end
+	end
+
+	# APIC cluster is late CPU init.
+	device apic_cluster 0 on
+		chip cpu/amd/model_lx
+			device apic 0 on end
+		end
+	end
+
 end
 
diff --git a/src/mainboard/digitallogic/msm800sev/Options.lb b/src/mainboard/digitallogic/msm800sev/Options.lb
index 4e73ccbfeb..8e2361b25a 100644
--- a/src/mainboard/digitallogic/msm800sev/Options.lb
+++ b/src/mainboard/digitallogic/msm800sev/Options.lb
@@ -21,7 +21,9 @@ uses ROM_IMAGE_SIZE
 uses ROM_SECTION_SIZE
 uses ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD_START
+uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
+uses CONFIG_PRECOMPRESSED_PAYLOAD
 uses PAYLOAD_SIZE
 uses _ROMBASE
 uses _RAMBASE
@@ -43,18 +45,20 @@ uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses CONFIG_VIDEO_MB
-
-default CONFIG_VIDEO_MB=8
-
+uses USE_DCACHE_RAM
+uses DCACHE_RAM_BASE
+uses DCACHE_RAM_SIZE
 
 ## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE  = 1024*1024
+default ROM_SIZE  = 256*1024
 
 ###
 ### Build options
 ###
-#default CONFIG_CONSOLE_VGA=1
-#default CONFIG_PCI_ROM_RUN=0
+default CONFIG_CONSOLE_VGA=0
+default CONFIG_VIDEO_MB=8
+default CONFIG_PCI_ROM_RUN=0
+
 ##
 ## Build code for the fallback boot
 ##
@@ -78,9 +82,8 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
 ##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=0
+default HAVE_PIRQ_TABLE=1
 default IRQ_SLOT_COUNT=6
-
 #object irq_tables.o
 
 ##
@@ -97,6 +100,13 @@ default ROM_IMAGE_SIZE = 65536
 default FALLBACK_SIZE = 131072
 
 ##
+## enable CACHE_AS_RAM specifics
+##
+default USE_DCACHE_RAM=1
+default DCACHE_RAM_BASE=0xc8000
+default DCACHE_RAM_SIZE=0x08000
+
+##
 ## Use a small 8K stack
 ##
 default STACK_SIZE=0x2000
diff --git a/src/mainboard/digitallogic/msm800sev/irq_tables.c b/src/mainboard/digitallogic/msm800sev/irq_tables.c
index 4322e20e9b..9236e529e5 100644
--- a/src/mainboard/digitallogic/msm800sev/irq_tables.c
+++ b/src/mainboard/digitallogic/msm800sev/irq_tables.c
@@ -1,3 +1,4 @@
+#if 0
 /* This file was generated by getpir.c, do not modify! 
    (but if you do, please run checkpir on it to verify)
  * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
@@ -58,3 +59,107 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 {
         return copy_pirq_routing_table(addr);
 }
+#endif
+/*
+* This file is part of the LinuxBIOS project.
+*
+* Copyright (C) 2007 Advanced Micro Devices
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA      02110-1301 USA
+*/
+
+#include <arch/pirq_routing.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <arch/pirq_routing.h>
+#include "../../../southbridge/amd/cs5536/cs5536.h"
+
+/* Platform IRQs */
+#define PIRQA 11
+#define PIRQB 5
+#define PIRQC 10
+#define PIRQD 10
+
+/* Map */
+#define M_PIRQA (1 << PIRQA)  /* Bitmap of supported IRQs */
+#define M_PIRQB (1 << PIRQB)  /* Bitmap of supported IRQs */
+#define M_PIRQC (1 << PIRQC)  /* Bitmap of supported IRQs */
+#define M_PIRQD (1 << PIRQD)  /* Bitmap of supported IRQs */
+
+/* Link */
+#define L_PIRQA  1 /* Means Slot INTx# Connects To Chipset INTA# */
+#define L_PIRQB  2 /* Means Slot INTx# Connects To Chipset INTB# */
+#define L_PIRQC  3 /* Means Slot INTx# Connects To Chipset INTC# */
+#define L_PIRQD  4 /* Means Slot INTx# Connects To Chipset INTD# */
+
+const struct irq_routing_table intel_irq_routing_table = {
+       PIRQ_SIGNATURE, /* u32 signature */
+       PIRQ_VERSION,   /* u16 version   */
+       32+16*IRQ_SLOT_COUNT,           /* there can be total 6 devices on the bus */
+       0x00,                   /* Where the interrupt router lies (bus) */
+       (0x0F<<3)|0x0,  /* Where the interrupt router lies (dev) */
+       0x00,                   /* IRQs devoted exclusively to PCI usage */
+       0x100B,                 /* Vendor */
+       0x002B,                 /* Device */
+       0,                              /* Crap (miniport) */
+       { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+       0x00,                   /*      u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
+       {
+               /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */
+               /* bus,         dev|fn,          {link, bitmap},         {link, bitmap},         {link, bitmap},         {link, bitmap},  slot, rfu */
+               {0x00,(0x01<<3)|0x0, {{L_PIRQA, M_PIRQA},        {0x00, 0x00},           {0x00, 0x00},           {0x00, 0x00}},    0x0, 0x0},    /* cpu */
+               {0x00,(0x0F<<3)|0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},        /* chipset */
+               {0x00,(0x0C<<3)|0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x1, 0x0},        /* slot1 */
+               {0x00,(0x0D<<3)|0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x2, 0x0},        /* slot2 */
+               {0x00,(0x0A<<3)|0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x3, 0x0},        /* slot3 */
+               {0x00,(0x0B<<3)|0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0},        /* slot4 */
+       }
+};
+
+
+
+unsigned long write_pirq_routing_table(unsigned long addr){
+       int i, j, k, num_entries;
+       unsigned int pirq[4];
+       uint16_t chipset_irq_map;
+       uint32_t pciAddr, pirtable_end;
+       struct irq_routing_table *pirq_tbl;
+
+       pirtable_end = copy_pirq_routing_table(addr);
+
+       /* Set up chipset IRQ steering */
+       pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
+       chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
+       printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr, chipset_irq_map);
+       outl(pciAddr & ~3, 0xCF8);
+       outl(chipset_irq_map, 0xCFC);
+
+       pirq_tbl = (struct irq_routing_table *)(addr);
+       num_entries = (pirq_tbl->size - 32)/16;
+
+       /* Set PCI IRQs */
+       for (i=0; i < num_entries; i++){
+               printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i, pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
+               for (j = 0; j < 4; j++){
+               printk_debug("INT: %c bitmap: %x ", 'A'+j, pirq_tbl->slots[i].irq[j].bitmap);
+                       for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++); /* finds lsb in bitmap to IRQ# */
+                       pirq[j] = k;
+                       printk_debug("PIRQ: %d\n", k);
+               }
+               pci_assign_irqs(pirq_tbl->slots[i].bus, pirq_tbl->slots[i].devfn, pirq);        /* bus, device, slots IRQs for {A,B,C,D} */
+       }
+
+       /* put the PIR table in memory and checksum */
+       return pirtable_end;
+}
\ No newline at end of file
diff --git a/src/mainboard/digitallogic/msm800sev/mainboard.c b/src/mainboard/digitallogic/msm800sev/mainboard.c
index 8bc24a43a3..95442eafb5 100644
--- a/src/mainboard/digitallogic/msm800sev/mainboard.c
+++ b/src/mainboard/digitallogic/msm800sev/mainboard.c
@@ -6,54 +6,140 @@
 #include <arch/io.h>
 #include <cpu/x86/msr.h>
 #include <cpu/amd/lxdef.h>
+#include "../../../southbridge/amd/cs5536/cs5536.h"
 #include "chip.h"
 
-#define DIVIL_LBAR_GPIO		0x5140000c
-static void init_gpio()
- {
+/* Print the platform configuration */
+void print_conf(void) {
+#if DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
+	int i;
+	unsigned long iol;
 	msr_t msr;
-	printk_debug("Initializing GPIO module...\n");
-
-	// initialize the GPIO LBAR
-	msr.lo = GPIO_BASE;
-	msr.hi = 0x0000f001;
-	wrmsr(DIVIL_LBAR_GPIO, msr);
-	msr = rdmsr(DIVIL_LBAR_GPIO);
-	printk_debug("DIVIL_LBAR_GPIO set to 0x%08x 0x%08x\n", msr.hi, msr.lo);
+
+	int cpu_msr_defs[] =  { CPU_BC_L2_CONF, CPU_IM_CONFIG,
+							CPU_DM_CONFIG0,  CPU_RCONF_DEFAULT,
+							CPU_RCONF_BYPASS, CPU_RCONF_A0_BF, CPU_RCONF_C0_DF, CPU_RCONF_E0_FF,
+							CPU_RCONF_SMM, CPU_RCONF_DMM, GLCP_DELAY_CONTROLS, GL_END
+							};
+
+	int gliu0_msr_defs[] = {MSR_GLIU0_BASE1, MSR_GLIU0_BASE2,  MSR_GLIU0_BASE4, MSR_GLIU0_BASE5, MSR_GLIU0_BASE6,
+							 GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, MSR_GLIU0_SYSMEM,
+							 GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, GLIU0_P2D_RO_2, MSR_GLIU0_SHADOW,
+							 GLIU0_IOD_BM_0, GLIU0_IOD_BM_1, GLIU0_IOD_BM_2,
+							 GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2, GLIU0_IOD_SC_3, GLIU0_IOD_SC_4, GLIU0_IOD_SC_5,
+							 GLIU0_GLD_MSR_COH, GL_END
+							};
+
+	int gliu1_msr_defs[] = {MSR_GLIU1_BASE1, MSR_GLIU1_BASE2, MSR_GLIU1_BASE3, MSR_GLIU1_BASE4, MSR_GLIU1_BASE5, MSR_GLIU1_BASE6,
+							 MSR_GLIU1_BASE7, MSR_GLIU1_BASE8, MSR_GLIU1_BASE9, MSR_GLIU1_BASE10,
+							 GLIU1_P2D_R_0, GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3, MSR_GLIU1_SHADOW,
+							 GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2,
+							 GLIU1_IOD_SC_0, GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3,
+							 GLIU1_GLD_MSR_COH, GL_END
+							};
+
+	int rconf_msr[] = { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3, CPU_RCONF4,
+						CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END
+							};
+
+	int cs5536_msr[] = { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, MDD_LEG_IO, MDD_PIN_OPT,
+						 MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH, MDD_IRQM_PRIM, GL_END
+							};
+
+	int pci_msr[] = { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF, GLPCI_C0_DF, GLPCI_E0_FF,
+					  GLPCI_RC0, GLPCI_RC1, GLPCI_RC2, GLPCI_RC3, GLPCI_ExtMSR, GLPCI_SPARE,
+						 GL_END
+							};
+
+	int dma_msr[] =	 { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2, MDD_DMA_SHAD3, MDD_DMA_SHAD4,
+							MDD_DMA_SHAD5, MDD_DMA_SHAD6, MDD_DMA_SHAD7, MDD_DMA_SHAD8,
+							MDD_DMA_SHAD9, GL_END
+							};
+
+
+	printk_debug("---------- CPU ------------\n");
+
+	for(i = 0; cpu_msr_defs[i] != GL_END; i++) {
+		msr = rdmsr(cpu_msr_defs[i]);
+		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cpu_msr_defs[i], msr.hi, msr.lo);
+	}
+
+	printk_debug("---------- GLIU 0 ------------\n");
+
+	for(i = 0; gliu0_msr_defs[i] != GL_END; i++) {
+		msr = rdmsr(gliu0_msr_defs[i]);
+		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", gliu0_msr_defs[i], msr.hi, msr.lo);
+	}
+
+	printk_debug("---------- GLIU 1 ------------\n");
+
+	for(i = 0; gliu1_msr_defs[i] != GL_END; i++) {
+		msr = rdmsr(gliu1_msr_defs[i]);
+		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", gliu1_msr_defs[i], msr.hi, msr.lo);
+	}
+
+	printk_debug("---------- RCONF ------------\n");
+
+	for(i = 0; rconf_msr[i] != GL_END; i++) {
+		msr = rdmsr(rconf_msr[i]);
+		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i], msr.hi, msr.lo);
+	}
+
+	printk_debug("---------- VARIA ------------\n");
+	msr = rdmsr(0x51300010);
+	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi, msr.lo);
+
+	msr = rdmsr(0x51400015);
+	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi, msr.lo);
+
+	printk_debug("---------- DIVIL IRQ ------------\n");
+	msr = rdmsr(MDD_IRQM_YLOW);
+	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi, msr.lo);
+	msr = rdmsr(MDD_IRQM_YHIGH);
+	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH, msr.hi, msr.lo);
+	msr = rdmsr(MDD_IRQM_ZLOW);
+	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi, msr.lo);
+	msr = rdmsr(MDD_IRQM_ZHIGH);
+	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH, msr.hi, msr.lo);
+
+
+	printk_debug("---------- PCI ------------\n");
+
+	for(i = 0; pci_msr[i] != GL_END; i++) {
+		msr = rdmsr(pci_msr[i]);
+		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i], msr.hi, msr.lo);
+	}
+
+	printk_debug("---------- LPC/UART DMA ------------\n");
+
+	for(i = 0; dma_msr[i] != GL_END; i++) {
+		msr = rdmsr(dma_msr[i]);
+		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i], msr.hi, msr.lo);
+	}
+
+	printk_debug("---------- CS5536 ------------\n");
+
+	for(i = 0; cs5536_msr[i] != GL_END; i++) {
+		msr = rdmsr(cs5536_msr[i]);
+		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i], msr.hi, msr.lo);
+	}
+
+	iol = inl(GPIOL_INPUT_ENABLE);
+	printk_debug("IOR 0x%08X is now 0x%08X\n", GPIOL_INPUT_ENABLE, iol);
+	iol = inl(GPIOL_EVENTS_ENABLE);
+	printk_debug("IOR 0x%08X is now 0x%08X\n", GPIOL_EVENTS_ENABLE, iol);
+	iol = inl(GPIOL_INPUT_INVERT_ENABLE);
+	printk_debug("IOR 0x%08X is now 0x%08X\n", GPIOL_INPUT_INVERT_ENABLE, iol);
+	iol = inl(GPIO_MAPPER_X);
+	printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_MAPPER_X, iol);
+#endif //DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
 }
 
+static void init(struct device *dev) {
 
-static void init(struct device *dev)
-{
-	unsigned bus = 0;
-	unsigned devNic = PCI_DEVFN(0xd, 0);	
-	unsigned devUsb = PCI_DEVFN(0xf, 4);
-	device_t usb = NULL, nic = NULL;
-	unsigned char irqUsb = 0xa, irqNic = 0xb;
-
-	printk_debug("DIGITALLOGIC MSM800SSEV  ENTER %s\n", __FUNCTION__);
-
-#if 0
-	// FIXME: do we need to initialize USB OHCI this way?
-	printk_debug("%s (%x,%x) set USB PCI interrupt line to %d\n", 
-		__FUNCTION__, bus, devUsb, irqUsb);
-
-	// initialize the USB controller
-	usb = dev_find_slot(bus, devUsb);
-	if (!usb) printk_err("Could not find USB\n");
-	else pci_write_config8(usb, PCI_INTERRUPT_LINE, irqUsb);
-
-	printk_debug("%s (%x,%x) set NIC PCI interrupt line to %d\n", 
-		__FUNCTION__, bus, devNic, irqNic);
-
-	// initialize theEEPRO 100
-	nic = dev_find_slot(bus, devNic);
-	if (!nic) printk_err("Could not find USB\n");
-	else pci_write_config8(nic, PCI_INTERRUPT_LINE, irqNic);
-#endif
-	init_gpio();
-
-	printk_debug("DIGITALLOGIC MSM800SSEV EXIT %s\n", __FUNCTION__);
+	printk_debug("MSM800SEV ENTER %s\n", __FUNCTION__);
+
+	printk_debug("MSM800SEV EXIT %s\n", __FUNCTION__);
 }
 
 static void enable_dev(struct device *dev)